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Searched refs:pci_config_put32 (Results 1 – 25 of 60) sorted by relevance

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/illumos-gate/usr/src/uts/intel/io/dktp/controller/ata/
H A Dsil3xxx.h80 pci_config_put32(handle, PCI_CONF_BA5_IND_ADDRESS, address); \
81 pci_config_put32(handle, PCI_CONF_BA5_IND_ACCESS, value); \
86 pci_config_put32(handle, PCI_CONF_BA5_IND_ADDRESS, address); \
/illumos-gate/usr/src/uts/common/io/usb/hcd/xhci/
H A Dxhci_quirks.c71 pci_config_put32(xhcip->xhci_cfg_handle, PCI_XHCI_INTEL_USB3_PSSEN, in xhci_reroute_intel()
76 pci_config_put32(xhcip->xhci_cfg_handle, PCI_XHCI_INTEL_XUSB2PR, in xhci_reroute_intel()
/illumos-gate/usr/src/uts/common/os/
H A Dsunpci.c127 pci_config_put32(ddi_acc_handle_t handle, off_t offset, uint32_t value) in pci_config_put32() function
693 pci_config_put32(confhdl, offset, *regbuf);
737 pci_config_put32(confhdl, offset, *p);
775 pci_config_put32(confhdl, PCI_CONF_BASE0, chs_p->chs_base0);
776 pci_config_put32(confhdl, PCI_CONF_BASE1, chs_p->chs_base1);
777 pci_config_put32(confhdl, PCI_CONF_BASE2, chs_p->chs_base2);
778 pci_config_put32(confhdl, PCI_CONF_BASE3, chs_p->chs_base3);
779 pci_config_put32(confhdl, PCI_CONF_BASE4, chs_p->chs_base4);
780 pci_config_put32(confhdl, PCI_CONF_BASE5, chs_p->chs_base5);
H A Dpcifm.c165 pci_config_put32(erpt_p->pe_hdl, in pcix_regs_gather()
256 pci_config_put32(erpt_p->pe_hdl, in pcix_regs_clear()
270 pci_config_put32(erpt_p->pe_hdl, in pcix_regs_clear()
275 pci_config_put32(erpt_p->pe_hdl, in pcix_regs_clear()
292 pci_config_put32(erpt_p->pe_hdl, in pcix_regs_clear()
304 pci_config_put32(erpt_p->pe_hdl, in pcix_regs_clear()
/illumos-gate/usr/src/uts/common/io/cardbus/
H A Dcardbus_cfg.c900 pci_config_put32(handle, offset, in cardbus_bridge_assign()
902 pci_config_put32(handle, offset + 4, in cardbus_bridge_assign()
920 pci_config_put32(handle, offset, 0xffffffff); in cardbus_bridge_assign()
923 pci_config_put32(handle, offset, in cardbus_bridge_assign()
936 pci_config_put32(handle, offset + 4, 0); in cardbus_bridge_assign()
956 pci_config_put32(handle, offset, io_answer); in cardbus_bridge_assign()
1485 pci_config_put32(handle, PCI_CBUS_MEM_BASE0, in cardbus_setup_bridge()
1496 pci_config_put32(handle, PCI_CBUS_IO_BASE0, in cardbus_setup_bridge()
1522 pci_config_put32(handle, PCI_CBUS_IO_BASE1, 0); in cardbus_setup_bridge()
1598 pci_config_put32(handle, PCI_CBUS_MEM_LIMIT0, in cardbus_update_bridge()
[all …]
/illumos-gate/usr/src/uts/sun4u/io/pci/
H A Ddb21554.c1037 pci_config_put32(dbp->conf_handle, in db_enable_io()
1286 pci_config_put32(dbp->conf_handle, in db_set_dvma_range()
1296 pci_config_put32(dbp->conf_handle, in db_set_dvma_range()
1299 pci_config_put32(dbp->conf_handle, in db_set_dvma_range()
1308 pci_config_put32(dbp->conf_handle, in db_set_dvma_range()
1318 pci_config_put32(dbp->conf_handle, in db_set_dvma_range()
1320 pci_config_put32(dbp->conf_handle, in db_set_dvma_range()
1333 pci_config_put32(dbp->conf_handle, in db_set_dvma_range()
1344 pci_config_put32(dbp->conf_handle, in db_set_dvma_range()
1347 pci_config_put32(dbp->conf_handle, in db_set_dvma_range()
[all …]
/illumos-gate/usr/src/uts/intel/io/hotplug/pcicfg/
H A Dpcicfg.c1953 pci_config_put32(handle, offset, in pcicfg_bridge_assign()
1968 pci_config_put32(handle, offset, io_answer); in pcicfg_bridge_assign()
2099 pci_config_put32(handle, offset, in pcicfg_device_assign()
2102 pci_config_put32(handle, offset + 4, in pcicfg_device_assign()
2137 pci_config_put32(handle, offset, in pcicfg_device_assign()
2164 pci_config_put32(handle, offset, in pcicfg_device_assign()
3311 pci_config_put32(handle, PCI_BCNF_PF_BASE_HIGH, in pcicfg_setup_bridge()
3681 pci_config_put32(config_handle, i, base); in pcicfg_populate_props_from_bar()
4034 pci_config_put32(h, PCI_BCNF_PF_BASE_HIGH, in pcicfg_probe_bridge()
4045 pci_config_put32(h, PCI_BCNF_PF_LIMIT_HIGH, in pcicfg_probe_bridge()
[all …]
/illumos-gate/usr/src/uts/common/io/bge/
H A Dbge_chip2.c215 pci_config_put32(bgep->cfg_handle, regno, regval); in bge_cfg_clr32()
373 pci_config_put32(handle, PCI_CONF_BGE_MHCR, 0); in bge_chip_cfg_init()
488 pci_config_put32(handle, PCI_CONF_BGE_MHCR, mhcr); in bge_chip_cfg_init()
559 pci_config_put32(handle, PCI_CONF_BGE_RIAAR, 0); in bge_chip_cfg_init()
560 pci_config_put32(handle, PCI_CONF_BGE_MWBAR, 0); in bge_chip_cfg_init()
3302 pci_config_put32(bgep->cfg_handle, in bge_chip_reset_engine()
3346 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, in bge_chip_reset_engine()
3803 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, in bge_chip_stop()
4400 pci_config_put32(bgep->cfg_handle, in bge_chip_start()
5019 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, in bge_chip_start()
[all …]
/illumos-gate/usr/src/uts/common/io/chxge/
H A Dch.c485 pci_config_put32(chp->ch_hpci, 0x44, 3); in ch_attach()
486 pci_config_put32(chp->ch_hpci, 0x44, 0); in ch_attach()
754 pci_config_put32(chp->ch_hpci, 0x44, 3); in ch_quiesce()
755 pci_config_put32(chp->ch_hpci, 0x44, 0); in ch_quiesce()
814 pci_config_put32(chp->ch_hpci, 0x44, 3); in ch_detach()
815 pci_config_put32(chp->ch_hpci, 0x44, 0); in ch_detach()
1432 pci_config_put32(chp->ch_hpci, 0x44, 3); in ch_reset()
1433 pci_config_put32(chp->ch_hpci, 0x44, 0); in ch_reset()
H A Dglue.c125 pci_config_put32(obj->ch_hpci, reg, val); in t1_os_pci_write_config_4()
282 pci_config_put32(chp->ch_hpci, pe->addr, pe->pe_reg_val); in pe_ioctl()
/illumos-gate/usr/src/uts/intel/io/mc-amd/
H A Dmcamd_pcicfg.c92 pci_config_put32(hdlp->cfh_hdl, offset, val); in mc_pcicfg_put32()
/illumos-gate/usr/src/uts/i86pc/io/pcplusmp/
H A Dapic_introp.c118 pci_config_put32(handle, in apic_pci_msi_enable_vector()
122 pci_config_put32(handle, in apic_pci_msi_enable_vector()
600 pci_config_put32(handle, msi_mask_off, (uint32_t)-1); in apic_grp_set_cpu()
631 pci_config_put32(handle, msi_mask_off, msi_pvm); in apic_grp_set_cpu()
H A Dapic_common.c1852 pci_config_put32(handle, cap_ptr + PCI_MSI_ADDR_OFFSET, 0); in apic_pci_msi_unconfigure()
1857 pci_config_put32(handle, in apic_pci_msi_unconfigure()
/illumos-gate/usr/src/uts/intel/io/amr/
H A Damrreg.h636 #define AMR_QPUT_IDB(sc, val) pci_config_put32(sc->regsmap_handle, \
640 #define AMR_QPUT_ODB(sc, val) pci_config_put32(sc->regsmap_handle, \
/illumos-gate/usr/src/uts/sun4/io/
H A Dpcicfg.c2008 pci_config_put32(handle, in pcicfg_bridge_assign()
2023 pci_config_put32(handle, offset, io_answer); in pcicfg_bridge_assign()
2148 pci_config_put32(handle, in pcicfg_device_assign()
2152 pci_config_put32(handle, offset + 4, in pcicfg_device_assign()
2181 pci_config_put32(handle, in pcicfg_device_assign()
2203 pci_config_put32(handle, in pcicfg_device_assign()
4210 pci_config_put32(config_handle, i, 0xffffffff); in pcicfg_populate_reg_props()
4497 pci_config_put32(h, PCI_CONF_ROM, 0xfffffffe); in pcicfg_fcode_probe()
4803 pci_config_put32(config_handle, i, base); in pcicfg_populate_props_from_bar()
6025 pci_config_put32(h, i, 0xffffffff); in pcicfg_fcode_assign_bars()
[all …]
/illumos-gate/usr/src/uts/intel/io/pciex/
H A Dpcieb_x86.c505 pci_config_put32(cfg_hdl, reg->offset, value); in pcieb_intel_serr_workaround()
602 pci_config_put32(bus_p->bus_cfg_hdl, in pcieb_intel_mps_workaround()
/illumos-gate/usr/src/uts/common/io/e1000g/
H A De1000g_debug.c581 pci_config_put32(handle, offset, 0xffffffff); in pciconfig_bar()
589 pci_config_put32(handle, offset, base); in pciconfig_bar()
/illumos-gate/usr/src/uts/common/io/1394/adapters/
H A Dhci1394_attach.c470 pci_config_put32(soft_state->pci_config, in hci1394_pci_init()
553 pci_config_put32(soft_state->pci_config, in hci1394_pci_resume()
/illumos-gate/usr/src/uts/sun4u/io/
H A Dpmubus.c561 pci_config_put32(softsp->pmubus_reghdl, offset, tmp); in pmubus_put32()
569 pci_config_put32(softsp->pmubus_reghdl, offset, value); in pmubus_put32()
/illumos-gate/usr/src/uts/common/io/
H A Dpci_cap.c324 pci_config_put32(h, offset, data); in pci_cap_put()
/illumos-gate/usr/src/uts/common/io/yge/
H A Dyge.c602 pci_config_put32(dev->d_pcih, PCI_OUR_REG_1, val); in yge_phy_power()
613 pci_config_put32(dev->d_pcih, PCI_OUR_REG_3, 0); in yge_phy_power()
619 pci_config_put32(dev->d_pcih, PCI_OUR_REG_4, our); in yge_phy_power()
624 pci_config_put32(dev->d_pcih, PCI_OUR_REG_5, our); in yge_phy_power()
626 pci_config_put32(dev->d_pcih, PCI_OUR_REG_1, 0); in yge_phy_power()
660 pci_config_put32(dev->d_pcih, PCI_OUR_REG_1, val); in yge_phy_power()
747 pci_config_put32(pcih, PCI_OUR_REG_1, val); in yge_reset()
1222 pci_config_put32(dev->d_pcih, PCI_OUR_REG_3, 0); in yge_attach()
1771 pci_config_put32(dev->d_pcih, PCI_OUR_REG_3, 0); in yge_resume()
/illumos-gate/usr/src/uts/common/io/ib/adapters/hermon/
H A Dhermon.c3911 pci_config_put32(hdl, i << 2, state->hs_cfg_data[i]); in hermon_sw_reset()
3921 pci_config_put32(hdl, offset + HERMON_PCI_CAP_DEV_OFFS, data32); in hermon_sw_reset()
3923 pci_config_put32(hdl, offset + HERMON_PCI_CAP_LNK_OFFS, data32); in hermon_sw_reset()
3925 pci_config_put32(hdl, 0x04, (state->hs_cfg_data[1] | 0x0006)); in hermon_sw_reset()
4193 (void) pci_config_put32(hdl, offset, addr << 16); in hermon_pci_read_vpd()
4968 pci_config_put32(pcihdl, i << 2, state->hs_cfg_data[i]); in hermon_quiesce()
5001 pci_config_put32(pcihdl, offset + HERMON_PCI_CAP_DEV_OFFS, data32); in hermon_quiesce()
5003 pci_config_put32(pcihdl, offset + HERMON_PCI_CAP_LNK_OFFS, data32); in hermon_quiesce()
5006 pci_config_put32(pcihdl, 0x04, (state->hs_cfg_data[1] | 0x0006)); in hermon_quiesce()
/illumos-gate/usr/src/uts/common/io/nge/
H A Dnge_chip.c174 pci_config_put32(ngep->cfg_handle, regno, regval); in nge_chip_poke_cfg()
635 pci_config_put32(handle, PCI_CONF_HT_INTERNAL, in nge_chip_cfg_init()
652 pci_config_put32(handle, PCI_CONF_HT_MSI_MASK, in nge_chip_cfg_init()
659 pci_config_put32(handle, PCI_CONF_HT_MSI_MAP_CAP, in nge_chip_cfg_init()
666 pci_config_put32(handle, PCI_CONF_HT_INTERNAL, in nge_chip_cfg_init()
/illumos-gate/usr/src/uts/common/io/xge/drv/
H A Dxge_osdep.h314 pci_config_put32(cfgh, where, val)
/illumos-gate/usr/src/uts/common/mapfiles/
H A Dddi.mapfile207 pci_config_put32 { FLAGS = EXTERN };

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