18a40a695Sgavinm /*
28a40a695Sgavinm * CDDL HEADER START
38a40a695Sgavinm *
48a40a695Sgavinm * The contents of this file are subject to the terms of the
58a40a695Sgavinm * Common Development and Distribution License (the "License").
68a40a695Sgavinm * You may not use this file except in compliance with the License.
78a40a695Sgavinm *
88a40a695Sgavinm * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
98a40a695Sgavinm * or http://www.opensolaris.org/os/licensing.
108a40a695Sgavinm * See the License for the specific language governing permissions
118a40a695Sgavinm * and limitations under the License.
128a40a695Sgavinm *
138a40a695Sgavinm * When distributing Covered Code, include this CDDL HEADER in each
148a40a695Sgavinm * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
158a40a695Sgavinm * If applicable, add the following below this CDDL HEADER, with the
168a40a695Sgavinm * fields enclosed by brackets "[]" replaced with your own identifying
178a40a695Sgavinm * information: Portions Copyright [yyyy] [name of copyright owner]
188a40a695Sgavinm *
198a40a695Sgavinm * CDDL HEADER END
208a40a695Sgavinm */
218a40a695Sgavinm
228a40a695Sgavinm /*
23*e4b86885SCheng Sean Ye * Copyright 2008 Sun Microsystems, Inc. All rights reserved.
248a40a695Sgavinm * Use is subject to license terms.
258a40a695Sgavinm */
268a40a695Sgavinm
278a40a695Sgavinm #include <sys/ddi.h>
288a40a695Sgavinm #include <sys/sunddi.h>
298a40a695Sgavinm
308a40a695Sgavinm #include <mcamd_pcicfg.h>
3120c794b3Sgavinm #include <sys/pci_cfgspace.h>
328a40a695Sgavinm
338a40a695Sgavinm struct _mc_pcicfg_hdl {
348a40a695Sgavinm mc_t *cfh_mc;
358a40a695Sgavinm enum mc_funcnum cfh_func;
368a40a695Sgavinm ddi_acc_handle_t cfh_hdl;
378a40a695Sgavinm };
388a40a695Sgavinm
398a40a695Sgavinm static int
mccfgsetup(struct _mc_pcicfg_hdl * hdlp,mc_t * mc,enum mc_funcnum func)408a40a695Sgavinm mccfgsetup(struct _mc_pcicfg_hdl *hdlp, mc_t *mc, enum mc_funcnum func)
418a40a695Sgavinm {
428a40a695Sgavinm hdlp->cfh_mc = mc;
438a40a695Sgavinm hdlp->cfh_func = func;
448a40a695Sgavinm
4520c794b3Sgavinm if (mc->mc_funcs[func].mcf_devi == NULL)
4620c794b3Sgavinm return (DDI_FAILURE);
4720c794b3Sgavinm
488a40a695Sgavinm if (pci_config_setup(mc->mc_funcs[func].mcf_devi, &hdlp->cfh_hdl) !=
498a40a695Sgavinm DDI_SUCCESS)
508a40a695Sgavinm return (DDI_FAILURE);
518a40a695Sgavinm
528a40a695Sgavinm return (DDI_SUCCESS);
538a40a695Sgavinm }
548a40a695Sgavinm
558a40a695Sgavinm int
mc_pcicfg_setup(mc_t * mc,enum mc_funcnum func,mc_pcicfg_hdl_t * cookiep)568a40a695Sgavinm mc_pcicfg_setup(mc_t *mc, enum mc_funcnum func, mc_pcicfg_hdl_t *cookiep)
578a40a695Sgavinm {
588a40a695Sgavinm struct _mc_pcicfg_hdl *hdlp;
598a40a695Sgavinm
608a40a695Sgavinm *cookiep = hdlp = kmem_alloc(sizeof (struct _mc_pcicfg_hdl), KM_SLEEP);
618a40a695Sgavinm
628a40a695Sgavinm if (mccfgsetup(hdlp, mc, func) == DDI_FAILURE) {
638a40a695Sgavinm kmem_free(hdlp, sizeof (*hdlp));
648a40a695Sgavinm return (DDI_FAILURE);
658a40a695Sgavinm }
668a40a695Sgavinm
678a40a695Sgavinm return (DDI_SUCCESS);
688a40a695Sgavinm }
698a40a695Sgavinm
708a40a695Sgavinm void
mc_pcicfg_teardown(mc_pcicfg_hdl_t cookie)718a40a695Sgavinm mc_pcicfg_teardown(mc_pcicfg_hdl_t cookie)
728a40a695Sgavinm {
738a40a695Sgavinm struct _mc_pcicfg_hdl *hdlp = cookie;
748a40a695Sgavinm
758a40a695Sgavinm pci_config_teardown(&hdlp->cfh_hdl);
768a40a695Sgavinm kmem_free(hdlp, sizeof (*hdlp));
778a40a695Sgavinm }
788a40a695Sgavinm
798a40a695Sgavinm uint32_t
mc_pcicfg_get32(mc_pcicfg_hdl_t cookie,off_t offset)808a40a695Sgavinm mc_pcicfg_get32(mc_pcicfg_hdl_t cookie, off_t offset)
818a40a695Sgavinm {
828a40a695Sgavinm struct _mc_pcicfg_hdl *hdlp = cookie;
838a40a695Sgavinm
848a40a695Sgavinm return (pci_config_get32(hdlp->cfh_hdl, offset));
858a40a695Sgavinm }
868a40a695Sgavinm
8720c794b3Sgavinm void
mc_pcicfg_put32(mc_pcicfg_hdl_t cookie,off_t offset,uint32_t val)8820c794b3Sgavinm mc_pcicfg_put32(mc_pcicfg_hdl_t cookie, off_t offset, uint32_t val)
8920c794b3Sgavinm {
9020c794b3Sgavinm struct _mc_pcicfg_hdl *hdlp = cookie;
9120c794b3Sgavinm
9220c794b3Sgavinm pci_config_put32(hdlp->cfh_hdl, offset, val);
9320c794b3Sgavinm }
9420c794b3Sgavinm
958a40a695Sgavinm uint32_t
mc_pcicfg_get32_nohdl(mc_t * mc,enum mc_funcnum func,off_t offset)968a40a695Sgavinm mc_pcicfg_get32_nohdl(mc_t *mc, enum mc_funcnum func, off_t offset)
978a40a695Sgavinm {
9820c794b3Sgavinm return ((*pci_getl_func)(0, MC_AMD_DEV_OFFSET + mc->mc_props.mcp_num,
9920c794b3Sgavinm func, offset));
1008a40a695Sgavinm }
1018a40a695Sgavinm
1028a40a695Sgavinm void
mc_pcicfg_put32_nohdl(mc_t * mc,enum mc_funcnum func,off_t offset,uint32_t val)1038a40a695Sgavinm mc_pcicfg_put32_nohdl(mc_t *mc, enum mc_funcnum func, off_t offset,
1048a40a695Sgavinm uint32_t val)
1058a40a695Sgavinm {
10620c794b3Sgavinm (*pci_putl_func)(0, MC_AMD_DEV_OFFSET + mc->mc_props.mcp_num,
1078a40a695Sgavinm func, offset, val);
1088a40a695Sgavinm }
109