108057504Sxy /*
208057504Sxy * This file is provided under a CDDLv1 license. When using or
308057504Sxy * redistributing this file, you may do so under this license.
408057504Sxy * In redistributing this file this license must be included
508057504Sxy * and no other modification of this header file is permitted.
608057504Sxy *
708057504Sxy * CDDL LICENSE SUMMARY
808057504Sxy *
9*caf05df5SMiles Xu, Sun Microsystems * Copyright(c) 1999 - 2009 Intel Corporation. All rights reserved.
1008057504Sxy *
1108057504Sxy * The contents of this file are subject to the terms of Version
1208057504Sxy * 1.0 of the Common Development and Distribution License (the "License").
1308057504Sxy *
1408057504Sxy * You should have received a copy of the License with this software.
1508057504Sxy * You can obtain a copy of the License at
1608057504Sxy * http://www.opensolaris.org/os/licensing.
1708057504Sxy * See the License for the specific language governing permissions
1808057504Sxy * and limitations under the License.
1908057504Sxy */
2008057504Sxy
2108057504Sxy /*
22*caf05df5SMiles Xu, Sun Microsystems * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
2308057504Sxy * Use is subject to license terms of the CDDLv1.
2408057504Sxy */
2508057504Sxy
2608057504Sxy /*
2708057504Sxy * **********************************************************************
2808057504Sxy * *
2908057504Sxy * Module Name: *
3025f2d433Sxy * e1000g_debug.c *
3108057504Sxy * *
3208057504Sxy * Abstract: *
3325f2d433Sxy * This module includes the debug routines *
3408057504Sxy * *
3508057504Sxy * **********************************************************************
3608057504Sxy */
3708057504Sxy #ifdef GCC
3808057504Sxy #ifdef __STDC__
3908057504Sxy #include <stdarg.h>
4008057504Sxy #else
4108057504Sxy #include <varargs.h>
4208057504Sxy #endif
4308057504Sxy #define _SYS_VARARGS_H
4408057504Sxy #endif
4508057504Sxy
4608057504Sxy #include "e1000g_debug.h"
4725f2d433Sxy #include "e1000g_sw.h"
484914a7d0Syy #ifdef E1000G_DEBUG
494914a7d0Syy #include <sys/pcie.h>
504914a7d0Syy #endif
5125f2d433Sxy
5225f2d433Sxy #ifdef E1000G_DEBUG
534914a7d0Syy #define WPL 8 /* 8 16-bit words per line */
54592a4d85Scc #define NUM_REGS 155 /* must match the array initializer */
554914a7d0Syy typedef struct {
564914a7d0Syy char name[10];
574914a7d0Syy uint32_t offset;
584914a7d0Syy } Regi_t;
59*caf05df5SMiles Xu, Sun Microsystems
6025f2d433Sxy int e1000g_debug = E1000G_WARN_LEVEL;
61*caf05df5SMiles Xu, Sun Microsystems #endif /* E1000G_DEBUG */
6225f2d433Sxy int e1000g_log_mode = E1000G_LOG_PRINT;
6308057504Sxy
6408057504Sxy void
e1000g_log(void * instance,int level,char * fmt,...)6525f2d433Sxy e1000g_log(void *instance, int level, char *fmt, ...)
6608057504Sxy {
6725f2d433Sxy struct e1000g *Adapter = (struct e1000g *)instance;
6808057504Sxy auto char name[NAMELEN];
6908057504Sxy auto char buf[BUFSZ];
7008057504Sxy va_list ap;
7108057504Sxy
7225f2d433Sxy switch (level) {
7325f2d433Sxy #ifdef E1000G_DEBUG
7425f2d433Sxy case E1000G_VERBOSE_LEVEL: /* 16 or 0x010 */
7525f2d433Sxy if (e1000g_debug < E1000G_VERBOSE_LEVEL)
7625f2d433Sxy return;
7725f2d433Sxy level = CE_CONT;
7825f2d433Sxy break;
7925f2d433Sxy
8025f2d433Sxy case E1000G_TRACE_LEVEL: /* 8 or 0x008 */
8125f2d433Sxy if (e1000g_debug < E1000G_TRACE_LEVEL)
8225f2d433Sxy return;
8325f2d433Sxy level = CE_CONT;
8425f2d433Sxy break;
8525f2d433Sxy
8625f2d433Sxy case E1000G_INFO_LEVEL: /* 4 or 0x004 */
8725f2d433Sxy if (e1000g_debug < E1000G_INFO_LEVEL)
8825f2d433Sxy return;
8925f2d433Sxy level = CE_CONT;
9025f2d433Sxy break;
9125f2d433Sxy
9225f2d433Sxy case E1000G_WARN_LEVEL: /* 2 or 0x002 */
9325f2d433Sxy if (e1000g_debug < E1000G_WARN_LEVEL)
9425f2d433Sxy return;
9525f2d433Sxy level = CE_CONT;
9625f2d433Sxy break;
9725f2d433Sxy
9825f2d433Sxy case E1000G_ERRS_LEVEL: /* 1 or 0x001 */
9925f2d433Sxy level = CE_CONT;
10025f2d433Sxy break;
10125f2d433Sxy #else
10225f2d433Sxy case CE_CONT:
10325f2d433Sxy case CE_NOTE:
10425f2d433Sxy case CE_WARN:
10525f2d433Sxy case CE_PANIC:
10625f2d433Sxy break;
10725f2d433Sxy #endif
10825f2d433Sxy default:
10925f2d433Sxy level = CE_CONT;
11025f2d433Sxy break;
11125f2d433Sxy }
11225f2d433Sxy
11308057504Sxy if (Adapter != NULL) {
11408057504Sxy (void) sprintf(name, "%s - e1000g[%d] ",
11508057504Sxy ddi_get_name(Adapter->dip), ddi_get_instance(Adapter->dip));
11608057504Sxy } else {
11708057504Sxy (void) sprintf(name, "e1000g");
11808057504Sxy }
11908057504Sxy /*
12008057504Sxy * va_start uses built in macro __builtin_va_alist from the
12108057504Sxy * compiler libs which requires compiler system to have
12208057504Sxy * __BUILTIN_VA_ARG_INCR defined.
12308057504Sxy */
12408057504Sxy /*
12508057504Sxy * Many compilation systems depend upon the use of special functions
12608057504Sxy * built into the the compilation system to handle variable argument
12708057504Sxy * lists and stack allocations. The method to obtain this in SunOS
12808057504Sxy * is to define the feature test macro "__BUILTIN_VA_ARG_INCR" which
12908057504Sxy * enables the following special built-in functions:
13008057504Sxy * __builtin_alloca
13108057504Sxy * __builtin_va_alist
13208057504Sxy * __builtin_va_arg_incr
13308057504Sxy * It is intended that the compilation system define this feature test
13408057504Sxy * macro, not the user of the system.
13508057504Sxy *
13608057504Sxy * The tests on the processor type are to provide a transitional period
13708057504Sxy * for existing compilation systems, and may be removed in a future
13808057504Sxy * release.
13908057504Sxy */
14008057504Sxy /*
14108057504Sxy * Using GNU gcc compiler it doesn't expand to va_start....
14208057504Sxy */
14308057504Sxy va_start(ap, fmt);
14408057504Sxy (void) vsprintf(buf, fmt, ap);
14508057504Sxy va_end(ap);
14608057504Sxy
14725f2d433Sxy if ((e1000g_log_mode & E1000G_LOG_ALL) == E1000G_LOG_ALL)
14825f2d433Sxy cmn_err(level, "%s: %s", name, buf);
14925f2d433Sxy else if (e1000g_log_mode & E1000G_LOG_DISPLAY)
15025f2d433Sxy cmn_err(level, "^%s: %s", name, buf);
15125f2d433Sxy else if (e1000g_log_mode & E1000G_LOG_PRINT)
15225f2d433Sxy cmn_err(level, "!%s: %s", name, buf);
15325f2d433Sxy else /* if they are not set properly then do both */
15408057504Sxy cmn_err(level, "%s: %s", name, buf);
15508057504Sxy }
1564914a7d0Syy
1574914a7d0Syy
1584914a7d0Syy
1594914a7d0Syy #ifdef E1000G_DEBUG
160a2e9a830Scc extern kmutex_t e1000g_nvm_lock;
161a2e9a830Scc
1624914a7d0Syy void
eeprom_dump(void * instance)1634914a7d0Syy eeprom_dump(void *instance)
1644914a7d0Syy {
1654914a7d0Syy struct e1000g *Adapter = (struct e1000g *)instance;
1664914a7d0Syy struct e1000_hw *hw = &Adapter->shared;
1674914a7d0Syy uint16_t eeprom[WPL], size_field;
1684914a7d0Syy int i, ret, sign, size, lines, offset = 0;
1694914a7d0Syy int ee_size[] =
1704914a7d0Syy {128, 256, 512, 1024, 2048, 4096, 16 * 1024, 32 * 1024, 64 * 1024};
1714914a7d0Syy
172a2e9a830Scc mutex_enter(&e1000g_nvm_lock);
173a2e9a830Scc
1744914a7d0Syy if (ret = e1000_read_nvm(hw, 0x12, 1, &size_field)) {
1754914a7d0Syy e1000g_log(Adapter, CE_WARN,
1764914a7d0Syy "e1000_read_nvm failed to read size: %d", ret);
177a2e9a830Scc goto eeprom_dump_end;
1784914a7d0Syy }
1794914a7d0Syy
1804914a7d0Syy sign = (size_field & 0xc000) >> 14;
1814914a7d0Syy if (sign != 1) {
1824914a7d0Syy e1000g_log(Adapter, CE_WARN,
1834914a7d0Syy "eeprom_dump invalid signature: %d", sign);
1844914a7d0Syy }
1854914a7d0Syy
1864914a7d0Syy size = (size_field & 0x3c00) >> 10;
1874914a7d0Syy if (size < 0 || size > 11) {
1884914a7d0Syy e1000g_log(Adapter, CE_WARN,
1894914a7d0Syy "eeprom_dump invalid size: %d", size);
1904914a7d0Syy }
1914914a7d0Syy
1924914a7d0Syy e1000g_log(Adapter, CE_CONT,
1934914a7d0Syy "eeprom_dump size field: %d eeprom bytes: %d\n",
1944914a7d0Syy size, ee_size[size]);
1954914a7d0Syy
1964914a7d0Syy e1000g_log(Adapter, CE_CONT,
1974914a7d0Syy "e1000_read_nvm hebs: %d\n", ((size_field & 0x000f) >> 10));
1984914a7d0Syy
1994914a7d0Syy lines = ee_size[size] / WPL / 2;
2004914a7d0Syy e1000g_log(Adapter, CE_CONT,
2014914a7d0Syy "dump eeprom %d lines of %d words per line\n", lines, WPL);
2024914a7d0Syy
2034914a7d0Syy for (i = 0; i < lines; i++) {
2044914a7d0Syy if (ret = e1000_read_nvm(hw, offset, WPL, eeprom)) {
2054914a7d0Syy e1000g_log(Adapter, CE_WARN,
2064914a7d0Syy "e1000_read_nvm failed: %d", ret);
207a2e9a830Scc goto eeprom_dump_end;
2084914a7d0Syy }
2094914a7d0Syy
2104914a7d0Syy e1000g_log(Adapter, CE_CONT,
2114914a7d0Syy "0x%04x %04x %04x %04x %04x %04x %04x %04x %04x\n",
2124914a7d0Syy offset,
2134914a7d0Syy eeprom[0], eeprom[1], eeprom[2], eeprom[3],
2144914a7d0Syy eeprom[4], eeprom[5], eeprom[6], eeprom[7]);
2154914a7d0Syy offset += WPL;
2164914a7d0Syy }
217a2e9a830Scc
218a2e9a830Scc eeprom_dump_end:
219a2e9a830Scc mutex_exit(&e1000g_nvm_lock);
2204914a7d0Syy }
2214914a7d0Syy
2224914a7d0Syy /*
2234914a7d0Syy * phy_dump - dump important phy registers
2244914a7d0Syy */
2254914a7d0Syy void
phy_dump(void * instance)2264914a7d0Syy phy_dump(void *instance)
2274914a7d0Syy {
2284914a7d0Syy struct e1000g *Adapter = (struct e1000g *)instance;
2294914a7d0Syy struct e1000_hw *hw = &Adapter->shared;
2304914a7d0Syy /* offset to each phy register */
2314914a7d0Syy int32_t offset[] =
2324914a7d0Syy { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
2334914a7d0Syy 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
2344914a7d0Syy 30, 31, 0x1796, 0x187A, 0x1895, 0x1F30, 0x1F35, 0x1F3E, 0x1F54,
2354914a7d0Syy 0x1F55, 0x1F56, 0x1F72, 0x1F76, 0x1F77, 0x1F78, 0x1F79, 0x1F98,
2364914a7d0Syy 0x2010, 0x2011, 0x20DC, 0x20DD, 0x20DE, 0x28B4, 0x2F52, 0x2F5B,
2374914a7d0Syy 0x2F70, 0x2F90, 0x2FB1, 0x2FB2 };
2384914a7d0Syy uint16_t value; /* register value */
2394914a7d0Syy uint32_t stat; /* status from e1000_read_phy_reg */
2404914a7d0Syy int i;
2414914a7d0Syy
2424914a7d0Syy e1000g_log(Adapter, CE_CONT, "Begin PHY dump\n");
2434914a7d0Syy for (i = 0; i < ((sizeof (offset)) / sizeof (offset[0])); i++) {
2444914a7d0Syy
2454914a7d0Syy stat = e1000_read_phy_reg(hw, offset[i], &value);
2464914a7d0Syy if (stat == 0) {
2474914a7d0Syy e1000g_log(Adapter, CE_CONT,
2484914a7d0Syy "phyreg offset: %d value: 0x%x\n",
2494914a7d0Syy offset[i], value);
2504914a7d0Syy } else {
2514914a7d0Syy e1000g_log(Adapter, CE_WARN,
2524914a7d0Syy "phyreg offset: %d ERROR: 0x%x\n",
2534914a7d0Syy offset[i], stat);
2544914a7d0Syy }
2554914a7d0Syy }
2564914a7d0Syy }
2574914a7d0Syy
2584914a7d0Syy uint32_t
e1000_read_reg(struct e1000_hw * hw,uint32_t offset)2594914a7d0Syy e1000_read_reg(struct e1000_hw *hw, uint32_t offset)
2604914a7d0Syy {
2614914a7d0Syy return (ddi_get32(((struct e1000g_osdep *)(hw)->back)->reg_handle,
262fe62dec3SChen-Liang Xu (uint32_t *)((uintptr_t)(hw)->hw_addr + offset)));
2634914a7d0Syy }
2644914a7d0Syy
2654914a7d0Syy
2664914a7d0Syy /*
2674914a7d0Syy * mac_dump - dump important mac registers
2684914a7d0Syy */
2694914a7d0Syy void
mac_dump(void * instance)2704914a7d0Syy mac_dump(void *instance)
2714914a7d0Syy {
2724914a7d0Syy struct e1000g *Adapter = (struct e1000g *)instance;
2734914a7d0Syy struct e1000_hw *hw = &Adapter->shared;
2744914a7d0Syy int i;
2754914a7d0Syy
2764914a7d0Syy /* {name, offset} for each mac register */
2774914a7d0Syy Regi_t macreg[NUM_REGS] = {
2784914a7d0Syy {"CTRL", E1000_CTRL}, {"STATUS", E1000_STATUS},
2794914a7d0Syy {"EECD", E1000_EECD}, {"EERD", E1000_EERD},
2804914a7d0Syy {"CTRL_EXT", E1000_CTRL_EXT}, {"FLA", E1000_FLA},
2814914a7d0Syy {"MDIC", E1000_MDIC}, {"SCTL", E1000_SCTL},
2824914a7d0Syy {"FCAL", E1000_FCAL}, {"FCAH", E1000_FCAH},
2834914a7d0Syy {"FCT", E1000_FCT}, {"VET", E1000_VET},
2844914a7d0Syy {"ICR", E1000_ICR}, {"ITR", E1000_ITR},
2854914a7d0Syy {"ICS", E1000_ICS}, {"IMS", E1000_IMS},
2864914a7d0Syy {"IMC", E1000_IMC}, {"IAM", E1000_IAM},
2874914a7d0Syy {"RCTL", E1000_RCTL}, {"FCTTV", E1000_FCTTV},
2884914a7d0Syy {"TXCW", E1000_TXCW}, {"RXCW", E1000_RXCW},
2894914a7d0Syy {"TCTL", E1000_TCTL}, {"TIPG", E1000_TIPG},
2904914a7d0Syy {"AIT", E1000_AIT}, {"LEDCTL", E1000_LEDCTL},
2914914a7d0Syy {"PBA", E1000_PBA}, {"PBS", E1000_PBS},
2924914a7d0Syy {"EEMNGCTL", E1000_EEMNGCTL}, {"ERT", E1000_ERT},
2934914a7d0Syy {"FCRTL", E1000_FCRTL}, {"FCRTH", E1000_FCRTH},
294592a4d85Scc {"PSRCTL", E1000_PSRCTL}, {"RDBAL(0)", E1000_RDBAL(0)},
295592a4d85Scc {"RDBAH(0)", E1000_RDBAH(0)}, {"RDLEN(0)", E1000_RDLEN(0)},
296592a4d85Scc {"RDH(0)", E1000_RDH(0)}, {"RDT(0)", E1000_RDT(0)},
297592a4d85Scc {"RDTR", E1000_RDTR}, {"RXDCTL(0)", E1000_RXDCTL(0)},
298592a4d85Scc {"RADV", E1000_RADV}, {"RDBAL(1)", E1000_RDBAL(1)},
299592a4d85Scc {"RDBAH(1)", E1000_RDBAH(1)}, {"RDLEN(1)", E1000_RDLEN(1)},
300592a4d85Scc {"RDH(1)", E1000_RDH(1)}, {"RDT(1)", E1000_RDT(1)},
301592a4d85Scc {"RXDCTL(1)", E1000_RXDCTL(1)}, {"RSRPD", E1000_RSRPD},
3024914a7d0Syy {"RAID", E1000_RAID}, {"CPUVEC", E1000_CPUVEC},
3034914a7d0Syy {"TDFH", E1000_TDFH}, {"TDFT", E1000_TDFT},
3044914a7d0Syy {"TDFHS", E1000_TDFHS}, {"TDFTS", E1000_TDFTS},
305592a4d85Scc {"TDFPC", E1000_TDFPC}, {"TDBAL(0)", E1000_TDBAL(0)},
306592a4d85Scc {"TDBAH(0)", E1000_TDBAH(0)}, {"TDLEN(0)", E1000_TDLEN(0)},
307592a4d85Scc {"TDH(0)", E1000_TDH(0)}, {"TDT(0)", E1000_TDT(0)},
308592a4d85Scc {"TIDV", E1000_TIDV}, {"TXDCTL(0)", E1000_TXDCTL(0)},
309592a4d85Scc {"TADV", E1000_TADV}, {"TARC(0)", E1000_TARC(0)},
310592a4d85Scc {"TDBAL(1)", E1000_TDBAL(1)}, {"TDBAH(1)", E1000_TDBAH(1)},
311592a4d85Scc {"TDLEN(1)", E1000_TDLEN(1)}, {"TDH(1)", E1000_TDH(1)},
312592a4d85Scc {"TDT(1)", E1000_TDT(1)}, {"TXDCTL(1)", E1000_TXDCTL(1)},
313592a4d85Scc {"TARC(1)", E1000_TARC(1)}, {"ALGNERRC", E1000_ALGNERRC},
3144914a7d0Syy {"RXERRC", E1000_RXERRC}, {"MPC", E1000_MPC},
3154914a7d0Syy {"SCC", E1000_SCC}, {"ECOL", E1000_ECOL},
3164914a7d0Syy {"MCC", E1000_MCC}, {"LATECOL", E1000_LATECOL},
3174914a7d0Syy {"COLC", E1000_COLC}, {"DC", E1000_DC},
3184914a7d0Syy {"TNCRS", E1000_TNCRS}, {"SEC", E1000_SEC},
3194914a7d0Syy {"CEXTERR", E1000_CEXTERR}, {"RLEC", E1000_RLEC},
3204914a7d0Syy {"XONRXC", E1000_XONRXC}, {"XONTXC", E1000_XONTXC},
3214914a7d0Syy {"XOFFRXC", E1000_XOFFRXC}, {"XOFFTXC", E1000_XOFFTXC},
3224914a7d0Syy {"FCRUC", E1000_FCRUC}, {"PRC64", E1000_PRC64},
3234914a7d0Syy {"PRC127", E1000_PRC127}, {"PRC255", E1000_PRC255},
3244914a7d0Syy {"PRC511", E1000_PRC511}, {"PRC1023", E1000_PRC1023},
3254914a7d0Syy {"PRC1522", E1000_PRC1522}, {"GPRC", E1000_GPRC},
3264914a7d0Syy {"BPRC", E1000_BPRC}, {"MPRC", E1000_MPRC},
3274914a7d0Syy {"GPTC", E1000_GPTC}, {"GORCL", E1000_GORCL},
3284914a7d0Syy {"GORCH", E1000_GORCH}, {"GOTCL", E1000_GOTCL},
3294914a7d0Syy {"GOTCH", E1000_GOTCH}, {"RNBC", E1000_RNBC},
3304914a7d0Syy {"RUC", E1000_RUC}, {"RFC", E1000_RFC},
3314914a7d0Syy {"ROC", E1000_ROC}, {"RJC", E1000_RJC},
3324914a7d0Syy {"MGTPRC", E1000_MGTPRC}, {"MGTPDC", E1000_MGTPDC},
3334914a7d0Syy {"MGTPTC", E1000_MGTPTC}, {"TORL", E1000_TORL},
3344914a7d0Syy {"TORH", E1000_TORH}, {"TOTL", E1000_TOTL},
3354914a7d0Syy {"TOTH", E1000_TOTH}, {"TPR", E1000_TPR},
3364914a7d0Syy {"TPT", E1000_TPT}, {"PTC64", E1000_PTC64},
3374914a7d0Syy {"PTC127", E1000_PTC127}, {"PTC255", E1000_PTC255},
3384914a7d0Syy {"PTC511", E1000_PTC511}, {"PTC1023", E1000_PTC1023},
3394914a7d0Syy {"PTC1522", E1000_PTC1522}, {"MPTC", E1000_MPTC},
3404914a7d0Syy {"BPTC", E1000_BPTC}, {"TSCTC", E1000_TSCTC},
3414914a7d0Syy {"TSCTFC", E1000_TSCTFC}, {"IAC", E1000_IAC},
3424914a7d0Syy {"ICRXPTC", E1000_ICRXPTC}, {"ICRXATC", E1000_ICRXATC},
3434914a7d0Syy {"ICTXPTC", E1000_ICTXPTC}, {"ICTXATC", E1000_ICTXATC},
3444914a7d0Syy {"ICTXQEC", E1000_ICTXQEC}, {"ICTXQMTC", E1000_ICTXQMTC},
3454914a7d0Syy {"ICRXDMTC", E1000_ICRXDMTC}, {"ICRXOC", E1000_ICRXOC},
3464914a7d0Syy {"RXCSUM", E1000_RXCSUM}, {"RFCTL", E1000_RFCTL},
3474914a7d0Syy {"WUC", E1000_WUC}, {"WUFC", E1000_WUFC},
3484914a7d0Syy {"WUS", E1000_WUS}, {"MRQC", E1000_MRQC},
3494914a7d0Syy {"MANC", E1000_MANC}, {"IPAV", E1000_IPAV},
3504914a7d0Syy {"MANC2H", E1000_MANC2H}, {"RSSIM", E1000_RSSIM},
3514914a7d0Syy {"RSSIR", E1000_RSSIR}, {"WUPL", E1000_WUPL},
3524914a7d0Syy {"GCR", E1000_GCR}, {"GSCL_1", E1000_GSCL_1},
3534914a7d0Syy {"GSCL_2", E1000_GSCL_2}, {"GSCL_3", E1000_GSCL_3},
3544914a7d0Syy {"GSCL_4", E1000_GSCL_4}, {"FACTPS", E1000_FACTPS},
3554914a7d0Syy {"FWSM", E1000_FWSM},
3564914a7d0Syy };
3574914a7d0Syy
3584914a7d0Syy e1000g_log(Adapter, CE_CONT, "Begin MAC dump\n");
3594914a7d0Syy
3604914a7d0Syy for (i = 0; i < NUM_REGS; i++) {
3614914a7d0Syy e1000g_log(Adapter, CE_CONT,
3624914a7d0Syy "macreg %10s offset: 0x%x value: 0x%x\n",
3634914a7d0Syy macreg[i].name, macreg[i].offset,
3644914a7d0Syy e1000_read_reg(hw, macreg[i].offset));
3654914a7d0Syy }
3664914a7d0Syy }
3674914a7d0Syy
3684914a7d0Syy void
pciconfig_dump(void * instance)3694914a7d0Syy pciconfig_dump(void *instance)
3704914a7d0Syy {
3714914a7d0Syy struct e1000g *Adapter = (struct e1000g *)instance;
3724914a7d0Syy ddi_acc_handle_t handle;
3734914a7d0Syy uint8_t cap_ptr;
3744914a7d0Syy uint8_t next_ptr;
3754914a7d0Syy off_t offset;
3764914a7d0Syy
3774914a7d0Syy handle = Adapter->osdep.cfg_handle;
3784914a7d0Syy
3794914a7d0Syy e1000g_log(Adapter, CE_CONT, "Begin dump PCI config space\n");
3804914a7d0Syy
3814914a7d0Syy e1000g_log(Adapter, CE_CONT,
3824914a7d0Syy "PCI_CONF_VENID:\t0x%x\n",
3834914a7d0Syy pci_config_get16(handle, PCI_CONF_VENID));
3844914a7d0Syy e1000g_log(Adapter, CE_CONT,
3854914a7d0Syy "PCI_CONF_DEVID:\t0x%x\n",
3864914a7d0Syy pci_config_get16(handle, PCI_CONF_DEVID));
3874914a7d0Syy e1000g_log(Adapter, CE_CONT,
3884914a7d0Syy "PCI_CONF_COMMAND:\t0x%x\n",
3894914a7d0Syy pci_config_get16(handle, PCI_CONF_COMM));
3904914a7d0Syy e1000g_log(Adapter, CE_CONT,
3914914a7d0Syy "PCI_CONF_STATUS:\t0x%x\n",
3924914a7d0Syy pci_config_get16(handle, PCI_CONF_STAT));
3934914a7d0Syy e1000g_log(Adapter, CE_CONT,
3944914a7d0Syy "PCI_CONF_REVID:\t0x%x\n",
3954914a7d0Syy pci_config_get8(handle, PCI_CONF_REVID));
3964914a7d0Syy e1000g_log(Adapter, CE_CONT,
3974914a7d0Syy "PCI_CONF_PROG_CLASS:\t0x%x\n",
3984914a7d0Syy pci_config_get8(handle, PCI_CONF_PROGCLASS));
3994914a7d0Syy e1000g_log(Adapter, CE_CONT,
4004914a7d0Syy "PCI_CONF_SUB_CLASS:\t0x%x\n",
4014914a7d0Syy pci_config_get8(handle, PCI_CONF_SUBCLASS));
4024914a7d0Syy e1000g_log(Adapter, CE_CONT,
4034914a7d0Syy "PCI_CONF_BAS_CLASS:\t0x%x\n",
4044914a7d0Syy pci_config_get8(handle, PCI_CONF_BASCLASS));
4054914a7d0Syy e1000g_log(Adapter, CE_CONT,
4064914a7d0Syy "PCI_CONF_CACHE_LINESZ:\t0x%x\n",
4074914a7d0Syy pci_config_get8(handle, PCI_CONF_CACHE_LINESZ));
4084914a7d0Syy e1000g_log(Adapter, CE_CONT,
4094914a7d0Syy "PCI_CONF_LATENCY_TIMER:\t0x%x\n",
4104914a7d0Syy pci_config_get8(handle, PCI_CONF_LATENCY_TIMER));
4114914a7d0Syy e1000g_log(Adapter, CE_CONT,
4124914a7d0Syy "PCI_CONF_HEADER_TYPE:\t0x%x\n",
4134914a7d0Syy pci_config_get8(handle, PCI_CONF_HEADER));
4144914a7d0Syy e1000g_log(Adapter, CE_CONT,
4154914a7d0Syy "PCI_CONF_BIST:\t0x%x\n",
4164914a7d0Syy pci_config_get8(handle, PCI_CONF_BIST));
417592a4d85Scc
418592a4d85Scc pciconfig_bar(Adapter, PCI_CONF_BASE0, "PCI_CONF_BASE0");
419592a4d85Scc pciconfig_bar(Adapter, PCI_CONF_BASE1, "PCI_CONF_BASE1");
420592a4d85Scc pciconfig_bar(Adapter, PCI_CONF_BASE2, "PCI_CONF_BASE2");
421592a4d85Scc pciconfig_bar(Adapter, PCI_CONF_BASE3, "PCI_CONF_BASE3");
422592a4d85Scc pciconfig_bar(Adapter, PCI_CONF_BASE4, "PCI_CONF_BASE4");
423592a4d85Scc pciconfig_bar(Adapter, PCI_CONF_BASE5, "PCI_CONF_BASE5");
424592a4d85Scc
4254914a7d0Syy e1000g_log(Adapter, CE_CONT,
4264914a7d0Syy "PCI_CONF_CIS:\t0x%x\n",
4274914a7d0Syy pci_config_get32(handle, PCI_CONF_CIS));
4284914a7d0Syy e1000g_log(Adapter, CE_CONT,
4294914a7d0Syy "PCI_CONF_SUBVENID:\t0x%x\n",
4304914a7d0Syy pci_config_get16(handle, PCI_CONF_SUBVENID));
4314914a7d0Syy e1000g_log(Adapter, CE_CONT,
4324914a7d0Syy "PCI_CONF_SUBSYSID:\t0x%x\n",
4334914a7d0Syy pci_config_get16(handle, PCI_CONF_SUBSYSID));
4344914a7d0Syy e1000g_log(Adapter, CE_CONT,
4354914a7d0Syy "PCI_CONF_ROM:\t0x%x\n",
4364914a7d0Syy pci_config_get32(handle, PCI_CONF_ROM));
4374914a7d0Syy
4384914a7d0Syy cap_ptr = pci_config_get8(handle, PCI_CONF_CAP_PTR);
4394914a7d0Syy
4404914a7d0Syy e1000g_log(Adapter, CE_CONT,
4414914a7d0Syy "PCI_CONF_CAP_PTR:\t0x%x\n", cap_ptr);
4424914a7d0Syy e1000g_log(Adapter, CE_CONT,
4434914a7d0Syy "PCI_CONF_ILINE:\t0x%x\n",
4444914a7d0Syy pci_config_get8(handle, PCI_CONF_ILINE));
4454914a7d0Syy e1000g_log(Adapter, CE_CONT,
4464914a7d0Syy "PCI_CONF_IPIN:\t0x%x\n",
4474914a7d0Syy pci_config_get8(handle, PCI_CONF_IPIN));
4484914a7d0Syy e1000g_log(Adapter, CE_CONT,
4494914a7d0Syy "PCI_CONF_MIN_G:\t0x%x\n",
4504914a7d0Syy pci_config_get8(handle, PCI_CONF_MIN_G));
4514914a7d0Syy e1000g_log(Adapter, CE_CONT,
4524914a7d0Syy "PCI_CONF_MAX_L:\t0x%x\n",
4534914a7d0Syy pci_config_get8(handle, PCI_CONF_MAX_L));
4544914a7d0Syy
4554914a7d0Syy /* Power Management */
4564914a7d0Syy offset = cap_ptr;
4574914a7d0Syy
4584914a7d0Syy e1000g_log(Adapter, CE_CONT,
4594914a7d0Syy "PCI_PM_CAP_ID:\t0x%x\n",
4604914a7d0Syy pci_config_get8(handle, offset));
4614914a7d0Syy
4624914a7d0Syy next_ptr = pci_config_get8(handle, offset + 1);
4634914a7d0Syy
4644914a7d0Syy e1000g_log(Adapter, CE_CONT,
4654914a7d0Syy "PCI_PM_NEXT_PTR:\t0x%x\n", next_ptr);
4664914a7d0Syy e1000g_log(Adapter, CE_CONT,
4674914a7d0Syy "PCI_PM_CAP:\t0x%x\n",
4684914a7d0Syy pci_config_get16(handle, offset + PCI_PMCAP));
4694914a7d0Syy e1000g_log(Adapter, CE_CONT,
4704914a7d0Syy "PCI_PM_CSR:\t0x%x\n",
4714914a7d0Syy pci_config_get16(handle, offset + PCI_PMCSR));
4724914a7d0Syy e1000g_log(Adapter, CE_CONT,
4734914a7d0Syy "PCI_PM_CSR_BSE:\t0x%x\n",
4744914a7d0Syy pci_config_get8(handle, offset + PCI_PMCSR_BSE));
4754914a7d0Syy e1000g_log(Adapter, CE_CONT,
4764914a7d0Syy "PCI_PM_DATA:\t0x%x\n",
4774914a7d0Syy pci_config_get8(handle, offset + PCI_PMDATA));
4784914a7d0Syy
4794914a7d0Syy /* MSI Configuration */
4804914a7d0Syy offset = next_ptr;
4814914a7d0Syy
4824914a7d0Syy e1000g_log(Adapter, CE_CONT,
4834914a7d0Syy "PCI_MSI_CAP_ID:\t0x%x\n",
4844914a7d0Syy pci_config_get8(handle, offset));
4854914a7d0Syy
4864914a7d0Syy next_ptr = pci_config_get8(handle, offset + 1);
4874914a7d0Syy
4884914a7d0Syy e1000g_log(Adapter, CE_CONT,
4894914a7d0Syy "PCI_MSI_NEXT_PTR:\t0x%x\n", next_ptr);
4904914a7d0Syy e1000g_log(Adapter, CE_CONT,
4914914a7d0Syy "PCI_MSI_CTRL:\t0x%x\n",
4924914a7d0Syy pci_config_get16(handle, offset + PCI_MSI_CTRL));
4934914a7d0Syy e1000g_log(Adapter, CE_CONT,
4944914a7d0Syy "PCI_MSI_ADDR:\t0x%x\n",
4954914a7d0Syy pci_config_get32(handle, offset + PCI_MSI_ADDR_OFFSET));
4964914a7d0Syy e1000g_log(Adapter, CE_CONT,
4974914a7d0Syy "PCI_MSI_ADDR_HI:\t0x%x\n",
4984914a7d0Syy pci_config_get32(handle, offset + 0x8));
4994914a7d0Syy e1000g_log(Adapter, CE_CONT,
5004914a7d0Syy "PCI_MSI_DATA:\t0x%x\n",
5014914a7d0Syy pci_config_get16(handle, offset + 0xC));
5024914a7d0Syy
5034914a7d0Syy /* PCI Express Configuration */
5044914a7d0Syy offset = next_ptr;
5054914a7d0Syy
5064914a7d0Syy e1000g_log(Adapter, CE_CONT,
5074914a7d0Syy "PCIE_CAP_ID:\t0x%x\n",
5084914a7d0Syy pci_config_get8(handle, offset + PCIE_CAP_ID));
5094914a7d0Syy
5104914a7d0Syy next_ptr = pci_config_get8(handle, offset + PCIE_CAP_NEXT_PTR);
5114914a7d0Syy
5124914a7d0Syy e1000g_log(Adapter, CE_CONT,
5134914a7d0Syy "PCIE_CAP_NEXT_PTR:\t0x%x\n", next_ptr);
5144914a7d0Syy e1000g_log(Adapter, CE_CONT,
5154914a7d0Syy "PCIE_PCIECAP:\t0x%x\n",
5164914a7d0Syy pci_config_get16(handle, offset + PCIE_PCIECAP));
5174914a7d0Syy e1000g_log(Adapter, CE_CONT,
5184914a7d0Syy "PCIE_DEVCAP:\t0x%x\n",
5194914a7d0Syy pci_config_get32(handle, offset + PCIE_DEVCAP));
5204914a7d0Syy e1000g_log(Adapter, CE_CONT,
5214914a7d0Syy "PCIE_DEVCTL:\t0x%x\n",
5224914a7d0Syy pci_config_get16(handle, offset + PCIE_DEVCTL));
5234914a7d0Syy e1000g_log(Adapter, CE_CONT,
5244914a7d0Syy "PCIE_DEVSTS:\t0x%x\n",
5254914a7d0Syy pci_config_get16(handle, offset + PCIE_DEVSTS));
5264914a7d0Syy e1000g_log(Adapter, CE_CONT,
5274914a7d0Syy "PCIE_LINKCAP:\t0x%x\n",
5284914a7d0Syy pci_config_get32(handle, offset + PCIE_LINKCAP));
5294914a7d0Syy e1000g_log(Adapter, CE_CONT,
5304914a7d0Syy "PCIE_LINKCTL:\t0x%x\n",
5314914a7d0Syy pci_config_get16(handle, offset + PCIE_LINKCTL));
5324914a7d0Syy e1000g_log(Adapter, CE_CONT,
5334914a7d0Syy "PCIE_LINKSTS:\t0x%x\n",
5344914a7d0Syy pci_config_get16(handle, offset + PCIE_LINKSTS));
5354914a7d0Syy }
536592a4d85Scc
537592a4d85Scc void
pciconfig_bar(void * instance,uint32_t offset,char * name)538592a4d85Scc pciconfig_bar(void *instance, uint32_t offset, char *name)
539592a4d85Scc {
540592a4d85Scc struct e1000g *Adapter = (struct e1000g *)instance;
541592a4d85Scc ddi_acc_handle_t handle = Adapter->osdep.cfg_handle;
542592a4d85Scc uint32_t base = pci_config_get32(handle, offset);
543592a4d85Scc uint16_t comm = pci_config_get16(handle, PCI_CONF_COMM);
544592a4d85Scc uint32_t size; /* derived size of the region */
545592a4d85Scc uint32_t bits_comm; /* command word bits to disable */
546592a4d85Scc uint32_t size_mask; /* mask for size extraction */
547592a4d85Scc char tag_type[32]; /* tag to show memory vs. i/o */
548592a4d85Scc char tag_mem[32]; /* tag to show memory characteristiccs */
549592a4d85Scc
550592a4d85Scc /* base address zero, simple print */
551592a4d85Scc if (base == 0) {
552592a4d85Scc e1000g_log(Adapter, CE_CONT, "%s:\t0x%x\n", name, base);
553592a4d85Scc
554592a4d85Scc /* base address non-zero, get size */
555592a4d85Scc } else {
556592a4d85Scc /* i/o factors that decode from the base address */
557592a4d85Scc if (base & PCI_BASE_SPACE_IO) {
558592a4d85Scc bits_comm = PCI_COMM_IO;
559592a4d85Scc size_mask = PCI_BASE_IO_ADDR_M;
560fe62dec3SChen-Liang Xu (void) strcpy(tag_type, "i/o port size:");
561fe62dec3SChen-Liang Xu (void) strcpy(tag_mem, "");
562592a4d85Scc /* memory factors that decode from the base address */
563592a4d85Scc } else {
564592a4d85Scc bits_comm = PCI_COMM_MAE;
565592a4d85Scc size_mask = PCI_BASE_M_ADDR_M;
566fe62dec3SChen-Liang Xu (void) strcpy(tag_type, "memory size:");
567592a4d85Scc if (base & PCI_BASE_TYPE_ALL)
568fe62dec3SChen-Liang Xu (void) strcpy(tag_mem, "64bit ");
569592a4d85Scc else
570fe62dec3SChen-Liang Xu (void) strcpy(tag_mem, "32bit ");
571592a4d85Scc if (base & PCI_BASE_PREF_M)
572fe62dec3SChen-Liang Xu (void) strcat(tag_mem, "prefetchable");
573592a4d85Scc else
574fe62dec3SChen-Liang Xu (void) strcat(tag_mem, "non-prefetchable");
575592a4d85Scc }
576592a4d85Scc
577592a4d85Scc /* disable memory decode */
578592a4d85Scc pci_config_put16(handle, PCI_CONF_COMM, (comm & ~bits_comm));
579592a4d85Scc
580592a4d85Scc /* write to base register */
581592a4d85Scc pci_config_put32(handle, offset, 0xffffffff);
582592a4d85Scc
583592a4d85Scc /* read back & compute size */
584592a4d85Scc size = pci_config_get32(handle, offset);
585592a4d85Scc size &= size_mask;
586592a4d85Scc size = (~size) + 1;
587592a4d85Scc
588592a4d85Scc /* restore base register */
589592a4d85Scc pci_config_put32(handle, offset, base);
590592a4d85Scc
591592a4d85Scc /* re-enable memory decode */
592592a4d85Scc pci_config_put16(handle, PCI_CONF_COMM, comm);
593592a4d85Scc
594592a4d85Scc /* print results */
595592a4d85Scc e1000g_log(Adapter, CE_CONT, "%s:\t0x%x %s 0x%x %s\n",
596592a4d85Scc name, base, tag_type, size, tag_mem);
597592a4d85Scc }
598592a4d85Scc }
599*caf05df5SMiles Xu, Sun Microsystems #endif /* E1000G_DEBUG */
600