1507c3241Smlf /* 2507c3241Smlf * CDDL HEADER START 3507c3241Smlf * 4507c3241Smlf * The contents of this file are subject to the terms of the 5*2d6eb4a5SToomas Soome * Common Development and Distribution License (the "License"). 6507c3241Smlf * You may not use this file except in compliance with the License. 7507c3241Smlf * 8507c3241Smlf * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9507c3241Smlf * or http://www.opensolaris.org/os/licensing. 10507c3241Smlf * See the License for the specific language governing permissions 11507c3241Smlf * and limitations under the License. 12507c3241Smlf * 13507c3241Smlf * When distributing Covered Code, include this CDDL HEADER in each 14507c3241Smlf * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15507c3241Smlf * If applicable, add the following below this CDDL HEADER, with the 16507c3241Smlf * fields enclosed by brackets "[]" replaced with your own identifying 17507c3241Smlf * information: Portions Copyright [yyyy] [name of copyright owner] 18507c3241Smlf * 19507c3241Smlf * CDDL HEADER END 20507c3241Smlf */ 21507c3241Smlf 22507c3241Smlf /* 23507c3241Smlf * Copyright 2004 Sun Microsystems, Inc. All rights reserved. 24507c3241Smlf * Use is subject to license terms. 25507c3241Smlf */ 26507c3241Smlf 27507c3241Smlf #ifndef _SIL3XXX_H 28507c3241Smlf #define _SIL3XXX_H 29507c3241Smlf 30507c3241Smlf #ifdef __cplusplus 31507c3241Smlf extern "C" { 32507c3241Smlf #endif 33507c3241Smlf 34507c3241Smlf /* 35507c3241Smlf * PCI IDs 36507c3241Smlf */ 37507c3241Smlf #define SILICON_IMAGE_VENDOR_ID 0x1095 38507c3241Smlf #define SIL3112_DEVICE_ID 0x3112 39507c3241Smlf #define SIL3114_DEVICE_ID 0x3114 40507c3241Smlf #define SIL3512_DEVICE_ID 0x3512 41507c3241Smlf 42507c3241Smlf /* Base Register 5 Indirect Address Offset */ 43507c3241Smlf 44507c3241Smlf #define PCI_CONF_BA5_IND_ADDRESS 0xc0 45507c3241Smlf #define PCI_CONF_BA5_IND_ACCESS 0xc4 46507c3241Smlf 47507c3241Smlf /* 48507c3241Smlf * FIS Configuration channel offsets 49507c3241Smlf * Sil3114 has 4 channels 50507c3241Smlf * Sil3112 has 2 channels 51507c3241Smlf * Sil3512 has 2 channels 52507c3241Smlf */ 53507c3241Smlf #define SFISCFG_0 0x14c /* SFISCfg Channel 0 */ 54507c3241Smlf #define SFISCFG_1 0x1cc /* SFISCfg Channel 1 */ 55507c3241Smlf #define SFISCFG_2 0x34c /* SFISCfg Channel 2 */ 56507c3241Smlf #define SFISCFG_3 0x3cc /* SFISCfg Channel 3 */ 57507c3241Smlf 58507c3241Smlf /* 59507c3241Smlf * FIFO count and contrl offsets for channel 0-4 60507c3241Smlf */ 61507c3241Smlf #define FIFO_CNTCTL_0 0x40 62507c3241Smlf #define FIFO_CNTCTL_1 0x44 63507c3241Smlf #define FIFO_CNTCTL_2 0x240 64507c3241Smlf #define FIFO_CNTCTL_3 0x244 65507c3241Smlf 66507c3241Smlf /* 67507c3241Smlf * Errata Sil-AN-0028-C (Sil3512 Rev 0.3) 68507c3241Smlf * Errata Sil-AN-0109-B2 (Sil3114 Rev 0.3) 69507c3241Smlf * To prevent erroneous ERR set for queued DMA transfers 70507c3241Smlf * greater then 8k, FIS reception for FIS0cfg needs to be set 71507c3241Smlf * to Accept FIS without Interlock 72507c3241Smlf * Default SFISCfg value of 0x10401555 in channel SFISCfg 73507c3241Smlf * register need to be changed to 0x10401554. 74507c3241Smlf */ 75507c3241Smlf #define SFISCFG_ERRATA 0x10401554 76507c3241Smlf 77507c3241Smlf 78507c3241Smlf #define PUT_BAR5_INDIRECT(handle, address, value) \ 79507c3241Smlf {\ 80507c3241Smlf pci_config_put32(handle, PCI_CONF_BA5_IND_ADDRESS, address); \ 81507c3241Smlf pci_config_put32(handle, PCI_CONF_BA5_IND_ACCESS, value); \ 82507c3241Smlf } 83507c3241Smlf 84507c3241Smlf #define GET_BAR5_INDIRECT(handle, address, rval) \ 85507c3241Smlf {\ 86507c3241Smlf pci_config_put32(handle, PCI_CONF_BA5_IND_ADDRESS, address); \ 87507c3241Smlf rval = pci_config_get32(handle, PCI_CONF_BA5_IND_ACCESS); \ 88507c3241Smlf } 89507c3241Smlf 90507c3241Smlf uint_t sil3xxx_init_controller(dev_info_t *, ushort_t, ushort_t); 91507c3241Smlf 92507c3241Smlf #ifdef __cplusplus 93507c3241Smlf } 94507c3241Smlf #endif 95507c3241Smlf 96507c3241Smlf #endif /* _SIL3XXX_H */ 97