1*618f2068SAndy Fiddaman# Chelsio T6 Factory Default configuration file. 2*618f2068SAndy Fiddaman# 3*618f2068SAndy Fiddaman# Copyright (C) 2014-2015 Chelsio Communications. All rights reserved. 4*618f2068SAndy Fiddaman# 5*618f2068SAndy Fiddaman# DO NOT MODIFY THIS FILE UNDER ANY CIRCUMSTANCES. MODIFICATION OF THIS FILE 6*618f2068SAndy Fiddaman# WILL RESULT IN A NON-FUNCTIONAL ADAPTER AND MAY RESULT IN PHYSICAL DAMAGE 7*618f2068SAndy Fiddaman# TO ADAPTERS. 8*618f2068SAndy Fiddaman 9*618f2068SAndy Fiddaman 10*618f2068SAndy Fiddaman# This file provides the default, power-on configuration for 2-port T6-based 11*618f2068SAndy Fiddaman# adapters shipped from the factory. These defaults are designed to address 12*618f2068SAndy Fiddaman# the needs of the vast majority of Terminator customers. The basic idea is to 13*618f2068SAndy Fiddaman# have a default configuration which allows a customer to plug a Terminator 14*618f2068SAndy Fiddaman# adapter in and have it work regardless of OS, driver or application except in 15*618f2068SAndy Fiddaman# the most unusual and/or demanding customer applications. 16*618f2068SAndy Fiddaman# 17*618f2068SAndy Fiddaman# Many of the Terminator resources which are described by this configuration 18*618f2068SAndy Fiddaman# are finite. This requires balancing the configuration/operation needs of 19*618f2068SAndy Fiddaman# device drivers across OSes and a large number of customer application. 20*618f2068SAndy Fiddaman# 21*618f2068SAndy Fiddaman# Some of the more important resources to allocate and their constaints are: 22*618f2068SAndy Fiddaman# 1. Virtual Interfaces: 256. 23*618f2068SAndy Fiddaman# 2. Ingress Queues with Free Lists: 1024. 24*618f2068SAndy Fiddaman# 3. Egress Queues: 128K. 25*618f2068SAndy Fiddaman# 4. MSI-X Vectors: 1088. 26*618f2068SAndy Fiddaman# 5. Multi-Port Support (MPS) TCAM: 336 entries to support MAC destination 27*618f2068SAndy Fiddaman# address matching on Ingress Packets. 28*618f2068SAndy Fiddaman# 29*618f2068SAndy Fiddaman# Some of the important OS/Driver resource needs are: 30*618f2068SAndy Fiddaman# 6. Some OS Drivers will manage all resources through a single Physical 31*618f2068SAndy Fiddaman# Function (currently PF4 but it could be any Physical Function). 32*618f2068SAndy Fiddaman# 7. Some OS Drivers will manage different ports and functions (NIC, 33*618f2068SAndy Fiddaman# storage, etc.) on different Physical Functions. For example, NIC 34*618f2068SAndy Fiddaman# functions for ports 0-1 on PF0-1, FCoE on PF4, iSCSI on PF5, etc. 35*618f2068SAndy Fiddaman# 36*618f2068SAndy Fiddaman# Some of the customer application needs which need to be accommodated: 37*618f2068SAndy Fiddaman# 8. Some customers will want to support large CPU count systems with 38*618f2068SAndy Fiddaman# good scaling. Thus, we'll need to accommodate a number of 39*618f2068SAndy Fiddaman# Ingress Queues and MSI-X Vectors to allow up to some number of CPUs 40*618f2068SAndy Fiddaman# to be involved per port and per application function. For example, 41*618f2068SAndy Fiddaman# in the case where all ports and application functions will be 42*618f2068SAndy Fiddaman# managed via a single Unified PF and we want to accommodate scaling up 43*618f2068SAndy Fiddaman# to 8 CPUs, we would want: 44*618f2068SAndy Fiddaman# 45*618f2068SAndy Fiddaman# 2 ports * 46*618f2068SAndy Fiddaman# 3 application functions (NIC, FCoE, iSCSI) per port * 47*618f2068SAndy Fiddaman# 16 Ingress Queue/MSI-X Vectors per application function 48*618f2068SAndy Fiddaman# 49*618f2068SAndy Fiddaman# for a total of 96 Ingress Queues and MSI-X Vectors on the Unified PF. 50*618f2068SAndy Fiddaman# (Plus a few for Firmware Event Queues, etc.) 51*618f2068SAndy Fiddaman# 52*618f2068SAndy Fiddaman# 9. Some customers will want to use PCI-E SR-IOV Capability to allow Virtual 53*618f2068SAndy Fiddaman# Machines to directly access T6 functionality via SR-IOV Virtual Functions 54*618f2068SAndy Fiddaman# and "PCI Device Passthrough" -- this is especially true for the NIC 55*618f2068SAndy Fiddaman# application functionality. 56*618f2068SAndy Fiddaman# 57*618f2068SAndy Fiddaman 58*618f2068SAndy Fiddaman 59*618f2068SAndy Fiddaman# Global configuration settings. 60*618f2068SAndy Fiddaman# 61*618f2068SAndy Fiddaman[global] 62*618f2068SAndy Fiddaman rss_glb_config_mode = basicvirtual 63*618f2068SAndy Fiddaman rss_glb_config_options = tnlmapen,hashtoeplitz,tnlalllkp 64*618f2068SAndy Fiddaman 65*618f2068SAndy Fiddaman # PL_TIMEOUT register 66*618f2068SAndy Fiddaman pl_timeout_value = 200 # the timeout value in units of us 67*618f2068SAndy Fiddaman 68*618f2068SAndy Fiddaman # The following Scatter Gather Engine (SGE) settings assume a 4KB Host 69*618f2068SAndy Fiddaman # Page Size and a 64B L1 Cache Line Size. It programs the 70*618f2068SAndy Fiddaman # EgrStatusPageSize and IngPadBoundary to 64B and the PktShift to 2. 71*618f2068SAndy Fiddaman # If a Master PF Driver finds itself on a machine with different 72*618f2068SAndy Fiddaman # parameters, then the Master PF Driver is responsible for initializing 73*618f2068SAndy Fiddaman # these parameters to appropriate values. 74*618f2068SAndy Fiddaman # 75*618f2068SAndy Fiddaman # Notes: 76*618f2068SAndy Fiddaman # 1. The Free List Buffer Sizes below are raw and the firmware will 77*618f2068SAndy Fiddaman # round them up to the Ingress Padding Boundary. 78*618f2068SAndy Fiddaman # 2. The SGE Timer Values below are expressed below in microseconds. 79*618f2068SAndy Fiddaman # The firmware will convert these values to Core Clock Ticks when 80*618f2068SAndy Fiddaman # it processes the configuration parameters. 81*618f2068SAndy Fiddaman # 82*618f2068SAndy Fiddaman reg[0x1008] = 0x40800/0x21c70 # SGE_CONTROL 83*618f2068SAndy Fiddaman reg[0x100c] = 0x22222222 # SGE_HOST_PAGE_SIZE 84*618f2068SAndy Fiddaman reg[0x10a0] = 0x01040810 # SGE_INGRESS_RX_THRESHOLD 85*618f2068SAndy Fiddaman reg[0x1044] = 4096 # SGE_FL_BUFFER_SIZE0 86*618f2068SAndy Fiddaman reg[0x1048] = 65536 # SGE_FL_BUFFER_SIZE1 87*618f2068SAndy Fiddaman reg[0x104c] = 1536 # SGE_FL_BUFFER_SIZE2 88*618f2068SAndy Fiddaman reg[0x1050] = 9024 # SGE_FL_BUFFER_SIZE3 89*618f2068SAndy Fiddaman reg[0x1054] = 9216 # SGE_FL_BUFFER_SIZE4 90*618f2068SAndy Fiddaman reg[0x1058] = 2048 # SGE_FL_BUFFER_SIZE5 91*618f2068SAndy Fiddaman reg[0x105c] = 128 # SGE_FL_BUFFER_SIZE6 92*618f2068SAndy Fiddaman reg[0x1060] = 8192 # SGE_FL_BUFFER_SIZE7 93*618f2068SAndy Fiddaman reg[0x1064] = 16384 # SGE_FL_BUFFER_SIZE8 94*618f2068SAndy Fiddaman 95*618f2068SAndy Fiddaman sge_timer_value = 5, 10, 20, 50, 100, 200 # SGE_TIMER_VALUE* in usecs 96*618f2068SAndy Fiddaman reg[0x10c4] = 0x20000000/0x20000000 # GK_CONTROL, enable 5th thread 97*618f2068SAndy Fiddaman 98*618f2068SAndy Fiddaman # Set the SGE Doorbell Queue Timer "tick" to 50us and initialize 99*618f2068SAndy Fiddaman # the Timer Table to a default set of values (which are multiples 100*618f2068SAndy Fiddaman # of the Timer Tick). Note that the set of Tick Multipliers are 101*618f2068SAndy Fiddaman # NOT sorted. The Host Drivers are expected to pick amongst them 102*618f2068SAndy Fiddaman # for (Tick * Multiplier[i]) values which most closely match the Host 103*618f2068SAndy Fiddaman # Drivers' needs. Also, most Host Drivers will be default start 104*618f2068SAndy Fiddaman # start with (Tick * Multiplier[0]), so this gives us some flexibility 105*618f2068SAndy Fiddaman # in terms of picking a Tick and a default Multiplier somewhere in 106*618f2068SAndy Fiddaman # the middle of the achievable set of (Tick * Multiplier[i]) values. 107*618f2068SAndy Fiddaman # Thus, the below select for 150us by this default. 108*618f2068SAndy Fiddaman # 109*618f2068SAndy Fiddaman sge_dbq_timertick = 50 110*618f2068SAndy Fiddaman sge_dbq_timer = 3, 2, 1, 5, 7, 9, 12, 16 111*618f2068SAndy Fiddaman 112*618f2068SAndy Fiddaman # enable TP_OUT_CONFIG.IPIDSPLITMODE 113*618f2068SAndy Fiddaman # Set TP_OUT_CONFIG.CCplAckMode to get srtt/rttvar 114*618f2068SAndy Fiddaman reg[0x7d04] = 0x00012000/0x00012000 115*618f2068SAndy Fiddaman 116*618f2068SAndy Fiddaman reg[0x7dc0] = 0x0e2f8849 # TP_SHIFT_CNT 117*618f2068SAndy Fiddaman 118*618f2068SAndy Fiddaman #Tick granularities in kbps 119*618f2068SAndy Fiddaman tsch_ticks = 100000, 10000, 1000, 10 120*618f2068SAndy Fiddaman 121*618f2068SAndy Fiddaman # TP_VLAN_PRI_MAP to select filter tuples and enable ServerSram 122*618f2068SAndy Fiddaman # filter control: compact, fcoemask 123*618f2068SAndy Fiddaman # server sram : srvrsram 124*618f2068SAndy Fiddaman # filter tuples : fragmentation, mpshittype, macmatch, ethertype, 125*618f2068SAndy Fiddaman # protocol, tos, vlan, vnic_id, port, fcoe 126*618f2068SAndy Fiddaman # valid filterModes are described the Terminator 5 Data Book 127*618f2068SAndy Fiddaman # vnicMode = pf_vf #default. Other values are outer_vlan, encapsulation 128*618f2068SAndy Fiddaman filterMode = fcoemask, srvrsram, fragmentation, mpshittype, protocol, vlan, port, fcoe 129*618f2068SAndy Fiddaman 130*618f2068SAndy Fiddaman # filter tuples enforced in LE active region (equal to or subset of filterMode) 131*618f2068SAndy Fiddaman filterMask = protocol, fcoe 132*618f2068SAndy Fiddaman 133*618f2068SAndy Fiddaman # Percentage of dynamic memory (in either the EDRAM or external MEM) 134*618f2068SAndy Fiddaman # to use for TP RX payload 135*618f2068SAndy Fiddaman tp_pmrx = 30 136*618f2068SAndy Fiddaman 137*618f2068SAndy Fiddaman # TP RX payload page size 138*618f2068SAndy Fiddaman tp_pmrx_pagesize = 64K 139*618f2068SAndy Fiddaman 140*618f2068SAndy Fiddaman # TP number of RX channels 141*618f2068SAndy Fiddaman tp_nrxch = 0 # 0 (auto) = 1 142*618f2068SAndy Fiddaman 143*618f2068SAndy Fiddaman # Percentage of dynamic memory (in either the EDRAM or external MEM) 144*618f2068SAndy Fiddaman # to use for TP TX payload 145*618f2068SAndy Fiddaman tp_pmtx = 50 146*618f2068SAndy Fiddaman 147*618f2068SAndy Fiddaman # TP TX payload page size 148*618f2068SAndy Fiddaman tp_pmtx_pagesize = 64K 149*618f2068SAndy Fiddaman 150*618f2068SAndy Fiddaman # TP number of TX channels 151*618f2068SAndy Fiddaman tp_ntxch = 0 # 0 (auto) = equal number of ports 152*618f2068SAndy Fiddaman 153*618f2068SAndy Fiddaman # TP OFLD MTUs 154*618f2068SAndy Fiddaman tp_mtus = 88, 256, 512, 576, 808, 1024, 1280, 1488, 1500, 2002, 2048, 4096, 4352, 8192, 9000, 9600 155*618f2068SAndy Fiddaman 156*618f2068SAndy Fiddaman # enable TP_OUT_CONFIG.IPIDSPLITMODE and CRXPKTENC 157*618f2068SAndy Fiddaman reg[0x7d04] = 0x00010008/0x00010008 158*618f2068SAndy Fiddaman 159*618f2068SAndy Fiddaman # TP_GLOBAL_CONFIG 160*618f2068SAndy Fiddaman reg[0x7d08] = 0x00000800/0x00000800 # set IssFromCplEnable 161*618f2068SAndy Fiddaman 162*618f2068SAndy Fiddaman # TP_PC_CONFIG 163*618f2068SAndy Fiddaman reg[0x7d48] = 0x00000000/0x00000400 # clear EnableFLMError 164*618f2068SAndy Fiddaman 165*618f2068SAndy Fiddaman # TP_PARA_REG0 166*618f2068SAndy Fiddaman reg[0x7d60] = 0x06000000/0x07000000 # set InitCWND to 6 167*618f2068SAndy Fiddaman 168*618f2068SAndy Fiddaman # ULPRX iSCSI Page Sizes 169*618f2068SAndy Fiddaman reg[0x19168] = 0x04020100 # 64K, 16K, 8K and 4K 170*618f2068SAndy Fiddaman 171*618f2068SAndy Fiddaman # LE_DB_CONFIG 172*618f2068SAndy Fiddaman reg[0x19c04] = 0x00000000/0x00440000 # LE Server SRAM disabled 173*618f2068SAndy Fiddaman # LE IPv4 compression disabled 174*618f2068SAndy Fiddaman # LE_DB_HASH_CONFIG 175*618f2068SAndy Fiddaman reg[0x19c28] = 0x00800000/0x01f00000 # LE Hash bucket size 8, 176*618f2068SAndy Fiddaman 177*618f2068SAndy Fiddaman # ULP_TX_CONFIG 178*618f2068SAndy Fiddaman reg[0x8dc0] = 0x00000104/0x00000104 # Enable ITT on PI err 179*618f2068SAndy Fiddaman # Enable more error msg for ... 180*618f2068SAndy Fiddaman # TPT error. 181*618f2068SAndy Fiddaman 182*618f2068SAndy Fiddaman # ULP_RX_MISC_FEATURE_ENABLE 183*618f2068SAndy Fiddaman #reg[0x1925c] = 0x01003400/0x01003400 # iscsi tag pi bit 184*618f2068SAndy Fiddaman # Enable offset decrement after ... 185*618f2068SAndy Fiddaman # PI extraction and before DDP 186*618f2068SAndy Fiddaman # ulp insert pi source info in DIF 187*618f2068SAndy Fiddaman # iscsi_eff_offset_en 188*618f2068SAndy Fiddaman 189*618f2068SAndy Fiddaman #Enable iscsi completion moderation feature 190*618f2068SAndy Fiddaman reg[0x1925c] = 0x000041c0/0x000031c0 # Enable offset decrement after 191*618f2068SAndy Fiddaman # PI extraction and before DDP. 192*618f2068SAndy Fiddaman # ulp insert pi source info in 193*618f2068SAndy Fiddaman # DIF. 194*618f2068SAndy Fiddaman # Enable iscsi hdr cmd mode. 195*618f2068SAndy Fiddaman # iscsi force cmd mode. 196*618f2068SAndy Fiddaman # Enable iscsi cmp mode. 197*618f2068SAndy Fiddaman # MC configuration 198*618f2068SAndy Fiddaman #mc_mode_brc[0] = 1 # mc0 - 1: enable BRC, 0: enable RBC, 2: enable BRBC 199*618f2068SAndy Fiddaman 200*618f2068SAndy Fiddaman # HMA configuration 201*618f2068SAndy Fiddaman hma_size = 92 # Size (in MBs) of host memory expected 202*618f2068SAndy Fiddaman hma_regions = stag,pbl,rq # What all regions to place in host memory 203*618f2068SAndy Fiddaman 204*618f2068SAndy Fiddaman #enable bottleneck-bw congestion control mode 205*618f2068SAndy Fiddaman #ofld_flags = 4 206*618f2068SAndy Fiddaman 207*618f2068SAndy Fiddaman# Some "definitions" to make the rest of this a bit more readable. We support 208*618f2068SAndy Fiddaman# 4 ports, 3 functions (NIC, FCoE and iSCSI), scaling up to 8 "CPU Queue Sets" 209*618f2068SAndy Fiddaman# per function per port ... 210*618f2068SAndy Fiddaman# 211*618f2068SAndy Fiddaman# NMSIX = 1088 # available MSI-X Vectors 212*618f2068SAndy Fiddaman# NVI = 256 # available Virtual Interfaces 213*618f2068SAndy Fiddaman# NMPSTCAM = 336 # MPS TCAM entries 214*618f2068SAndy Fiddaman# 215*618f2068SAndy Fiddaman# NPORTS = 2 # ports 216*618f2068SAndy Fiddaman# NCPUS = 16 # CPUs we want to support scalably 217*618f2068SAndy Fiddaman# NFUNCS = 3 # functions per port (NIC, FCoE, iSCSI) 218*618f2068SAndy Fiddaman 219*618f2068SAndy Fiddaman# Breakdown of Virtual Interface/Queue/Interrupt resources for the "Unified 220*618f2068SAndy Fiddaman# PF" which many OS Drivers will use to manage most or all functions. 221*618f2068SAndy Fiddaman# 222*618f2068SAndy Fiddaman# Each Ingress Queue can use one MSI-X interrupt but some Ingress Queues can 223*618f2068SAndy Fiddaman# use Forwarded Interrupt Ingress Queues. For these latter, an Ingress Queue 224*618f2068SAndy Fiddaman# would be created and the Queue ID of a Forwarded Interrupt Ingress Queue 225*618f2068SAndy Fiddaman# will be specified as the "Ingress Queue Asynchronous Destination Index." 226*618f2068SAndy Fiddaman# Thus, the number of MSI-X Vectors assigned to the Unified PF will be less 227*618f2068SAndy Fiddaman# than or equal to the number of Ingress Queues ... 228*618f2068SAndy Fiddaman# 229*618f2068SAndy Fiddaman# NVI_NIC = 4 # NIC access to NPORTS 230*618f2068SAndy Fiddaman# NFLIQ_NIC = 32 # NIC Ingress Queues with Free Lists 231*618f2068SAndy Fiddaman# NETHCTRL_NIC = 32 # NIC Ethernet Control/TX Queues 232*618f2068SAndy Fiddaman# NEQ_NIC = 64 # NIC Egress Queues (FL, ETHCTRL/TX) 233*618f2068SAndy Fiddaman# NMPSTCAM_NIC = 16 # NIC MPS TCAM Entries (NPORTS*4) 234*618f2068SAndy Fiddaman# NMSIX_NIC = 32 # NIC MSI-X Interrupt Vectors (FLIQ) 235*618f2068SAndy Fiddaman# 236*618f2068SAndy Fiddaman# NVI_OFLD = 0 # Offload uses NIC function to access ports 237*618f2068SAndy Fiddaman# NFLIQ_OFLD = 16 # Offload Ingress Queues with Free Lists 238*618f2068SAndy Fiddaman# NETHCTRL_OFLD = 0 # Offload Ethernet Control/TX Queues 239*618f2068SAndy Fiddaman# NEQ_OFLD = 16 # Offload Egress Queues (FL) 240*618f2068SAndy Fiddaman# NMPSTCAM_OFLD = 0 # Offload MPS TCAM Entries (uses NIC's) 241*618f2068SAndy Fiddaman# NMSIX_OFLD = 16 # Offload MSI-X Interrupt Vectors (FLIQ) 242*618f2068SAndy Fiddaman# 243*618f2068SAndy Fiddaman# NVI_RDMA = 0 # RDMA uses NIC function to access ports 244*618f2068SAndy Fiddaman# NFLIQ_RDMA = 4 # RDMA Ingress Queues with Free Lists 245*618f2068SAndy Fiddaman# NETHCTRL_RDMA = 0 # RDMA Ethernet Control/TX Queues 246*618f2068SAndy Fiddaman# NEQ_RDMA = 4 # RDMA Egress Queues (FL) 247*618f2068SAndy Fiddaman# NMPSTCAM_RDMA = 0 # RDMA MPS TCAM Entries (uses NIC's) 248*618f2068SAndy Fiddaman# NMSIX_RDMA = 4 # RDMA MSI-X Interrupt Vectors (FLIQ) 249*618f2068SAndy Fiddaman# 250*618f2068SAndy Fiddaman# NEQ_WD = 128 # Wire Direct TX Queues and FLs 251*618f2068SAndy Fiddaman# NETHCTRL_WD = 64 # Wire Direct TX Queues 252*618f2068SAndy Fiddaman# NFLIQ_WD = 64 ` # Wire Direct Ingress Queues with Free Lists 253*618f2068SAndy Fiddaman# 254*618f2068SAndy Fiddaman# NVI_ISCSI = 4 # ISCSI access to NPORTS 255*618f2068SAndy Fiddaman# NFLIQ_ISCSI = 4 # ISCSI Ingress Queues with Free Lists 256*618f2068SAndy Fiddaman# NETHCTRL_ISCSI = 0 # ISCSI Ethernet Control/TX Queues 257*618f2068SAndy Fiddaman# NEQ_ISCSI = 4 # ISCSI Egress Queues (FL) 258*618f2068SAndy Fiddaman# NMPSTCAM_ISCSI = 4 # ISCSI MPS TCAM Entries (NPORTS) 259*618f2068SAndy Fiddaman# NMSIX_ISCSI = 4 # ISCSI MSI-X Interrupt Vectors (FLIQ) 260*618f2068SAndy Fiddaman# 261*618f2068SAndy Fiddaman# NVI_FCOE = 4 # FCOE access to NPORTS 262*618f2068SAndy Fiddaman# NFLIQ_FCOE = 34 # FCOE Ingress Queues with Free Lists 263*618f2068SAndy Fiddaman# NETHCTRL_FCOE = 32 # FCOE Ethernet Control/TX Queues 264*618f2068SAndy Fiddaman# NEQ_FCOE = 66 # FCOE Egress Queues (FL) 265*618f2068SAndy Fiddaman# NMPSTCAM_FCOE = 32 # FCOE MPS TCAM Entries (NPORTS) 266*618f2068SAndy Fiddaman# NMSIX_FCOE = 34 # FCOE MSI-X Interrupt Vectors (FLIQ) 267*618f2068SAndy Fiddaman 268*618f2068SAndy Fiddaman# Two extra Ingress Queues per function for Firmware Events and Forwarded 269*618f2068SAndy Fiddaman# Interrupts, and two extra interrupts per function for Firmware Events (or a 270*618f2068SAndy Fiddaman# Forwarded Interrupt Queue) and General Interrupts per function. 271*618f2068SAndy Fiddaman# 272*618f2068SAndy Fiddaman# NFLIQ_EXTRA = 6 # "extra" Ingress Queues 2*NFUNCS (Firmware and 273*618f2068SAndy Fiddaman# # Forwarded Interrupts 274*618f2068SAndy Fiddaman# NMSIX_EXTRA = 6 # extra interrupts 2*NFUNCS (Firmware and 275*618f2068SAndy Fiddaman# # General Interrupts 276*618f2068SAndy Fiddaman 277*618f2068SAndy Fiddaman# Microsoft HyperV resources. The HyperV Virtual Ingress Queues will have 278*618f2068SAndy Fiddaman# their interrupts forwarded to another set of Forwarded Interrupt Queues. 279*618f2068SAndy Fiddaman# 280*618f2068SAndy Fiddaman# NVI_HYPERV = 16 # VMs we want to support 281*618f2068SAndy Fiddaman# NVIIQ_HYPERV = 2 # Virtual Ingress Queues with Free Lists per VM 282*618f2068SAndy Fiddaman# NFLIQ_HYPERV = 40 # VIQs + NCPUS Forwarded Interrupt Queues 283*618f2068SAndy Fiddaman# NEQ_HYPERV = 32 # VIQs Free Lists 284*618f2068SAndy Fiddaman# NMPSTCAM_HYPERV = 16 # MPS TCAM Entries (NVI_HYPERV) 285*618f2068SAndy Fiddaman# NMSIX_HYPERV = 8 # NCPUS Forwarded Interrupt Queues 286*618f2068SAndy Fiddaman 287*618f2068SAndy Fiddaman# Adding all of the above Unified PF resource needs together: (NIC + OFLD + 288*618f2068SAndy Fiddaman# RDMA + ISCSI + FCOE + EXTRA + HYPERV) 289*618f2068SAndy Fiddaman# 290*618f2068SAndy Fiddaman# NVI_UNIFIED = 28 291*618f2068SAndy Fiddaman# NFLIQ_UNIFIED = 106 292*618f2068SAndy Fiddaman# NETHCTRL_UNIFIED = 32 293*618f2068SAndy Fiddaman# NEQ_UNIFIED = 124 294*618f2068SAndy Fiddaman# NMPSTCAM_UNIFIED = 40 295*618f2068SAndy Fiddaman# 296*618f2068SAndy Fiddaman# The sum of all the MSI-X resources above is 74 MSI-X Vectors but we'll round 297*618f2068SAndy Fiddaman# that up to 128 to make sure the Unified PF doesn't run out of resources. 298*618f2068SAndy Fiddaman# 299*618f2068SAndy Fiddaman# NMSIX_UNIFIED = 128 300*618f2068SAndy Fiddaman# 301*618f2068SAndy Fiddaman# The Storage PFs could need up to NPORTS*NCPUS + NMSIX_EXTRA MSI-X Vectors 302*618f2068SAndy Fiddaman# which is 34 but they're probably safe with 32. 303*618f2068SAndy Fiddaman# 304*618f2068SAndy Fiddaman# NMSIX_STORAGE = 32 305*618f2068SAndy Fiddaman 306*618f2068SAndy Fiddaman# Note: The UnifiedPF is PF4 which doesn't have any Virtual Functions 307*618f2068SAndy Fiddaman# associated with it. Thus, the MSI-X Vector allocations we give to the 308*618f2068SAndy Fiddaman# UnifiedPF aren't inherited by any Virtual Functions. As a result we can 309*618f2068SAndy Fiddaman# provision many more Virtual Functions than we can if the UnifiedPF were 310*618f2068SAndy Fiddaman# one of PF0-3. 311*618f2068SAndy Fiddaman# 312*618f2068SAndy Fiddaman 313*618f2068SAndy Fiddaman# All of the below PCI-E parameters are actually stored in various *_init.txt 314*618f2068SAndy Fiddaman# files. We include them below essentially as comments. 315*618f2068SAndy Fiddaman# 316*618f2068SAndy Fiddaman# For PF0-3 we assign 8 vectors each for NIC Ingress Queues of the associated 317*618f2068SAndy Fiddaman# ports 0-3. 318*618f2068SAndy Fiddaman# 319*618f2068SAndy Fiddaman# For PF4, the Unified PF, we give it an MSI-X Table Size as outlined above. 320*618f2068SAndy Fiddaman# 321*618f2068SAndy Fiddaman# For PF5-6 we assign enough MSI-X Vectors to support FCoE and iSCSI 322*618f2068SAndy Fiddaman# storage applications across all four possible ports. 323*618f2068SAndy Fiddaman# 324*618f2068SAndy Fiddaman# Additionally, since the UnifiedPF isn't one of the per-port Physical 325*618f2068SAndy Fiddaman# Functions, we give the UnifiedPF and the PF0-3 Physical Functions 326*618f2068SAndy Fiddaman# different PCI Device IDs which will allow Unified and Per-Port Drivers 327*618f2068SAndy Fiddaman# to directly select the type of Physical Function to which they wish to be 328*618f2068SAndy Fiddaman# attached. 329*618f2068SAndy Fiddaman# 330*618f2068SAndy Fiddaman# Note that the actual values used for the PCI-E Intelectual Property will be 331*618f2068SAndy Fiddaman# 1 less than those below since that's the way it "counts" things. For 332*618f2068SAndy Fiddaman# readability, we use the number we actually mean ... 333*618f2068SAndy Fiddaman# 334*618f2068SAndy Fiddaman# PF0_INT = 8 # NCPUS 335*618f2068SAndy Fiddaman# PF1_INT = 8 # NCPUS 336*618f2068SAndy Fiddaman# PF0_3_INT = 32 # PF0_INT + PF1_INT + PF2_INT + PF3_INT 337*618f2068SAndy Fiddaman# 338*618f2068SAndy Fiddaman# PF4_INT = 128 # NMSIX_UNIFIED 339*618f2068SAndy Fiddaman# PF5_INT = 32 # NMSIX_STORAGE 340*618f2068SAndy Fiddaman# PF6_INT = 32 # NMSIX_STORAGE 341*618f2068SAndy Fiddaman# PF7_INT = 0 # Nothing Assigned 342*618f2068SAndy Fiddaman# PF4_7_INT = 192 # PF4_INT + PF5_INT + PF6_INT + PF7_INT 343*618f2068SAndy Fiddaman# 344*618f2068SAndy Fiddaman# PF0_7_INT = 224 # PF0_3_INT + PF4_7_INT 345*618f2068SAndy Fiddaman# 346*618f2068SAndy Fiddaman# With the above we can get 17 VFs/PF0-3 (limited by 336 MPS TCAM entries) 347*618f2068SAndy Fiddaman# but we'll lower that to 16 to make our total 64 and a nice power of 2 ... 348*618f2068SAndy Fiddaman# 349*618f2068SAndy Fiddaman# NVF = 16 350*618f2068SAndy Fiddaman 351*618f2068SAndy Fiddaman 352*618f2068SAndy Fiddaman# For those OSes which manage different ports on different PFs, we need 353*618f2068SAndy Fiddaman# only enough resources to support a single port's NIC application functions 354*618f2068SAndy Fiddaman# on PF0-3. The below assumes that we're only doing NIC with NCPUS "Queue 355*618f2068SAndy Fiddaman# Sets" for ports 0-3. The FCoE and iSCSI functions for such OSes will be 356*618f2068SAndy Fiddaman# managed on the "storage PFs" (see below). 357*618f2068SAndy Fiddaman# 358*618f2068SAndy Fiddaman[function "0"] 359*618f2068SAndy Fiddaman nvf = 16 # NVF on this function 360*618f2068SAndy Fiddaman wx_caps = all # write/execute permissions for all commands 361*618f2068SAndy Fiddaman r_caps = all # read permissions for all commands 362*618f2068SAndy Fiddaman nvi = 1 # 1 port 363*618f2068SAndy Fiddaman niqflint = 8 # NCPUS "Queue Sets" 364*618f2068SAndy Fiddaman nethctrl = 8 # NCPUS "Queue Sets" 365*618f2068SAndy Fiddaman neq = 16 # niqflint + nethctrl Egress Queues 366*618f2068SAndy Fiddaman nexactf = 8 # number of exact MPSTCAM MAC filters 367*618f2068SAndy Fiddaman cmask = all # access to all channels 368*618f2068SAndy Fiddaman pmask = 0x1 # access to only one port 369*618f2068SAndy Fiddaman 370*618f2068SAndy Fiddaman 371*618f2068SAndy Fiddaman[function "1"] 372*618f2068SAndy Fiddaman nvf = 16 # NVF on this function 373*618f2068SAndy Fiddaman wx_caps = all # write/execute permissions for all commands 374*618f2068SAndy Fiddaman r_caps = all # read permissions for all commands 375*618f2068SAndy Fiddaman nvi = 1 # 1 port 376*618f2068SAndy Fiddaman niqflint = 8 # NCPUS "Queue Sets" 377*618f2068SAndy Fiddaman nethctrl = 8 # NCPUS "Queue Sets" 378*618f2068SAndy Fiddaman neq = 16 # niqflint + nethctrl Egress Queues 379*618f2068SAndy Fiddaman nexactf = 8 # number of exact MPSTCAM MAC filters 380*618f2068SAndy Fiddaman cmask = all # access to all channels 381*618f2068SAndy Fiddaman pmask = 0x2 # access to only one port 382*618f2068SAndy Fiddaman 383*618f2068SAndy Fiddaman[function "2"] 384*618f2068SAndy Fiddaman nvf = 16 # NVF on this function 385*618f2068SAndy Fiddaman wx_caps = all # write/execute permissions for all commands 386*618f2068SAndy Fiddaman r_caps = all # read permissions for all commands 387*618f2068SAndy Fiddaman nvi = 1 # 1 port 388*618f2068SAndy Fiddaman niqflint = 8 # NCPUS "Queue Sets" 389*618f2068SAndy Fiddaman nethctrl = 8 # NCPUS "Queue Sets" 390*618f2068SAndy Fiddaman neq = 16 # niqflint + nethctrl Egress Queues 391*618f2068SAndy Fiddaman nexactf = 8 # number of exact MPSTCAM MAC filters 392*618f2068SAndy Fiddaman cmask = all # access to all channels 393*618f2068SAndy Fiddaman pmask = 0x4 # access to only one port 394*618f2068SAndy Fiddaman 395*618f2068SAndy Fiddaman[function "3"] 396*618f2068SAndy Fiddaman nvf = 16 # NVF on this function 397*618f2068SAndy Fiddaman wx_caps = all # write/execute permissions for all commands 398*618f2068SAndy Fiddaman r_caps = all # read permissions for all commands 399*618f2068SAndy Fiddaman nvi = 1 # 1 port 400*618f2068SAndy Fiddaman niqflint = 8 # NCPUS "Queue Sets" 401*618f2068SAndy Fiddaman nethctrl = 8 # NCPUS "Queue Sets" 402*618f2068SAndy Fiddaman neq = 16 # niqflint + nethctrl Egress Queues 403*618f2068SAndy Fiddaman nexactf = 8 # number of exact MPSTCAM MAC filters 404*618f2068SAndy Fiddaman cmask = all # access to all channels 405*618f2068SAndy Fiddaman pmask = 0x8 # access to only one port 406*618f2068SAndy Fiddaman 407*618f2068SAndy Fiddaman 408*618f2068SAndy Fiddaman# Some OS Drivers manage all application functions for all ports via PF4. 409*618f2068SAndy Fiddaman# Thus we need to provide a large number of resources here. For Egress 410*618f2068SAndy Fiddaman# Queues we need to account for both TX Queues as well as Free List Queues 411*618f2068SAndy Fiddaman# (because the host is responsible for producing Free List Buffers for the 412*618f2068SAndy Fiddaman# hardware to consume). 413*618f2068SAndy Fiddaman# 414*618f2068SAndy Fiddaman[function "4"] 415*618f2068SAndy Fiddaman wx_caps = all # write/execute permissions for all commands 416*618f2068SAndy Fiddaman r_caps = all # read permissions for all commands 417*618f2068SAndy Fiddaman nvi = 28 # NVI_UNIFIED 418*618f2068SAndy Fiddaman niqflint = 218 # NFLIQ_UNIFIED + NLFIQ_WD + NFLIQ_CRYPTO (32) 419*618f2068SAndy Fiddaman nethctrl = 116 # NETHCTRL_UNIFIED + NETHCTRL_WD + ncrypto_lookaside 420*618f2068SAndy Fiddaman neq = 256 # NEQ_UNIFIED + NEQ_WD 421*618f2068SAndy Fiddaman nqpcq = 12288 422*618f2068SAndy Fiddaman nexactf = 40 # NMPSTCAM_UNIFIED 423*618f2068SAndy Fiddaman nrawf = 2 424*618f2068SAndy Fiddaman cmask = all # access to all channels 425*618f2068SAndy Fiddaman pmask = all # access to all four ports ... 426*618f2068SAndy Fiddaman nethofld = 1024 # number of user mode ethernet flow contexts 427*618f2068SAndy Fiddaman ncrypto_lookaside = 16 # Number of lookaside flow contexts 428*618f2068SAndy Fiddaman nclip = 320 # number of clip region entries 429*618f2068SAndy Fiddaman nfilter = 496 # number of filter region entries 430*618f2068SAndy Fiddaman nserver = 496 # number of server region entries 431*618f2068SAndy Fiddaman nhash = 12288 # number of hash region entries 432*618f2068SAndy Fiddaman nhpfilter = 64 # number of high priority filter region entries 433*618f2068SAndy Fiddaman protocol = nic_vm, ofld, rddp, rdmac, iscsi_initiator_pdu, iscsi_target_pdu, iscsi_t10dif, tlskeys, crypto_lookaside, ipsec_inline, nic_hashfilter, nic_ktls_ofld 434*618f2068SAndy Fiddaman tp_l2t = 3072 435*618f2068SAndy Fiddaman tp_ddp = 2 436*618f2068SAndy Fiddaman tp_ddp_iscsi = 2 437*618f2068SAndy Fiddaman tp_tls_key = 2 438*618f2068SAndy Fiddaman tp_tls_mxrxsize = 17408 # 16384 + 1024, governs max rx data, pm max xfer len, rx coalesce sizes 439*618f2068SAndy Fiddaman tp_stag = 2 440*618f2068SAndy Fiddaman tp_pbl = 7 441*618f2068SAndy Fiddaman tp_rq = 7 442*618f2068SAndy Fiddaman tp_srq = 128 443*618f2068SAndy Fiddaman 444*618f2068SAndy Fiddaman# We have FCoE and iSCSI storage functions on PF5 and PF6 each of which may 445*618f2068SAndy Fiddaman# need to have Virtual Interfaces on each of the four ports with up to NCPUS 446*618f2068SAndy Fiddaman# "Queue Sets" each. 447*618f2068SAndy Fiddaman# 448*618f2068SAndy Fiddaman[function "5"] 449*618f2068SAndy Fiddaman wx_caps = all # write/execute permissions for all commands 450*618f2068SAndy Fiddaman r_caps = all # read permissions for all commands 451*618f2068SAndy Fiddaman nvi = 4 # NPORTS 452*618f2068SAndy Fiddaman niqflint = 34 # NPORTS*NCPUS + NMSIX_EXTRA 453*618f2068SAndy Fiddaman nethctrl = 32 # NPORTS*NCPUS 454*618f2068SAndy Fiddaman neq = 64 # NPORTS*NCPUS * 2 (FL, ETHCTRL/TX) 455*618f2068SAndy Fiddaman nexactf = 16 # (NPORTS *(no of snmc grp + 1 hw mac) + 1 anmc grp)) rounded to 16. 456*618f2068SAndy Fiddaman cmask = all # access to all channels 457*618f2068SAndy Fiddaman pmask = all # access to all four ports ... 458*618f2068SAndy Fiddaman nserver = 16 459*618f2068SAndy Fiddaman nhash = 2048 460*618f2068SAndy Fiddaman tp_l2t = 1020 461*618f2068SAndy Fiddaman nclip = 64 462*618f2068SAndy Fiddaman protocol = iscsi_initiator_fofld 463*618f2068SAndy Fiddaman tp_ddp_iscsi = 2 464*618f2068SAndy Fiddaman iscsi_ntask = 2048 465*618f2068SAndy Fiddaman iscsi_nsess = 2048 466*618f2068SAndy Fiddaman iscsi_nconn_per_session = 1 467*618f2068SAndy Fiddaman iscsi_ninitiator_instance = 64 468*618f2068SAndy Fiddaman 469*618f2068SAndy Fiddaman 470*618f2068SAndy Fiddaman[function "6"] 471*618f2068SAndy Fiddaman wx_caps = all # write/execute permissions for all commands 472*618f2068SAndy Fiddaman r_caps = all # read permissions for all commands 473*618f2068SAndy Fiddaman nvi = 4 # NPORTS 474*618f2068SAndy Fiddaman niqflint = 34 # NPORTS*NCPUS + NMSIX_EXTRA 475*618f2068SAndy Fiddaman nethctrl = 32 # NPORTS*NCPUS 476*618f2068SAndy Fiddaman neq = 66 # NPORTS*NCPUS * 2 (FL, ETHCTRL/TX) + 2 (EXTRA) 477*618f2068SAndy Fiddaman nexactf = 32 # NPORTS + adding 28 exact entries for FCoE 478*618f2068SAndy Fiddaman # which is OK since < MIN(SUM PF0..3, PF4) 479*618f2068SAndy Fiddaman # and we never load PF0..3 and PF4 concurrently 480*618f2068SAndy Fiddaman cmask = all # access to all channels 481*618f2068SAndy Fiddaman pmask = all # access to all four ports ... 482*618f2068SAndy Fiddaman nhash = 2048 483*618f2068SAndy Fiddaman tp_l2t = 4 484*618f2068SAndy Fiddaman protocol = fcoe_initiator 485*618f2068SAndy Fiddaman tp_ddp = 1 486*618f2068SAndy Fiddaman fcoe_nfcf = 16 487*618f2068SAndy Fiddaman fcoe_nvnp = 32 488*618f2068SAndy Fiddaman fcoe_nssn = 1024 489*618f2068SAndy Fiddaman 490*618f2068SAndy Fiddaman 491*618f2068SAndy Fiddaman# The following function, 1023, is not an actual PCIE function but is used to 492*618f2068SAndy Fiddaman# configure and reserve firmware internal resources that come from the global 493*618f2068SAndy Fiddaman# resource pool. 494*618f2068SAndy Fiddaman# 495*618f2068SAndy Fiddaman[function "1023"] 496*618f2068SAndy Fiddaman wx_caps = all # write/execute permissions for all commands 497*618f2068SAndy Fiddaman r_caps = all # read permissions for all commands 498*618f2068SAndy Fiddaman nvi = 4 # NVI_UNIFIED 499*618f2068SAndy Fiddaman cmask = all # access to all channels 500*618f2068SAndy Fiddaman pmask = all # access to all four ports ... 501*618f2068SAndy Fiddaman nexactf = 8 # NPORTS + DCBX + 502*618f2068SAndy Fiddaman nfilter = 16 # number of filter region entries 503*618f2068SAndy Fiddaman 504*618f2068SAndy Fiddaman 505*618f2068SAndy Fiddaman# For Virtual functions, we only allow NIC functionality and we only allow 506*618f2068SAndy Fiddaman# access to one port (1 << PF). Note that because of limitations in the 507*618f2068SAndy Fiddaman# Scatter Gather Engine (SGE) hardware which checks writes to VF KDOORBELL 508*618f2068SAndy Fiddaman# and GTS registers, the number of Ingress and Egress Queues must be a power 509*618f2068SAndy Fiddaman# of 2. 510*618f2068SAndy Fiddaman# 511*618f2068SAndy Fiddaman[function "0/*"] # NVF 512*618f2068SAndy Fiddaman wx_caps = 0x82 # DMAQ | VF 513*618f2068SAndy Fiddaman r_caps = 0x86 # DMAQ | VF | PORT 514*618f2068SAndy Fiddaman nvi = 1 # 1 port 515*618f2068SAndy Fiddaman niqflint = 6 # 2 "Queue Sets" + NXIQ 516*618f2068SAndy Fiddaman nethctrl = 4 # 2 "Queue Sets" 517*618f2068SAndy Fiddaman neq = 8 # 2 "Queue Sets" * 2 518*618f2068SAndy Fiddaman nexactf = 4 519*618f2068SAndy Fiddaman cmask = all # access to all channels 520*618f2068SAndy Fiddaman pmask = 0x1 # access to only one port ... 521*618f2068SAndy Fiddaman 522*618f2068SAndy Fiddaman 523*618f2068SAndy Fiddaman[function "1/*"] # NVF 524*618f2068SAndy Fiddaman wx_caps = 0x82 # DMAQ | VF 525*618f2068SAndy Fiddaman r_caps = 0x86 # DMAQ | VF | PORT 526*618f2068SAndy Fiddaman nvi = 1 # 1 port 527*618f2068SAndy Fiddaman niqflint = 6 # 2 "Queue Sets" + NXIQ 528*618f2068SAndy Fiddaman nethctrl = 4 # 2 "Queue Sets" 529*618f2068SAndy Fiddaman neq = 8 # 2 "Queue Sets" * 2 530*618f2068SAndy Fiddaman nexactf = 4 531*618f2068SAndy Fiddaman cmask = all # access to all channels 532*618f2068SAndy Fiddaman pmask = 0x2 # access to only one port ... 533*618f2068SAndy Fiddaman 534*618f2068SAndy Fiddaman[function "2/*"] # NVF 535*618f2068SAndy Fiddaman wx_caps = 0x82 # DMAQ | VF 536*618f2068SAndy Fiddaman r_caps = 0x86 # DMAQ | VF | PORT 537*618f2068SAndy Fiddaman nvi = 1 # 1 port 538*618f2068SAndy Fiddaman niqflint = 6 # 2 "Queue Sets" + NXIQ 539*618f2068SAndy Fiddaman nethctrl = 4 # 2 "Queue Sets" 540*618f2068SAndy Fiddaman neq = 8 # 2 "Queue Sets" * 2 541*618f2068SAndy Fiddaman nexactf = 4 542*618f2068SAndy Fiddaman cmask = all # access to all channels 543*618f2068SAndy Fiddaman pmask = 0x1 # access to only one port ... 544*618f2068SAndy Fiddaman 545*618f2068SAndy Fiddaman 546*618f2068SAndy Fiddaman[function "3/*"] # NVF 547*618f2068SAndy Fiddaman wx_caps = 0x82 # DMAQ | VF 548*618f2068SAndy Fiddaman r_caps = 0x86 # DMAQ | VF | PORT 549*618f2068SAndy Fiddaman nvi = 1 # 1 port 550*618f2068SAndy Fiddaman niqflint = 6 # 2 "Queue Sets" + NXIQ 551*618f2068SAndy Fiddaman nethctrl = 4 # 2 "Queue Sets" 552*618f2068SAndy Fiddaman neq = 8 # 2 "Queue Sets" * 2 553*618f2068SAndy Fiddaman nexactf = 4 554*618f2068SAndy Fiddaman cmask = all # access to all channels 555*618f2068SAndy Fiddaman pmask = 0x2 # access to only one port ... 556*618f2068SAndy Fiddaman 557*618f2068SAndy Fiddaman# MPS features a 196608 bytes ingress buffer that is used for ingress buffering 558*618f2068SAndy Fiddaman# for packets from the wire as well as the loopback path of the L2 switch. The 559*618f2068SAndy Fiddaman# folling params control how the buffer memory is distributed and the L2 flow 560*618f2068SAndy Fiddaman# control settings: 561*618f2068SAndy Fiddaman# 562*618f2068SAndy Fiddaman# bg_mem: %-age of mem to use for port/buffer group 563*618f2068SAndy Fiddaman# lpbk_mem: %-age of port/bg mem to use for loopback 564*618f2068SAndy Fiddaman# hwm: high watermark; bytes available when starting to send pause 565*618f2068SAndy Fiddaman# frames (in units of 0.1 MTU) 566*618f2068SAndy Fiddaman# lwm: low watermark; bytes remaining when sending 'unpause' frame 567*618f2068SAndy Fiddaman# (in inuits of 0.1 MTU) 568*618f2068SAndy Fiddaman# dwm: minimum delta between high and low watermark (in units of 100 569*618f2068SAndy Fiddaman# Bytes) 570*618f2068SAndy Fiddaman# 571*618f2068SAndy Fiddaman[port "0"] 572*618f2068SAndy Fiddaman dcb = ppp, dcbx # configure for DCB PPP and enable DCBX offload 573*618f2068SAndy Fiddaman #bg_mem = 25 574*618f2068SAndy Fiddaman #lpbk_mem = 25 575*618f2068SAndy Fiddaman hwm = 60 576*618f2068SAndy Fiddaman lwm = 15 577*618f2068SAndy Fiddaman dwm = 30 578*618f2068SAndy Fiddaman dcb_app_tlv[0] = 0x8906, ethertype, 3 579*618f2068SAndy Fiddaman dcb_app_tlv[1] = 0x8914, ethertype, 3 580*618f2068SAndy Fiddaman dcb_app_tlv[2] = 3260, socketnum, 5 581*618f2068SAndy Fiddaman 582*618f2068SAndy Fiddaman[port "1"] 583*618f2068SAndy Fiddaman dcb = ppp, dcbx 584*618f2068SAndy Fiddaman #bg_mem = 25 585*618f2068SAndy Fiddaman #lpbk_mem = 25 586*618f2068SAndy Fiddaman hwm = 60 587*618f2068SAndy Fiddaman lwm = 15 588*618f2068SAndy Fiddaman dwm = 30 589*618f2068SAndy Fiddaman dcb_app_tlv[0] = 0x8906, ethertype, 3 590*618f2068SAndy Fiddaman dcb_app_tlv[1] = 0x8914, ethertype, 3 591*618f2068SAndy Fiddaman dcb_app_tlv[2] = 3260, socketnum, 5 592*618f2068SAndy Fiddaman 593*618f2068SAndy Fiddaman[fini] 594*618f2068SAndy Fiddaman version = 0x1425001d 595*618f2068SAndy Fiddaman checksum = 0xa1403d73 596*618f2068SAndy Fiddaman 597*618f2068SAndy Fiddaman# Total resources used by above allocations: 598*618f2068SAndy Fiddaman# Virtual Interfaces: 104 599*618f2068SAndy Fiddaman# Ingress Queues/w Free Lists and Interrupts: 526 600*618f2068SAndy Fiddaman# Egress Queues: 702 601*618f2068SAndy Fiddaman# MPS TCAM Entries: 336 602*618f2068SAndy Fiddaman# MSI-X Vectors: 736 603*618f2068SAndy Fiddaman# Virtual Functions: 64 604