1# Chelsio T6 Factory Default configuration file. 2# 3# Copyright (C) 2014-2015 Chelsio Communications. All rights reserved. 4# 5# DO NOT MODIFY THIS FILE UNDER ANY CIRCUMSTANCES. MODIFICATION OF THIS FILE 6# WILL RESULT IN A NON-FUNCTIONAL ADAPTER AND MAY RESULT IN PHYSICAL DAMAGE 7# TO ADAPTERS. 8 9 10# This file provides the default, power-on configuration for 2-port T6-based 11# adapters shipped from the factory. These defaults are designed to address 12# the needs of the vast majority of Terminator customers. The basic idea is to 13# have a default configuration which allows a customer to plug a Terminator 14# adapter in and have it work regardless of OS, driver or application except in 15# the most unusual and/or demanding customer applications. 16# 17# Many of the Terminator resources which are described by this configuration 18# are finite. This requires balancing the configuration/operation needs of 19# device drivers across OSes and a large number of customer application. 20# 21# Some of the more important resources to allocate and their constaints are: 22# 1. Virtual Interfaces: 256. 23# 2. Ingress Queues with Free Lists: 1024. 24# 3. Egress Queues: 128K. 25# 4. MSI-X Vectors: 1088. 26# 5. Multi-Port Support (MPS) TCAM: 336 entries to support MAC destination 27# address matching on Ingress Packets. 28# 29# Some of the important OS/Driver resource needs are: 30# 6. Some OS Drivers will manage all resources through a single Physical 31# Function (currently PF4 but it could be any Physical Function). 32# 7. Some OS Drivers will manage different ports and functions (NIC, 33# storage, etc.) on different Physical Functions. For example, NIC 34# functions for ports 0-1 on PF0-1, FCoE on PF4, iSCSI on PF5, etc. 35# 36# Some of the customer application needs which need to be accommodated: 37# 8. Some customers will want to support large CPU count systems with 38# good scaling. Thus, we'll need to accommodate a number of 39# Ingress Queues and MSI-X Vectors to allow up to some number of CPUs 40# to be involved per port and per application function. For example, 41# in the case where all ports and application functions will be 42# managed via a single Unified PF and we want to accommodate scaling up 43# to 8 CPUs, we would want: 44# 45# 2 ports * 46# 3 application functions (NIC, FCoE, iSCSI) per port * 47# 16 Ingress Queue/MSI-X Vectors per application function 48# 49# for a total of 96 Ingress Queues and MSI-X Vectors on the Unified PF. 50# (Plus a few for Firmware Event Queues, etc.) 51# 52# 9. Some customers will want to use PCI-E SR-IOV Capability to allow Virtual 53# Machines to directly access T6 functionality via SR-IOV Virtual Functions 54# and "PCI Device Passthrough" -- this is especially true for the NIC 55# application functionality. 56# 57 58 59# Global configuration settings. 60# 61[global] 62 rss_glb_config_mode = basicvirtual 63 rss_glb_config_options = tnlmapen,hashtoeplitz,tnlalllkp 64 65 # PL_TIMEOUT register 66 pl_timeout_value = 200 # the timeout value in units of us 67 68 # The following Scatter Gather Engine (SGE) settings assume a 4KB Host 69 # Page Size and a 64B L1 Cache Line Size. It programs the 70 # EgrStatusPageSize and IngPadBoundary to 64B and the PktShift to 2. 71 # If a Master PF Driver finds itself on a machine with different 72 # parameters, then the Master PF Driver is responsible for initializing 73 # these parameters to appropriate values. 74 # 75 # Notes: 76 # 1. The Free List Buffer Sizes below are raw and the firmware will 77 # round them up to the Ingress Padding Boundary. 78 # 2. The SGE Timer Values below are expressed below in microseconds. 79 # The firmware will convert these values to Core Clock Ticks when 80 # it processes the configuration parameters. 81 # 82 reg[0x1008] = 0x40800/0x21c70 # SGE_CONTROL 83 reg[0x100c] = 0x22222222 # SGE_HOST_PAGE_SIZE 84 reg[0x10a0] = 0x01040810 # SGE_INGRESS_RX_THRESHOLD 85 reg[0x1044] = 4096 # SGE_FL_BUFFER_SIZE0 86 reg[0x1048] = 65536 # SGE_FL_BUFFER_SIZE1 87 reg[0x104c] = 1536 # SGE_FL_BUFFER_SIZE2 88 reg[0x1050] = 9024 # SGE_FL_BUFFER_SIZE3 89 reg[0x1054] = 9216 # SGE_FL_BUFFER_SIZE4 90 reg[0x1058] = 2048 # SGE_FL_BUFFER_SIZE5 91 reg[0x105c] = 128 # SGE_FL_BUFFER_SIZE6 92 reg[0x1060] = 8192 # SGE_FL_BUFFER_SIZE7 93 reg[0x1064] = 16384 # SGE_FL_BUFFER_SIZE8 94 95 sge_timer_value = 5, 10, 20, 50, 100, 200 # SGE_TIMER_VALUE* in usecs 96 reg[0x10c4] = 0x20000000/0x20000000 # GK_CONTROL, enable 5th thread 97 98 # Set the SGE Doorbell Queue Timer "tick" to 50us and initialize 99 # the Timer Table to a default set of values (which are multiples 100 # of the Timer Tick). Note that the set of Tick Multipliers are 101 # NOT sorted. The Host Drivers are expected to pick amongst them 102 # for (Tick * Multiplier[i]) values which most closely match the Host 103 # Drivers' needs. Also, most Host Drivers will be default start 104 # start with (Tick * Multiplier[0]), so this gives us some flexibility 105 # in terms of picking a Tick and a default Multiplier somewhere in 106 # the middle of the achievable set of (Tick * Multiplier[i]) values. 107 # Thus, the below select for 150us by this default. 108 # 109 sge_dbq_timertick = 50 110 sge_dbq_timer = 3, 2, 1, 5, 7, 9, 12, 16 111 112 # enable TP_OUT_CONFIG.IPIDSPLITMODE 113 # Set TP_OUT_CONFIG.CCplAckMode to get srtt/rttvar 114 reg[0x7d04] = 0x00012000/0x00012000 115 116 reg[0x7dc0] = 0x0e2f8849 # TP_SHIFT_CNT 117 118 #Tick granularities in kbps 119 tsch_ticks = 100000, 10000, 1000, 10 120 121 # TP_VLAN_PRI_MAP to select filter tuples and enable ServerSram 122 # filter control: compact, fcoemask 123 # server sram : srvrsram 124 # filter tuples : fragmentation, mpshittype, macmatch, ethertype, 125 # protocol, tos, vlan, vnic_id, port, fcoe 126 # valid filterModes are described the Terminator 5 Data Book 127 # vnicMode = pf_vf #default. Other values are outer_vlan, encapsulation 128 filterMode = fcoemask, srvrsram, fragmentation, mpshittype, protocol, vlan, port, fcoe 129 130 # filter tuples enforced in LE active region (equal to or subset of filterMode) 131 filterMask = protocol, fcoe 132 133 # Percentage of dynamic memory (in either the EDRAM or external MEM) 134 # to use for TP RX payload 135 tp_pmrx = 30 136 137 # TP RX payload page size 138 tp_pmrx_pagesize = 64K 139 140 # TP number of RX channels 141 tp_nrxch = 0 # 0 (auto) = 1 142 143 # Percentage of dynamic memory (in either the EDRAM or external MEM) 144 # to use for TP TX payload 145 tp_pmtx = 50 146 147 # TP TX payload page size 148 tp_pmtx_pagesize = 64K 149 150 # TP number of TX channels 151 tp_ntxch = 0 # 0 (auto) = equal number of ports 152 153 # TP OFLD MTUs 154 tp_mtus = 88, 256, 512, 576, 808, 1024, 1280, 1488, 1500, 2002, 2048, 4096, 4352, 8192, 9000, 9600 155 156 # enable TP_OUT_CONFIG.IPIDSPLITMODE and CRXPKTENC 157 reg[0x7d04] = 0x00010008/0x00010008 158 159 # TP_GLOBAL_CONFIG 160 reg[0x7d08] = 0x00000800/0x00000800 # set IssFromCplEnable 161 162 # TP_PC_CONFIG 163 reg[0x7d48] = 0x00000000/0x00000400 # clear EnableFLMError 164 165 # TP_PARA_REG0 166 reg[0x7d60] = 0x06000000/0x07000000 # set InitCWND to 6 167 168 # ULPRX iSCSI Page Sizes 169 reg[0x19168] = 0x04020100 # 64K, 16K, 8K and 4K 170 171 # LE_DB_CONFIG 172 reg[0x19c04] = 0x00000000/0x00440000 # LE Server SRAM disabled 173 # LE IPv4 compression disabled 174 # LE_DB_HASH_CONFIG 175 reg[0x19c28] = 0x00800000/0x01f00000 # LE Hash bucket size 8, 176 177 # ULP_TX_CONFIG 178 reg[0x8dc0] = 0x00000104/0x00000104 # Enable ITT on PI err 179 # Enable more error msg for ... 180 # TPT error. 181 182 # ULP_RX_MISC_FEATURE_ENABLE 183 #reg[0x1925c] = 0x01003400/0x01003400 # iscsi tag pi bit 184 # Enable offset decrement after ... 185 # PI extraction and before DDP 186 # ulp insert pi source info in DIF 187 # iscsi_eff_offset_en 188 189 #Enable iscsi completion moderation feature 190 reg[0x1925c] = 0x000041c0/0x000031c0 # Enable offset decrement after 191 # PI extraction and before DDP. 192 # ulp insert pi source info in 193 # DIF. 194 # Enable iscsi hdr cmd mode. 195 # iscsi force cmd mode. 196 # Enable iscsi cmp mode. 197 # MC configuration 198 #mc_mode_brc[0] = 1 # mc0 - 1: enable BRC, 0: enable RBC, 2: enable BRBC 199 200 # HMA configuration 201 hma_size = 92 # Size (in MBs) of host memory expected 202 hma_regions = stag,pbl,rq # What all regions to place in host memory 203 204 #enable bottleneck-bw congestion control mode 205 #ofld_flags = 4 206 207# Some "definitions" to make the rest of this a bit more readable. We support 208# 4 ports, 3 functions (NIC, FCoE and iSCSI), scaling up to 8 "CPU Queue Sets" 209# per function per port ... 210# 211# NMSIX = 1088 # available MSI-X Vectors 212# NVI = 256 # available Virtual Interfaces 213# NMPSTCAM = 336 # MPS TCAM entries 214# 215# NPORTS = 2 # ports 216# NCPUS = 16 # CPUs we want to support scalably 217# NFUNCS = 3 # functions per port (NIC, FCoE, iSCSI) 218 219# Breakdown of Virtual Interface/Queue/Interrupt resources for the "Unified 220# PF" which many OS Drivers will use to manage most or all functions. 221# 222# Each Ingress Queue can use one MSI-X interrupt but some Ingress Queues can 223# use Forwarded Interrupt Ingress Queues. For these latter, an Ingress Queue 224# would be created and the Queue ID of a Forwarded Interrupt Ingress Queue 225# will be specified as the "Ingress Queue Asynchronous Destination Index." 226# Thus, the number of MSI-X Vectors assigned to the Unified PF will be less 227# than or equal to the number of Ingress Queues ... 228# 229# NVI_NIC = 4 # NIC access to NPORTS 230# NFLIQ_NIC = 32 # NIC Ingress Queues with Free Lists 231# NETHCTRL_NIC = 32 # NIC Ethernet Control/TX Queues 232# NEQ_NIC = 64 # NIC Egress Queues (FL, ETHCTRL/TX) 233# NMPSTCAM_NIC = 16 # NIC MPS TCAM Entries (NPORTS*4) 234# NMSIX_NIC = 32 # NIC MSI-X Interrupt Vectors (FLIQ) 235# 236# NVI_OFLD = 0 # Offload uses NIC function to access ports 237# NFLIQ_OFLD = 16 # Offload Ingress Queues with Free Lists 238# NETHCTRL_OFLD = 0 # Offload Ethernet Control/TX Queues 239# NEQ_OFLD = 16 # Offload Egress Queues (FL) 240# NMPSTCAM_OFLD = 0 # Offload MPS TCAM Entries (uses NIC's) 241# NMSIX_OFLD = 16 # Offload MSI-X Interrupt Vectors (FLIQ) 242# 243# NVI_RDMA = 0 # RDMA uses NIC function to access ports 244# NFLIQ_RDMA = 4 # RDMA Ingress Queues with Free Lists 245# NETHCTRL_RDMA = 0 # RDMA Ethernet Control/TX Queues 246# NEQ_RDMA = 4 # RDMA Egress Queues (FL) 247# NMPSTCAM_RDMA = 0 # RDMA MPS TCAM Entries (uses NIC's) 248# NMSIX_RDMA = 4 # RDMA MSI-X Interrupt Vectors (FLIQ) 249# 250# NEQ_WD = 128 # Wire Direct TX Queues and FLs 251# NETHCTRL_WD = 64 # Wire Direct TX Queues 252# NFLIQ_WD = 64 ` # Wire Direct Ingress Queues with Free Lists 253# 254# NVI_ISCSI = 4 # ISCSI access to NPORTS 255# NFLIQ_ISCSI = 4 # ISCSI Ingress Queues with Free Lists 256# NETHCTRL_ISCSI = 0 # ISCSI Ethernet Control/TX Queues 257# NEQ_ISCSI = 4 # ISCSI Egress Queues (FL) 258# NMPSTCAM_ISCSI = 4 # ISCSI MPS TCAM Entries (NPORTS) 259# NMSIX_ISCSI = 4 # ISCSI MSI-X Interrupt Vectors (FLIQ) 260# 261# NVI_FCOE = 4 # FCOE access to NPORTS 262# NFLIQ_FCOE = 34 # FCOE Ingress Queues with Free Lists 263# NETHCTRL_FCOE = 32 # FCOE Ethernet Control/TX Queues 264# NEQ_FCOE = 66 # FCOE Egress Queues (FL) 265# NMPSTCAM_FCOE = 32 # FCOE MPS TCAM Entries (NPORTS) 266# NMSIX_FCOE = 34 # FCOE MSI-X Interrupt Vectors (FLIQ) 267 268# Two extra Ingress Queues per function for Firmware Events and Forwarded 269# Interrupts, and two extra interrupts per function for Firmware Events (or a 270# Forwarded Interrupt Queue) and General Interrupts per function. 271# 272# NFLIQ_EXTRA = 6 # "extra" Ingress Queues 2*NFUNCS (Firmware and 273# # Forwarded Interrupts 274# NMSIX_EXTRA = 6 # extra interrupts 2*NFUNCS (Firmware and 275# # General Interrupts 276 277# Microsoft HyperV resources. The HyperV Virtual Ingress Queues will have 278# their interrupts forwarded to another set of Forwarded Interrupt Queues. 279# 280# NVI_HYPERV = 16 # VMs we want to support 281# NVIIQ_HYPERV = 2 # Virtual Ingress Queues with Free Lists per VM 282# NFLIQ_HYPERV = 40 # VIQs + NCPUS Forwarded Interrupt Queues 283# NEQ_HYPERV = 32 # VIQs Free Lists 284# NMPSTCAM_HYPERV = 16 # MPS TCAM Entries (NVI_HYPERV) 285# NMSIX_HYPERV = 8 # NCPUS Forwarded Interrupt Queues 286 287# Adding all of the above Unified PF resource needs together: (NIC + OFLD + 288# RDMA + ISCSI + FCOE + EXTRA + HYPERV) 289# 290# NVI_UNIFIED = 28 291# NFLIQ_UNIFIED = 106 292# NETHCTRL_UNIFIED = 32 293# NEQ_UNIFIED = 124 294# NMPSTCAM_UNIFIED = 40 295# 296# The sum of all the MSI-X resources above is 74 MSI-X Vectors but we'll round 297# that up to 128 to make sure the Unified PF doesn't run out of resources. 298# 299# NMSIX_UNIFIED = 128 300# 301# The Storage PFs could need up to NPORTS*NCPUS + NMSIX_EXTRA MSI-X Vectors 302# which is 34 but they're probably safe with 32. 303# 304# NMSIX_STORAGE = 32 305 306# Note: The UnifiedPF is PF4 which doesn't have any Virtual Functions 307# associated with it. Thus, the MSI-X Vector allocations we give to the 308# UnifiedPF aren't inherited by any Virtual Functions. As a result we can 309# provision many more Virtual Functions than we can if the UnifiedPF were 310# one of PF0-3. 311# 312 313# All of the below PCI-E parameters are actually stored in various *_init.txt 314# files. We include them below essentially as comments. 315# 316# For PF0-3 we assign 8 vectors each for NIC Ingress Queues of the associated 317# ports 0-3. 318# 319# For PF4, the Unified PF, we give it an MSI-X Table Size as outlined above. 320# 321# For PF5-6 we assign enough MSI-X Vectors to support FCoE and iSCSI 322# storage applications across all four possible ports. 323# 324# Additionally, since the UnifiedPF isn't one of the per-port Physical 325# Functions, we give the UnifiedPF and the PF0-3 Physical Functions 326# different PCI Device IDs which will allow Unified and Per-Port Drivers 327# to directly select the type of Physical Function to which they wish to be 328# attached. 329# 330# Note that the actual values used for the PCI-E Intelectual Property will be 331# 1 less than those below since that's the way it "counts" things. For 332# readability, we use the number we actually mean ... 333# 334# PF0_INT = 8 # NCPUS 335# PF1_INT = 8 # NCPUS 336# PF0_3_INT = 32 # PF0_INT + PF1_INT + PF2_INT + PF3_INT 337# 338# PF4_INT = 128 # NMSIX_UNIFIED 339# PF5_INT = 32 # NMSIX_STORAGE 340# PF6_INT = 32 # NMSIX_STORAGE 341# PF7_INT = 0 # Nothing Assigned 342# PF4_7_INT = 192 # PF4_INT + PF5_INT + PF6_INT + PF7_INT 343# 344# PF0_7_INT = 224 # PF0_3_INT + PF4_7_INT 345# 346# With the above we can get 17 VFs/PF0-3 (limited by 336 MPS TCAM entries) 347# but we'll lower that to 16 to make our total 64 and a nice power of 2 ... 348# 349# NVF = 16 350 351 352# For those OSes which manage different ports on different PFs, we need 353# only enough resources to support a single port's NIC application functions 354# on PF0-3. The below assumes that we're only doing NIC with NCPUS "Queue 355# Sets" for ports 0-3. The FCoE and iSCSI functions for such OSes will be 356# managed on the "storage PFs" (see below). 357# 358[function "0"] 359 nvf = 16 # NVF on this function 360 wx_caps = all # write/execute permissions for all commands 361 r_caps = all # read permissions for all commands 362 nvi = 1 # 1 port 363 niqflint = 8 # NCPUS "Queue Sets" 364 nethctrl = 8 # NCPUS "Queue Sets" 365 neq = 16 # niqflint + nethctrl Egress Queues 366 nexactf = 8 # number of exact MPSTCAM MAC filters 367 cmask = all # access to all channels 368 pmask = 0x1 # access to only one port 369 370 371[function "1"] 372 nvf = 16 # NVF on this function 373 wx_caps = all # write/execute permissions for all commands 374 r_caps = all # read permissions for all commands 375 nvi = 1 # 1 port 376 niqflint = 8 # NCPUS "Queue Sets" 377 nethctrl = 8 # NCPUS "Queue Sets" 378 neq = 16 # niqflint + nethctrl Egress Queues 379 nexactf = 8 # number of exact MPSTCAM MAC filters 380 cmask = all # access to all channels 381 pmask = 0x2 # access to only one port 382 383[function "2"] 384 nvf = 16 # NVF on this function 385 wx_caps = all # write/execute permissions for all commands 386 r_caps = all # read permissions for all commands 387 nvi = 1 # 1 port 388 niqflint = 8 # NCPUS "Queue Sets" 389 nethctrl = 8 # NCPUS "Queue Sets" 390 neq = 16 # niqflint + nethctrl Egress Queues 391 nexactf = 8 # number of exact MPSTCAM MAC filters 392 cmask = all # access to all channels 393 pmask = 0x4 # access to only one port 394 395[function "3"] 396 nvf = 16 # NVF on this function 397 wx_caps = all # write/execute permissions for all commands 398 r_caps = all # read permissions for all commands 399 nvi = 1 # 1 port 400 niqflint = 8 # NCPUS "Queue Sets" 401 nethctrl = 8 # NCPUS "Queue Sets" 402 neq = 16 # niqflint + nethctrl Egress Queues 403 nexactf = 8 # number of exact MPSTCAM MAC filters 404 cmask = all # access to all channels 405 pmask = 0x8 # access to only one port 406 407 408# Some OS Drivers manage all application functions for all ports via PF4. 409# Thus we need to provide a large number of resources here. For Egress 410# Queues we need to account for both TX Queues as well as Free List Queues 411# (because the host is responsible for producing Free List Buffers for the 412# hardware to consume). 413# 414[function "4"] 415 wx_caps = all # write/execute permissions for all commands 416 r_caps = all # read permissions for all commands 417 nvi = 28 # NVI_UNIFIED 418 niqflint = 218 # NFLIQ_UNIFIED + NLFIQ_WD + NFLIQ_CRYPTO (32) 419 nethctrl = 116 # NETHCTRL_UNIFIED + NETHCTRL_WD + ncrypto_lookaside 420 neq = 256 # NEQ_UNIFIED + NEQ_WD 421 nqpcq = 12288 422 nexactf = 40 # NMPSTCAM_UNIFIED 423 nrawf = 2 424 cmask = all # access to all channels 425 pmask = all # access to all four ports ... 426 nethofld = 1024 # number of user mode ethernet flow contexts 427 ncrypto_lookaside = 16 # Number of lookaside flow contexts 428 nclip = 320 # number of clip region entries 429 nfilter = 496 # number of filter region entries 430 nserver = 496 # number of server region entries 431 nhash = 12288 # number of hash region entries 432 nhpfilter = 64 # number of high priority filter region entries 433 protocol = nic_vm, ofld, rddp, rdmac, iscsi_initiator_pdu, iscsi_target_pdu, iscsi_t10dif, tlskeys, crypto_lookaside, ipsec_inline, nic_hashfilter, nic_ktls_ofld 434 tp_l2t = 3072 435 tp_ddp = 2 436 tp_ddp_iscsi = 2 437 tp_tls_key = 2 438 tp_tls_mxrxsize = 17408 # 16384 + 1024, governs max rx data, pm max xfer len, rx coalesce sizes 439 tp_stag = 2 440 tp_pbl = 7 441 tp_rq = 7 442 tp_srq = 128 443 444# We have FCoE and iSCSI storage functions on PF5 and PF6 each of which may 445# need to have Virtual Interfaces on each of the four ports with up to NCPUS 446# "Queue Sets" each. 447# 448[function "5"] 449 wx_caps = all # write/execute permissions for all commands 450 r_caps = all # read permissions for all commands 451 nvi = 4 # NPORTS 452 niqflint = 34 # NPORTS*NCPUS + NMSIX_EXTRA 453 nethctrl = 32 # NPORTS*NCPUS 454 neq = 64 # NPORTS*NCPUS * 2 (FL, ETHCTRL/TX) 455 nexactf = 16 # (NPORTS *(no of snmc grp + 1 hw mac) + 1 anmc grp)) rounded to 16. 456 cmask = all # access to all channels 457 pmask = all # access to all four ports ... 458 nserver = 16 459 nhash = 2048 460 tp_l2t = 1020 461 nclip = 64 462 protocol = iscsi_initiator_fofld 463 tp_ddp_iscsi = 2 464 iscsi_ntask = 2048 465 iscsi_nsess = 2048 466 iscsi_nconn_per_session = 1 467 iscsi_ninitiator_instance = 64 468 469 470[function "6"] 471 wx_caps = all # write/execute permissions for all commands 472 r_caps = all # read permissions for all commands 473 nvi = 4 # NPORTS 474 niqflint = 34 # NPORTS*NCPUS + NMSIX_EXTRA 475 nethctrl = 32 # NPORTS*NCPUS 476 neq = 66 # NPORTS*NCPUS * 2 (FL, ETHCTRL/TX) + 2 (EXTRA) 477 nexactf = 32 # NPORTS + adding 28 exact entries for FCoE 478 # which is OK since < MIN(SUM PF0..3, PF4) 479 # and we never load PF0..3 and PF4 concurrently 480 cmask = all # access to all channels 481 pmask = all # access to all four ports ... 482 nhash = 2048 483 tp_l2t = 4 484 protocol = fcoe_initiator 485 tp_ddp = 1 486 fcoe_nfcf = 16 487 fcoe_nvnp = 32 488 fcoe_nssn = 1024 489 490 491# The following function, 1023, is not an actual PCIE function but is used to 492# configure and reserve firmware internal resources that come from the global 493# resource pool. 494# 495[function "1023"] 496 wx_caps = all # write/execute permissions for all commands 497 r_caps = all # read permissions for all commands 498 nvi = 4 # NVI_UNIFIED 499 cmask = all # access to all channels 500 pmask = all # access to all four ports ... 501 nexactf = 8 # NPORTS + DCBX + 502 nfilter = 16 # number of filter region entries 503 504 505# For Virtual functions, we only allow NIC functionality and we only allow 506# access to one port (1 << PF). Note that because of limitations in the 507# Scatter Gather Engine (SGE) hardware which checks writes to VF KDOORBELL 508# and GTS registers, the number of Ingress and Egress Queues must be a power 509# of 2. 510# 511[function "0/*"] # NVF 512 wx_caps = 0x82 # DMAQ | VF 513 r_caps = 0x86 # DMAQ | VF | PORT 514 nvi = 1 # 1 port 515 niqflint = 6 # 2 "Queue Sets" + NXIQ 516 nethctrl = 4 # 2 "Queue Sets" 517 neq = 8 # 2 "Queue Sets" * 2 518 nexactf = 4 519 cmask = all # access to all channels 520 pmask = 0x1 # access to only one port ... 521 522 523[function "1/*"] # NVF 524 wx_caps = 0x82 # DMAQ | VF 525 r_caps = 0x86 # DMAQ | VF | PORT 526 nvi = 1 # 1 port 527 niqflint = 6 # 2 "Queue Sets" + NXIQ 528 nethctrl = 4 # 2 "Queue Sets" 529 neq = 8 # 2 "Queue Sets" * 2 530 nexactf = 4 531 cmask = all # access to all channels 532 pmask = 0x2 # access to only one port ... 533 534[function "2/*"] # NVF 535 wx_caps = 0x82 # DMAQ | VF 536 r_caps = 0x86 # DMAQ | VF | PORT 537 nvi = 1 # 1 port 538 niqflint = 6 # 2 "Queue Sets" + NXIQ 539 nethctrl = 4 # 2 "Queue Sets" 540 neq = 8 # 2 "Queue Sets" * 2 541 nexactf = 4 542 cmask = all # access to all channels 543 pmask = 0x1 # access to only one port ... 544 545 546[function "3/*"] # NVF 547 wx_caps = 0x82 # DMAQ | VF 548 r_caps = 0x86 # DMAQ | VF | PORT 549 nvi = 1 # 1 port 550 niqflint = 6 # 2 "Queue Sets" + NXIQ 551 nethctrl = 4 # 2 "Queue Sets" 552 neq = 8 # 2 "Queue Sets" * 2 553 nexactf = 4 554 cmask = all # access to all channels 555 pmask = 0x2 # access to only one port ... 556 557# MPS features a 196608 bytes ingress buffer that is used for ingress buffering 558# for packets from the wire as well as the loopback path of the L2 switch. The 559# folling params control how the buffer memory is distributed and the L2 flow 560# control settings: 561# 562# bg_mem: %-age of mem to use for port/buffer group 563# lpbk_mem: %-age of port/bg mem to use for loopback 564# hwm: high watermark; bytes available when starting to send pause 565# frames (in units of 0.1 MTU) 566# lwm: low watermark; bytes remaining when sending 'unpause' frame 567# (in inuits of 0.1 MTU) 568# dwm: minimum delta between high and low watermark (in units of 100 569# Bytes) 570# 571[port "0"] 572 dcb = ppp, dcbx # configure for DCB PPP and enable DCBX offload 573 #bg_mem = 25 574 #lpbk_mem = 25 575 hwm = 60 576 lwm = 15 577 dwm = 30 578 dcb_app_tlv[0] = 0x8906, ethertype, 3 579 dcb_app_tlv[1] = 0x8914, ethertype, 3 580 dcb_app_tlv[2] = 3260, socketnum, 5 581 582[port "1"] 583 dcb = ppp, dcbx 584 #bg_mem = 25 585 #lpbk_mem = 25 586 hwm = 60 587 lwm = 15 588 dwm = 30 589 dcb_app_tlv[0] = 0x8906, ethertype, 3 590 dcb_app_tlv[1] = 0x8914, ethertype, 3 591 dcb_app_tlv[2] = 3260, socketnum, 5 592 593[fini] 594 version = 0x1425001d 595 checksum = 0xa1403d73 596 597# Total resources used by above allocations: 598# Virtual Interfaces: 104 599# Ingress Queues/w Free Lists and Interrupts: 526 600# Egress Queues: 702 601# MPS TCAM Entries: 336 602# MSI-X Vectors: 736 603# Virtual Functions: 64 604