1[
2  {
3    "Unit": "CBO",
4    "EventCode": "0xA",
5    "UMask": "0x0",
6    "EventName": "UNC_C_BOUNCE_CONTROL",
7    "BriefDescription": "Bounce Control",
8    "PublicDescription": "tbd",
9    "Counter": "0,1,2,3",
10    "MSRValue": "0x00",
11    "ELLC": "0",
12    "Filter": "na",
13    "ExtSel": "0",
14    "EVENT_STATUS": "0"
15  },
16  {
17    "Unit": "CBO",
18    "EventCode": "0x0",
19    "UMask": "0x0",
20    "EventName": "UNC_C_CLOCKTICKS",
21    "BriefDescription": "Uncore Clocks",
22    "PublicDescription": "tbd",
23    "Counter": "0,1,2,3",
24    "MSRValue": "0x00",
25    "ELLC": "0",
26    "Filter": "na",
27    "ExtSel": "0",
28    "EVENT_STATUS": "0"
29  },
30  {
31    "Unit": "CBO",
32    "EventCode": "0x1F",
33    "UMask": "0x0",
34    "EventName": "UNC_C_COUNTER0_OCCUPANCY",
35    "BriefDescription": "Counter 0 Occupancy",
36    "PublicDescription": "Since occupancy counts can only be captured in the Cbo's 0 counter, this event allows a user to capture occupancy related information by filtering the Cb0 occupancy count captured in Counter 0.   The filtering available is found in the control register - threshold, invert and edge detect.   E.g. setting threshold to 1 can effectively monitor how many cycles the monitored queue has an entry.",
37    "Counter": "0,1,2,3",
38    "MSRValue": "0x00",
39    "ELLC": "0",
40    "Filter": "na",
41    "ExtSel": "0",
42    "EVENT_STATUS": "0"
43  },
44  {
45    "Unit": "CBO",
46    "EventCode": "0x9",
47    "UMask": "0x0",
48    "EventName": "UNC_C_FAST_ASSERTED",
49    "BriefDescription": "FaST wire asserted",
50    "PublicDescription": "Counts the number of cycles either the local distress or incoming distress signals are asserted.  Incoming distress includes both up and dn.",
51    "Counter": "0,1",
52    "MSRValue": "0x00",
53    "ELLC": "0",
54    "Filter": "na",
55    "ExtSel": "0",
56    "EVENT_STATUS": "0"
57  },
58  {
59    "Unit": "CBO",
60    "EventCode": "0x34",
61    "UMask": "0x3",
62    "EventName": "UNC_C_LLC_LOOKUP.DATA_READ",
63    "BriefDescription": "Cache Lookups; Data Read Request",
64    "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Read transactions",
65    "Counter": "0,1,2,3",
66    "MSRValue": "0x00",
67    "ELLC": "0",
68    "Filter": "CBoFilter0[23:17]",
69    "ExtSel": "0",
70    "EVENT_STATUS": "0"
71  },
72  {
73    "Unit": "CBO",
74    "EventCode": "0x34",
75    "UMask": "0x5",
76    "EventName": "UNC_C_LLC_LOOKUP.WRITE",
77    "BriefDescription": "Cache Lookups; Write Requests",
78    "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Writeback transactions from L2 to the LLC  This includes all write transactions -- both Cachable and UC.",
79    "Counter": "0,1,2,3",
80    "MSRValue": "0x00",
81    "ELLC": "0",
82    "Filter": "CBoFilter0[23:17]",
83    "ExtSel": "0",
84    "EVENT_STATUS": "0"
85  },
86  {
87    "Unit": "CBO",
88    "EventCode": "0x34",
89    "UMask": "0x9",
90    "EventName": "UNC_C_LLC_LOOKUP.REMOTE_SNOOP",
91    "BriefDescription": "Cache Lookups; External Snoop Request",
92    "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Filters for only snoop requests coming from the remote socket(s) through the IPQ.",
93    "Counter": "0,1,2,3",
94    "MSRValue": "0x00",
95    "ELLC": "0",
96    "Filter": "CBoFilter0[23:17]",
97    "ExtSel": "0",
98    "EVENT_STATUS": "0"
99  },
100  {
101    "Unit": "CBO",
102    "EventCode": "0x34",
103    "UMask": "0x11",
104    "EventName": "UNC_C_LLC_LOOKUP.ANY",
105    "BriefDescription": "Cache Lookups; Any Request",
106    "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Filters for any transaction originating from the IPQ or IRQ.  This does not include lookups originating from the ISMQ.",
107    "Counter": "0,1,2,3",
108    "MSRValue": "0x00",
109    "ELLC": "0",
110    "Filter": "CBoFilter0[23:17]",
111    "ExtSel": "0",
112    "EVENT_STATUS": "0"
113  },
114  {
115    "Unit": "CBO",
116    "EventCode": "0x34",
117    "UMask": "0x41",
118    "EventName": "UNC_C_LLC_LOOKUP.NID",
119    "BriefDescription": "Cache Lookups; Lookups that Match NID",
120    "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Qualify one of the other subevents by the Target NID.  The NID is programmed in Cn_MSR_PMON_BOX_FILTER.nid.   In conjunction with STATE = I, it is possible to monitor misses to specific NIDs in the system.",
121    "Counter": "0,1,2,3",
122    "MSRValue": "0x00",
123    "ELLC": "0",
124    "Filter": "CBoFilter0[23:17]",
125    "ExtSel": "0",
126    "EVENT_STATUS": "0"
127  },
128  {
129    "Unit": "CBO",
130    "EventCode": "0x34",
131    "UMask": "0x21",
132    "EventName": "UNC_C_LLC_LOOKUP.READ",
133    "BriefDescription": "Cache Lookups; Any Read Request",
134    "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Read transactions",
135    "Counter": "0,1,2,3",
136    "MSRValue": "0x00",
137    "ELLC": "0",
138    "Filter": "CBoFilter0[22:18]",
139    "ExtSel": "0",
140    "EVENT_STATUS": "0"
141  },
142  {
143    "Unit": "CBO",
144    "EventCode": "0x37",
145    "UMask": "0x1",
146    "EventName": "UNC_C_LLC_VICTIMS.M_STATE",
147    "BriefDescription": "Lines Victimized; Lines in M state",
148    "PublicDescription": "Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
149    "Counter": "0,1,2,3",
150    "MSRValue": "0x00",
151    "ELLC": "0",
152    "Filter": "na",
153    "ExtSel": "0",
154    "EVENT_STATUS": "0"
155  },
156  {
157    "Unit": "CBO",
158    "EventCode": "0x37",
159    "UMask": "0x2",
160    "EventName": "UNC_C_LLC_VICTIMS.E_STATE",
161    "BriefDescription": "Lines Victimized; Lines in E state",
162    "PublicDescription": "Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
163    "Counter": "0,1,2,3",
164    "MSRValue": "0x00",
165    "ELLC": "0",
166    "Filter": "na",
167    "ExtSel": "0",
168    "EVENT_STATUS": "0"
169  },
170  {
171    "Unit": "CBO",
172    "EventCode": "0x37",
173    "UMask": "0x4",
174    "EventName": "UNC_C_LLC_VICTIMS.S_STATE",
175    "BriefDescription": "Lines in S State",
176    "PublicDescription": "Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
177    "Counter": "0,1,2,3",
178    "MSRValue": "0x00",
179    "ELLC": "0",
180    "Filter": "na",
181    "ExtSel": "0",
182    "EVENT_STATUS": "0"
183  },
184  {
185    "Unit": "CBO",
186    "EventCode": "0x37",
187    "UMask": "0x8",
188    "EventName": "UNC_C_LLC_VICTIMS.F_STATE",
189    "BriefDescription": "Lines Victimized",
190    "PublicDescription": "Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
191    "Counter": "0,1,2,3",
192    "MSRValue": "0x00",
193    "ELLC": "0",
194    "Filter": "na",
195    "ExtSel": "0",
196    "EVENT_STATUS": "0"
197  },
198  {
199    "Unit": "CBO",
200    "EventCode": "0x37",
201    "UMask": "0x40",
202    "EventName": "UNC_C_LLC_VICTIMS.NID",
203    "BriefDescription": "Lines Victimized; Victimized Lines that Match NID",
204    "PublicDescription": "Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.; Qualify one of the other subevents by the Target NID.  The NID is programmed in Cn_MSR_PMON_BOX_FILTER.nid.   In conjunction with STATE = I, it is possible to monitor misses to specific NIDs in the system.",
205    "Counter": "0,1,2,3",
206    "MSRValue": "0x00",
207    "ELLC": "0",
208    "Filter": "CBoFilter1[17:10]",
209    "ExtSel": "0",
210    "EVENT_STATUS": "0"
211  },
212  {
213    "Unit": "CBO",
214    "EventCode": "0x37",
215    "UMask": "0x10",
216    "EventName": "UNC_C_LLC_VICTIMS.MISS",
217    "BriefDescription": "Lines Victimized",
218    "PublicDescription": "Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
219    "Counter": "0,1,2,3",
220    "MSRValue": "0x00",
221    "ELLC": "0",
222    "Filter": "na",
223    "ExtSel": "0",
224    "EVENT_STATUS": "0"
225  },
226  {
227    "Unit": "CBO",
228    "EventCode": "0x39",
229    "UMask": "0x1",
230    "EventName": "UNC_C_MISC.RSPI_WAS_FSE",
231    "BriefDescription": "Cbo Misc; Silent Snoop Eviction",
232    "PublicDescription": "Miscellaneous events in the Cbo.; Counts the number of times when a Snoop hit in FSE states and triggered a silent eviction.  This is useful because this information is lost in the PRE encodings.",
233    "Counter": "0,1,2,3",
234    "MSRValue": "0x00",
235    "ELLC": "0",
236    "Filter": "na",
237    "ExtSel": "0",
238    "EVENT_STATUS": "0"
239  },
240  {
241    "Unit": "CBO",
242    "EventCode": "0x39",
243    "UMask": "0x2",
244    "EventName": "UNC_C_MISC.WC_ALIASING",
245    "BriefDescription": "Cbo Misc; Write Combining Aliasing",
246    "PublicDescription": "Miscellaneous events in the Cbo.; Counts the number of times that a USWC write (WCIL(F)) transaction hit in the LLC in M state, triggering a WBMtoI followed by the USWC write.  This occurs when there is WC aliasing.",
247    "Counter": "0,1,2,3",
248    "MSRValue": "0x00",
249    "ELLC": "0",
250    "Filter": "na",
251    "ExtSel": "0",
252    "EVENT_STATUS": "0"
253  },
254  {
255    "Unit": "CBO",
256    "EventCode": "0x39",
257    "UMask": "0x4",
258    "EventName": "UNC_C_MISC.STARTED",
259    "BriefDescription": "Cbo Misc",
260    "PublicDescription": "Miscellaneous events in the Cbo.",
261    "Counter": "0,1,2,3",
262    "MSRValue": "0x00",
263    "ELLC": "0",
264    "Filter": "na",
265    "ExtSel": "0",
266    "EVENT_STATUS": "0"
267  },
268  {
269    "Unit": "CBO",
270    "EventCode": "0x39",
271    "UMask": "0x8",
272    "EventName": "UNC_C_MISC.RFO_HIT_S",
273    "BriefDescription": "Cbo Misc; RFO HitS",
274    "PublicDescription": "Miscellaneous events in the Cbo.; Number of times that an RFO hit in S state.  This is useful for determining if it might be good for a workload to use RspIWB instead of RspSWB.",
275    "Counter": "0,1,2,3",
276    "MSRValue": "0x00",
277    "ELLC": "0",
278    "Filter": "na",
279    "ExtSel": "0",
280    "EVENT_STATUS": "0"
281  },
282  {
283    "Unit": "CBO",
284    "EventCode": "0x39",
285    "UMask": "0x10",
286    "EventName": "UNC_C_MISC.CVZERO_PREFETCH_VICTIM",
287    "BriefDescription": "Cbo Misc; Clean Victim with raw CV=0",
288    "PublicDescription": "Miscellaneous events in the Cbo.",
289    "Counter": "0,1,2,3",
290    "MSRValue": "0x00",
291    "ELLC": "0",
292    "Filter": "na",
293    "ExtSel": "0",
294    "EVENT_STATUS": "0"
295  },
296  {
297    "Unit": "CBO",
298    "EventCode": "0x39",
299    "UMask": "0x20",
300    "EventName": "UNC_C_MISC.CVZERO_PREFETCH_MISS",
301    "BriefDescription": "Cbo Misc; DRd hitting non-M with raw CV=0",
302    "PublicDescription": "Miscellaneous events in the Cbo.",
303    "Counter": "0,1,2,3",
304    "MSRValue": "0x00",
305    "ELLC": "0",
306    "Filter": "na",
307    "ExtSel": "0",
308    "EVENT_STATUS": "0"
309  },
310  {
311    "Unit": "CBO",
312    "EventCode": "0x3C",
313    "UMask": "0x1",
314    "EventName": "UNC_C_QLRU.AGE0",
315    "BriefDescription": "LRU Queue; LRU Age 0",
316    "PublicDescription": "How often age was set to 0",
317    "Counter": "0,1,2,3",
318    "MSRValue": "0x00",
319    "ELLC": "0",
320    "Filter": "na",
321    "ExtSel": "0",
322    "EVENT_STATUS": "0"
323  },
324  {
325    "Unit": "CBO",
326    "EventCode": "0x3C",
327    "UMask": "0x2",
328    "EventName": "UNC_C_QLRU.AGE1",
329    "BriefDescription": "LRU Queue; LRU Age 1",
330    "PublicDescription": "How often age was set to 1",
331    "Counter": "0,1,2,3",
332    "MSRValue": "0x00",
333    "ELLC": "0",
334    "Filter": "na",
335    "ExtSel": "0",
336    "EVENT_STATUS": "0"
337  },
338  {
339    "Unit": "CBO",
340    "EventCode": "0x3C",
341    "UMask": "0x4",
342    "EventName": "UNC_C_QLRU.AGE2",
343    "BriefDescription": "LRU Queue; LRU Age 2",
344    "PublicDescription": "How often age was set to 2",
345    "Counter": "0,1,2,3",
346    "MSRValue": "0x00",
347    "ELLC": "0",
348    "Filter": "na",
349    "ExtSel": "0",
350    "EVENT_STATUS": "0"
351  },
352  {
353    "Unit": "CBO",
354    "EventCode": "0x3C",
355    "UMask": "0x8",
356    "EventName": "UNC_C_QLRU.AGE3",
357    "BriefDescription": "LRU Queue; LRU Age 3",
358    "PublicDescription": "How often age was set to 3",
359    "Counter": "0,1,2,3",
360    "MSRValue": "0x00",
361    "ELLC": "0",
362    "Filter": "na",
363    "ExtSel": "0",
364    "EVENT_STATUS": "0"
365  },
366  {
367    "Unit": "CBO",
368    "EventCode": "0x3C",
369    "UMask": "0x10",
370    "EventName": "UNC_C_QLRU.LRU_DECREMENT",
371    "BriefDescription": "LRU Queue; LRU Bits Decremented",
372    "PublicDescription": "How often all LRU bits were decremented by 1",
373    "Counter": "0,1,2,3",
374    "MSRValue": "0x00",
375    "ELLC": "0",
376    "Filter": "na",
377    "ExtSel": "0",
378    "EVENT_STATUS": "0"
379  },
380  {
381    "Unit": "CBO",
382    "EventCode": "0x3C",
383    "UMask": "0x20",
384    "EventName": "UNC_C_QLRU.VICTIM_NON_ZERO",
385    "BriefDescription": "LRU Queue; Non-0 Aged Victim",
386    "PublicDescription": "How often we picked a victim that had a non-zero age",
387    "Counter": "0,1,2,3",
388    "MSRValue": "0x00",
389    "ELLC": "0",
390    "Filter": "na",
391    "ExtSel": "0",
392    "EVENT_STATUS": "0"
393  },
394  {
395    "Unit": "CBO",
396    "EventCode": "0x1B",
397    "UMask": "0x1",
398    "EventName": "UNC_C_RING_AD_USED.UP_EVEN",
399    "BriefDescription": "AD Ring In Use; Up and Even",
400    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity.",
401    "Counter": "0,1,2,3",
402    "MSRValue": "0x00",
403    "ELLC": "0",
404    "Filter": "na",
405    "ExtSel": "0",
406    "EVENT_STATUS": "0"
407  },
408  {
409    "Unit": "CBO",
410    "EventCode": "0x1B",
411    "UMask": "0x2",
412    "EventName": "UNC_C_RING_AD_USED.UP_ODD",
413    "BriefDescription": "AD Ring In Use; Up and Odd",
414    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity.",
415    "Counter": "0,1,2,3",
416    "MSRValue": "0x00",
417    "ELLC": "0",
418    "Filter": "na",
419    "ExtSel": "0",
420    "EVENT_STATUS": "0"
421  },
422  {
423    "Unit": "CBO",
424    "EventCode": "0x1B",
425    "UMask": "0x4",
426    "EventName": "UNC_C_RING_AD_USED.DOWN_EVEN",
427    "BriefDescription": "AD Ring In Use; Down and Even",
428    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Even ring polarity.",
429    "Counter": "0,1,2,3",
430    "MSRValue": "0x00",
431    "ELLC": "0",
432    "Filter": "na",
433    "ExtSel": "0",
434    "EVENT_STATUS": "0"
435  },
436  {
437    "Unit": "CBO",
438    "EventCode": "0x1B",
439    "UMask": "0x8",
440    "EventName": "UNC_C_RING_AD_USED.DOWN_ODD",
441    "BriefDescription": "AD Ring In Use; Down and Odd",
442    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity.",
443    "Counter": "0,1,2,3",
444    "MSRValue": "0x00",
445    "ELLC": "0",
446    "Filter": "na",
447    "ExtSel": "0",
448    "EVENT_STATUS": "0"
449  },
450  {
451    "Unit": "CBO",
452    "EventCode": "0x1B",
453    "UMask": "0x3",
454    "EventName": "UNC_C_RING_AD_USED.UP",
455    "BriefDescription": "AD Ring In Use; Up",
456    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
457    "Counter": "0,1,2,3",
458    "MSRValue": "0x00",
459    "ELLC": "0",
460    "Filter": "na",
461    "ExtSel": "0",
462    "EVENT_STATUS": "0"
463  },
464  {
465    "Unit": "CBO",
466    "EventCode": "0x1B",
467    "UMask": "0xC",
468    "EventName": "UNC_C_RING_AD_USED.DOWN",
469    "BriefDescription": "AD Ring In Use; Down",
470    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
471    "Counter": "0,1,2,3",
472    "MSRValue": "0x00",
473    "ELLC": "0",
474    "Filter": "na",
475    "ExtSel": "0",
476    "EVENT_STATUS": "0"
477  },
478  {
479    "Unit": "CBO",
480    "EventCode": "0x1B",
481    "UMask": "0xF",
482    "EventName": "UNC_C_RING_AD_USED.ALL",
483    "BriefDescription": "AD Ring In Use; All",
484    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
485    "Counter": "0,1,2,3",
486    "MSRValue": "0x00",
487    "ELLC": "0",
488    "Filter": "na",
489    "ExtSel": "0",
490    "EVENT_STATUS": "0"
491  },
492  {
493    "Unit": "CBO",
494    "EventCode": "0x1C",
495    "UMask": "0x1",
496    "EventName": "UNC_C_RING_AK_USED.UP_EVEN",
497    "BriefDescription": "AK Ring In Use; Up and Even",
498    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity.",
499    "Counter": "0,1,2,3",
500    "MSRValue": "0x00",
501    "ELLC": "0",
502    "Filter": "na",
503    "ExtSel": "0",
504    "EVENT_STATUS": "0"
505  },
506  {
507    "Unit": "CBO",
508    "EventCode": "0x1C",
509    "UMask": "0x2",
510    "EventName": "UNC_C_RING_AK_USED.UP_ODD",
511    "BriefDescription": "AK Ring In Use; Up and Odd",
512    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity.",
513    "Counter": "0,1,2,3",
514    "MSRValue": "0x00",
515    "ELLC": "0",
516    "Filter": "na",
517    "ExtSel": "0",
518    "EVENT_STATUS": "0"
519  },
520  {
521    "Unit": "CBO",
522    "EventCode": "0x1C",
523    "UMask": "0x4",
524    "EventName": "UNC_C_RING_AK_USED.DOWN_EVEN",
525    "BriefDescription": "AK Ring In Use; Down and Even",
526    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Even ring polarity.",
527    "Counter": "0,1,2,3",
528    "MSRValue": "0x00",
529    "ELLC": "0",
530    "Filter": "na",
531    "ExtSel": "0",
532    "EVENT_STATUS": "0"
533  },
534  {
535    "Unit": "CBO",
536    "EventCode": "0x1C",
537    "UMask": "0x8",
538    "EventName": "UNC_C_RING_AK_USED.DOWN_ODD",
539    "BriefDescription": "AK Ring In Use; Down and Odd",
540    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity.",
541    "Counter": "0,1,2,3",
542    "MSRValue": "0x00",
543    "ELLC": "0",
544    "Filter": "na",
545    "ExtSel": "0",
546    "EVENT_STATUS": "0"
547  },
548  {
549    "Unit": "CBO",
550    "EventCode": "0x1C",
551    "UMask": "0x3",
552    "EventName": "UNC_C_RING_AK_USED.UP",
553    "BriefDescription": "AK Ring In Use; Up",
554    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
555    "Counter": "0,1,2,3",
556    "MSRValue": "0x00",
557    "ELLC": "0",
558    "Filter": "na",
559    "ExtSel": "0",
560    "EVENT_STATUS": "0"
561  },
562  {
563    "Unit": "CBO",
564    "EventCode": "0x1C",
565    "UMask": "0xC",
566    "EventName": "UNC_C_RING_AK_USED.DOWN",
567    "BriefDescription": "AK Ring In Use; Down",
568    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
569    "Counter": "0,1,2,3",
570    "MSRValue": "0x00",
571    "ELLC": "0",
572    "Filter": "na",
573    "ExtSel": "0",
574    "EVENT_STATUS": "0"
575  },
576  {
577    "Unit": "CBO",
578    "EventCode": "0x1C",
579    "UMask": "0xF",
580    "EventName": "UNC_C_RING_AK_USED.ALL",
581    "BriefDescription": "AK Ring In Use; All",
582    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
583    "Counter": "0,1,2,3",
584    "MSRValue": "0x00",
585    "ELLC": "0",
586    "Filter": "na",
587    "ExtSel": "0",
588    "EVENT_STATUS": "0"
589  },
590  {
591    "Unit": "CBO",
592    "EventCode": "0x1D",
593    "UMask": "0x1",
594    "EventName": "UNC_C_RING_BL_USED.UP_EVEN",
595    "BriefDescription": "BL Ring in Use; Up and Even",
596    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity.",
597    "Counter": "0,1,2,3",
598    "MSRValue": "0x00",
599    "ELLC": "0",
600    "Filter": "na",
601    "ExtSel": "0",
602    "EVENT_STATUS": "0"
603  },
604  {
605    "Unit": "CBO",
606    "EventCode": "0x1D",
607    "UMask": "0x2",
608    "EventName": "UNC_C_RING_BL_USED.UP_ODD",
609    "BriefDescription": "BL Ring in Use; Up and Odd",
610    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity.",
611    "Counter": "0,1,2,3",
612    "MSRValue": "0x00",
613    "ELLC": "0",
614    "Filter": "na",
615    "ExtSel": "0",
616    "EVENT_STATUS": "0"
617  },
618  {
619    "Unit": "CBO",
620    "EventCode": "0x1D",
621    "UMask": "0x4",
622    "EventName": "UNC_C_RING_BL_USED.DOWN_EVEN",
623    "BriefDescription": "BL Ring in Use; Down and Even",
624    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Even ring polarity.",
625    "Counter": "0,1,2,3",
626    "MSRValue": "0x00",
627    "ELLC": "0",
628    "Filter": "na",
629    "ExtSel": "0",
630    "EVENT_STATUS": "0"
631  },
632  {
633    "Unit": "CBO",
634    "EventCode": "0x1D",
635    "UMask": "0x8",
636    "EventName": "UNC_C_RING_BL_USED.DOWN_ODD",
637    "BriefDescription": "BL Ring in Use; Down and Odd",
638    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity.",
639    "Counter": "0,1,2,3",
640    "MSRValue": "0x00",
641    "ELLC": "0",
642    "Filter": "na",
643    "ExtSel": "0",
644    "EVENT_STATUS": "0"
645  },
646  {
647    "Unit": "CBO",
648    "EventCode": "0x1D",
649    "UMask": "0x3",
650    "EventName": "UNC_C_RING_BL_USED.UP",
651    "BriefDescription": "BL Ring in Use; Up",
652    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
653    "Counter": "0,1,2,3",
654    "MSRValue": "0x00",
655    "ELLC": "0",
656    "Filter": "na",
657    "ExtSel": "0",
658    "EVENT_STATUS": "0"
659  },
660  {
661    "Unit": "CBO",
662    "EventCode": "0x1D",
663    "UMask": "0xC",
664    "EventName": "UNC_C_RING_BL_USED.DOWN",
665    "BriefDescription": "BL Ring in Use; Down",
666    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
667    "Counter": "0,1,2,3",
668    "MSRValue": "0x00",
669    "ELLC": "0",
670    "Filter": "na",
671    "ExtSel": "0",
672    "EVENT_STATUS": "0"
673  },
674  {
675    "Unit": "CBO",
676    "EventCode": "0x1D",
677    "UMask": "0xF",
678    "EventName": "UNC_C_RING_BL_USED.ALL",
679    "BriefDescription": "BL Ring in Use; Down",
680    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
681    "Counter": "0,1,2,3",
682    "MSRValue": "0x00",
683    "ELLC": "0",
684    "Filter": "na",
685    "ExtSel": "0",
686    "EVENT_STATUS": "0"
687  },
688  {
689    "Unit": "CBO",
690    "EventCode": "0x5",
691    "UMask": "0x1",
692    "EventName": "UNC_C_RING_BOUNCES.AD",
693    "BriefDescription": "Number of LLC responses that bounced on the Ring.; AD",
694    "PublicDescription": "tbd",
695    "Counter": "0,1,2,3",
696    "MSRValue": "0x00",
697    "ELLC": "0",
698    "Filter": "na",
699    "ExtSel": "0",
700    "EVENT_STATUS": "0"
701  },
702  {
703    "Unit": "CBO",
704    "EventCode": "0x5",
705    "UMask": "0x2",
706    "EventName": "UNC_C_RING_BOUNCES.AK",
707    "BriefDescription": "Number of LLC responses that bounced on the Ring.; AK",
708    "PublicDescription": "tbd",
709    "Counter": "0,1,2,3",
710    "MSRValue": "0x00",
711    "ELLC": "0",
712    "Filter": "na",
713    "ExtSel": "0",
714    "EVENT_STATUS": "0"
715  },
716  {
717    "Unit": "CBO",
718    "EventCode": "0x5",
719    "UMask": "0x4",
720    "EventName": "UNC_C_RING_BOUNCES.BL",
721    "BriefDescription": "Number of LLC responses that bounced on the Ring.; BL",
722    "PublicDescription": "tbd",
723    "Counter": "0,1,2,3",
724    "MSRValue": "0x00",
725    "ELLC": "0",
726    "Filter": "na",
727    "ExtSel": "0",
728    "EVENT_STATUS": "0"
729  },
730  {
731    "Unit": "CBO",
732    "EventCode": "0x5",
733    "UMask": "0x10",
734    "EventName": "UNC_C_RING_BOUNCES.IV",
735    "BriefDescription": "Number of LLC responses that bounced on the Ring.; Snoops of processor's cache.",
736    "PublicDescription": "tbd",
737    "Counter": "0,1,2,3",
738    "MSRValue": "0x00",
739    "ELLC": "0",
740    "Filter": "na",
741    "ExtSel": "0",
742    "EVENT_STATUS": "0"
743  },
744  {
745    "Unit": "CBO",
746    "EventCode": "0x1E",
747    "UMask": "0xF",
748    "EventName": "UNC_C_RING_IV_USED.ANY",
749    "BriefDescription": "BL Ring in Use; Any",
750    "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring in HSX  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD.; Filters any polarity",
751    "Counter": "0,1,2,3",
752    "MSRValue": "0x00",
753    "ELLC": "0",
754    "Filter": "na",
755    "ExtSel": "0",
756    "EVENT_STATUS": "0"
757  },
758  {
759    "Unit": "CBO",
760    "EventCode": "0x1E",
761    "UMask": "0x3",
762    "EventName": "UNC_C_RING_IV_USED.UP",
763    "BriefDescription": "BL Ring in Use; Any",
764    "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring in HSX  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD.; Filters any polarity",
765    "Counter": "0,1,2,3",
766    "MSRValue": "0x00",
767    "ELLC": "0",
768    "Filter": "na",
769    "ExtSel": "0",
770    "EVENT_STATUS": "0"
771  },
772  {
773    "Unit": "CBO",
774    "EventCode": "0x1E",
775    "UMask": "0xCC",
776    "EventName": "UNC_C_RING_IV_USED.DOWN",
777    "BriefDescription": "BL Ring in Use; Down",
778    "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring in HSX  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD.; Filters for Down polarity",
779    "Counter": "0,1,2,3",
780    "MSRValue": "0x00",
781    "ELLC": "0",
782    "Filter": "na",
783    "ExtSel": "0",
784    "EVENT_STATUS": "0"
785  },
786  {
787    "Unit": "CBO",
788    "EventCode": "0x1E",
789    "UMask": "0xC",
790    "EventName": "UNC_C_RING_IV_USED.DN",
791    "BriefDescription": "BL Ring in Use; Any",
792    "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring in HSX  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD.; Filters any polarity",
793    "Counter": "0,1,2,3",
794    "MSRValue": "0x00",
795    "ELLC": "0",
796    "Filter": "na",
797    "ExtSel": "0",
798    "EVENT_STATUS": "0"
799  },
800  {
801    "Unit": "CBO",
802    "EventCode": "0x6",
803    "UMask": "0x1",
804    "EventName": "UNC_C_RING_SINK_STARVED.AD",
805    "BriefDescription": "AD",
806    "PublicDescription": "tbd",
807    "Counter": "0,1,2,3",
808    "MSRValue": "0x00",
809    "ELLC": "0",
810    "Filter": "na",
811    "ExtSel": "0",
812    "EVENT_STATUS": "0"
813  },
814  {
815    "Unit": "CBO",
816    "EventCode": "0x6",
817    "UMask": "0x2",
818    "EventName": "UNC_C_RING_SINK_STARVED.AK",
819    "BriefDescription": "AK",
820    "PublicDescription": "tbd",
821    "Counter": "0,1,2,3",
822    "MSRValue": "0x00",
823    "ELLC": "0",
824    "Filter": "na",
825    "ExtSel": "0",
826    "EVENT_STATUS": "0"
827  },
828  {
829    "Unit": "CBO",
830    "EventCode": "0x6",
831    "UMask": "0x8",
832    "EventName": "UNC_C_RING_SINK_STARVED.IV",
833    "BriefDescription": "IV",
834    "PublicDescription": "tbd",
835    "Counter": "0,1,2,3",
836    "MSRValue": "0x00",
837    "ELLC": "0",
838    "Filter": "na",
839    "ExtSel": "0",
840    "EVENT_STATUS": "0"
841  },
842  {
843    "Unit": "CBO",
844    "EventCode": "0x6",
845    "UMask": "0x4",
846    "EventName": "UNC_C_RING_SINK_STARVED.BL",
847    "BriefDescription": "BL",
848    "PublicDescription": "tbd",
849    "Counter": "0,1,2,3",
850    "MSRValue": "0x00",
851    "ELLC": "0",
852    "Filter": "na",
853    "ExtSel": "0",
854    "EVENT_STATUS": "0"
855  },
856  {
857    "Unit": "CBO",
858    "EventCode": "0x7",
859    "UMask": "0x0",
860    "EventName": "UNC_C_RING_SRC_THRTL",
861    "BriefDescription": "Number of cycles the Cbo is actively throttling traffic onto the Ring in order to limit bounce traffic.",
862    "PublicDescription": "tbd",
863    "Counter": "0,1,2,3",
864    "MSRValue": "0x00",
865    "ELLC": "0",
866    "Filter": "na",
867    "ExtSel": "0",
868    "EVENT_STATUS": "0"
869  },
870  {
871    "Unit": "CBO",
872    "EventCode": "0x12",
873    "UMask": "0x1",
874    "EventName": "UNC_C_RxR_EXT_STARVED.IRQ",
875    "BriefDescription": "Ingress Arbiter Blocking Cycles; IPQ",
876    "PublicDescription": "Counts cycles in external starvation.  This occurs when one of the ingress queues is being starved by the other queues.; IRQ is externally starved and therefore we are blocking the IPQ.",
877    "Counter": "0,1,2,3",
878    "MSRValue": "0x00",
879    "ELLC": "0",
880    "Filter": "na",
881    "ExtSel": "0",
882    "EVENT_STATUS": "0"
883  },
884  {
885    "Unit": "CBO",
886    "EventCode": "0x12",
887    "UMask": "0x2",
888    "EventName": "UNC_C_RxR_EXT_STARVED.IPQ",
889    "BriefDescription": "Ingress Arbiter Blocking Cycles; IRQ",
890    "PublicDescription": "Counts cycles in external starvation.  This occurs when one of the ingress queues is being starved by the other queues.; IPQ is externally startved and therefore we are blocking the IRQ.",
891    "Counter": "0,1,2,3",
892    "MSRValue": "0x00",
893    "ELLC": "0",
894    "Filter": "na",
895    "ExtSel": "0",
896    "EVENT_STATUS": "0"
897  },
898  {
899    "Unit": "CBO",
900    "EventCode": "0x12",
901    "UMask": "0x4",
902    "EventName": "UNC_C_RxR_EXT_STARVED.PRQ",
903    "BriefDescription": "Ingress Arbiter Blocking Cycles; PRQ",
904    "PublicDescription": "Counts cycles in external starvation.  This occurs when one of the ingress queues is being starved by the other queues.",
905    "Counter": "0,1,2,3",
906    "MSRValue": "0x00",
907    "ELLC": "0",
908    "Filter": "na",
909    "ExtSel": "0",
910    "EVENT_STATUS": "0"
911  },
912  {
913    "Unit": "CBO",
914    "EventCode": "0x12",
915    "UMask": "0x8",
916    "EventName": "UNC_C_RxR_EXT_STARVED.ISMQ_BIDS",
917    "BriefDescription": "Ingress Arbiter Blocking Cycles; ISMQ_BID",
918    "PublicDescription": "Counts cycles in external starvation.  This occurs when one of the ingress queues is being starved by the other queues.; Number of times that the ISMQ Bid.",
919    "Counter": "0,1,2,3",
920    "MSRValue": "0x00",
921    "ELLC": "0",
922    "Filter": "na",
923    "ExtSel": "0",
924    "EVENT_STATUS": "0"
925  },
926  {
927    "Unit": "CBO",
928    "EventCode": "0x13",
929    "UMask": "0x1",
930    "EventName": "UNC_C_RxR_INSERTS.IRQ",
931    "BriefDescription": "Ingress Allocations; IRQ",
932    "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.",
933    "Counter": "0,1,2,3",
934    "MSRValue": "0x00",
935    "ELLC": "0",
936    "Filter": "na",
937    "ExtSel": "0",
938    "EVENT_STATUS": "0"
939  },
940  {
941    "Unit": "CBO",
942    "EventCode": "0x13",
943    "UMask": "0x2",
944    "EventName": "UNC_C_RxR_INSERTS.IRQ_REJ",
945    "BriefDescription": "Ingress Allocations; IRQ Rejected",
946    "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.",
947    "Counter": "0,1,2,3",
948    "MSRValue": "0x00",
949    "ELLC": "0",
950    "Filter": "na",
951    "ExtSel": "0",
952    "EVENT_STATUS": "0"
953  },
954  {
955    "Unit": "CBO",
956    "EventCode": "0x13",
957    "UMask": "0x4",
958    "EventName": "UNC_C_RxR_INSERTS.IPQ",
959    "BriefDescription": "Ingress Allocations; IPQ",
960    "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.",
961    "Counter": "0,1,2,3",
962    "MSRValue": "0x00",
963    "ELLC": "0",
964    "Filter": "na",
965    "ExtSel": "0",
966    "EVENT_STATUS": "0"
967  },
968  {
969    "Unit": "CBO",
970    "EventCode": "0x13",
971    "UMask": "0x10",
972    "EventName": "UNC_C_RxR_INSERTS.PRQ",
973    "BriefDescription": "Ingress Allocations; PRQ",
974    "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.",
975    "Counter": "0,1,2,3",
976    "MSRValue": "0x00",
977    "ELLC": "0",
978    "Filter": "na",
979    "ExtSel": "0",
980    "EVENT_STATUS": "0"
981  },
982  {
983    "Unit": "CBO",
984    "EventCode": "0x13",
985    "UMask": "0x20",
986    "EventName": "UNC_C_RxR_INSERTS.PRQ_REJ",
987    "BriefDescription": "Ingress Allocations; PRQ",
988    "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.",
989    "Counter": "0,1,2,3",
990    "MSRValue": "0x00",
991    "ELLC": "0",
992    "Filter": "na",
993    "ExtSel": "0",
994    "EVENT_STATUS": "0"
995  },
996  {
997    "Unit": "CBO",
998    "EventCode": "0x14",
999    "UMask": "0x1",
1000    "EventName": "UNC_C_RxR_INT_STARVED.IRQ",
1001    "BriefDescription": "Ingress Internal Starvation Cycles; IRQ",
1002    "PublicDescription": "Counts cycles in internal starvation.  This occurs when one (or more) of the entries in the ingress queue are being starved out by other entries in that queue.; Cycles with the IRQ in Internal Starvation.",
1003    "Counter": "0,1,2,3",
1004    "MSRValue": "0x00",
1005    "ELLC": "0",
1006    "Filter": "na",
1007    "ExtSel": "0",
1008    "EVENT_STATUS": "0"
1009  },
1010  {
1011    "Unit": "CBO",
1012    "EventCode": "0x14",
1013    "UMask": "0x4",
1014    "EventName": "UNC_C_RxR_INT_STARVED.IPQ",
1015    "BriefDescription": "Ingress Internal Starvation Cycles; IPQ",
1016    "PublicDescription": "Counts cycles in internal starvation.  This occurs when one (or more) of the entries in the ingress queue are being starved out by other entries in that queue.; Cycles with the IPQ in Internal Starvation.",
1017    "Counter": "0,1,2,3",
1018    "MSRValue": "0x00",
1019    "ELLC": "0",
1020    "Filter": "na",
1021    "ExtSel": "0",
1022    "EVENT_STATUS": "0"
1023  },
1024  {
1025    "Unit": "CBO",
1026    "EventCode": "0x14",
1027    "UMask": "0x8",
1028    "EventName": "UNC_C_RxR_INT_STARVED.ISMQ",
1029    "BriefDescription": "Ingress Internal Starvation Cycles; ISMQ",
1030    "PublicDescription": "Counts cycles in internal starvation.  This occurs when one (or more) of the entries in the ingress queue are being starved out by other entries in that queue.; Cycles with the ISMQ in Internal Starvation.",
1031    "Counter": "0,1,2,3",
1032    "MSRValue": "0x00",
1033    "ELLC": "0",
1034    "Filter": "na",
1035    "ExtSel": "0",
1036    "EVENT_STATUS": "0"
1037  },
1038  {
1039    "Unit": "CBO",
1040    "EventCode": "0x14",
1041    "UMask": "0x10",
1042    "EventName": "UNC_C_RxR_INT_STARVED.PRQ",
1043    "BriefDescription": "Ingress Internal Starvation Cycles; PRQ",
1044    "PublicDescription": "Counts cycles in internal starvation.  This occurs when one (or more) of the entries in the ingress queue are being starved out by other entries in that queue.",
1045    "Counter": "0,1,2,3",
1046    "MSRValue": "0x00",
1047    "ELLC": "0",
1048    "Filter": "na",
1049    "ExtSel": "0",
1050    "EVENT_STATUS": "0"
1051  },
1052  {
1053    "Unit": "CBO",
1054    "EventCode": "0x31",
1055    "UMask": "0x1",
1056    "EventName": "UNC_C_RxR_IPQ_RETRY.ANY",
1057    "BriefDescription": "Probe Queue Retries; Any Reject",
1058    "PublicDescription": "Number of times a snoop (probe) request had to retry.  Filters exist to cover some of the common cases retries.; Counts the number of times that a request form the IPQ was retried because of a TOR reject.  TOR rejects from the IPQ can be caused by the Egress being full or Address Conflicts.",
1059    "Counter": "0,1,2,3",
1060    "MSRValue": "0x00",
1061    "ELLC": "0",
1062    "Filter": "na",
1063    "ExtSel": "0",
1064    "EVENT_STATUS": "0"
1065  },
1066  {
1067    "Unit": "CBO",
1068    "EventCode": "0x31",
1069    "UMask": "0x2",
1070    "EventName": "UNC_C_RxR_IPQ_RETRY.FULL",
1071    "BriefDescription": "Probe Queue Retries; No Egress Credits",
1072    "PublicDescription": "Number of times a snoop (probe) request had to retry.  Filters exist to cover some of the common cases retries.; Counts the number of times that a request form the IPQ was retried because of a TOR reject from the Egress being full.  IPQ requests make use of the AD Egress for regular responses, the BL egress to forward data, and the AK egress to return credits.",
1073    "Counter": "0,1,2,3",
1074    "MSRValue": "0x00",
1075    "ELLC": "0",
1076    "Filter": "na",
1077    "ExtSel": "0",
1078    "EVENT_STATUS": "0"
1079  },
1080  {
1081    "Unit": "CBO",
1082    "EventCode": "0x31",
1083    "UMask": "0x4",
1084    "EventName": "UNC_C_RxR_IPQ_RETRY.ADDR_CONFLICT",
1085    "BriefDescription": "Probe Queue Retries; Address Conflict",
1086    "PublicDescription": "Number of times a snoop (probe) request had to retry.  Filters exist to cover some of the common cases retries.; Counts the number of times that a request form the IPQ was retried because of a TOR reject from an address conflicts.  Address conflicts out of the IPQ should be rare.  They will generally only occur if two different sockets are sending requests to the same address at the same time.  This is a true conflict case, unlike the IPQ Address Conflict which is commonly caused by prefetching characteristics.",
1087    "Counter": "0,1,2,3",
1088    "MSRValue": "0x00",
1089    "ELLC": "0",
1090    "Filter": "na",
1091    "ExtSel": "0",
1092    "EVENT_STATUS": "0"
1093  },
1094  {
1095    "Unit": "CBO",
1096    "EventCode": "0x31",
1097    "UMask": "0x10",
1098    "EventName": "UNC_C_RxR_IPQ_RETRY.QPI_CREDITS",
1099    "BriefDescription": "Probe Queue Retries; No QPI Credits",
1100    "PublicDescription": "Number of times a snoop (probe) request had to retry.  Filters exist to cover some of the common cases retries.",
1101    "Counter": "0,1,2,3",
1102    "MSRValue": "0x00",
1103    "ELLC": "0",
1104    "Filter": "na",
1105    "ExtSel": "0",
1106    "EVENT_STATUS": "0"
1107  },
1108  {
1109    "Unit": "CBO",
1110    "EventCode": "0x28",
1111    "UMask": "0x1",
1112    "EventName": "UNC_C_RxR_IPQ_RETRY2.AD_SBO",
1113    "BriefDescription": "Probe Queue Retries; No AD Sbo Credits",
1114    "PublicDescription": "Number of times a snoop (probe) request had to retry.  Filters exist to cover some of the common cases retries.; Counts the number of times that a request from the IPQ was retried because of it lacked credits to send an AD packet to the Sbo.",
1115    "Counter": "0,1,2,3",
1116    "MSRValue": "0x00",
1117    "ELLC": "0",
1118    "Filter": "na",
1119    "ExtSel": "0",
1120    "EVENT_STATUS": "0"
1121  },
1122  {
1123    "Unit": "CBO",
1124    "EventCode": "0x28",
1125    "UMask": "0x40",
1126    "EventName": "UNC_C_RxR_IPQ_RETRY2.TARGET",
1127    "BriefDescription": "Probe Queue Retries; Target Node Filter",
1128    "PublicDescription": "Number of times a snoop (probe) request had to retry.  Filters exist to cover some of the common cases retries.; Counts the number of times that a request from the IPQ was retried filtered by the Target NodeID as specified in the Cbox's Filter register.",
1129    "Counter": "0,1,2,3",
1130    "MSRValue": "0x00",
1131    "ELLC": "0",
1132    "Filter": "CBoFilter1[15:0]",
1133    "ExtSel": "0",
1134    "EVENT_STATUS": "0"
1135  },
1136  {
1137    "Unit": "CBO",
1138    "EventCode": "0x32",
1139    "UMask": "0x1",
1140    "EventName": "UNC_C_RxR_IRQ_RETRY.ANY",
1141    "BriefDescription": "Ingress Request Queue Rejects; Any Reject",
1142    "PublicDescription": "Counts the number of IRQ retries that occur.  Requests from the IRQ are retried if they are rejected from the TOR pipeline for a variety of reasons.  Some of the most common reasons include if the Egress is full, there are no RTIDs, or there is a Physical Address match to another outstanding request.",
1143    "Counter": "0,1,2,3",
1144    "MSRValue": "0x00",
1145    "ELLC": "0",
1146    "Filter": "na",
1147    "ExtSel": "0",
1148    "EVENT_STATUS": "0"
1149  },
1150  {
1151    "Unit": "CBO",
1152    "EventCode": "0x32",
1153    "UMask": "0x2",
1154    "EventName": "UNC_C_RxR_IRQ_RETRY.FULL",
1155    "BriefDescription": "Ingress Request Queue Rejects; No Egress Credits",
1156    "PublicDescription": "Counts the number of times that a request from the IRQ was retried because it failed to acquire an entry in the Egress.  The egress is the buffer that queues up for allocating onto the ring.  IRQ requests can make use of all four rings and all four Egresses.  If any of the queues that a given request needs to make use of are full, the request will be retried.",
1157    "Counter": "0,1,2,3",
1158    "MSRValue": "0x00",
1159    "ELLC": "0",
1160    "Filter": "na",
1161    "ExtSel": "0",
1162    "EVENT_STATUS": "0"
1163  },
1164  {
1165    "Unit": "CBO",
1166    "EventCode": "0x32",
1167    "UMask": "0x4",
1168    "EventName": "UNC_C_RxR_IRQ_RETRY.ADDR_CONFLICT",
1169    "BriefDescription": "Ingress Request Queue Rejects; Address Conflict",
1170    "PublicDescription": "Counts the number of times that a request from the IRQ was retried because of an address match in the TOR.  In order to maintain coherency, requests to the same address are not allowed to pass each other up in the Cbo.  Therefore, if there is an outstanding request to a given address, one cannot issue another request to that address until it is complete.  This comes up most commonly with prefetches.  Outstanding prefetches occasionally will not complete their memory fetch and a demand request to the same address will then sit in the IRQ and get retried until the prefetch fills the data into the LLC.  Therefore, it will not be uncommon to see this case in high bandwidth streaming workloads when the LLC Prefetcher in the core is enabled.",
1171    "Counter": "0,1,2,3",
1172    "MSRValue": "0x00",
1173    "ELLC": "0",
1174    "Filter": "na",
1175    "ExtSel": "0",
1176    "EVENT_STATUS": "0"
1177  },
1178  {
1179    "Unit": "CBO",
1180    "EventCode": "0x32",
1181    "UMask": "0x8",
1182    "EventName": "UNC_C_RxR_IRQ_RETRY.RTID",
1183    "BriefDescription": "Ingress Request Queue Rejects; No RTIDs",
1184    "PublicDescription": "Counts the number of times that requests from the IRQ were retried because there were no RTIDs available.  RTIDs are required after a request misses the LLC and needs to send snoops and/or requests to memory.  If there are no RTIDs available, requests will queue up in the IRQ and retry until one becomes available.  Note that there are multiple RTID pools for the different sockets.  There may be cases where the local RTIDs are all used, but requests destined for remote memory can still acquire an RTID because there are remote RTIDs available.  This event does not provide any filtering for this case.",
1185    "Counter": "0,1,2,3",
1186    "MSRValue": "0x00",
1187    "ELLC": "0",
1188    "Filter": "na",
1189    "ExtSel": "0",
1190    "EVENT_STATUS": "0"
1191  },
1192  {
1193    "Unit": "CBO",
1194    "EventCode": "0x32",
1195    "UMask": "0x10",
1196    "EventName": "UNC_C_RxR_IRQ_RETRY.QPI_CREDITS",
1197    "BriefDescription": "Ingress Request Queue Rejects; No QPI Credits",
1198    "PublicDescription": "Number of requests rejects because of lack of QPI Ingress credits.  These credits are required in order to send transactions to the QPI agent.  Please see the QPI_IGR_CREDITS events for more information.",
1199    "Counter": "0,1,2,3",
1200    "MSRValue": "0x00",
1201    "ELLC": "0",
1202    "Filter": "na",
1203    "ExtSel": "0",
1204    "EVENT_STATUS": "0"
1205  },
1206  {
1207    "Unit": "CBO",
1208    "EventCode": "0x32",
1209    "UMask": "0x20",
1210    "EventName": "UNC_C_RxR_IRQ_RETRY.IIO_CREDITS",
1211    "BriefDescription": "Ingress Request Queue Rejects; No IIO Credits",
1212    "PublicDescription": "Number of times a request attempted to acquire the NCS/NCB credit for sending messages on BL to the IIO.  There is a single credit in each CBo that is shared between the NCS and NCB message classes for sending transactions on the BL ring (such as read data) to the IIO.",
1213    "Counter": "0,1,2,3",
1214    "MSRValue": "0x00",
1215    "ELLC": "0",
1216    "Filter": "na",
1217    "ExtSel": "0",
1218    "EVENT_STATUS": "0"
1219  },
1220  {
1221    "Unit": "CBO",
1222    "EventCode": "0x32",
1223    "UMask": "0x40",
1224    "EventName": "UNC_C_RxR_IRQ_RETRY.NID",
1225    "BriefDescription": "Ingress Request Queue Rejects",
1226    "PublicDescription": "Qualify one of the other subevents by a given RTID destination NID.  The NID is programmed in Cn_MSR_PMON_BOX_FILTER1.nid.",
1227    "Counter": "0,1,2,3",
1228    "MSRValue": "0x00",
1229    "ELLC": "0",
1230    "Filter": "CBoFilter1[15:0]",
1231    "ExtSel": "0",
1232    "EVENT_STATUS": "0"
1233  },
1234  {
1235    "Unit": "CBO",
1236    "EventCode": "0x29",
1237    "UMask": "0x1",
1238    "EventName": "UNC_C_RxR_IRQ_RETRY2.AD_SBO",
1239    "BriefDescription": "Ingress Request Queue Rejects; No AD Sbo Credits",
1240    "PublicDescription": "Counts the number of times that a request from the IPQ was retried because of it lacked credits to send an AD packet to the Sbo.",
1241    "Counter": "0,1,2,3",
1242    "MSRValue": "0x00",
1243    "ELLC": "0",
1244    "Filter": "na",
1245    "ExtSel": "0",
1246    "EVENT_STATUS": "0"
1247  },
1248  {
1249    "Unit": "CBO",
1250    "EventCode": "0x29",
1251    "UMask": "0x2",
1252    "EventName": "UNC_C_RxR_IRQ_RETRY2.BL_SBO",
1253    "BriefDescription": "Ingress Request Queue Rejects; No BL Sbo Credits",
1254    "PublicDescription": "Counts the number of times that a request from the IPQ was retried because of it lacked credits to send an BL packet to the Sbo.",
1255    "Counter": "0,1,2,3",
1256    "MSRValue": "0x00",
1257    "ELLC": "0",
1258    "Filter": "na",
1259    "ExtSel": "0",
1260    "EVENT_STATUS": "0"
1261  },
1262  {
1263    "Unit": "CBO",
1264    "EventCode": "0x29",
1265    "UMask": "0x40",
1266    "EventName": "UNC_C_RxR_IRQ_RETRY2.TARGET",
1267    "BriefDescription": "Ingress Request Queue Rejects; Target Node Filter",
1268    "PublicDescription": "Counts the number of times that a request from the IPQ was retried filtered by the Target NodeID as specified in the Cbox's Filter register.",
1269    "Counter": "0,1,2,3",
1270    "MSRValue": "0x00",
1271    "ELLC": "0",
1272    "Filter": "CBoFilter1[15:0]",
1273    "ExtSel": "0",
1274    "EVENT_STATUS": "0"
1275  },
1276  {
1277    "Unit": "CBO",
1278    "EventCode": "0x33",
1279    "UMask": "0x1",
1280    "EventName": "UNC_C_RxR_ISMQ_RETRY.ANY",
1281    "BriefDescription": "ISMQ Retries; Any Reject",
1282    "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.; Counts the total number of times that a request from the ISMQ retried because of a TOR reject.  ISMQ requests generally will not need to retry (or at least ISMQ retries are less common than IRQ retries).  ISMQ requests will retry if they are not able to acquire a needed Egress credit to get onto the ring, or for cache evictions that need to acquire an RTID.  Most ISMQ requests already have an RTID, so eviction retries will be less common here.",
1283    "Counter": "0,1,2,3",
1284    "MSRValue": "0x00",
1285    "ELLC": "0",
1286    "Filter": "na",
1287    "ExtSel": "0",
1288    "EVENT_STATUS": "0"
1289  },
1290  {
1291    "Unit": "CBO",
1292    "EventCode": "0x33",
1293    "UMask": "0x2",
1294    "EventName": "UNC_C_RxR_ISMQ_RETRY.FULL",
1295    "BriefDescription": "ISMQ Retries; No Egress Credits",
1296    "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.; Counts the number of times that a request from the ISMQ retried because of a TOR reject caused by a lack of Egress credits. The egress is the buffer that queues up for allocating onto the ring.  If any of the Egress queues that a given request needs to make use of are full, the request will be retried.",
1297    "Counter": "0,1,2,3",
1298    "MSRValue": "0x00",
1299    "ELLC": "0",
1300    "Filter": "na",
1301    "ExtSel": "0",
1302    "EVENT_STATUS": "0"
1303  },
1304  {
1305    "Unit": "CBO",
1306    "EventCode": "0x33",
1307    "UMask": "0x8",
1308    "EventName": "UNC_C_RxR_ISMQ_RETRY.RTID",
1309    "BriefDescription": "ISMQ Retries; No RTIDs",
1310    "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.; Counts the number of times that a request from the ISMQ retried because of a TOR reject caused by no RTIDs.  M-state cache evictions are serviced through the ISMQ, and must acquire an RTID in order to write back to memory.  If no RTIDs are available, they will be retried.",
1311    "Counter": "0,1,2,3",
1312    "MSRValue": "0x00",
1313    "ELLC": "0",
1314    "Filter": "na",
1315    "ExtSel": "0",
1316    "EVENT_STATUS": "0"
1317  },
1318  {
1319    "Unit": "CBO",
1320    "EventCode": "0x33",
1321    "UMask": "0x10",
1322    "EventName": "UNC_C_RxR_ISMQ_RETRY.QPI_CREDITS",
1323    "BriefDescription": "ISMQ Retries; No QPI Credits",
1324    "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.",
1325    "Counter": "0,1,2,3",
1326    "MSRValue": "0x00",
1327    "ELLC": "0",
1328    "Filter": "na",
1329    "ExtSel": "0",
1330    "EVENT_STATUS": "0"
1331  },
1332  {
1333    "Unit": "CBO",
1334    "EventCode": "0x33",
1335    "UMask": "0x20",
1336    "EventName": "UNC_C_RxR_ISMQ_RETRY.IIO_CREDITS",
1337    "BriefDescription": "ISMQ Retries; No IIO Credits",
1338    "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.; Number of times a request attempted to acquire the NCS/NCB credit for sending messages on BL to the IIO.  There is a single credit in each CBo that is shared between the NCS and NCB message classes for sending transactions on the BL ring (such as read data) to the IIO.",
1339    "Counter": "0,1,2,3",
1340    "MSRValue": "0x00",
1341    "ELLC": "0",
1342    "Filter": "na",
1343    "ExtSel": "0",
1344    "EVENT_STATUS": "0"
1345  },
1346  {
1347    "Unit": "CBO",
1348    "EventCode": "0x33",
1349    "UMask": "0x80",
1350    "EventName": "UNC_C_RxR_ISMQ_RETRY.WB_CREDITS",
1351    "BriefDescription": "ISMQ Retries",
1352    "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.; Qualify one of the other subevents by a given RTID destination NID.  The NID is programmed in Cn_MSR_PMON_BOX_FILTER1.nid.",
1353    "Counter": "0,1,2,3",
1354    "MSRValue": "0x00",
1355    "ELLC": "0",
1356    "Filter": "CBoFilter1[15:0]",
1357    "ExtSel": "0",
1358    "EVENT_STATUS": "0"
1359  },
1360  {
1361    "Unit": "CBO",
1362    "EventCode": "0x33",
1363    "UMask": "0x40",
1364    "EventName": "UNC_C_RxR_ISMQ_RETRY.NID",
1365    "BriefDescription": "ISMQ Retries",
1366    "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.; Qualify one of the other subevents by a given RTID destination NID.  The NID is programmed in Cn_MSR_PMON_BOX_FILTER1.nid.",
1367    "Counter": "0,1,2,3",
1368    "MSRValue": "0x00",
1369    "ELLC": "0",
1370    "Filter": "CBoFilter1[15:0]",
1371    "ExtSel": "0",
1372    "EVENT_STATUS": "0"
1373  },
1374  {
1375    "Unit": "CBO",
1376    "EventCode": "0x2A",
1377    "UMask": "0x1",
1378    "EventName": "UNC_C_RxR_ISMQ_RETRY2.AD_SBO",
1379    "BriefDescription": "ISMQ Request Queue Rejects; No AD Sbo Credits",
1380    "PublicDescription": "Counts the number of times that a request from the ISMQ was retried because of it lacked credits to send an AD packet to the Sbo.",
1381    "Counter": "0,1,2,3",
1382    "MSRValue": "0x00",
1383    "ELLC": "0",
1384    "Filter": "na",
1385    "ExtSel": "0",
1386    "EVENT_STATUS": "0"
1387  },
1388  {
1389    "Unit": "CBO",
1390    "EventCode": "0x2A",
1391    "UMask": "0x2",
1392    "EventName": "UNC_C_RxR_ISMQ_RETRY2.BL_SBO",
1393    "BriefDescription": "ISMQ Request Queue Rejects; No BL Sbo Credits",
1394    "PublicDescription": "Counts the number of times that a request from the ISMQ was retried because of it lacked credits to send an BL packet to the Sbo.",
1395    "Counter": "0,1,2,3",
1396    "MSRValue": "0x00",
1397    "ELLC": "0",
1398    "Filter": "na",
1399    "ExtSel": "0",
1400    "EVENT_STATUS": "0"
1401  },
1402  {
1403    "Unit": "CBO",
1404    "EventCode": "0x2A",
1405    "UMask": "0x40",
1406    "EventName": "UNC_C_RxR_ISMQ_RETRY2.TARGET",
1407    "BriefDescription": "ISMQ Request Queue Rejects; Target Node Filter",
1408    "PublicDescription": "Counts the number of times that a request from the ISMQ was retried filtered by the Target NodeID as specified in the Cbox's Filter register.",
1409    "Counter": "0,1,2,3",
1410    "MSRValue": "0x00",
1411    "ELLC": "0",
1412    "Filter": "CBoFilter1[15:0]",
1413    "ExtSel": "0",
1414    "EVENT_STATUS": "0"
1415  },
1416  {
1417    "Unit": "CBO",
1418    "EventCode": "0x11",
1419    "UMask": "0x1",
1420    "EventName": "UNC_C_RxR_OCCUPANCY.IRQ",
1421    "BriefDescription": "Ingress Occupancy; IRQ",
1422    "PublicDescription": "Counts number of entries in the specified Ingress queue in each cycle.",
1423    "Counter": "0",
1424    "MSRValue": "0x00",
1425    "ELLC": "0",
1426    "Filter": "na",
1427    "ExtSel": "0",
1428    "EVENT_STATUS": "0"
1429  },
1430  {
1431    "Unit": "CBO",
1432    "EventCode": "0x11",
1433    "UMask": "0x4",
1434    "EventName": "UNC_C_RxR_OCCUPANCY.IPQ",
1435    "BriefDescription": "Ingress Occupancy; IPQ",
1436    "PublicDescription": "Counts number of entries in the specified Ingress queue in each cycle.",
1437    "Counter": "0",
1438    "MSRValue": "0x00",
1439    "ELLC": "0",
1440    "Filter": "na",
1441    "ExtSel": "0",
1442    "EVENT_STATUS": "0"
1443  },
1444  {
1445    "Unit": "CBO",
1446    "EventCode": "0x11",
1447    "UMask": "0x20",
1448    "EventName": "UNC_C_RxR_OCCUPANCY.PRQ_REJ",
1449    "BriefDescription": "Ingress Occupancy; PRQ Rejects",
1450    "PublicDescription": "Counts number of entries in the specified Ingress queue in each cycle.",
1451    "Counter": "0",
1452    "MSRValue": "0x00",
1453    "ELLC": "0",
1454    "Filter": "na",
1455    "ExtSel": "0",
1456    "EVENT_STATUS": "0"
1457  },
1458  {
1459    "Unit": "CBO",
1460    "EventCode": "0x3D",
1461    "UMask": "0x1",
1462    "EventName": "UNC_C_SBO_CREDITS_ACQUIRED.AD",
1463    "BriefDescription": "SBo Credits Acquired; For AD Ring",
1464    "PublicDescription": "Number of Sbo credits acquired in a given cycle, per ring.  Each Cbo is assigned an Sbo it can communicate with.",
1465    "Counter": "0,1,2,3",
1466    "MSRValue": "0x00",
1467    "ELLC": "0",
1468    "Filter": "na",
1469    "ExtSel": "0",
1470    "EVENT_STATUS": "0"
1471  },
1472  {
1473    "Unit": "CBO",
1474    "EventCode": "0x3D",
1475    "UMask": "0x2",
1476    "EventName": "UNC_C_SBO_CREDITS_ACQUIRED.BL",
1477    "BriefDescription": "SBo Credits Acquired; For BL Ring",
1478    "PublicDescription": "Number of Sbo credits acquired in a given cycle, per ring.  Each Cbo is assigned an Sbo it can communicate with.",
1479    "Counter": "0,1,2,3",
1480    "MSRValue": "0x00",
1481    "ELLC": "0",
1482    "Filter": "na",
1483    "ExtSel": "0",
1484    "EVENT_STATUS": "0"
1485  },
1486  {
1487    "Unit": "CBO",
1488    "EventCode": "0x3E",
1489    "UMask": "0x1",
1490    "EventName": "UNC_C_SBO_CREDIT_OCCUPANCY.AD",
1491    "BriefDescription": "SBo Credits Occupancy; For AD Ring",
1492    "PublicDescription": "Number of Sbo credits in use in a given cycle, per ring.  Each Cbo is assigned an Sbo it can communicate with.",
1493    "Counter": "0",
1494    "MSRValue": "0x00",
1495    "ELLC": "0",
1496    "Filter": "na",
1497    "ExtSel": "0",
1498    "EVENT_STATUS": "0"
1499  },
1500  {
1501    "Unit": "CBO",
1502    "EventCode": "0x3E",
1503    "UMask": "0x2",
1504    "EventName": "UNC_C_SBO_CREDIT_OCCUPANCY.BL",
1505    "BriefDescription": "SBo Credits Occupancy; For BL Ring",
1506    "PublicDescription": "Number of Sbo credits in use in a given cycle, per ring.  Each Cbo is assigned an Sbo it can communicate with.",
1507    "Counter": "0",
1508    "MSRValue": "0x00",
1509    "ELLC": "0",
1510    "Filter": "na",
1511    "ExtSel": "0",
1512    "EVENT_STATUS": "0"
1513  },
1514  {
1515    "Unit": "CBO",
1516    "EventCode": "0x35",
1517    "UMask": "0x1",
1518    "EventName": "UNC_C_TOR_INSERTS.OPCODE",
1519    "BriefDescription": "TOR Inserts; Opcode Match",
1520    "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)",
1521    "Counter": "0,1,2,3",
1522    "MSRValue": "0x00",
1523    "ELLC": "0",
1524    "Filter": "CBoFilter1[28:20]",
1525    "ExtSel": "0",
1526    "EVENT_STATUS": "0"
1527  },
1528  {
1529    "Unit": "CBO",
1530    "EventCode": "0x35",
1531    "UMask": "0x4",
1532    "EventName": "UNC_C_TOR_INSERTS.EVICTION",
1533    "BriefDescription": "TOR Inserts; Evictions",
1534    "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Eviction transactions inserted into the TOR.  Evictions can be quick, such as when the line is in the F, S, or E states and no core valid bits are set.  They can also be longer if either CV bits are set (so the cores need to be snooped) and/or if there is a HitM (in which case it is necessary to write the request out to memory).",
1535    "Counter": "0,1,2,3",
1536    "MSRValue": "0x00",
1537    "ELLC": "0",
1538    "Filter": "na",
1539    "ExtSel": "0",
1540    "EVENT_STATUS": "0"
1541  },
1542  {
1543    "Unit": "CBO",
1544    "EventCode": "0x35",
1545    "UMask": "0x8",
1546    "EventName": "UNC_C_TOR_INSERTS.ALL",
1547    "BriefDescription": "TOR Inserts; All",
1548    "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; All transactions inserted into the TOR.    This includes requests that reside in the TOR for a short time, such as LLC Hits that do not need to snoop cores or requests that get rejected and have to be retried through one of the ingress queues.  The TOR is more commonly a bottleneck in skews with smaller core counts, where the ratio of RTIDs to TOR entries is larger.  Note that there are reserved TOR entries for various request types, so it is possible that a given request type be blocked with an occupancy that is less than 20.  Also note that generally requests will not be able to arbitrate into the TOR pipeline if there are no available TOR slots.",
1549    "Counter": "0,1,2,3",
1550    "MSRValue": "0x00",
1551    "ELLC": "0",
1552    "Filter": "na",
1553    "ExtSel": "0",
1554    "EVENT_STATUS": "0"
1555  },
1556  {
1557    "Unit": "CBO",
1558    "EventCode": "0x35",
1559    "UMask": "0x10",
1560    "EventName": "UNC_C_TOR_INSERTS.WB",
1561    "BriefDescription": "TOR Inserts; Writebacks",
1562    "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Write transactions inserted into the TOR.   This does not include RFO, but actual operations that contain data being sent from the core.",
1563    "Counter": "0,1,2,3",
1564    "MSRValue": "0x00",
1565    "ELLC": "0",
1566    "Filter": "na",
1567    "ExtSel": "0",
1568    "EVENT_STATUS": "0"
1569  },
1570  {
1571    "Unit": "CBO",
1572    "EventCode": "0x35",
1573    "UMask": "0x3",
1574    "EventName": "UNC_C_TOR_INSERTS.MISS_OPCODE",
1575    "BriefDescription": "TOR Inserts; Miss Opcode Match",
1576    "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.",
1577    "Counter": "0,1,2,3",
1578    "MSRValue": "0x00",
1579    "ELLC": "0",
1580    "Filter": "CBoFilter1[28:20]",
1581    "ExtSel": "0",
1582    "EVENT_STATUS": "0"
1583  },
1584  {
1585    "Unit": "CBO",
1586    "EventCode": "0x35",
1587    "UMask": "0x41",
1588    "EventName": "UNC_C_TOR_INSERTS.NID_OPCODE",
1589    "BriefDescription": "TOR Inserts; NID and Opcode Matched",
1590    "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Transactions inserted into the TOR that match a NID and an opcode.",
1591    "Counter": "0,1,2,3",
1592    "MSRValue": "0x00",
1593    "ELLC": "0",
1594    "Filter": "CBoFilter1[28:20], CBoFilter1[15:0]",
1595    "ExtSel": "0",
1596    "EVENT_STATUS": "0"
1597  },
1598  {
1599    "Unit": "CBO",
1600    "EventCode": "0x35",
1601    "UMask": "0x44",
1602    "EventName": "UNC_C_TOR_INSERTS.NID_EVICTION",
1603    "BriefDescription": "TOR Inserts; NID Matched Evictions",
1604    "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; NID matched eviction transactions inserted into the TOR.",
1605    "Counter": "0,1,2,3",
1606    "MSRValue": "0x00",
1607    "ELLC": "0",
1608    "Filter": "CBoFilter1[15:0]",
1609    "ExtSel": "0",
1610    "EVENT_STATUS": "0"
1611  },
1612  {
1613    "Unit": "CBO",
1614    "EventCode": "0x35",
1615    "UMask": "0x48",
1616    "EventName": "UNC_C_TOR_INSERTS.NID_ALL",
1617    "BriefDescription": "TOR Inserts; NID Matched",
1618    "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; All NID matched (matches an RTID destination) transactions inserted into the TOR.  The NID is programmed in Cn_MSR_PMON_BOX_FILTER.nid.  In conjunction with STATE = I, it is possible to monitor misses to specific NIDs in the system.",
1619    "Counter": "0,1,2,3",
1620    "MSRValue": "0x00",
1621    "ELLC": "0",
1622    "Filter": "CBoFilter1[15:0]",
1623    "ExtSel": "0",
1624    "EVENT_STATUS": "0"
1625  },
1626  {
1627    "Unit": "CBO",
1628    "EventCode": "0x35",
1629    "UMask": "0x50",
1630    "EventName": "UNC_C_TOR_INSERTS.NID_WB",
1631    "BriefDescription": "TOR Inserts; NID Matched Writebacks",
1632    "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; NID matched write transactions inserted into the TOR.",
1633    "Counter": "0,1,2,3",
1634    "MSRValue": "0x00",
1635    "ELLC": "0",
1636    "Filter": "CBoFilter1[15:0]",
1637    "ExtSel": "0",
1638    "EVENT_STATUS": "0"
1639  },
1640  {
1641    "Unit": "CBO",
1642    "EventCode": "0x35",
1643    "UMask": "0x43",
1644    "EventName": "UNC_C_TOR_INSERTS.NID_MISS_OPCODE",
1645    "BriefDescription": "TOR Inserts; NID and Opcode Matched Miss",
1646    "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Miss transactions inserted into the TOR that match a NID and an opcode.",
1647    "Counter": "0,1,2,3",
1648    "MSRValue": "0x00",
1649    "ELLC": "0",
1650    "Filter": "CBoFilter1[28:20], CBoFilter1[15:0]",
1651    "ExtSel": "0",
1652    "EVENT_STATUS": "0"
1653  },
1654  {
1655    "Unit": "CBO",
1656    "EventCode": "0x35",
1657    "UMask": "0x4A",
1658    "EventName": "UNC_C_TOR_INSERTS.NID_MISS_ALL",
1659    "BriefDescription": "TOR Inserts; NID Matched Miss All",
1660    "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; All NID matched miss requests that were inserted into the TOR.",
1661    "Counter": "0,1,2,3",
1662    "MSRValue": "0x00",
1663    "ELLC": "0",
1664    "Filter": "CBoFilter1[15:0]",
1665    "ExtSel": "0",
1666    "EVENT_STATUS": "0"
1667  },
1668  {
1669    "Unit": "CBO",
1670    "EventCode": "0x35",
1671    "UMask": "0x2A",
1672    "EventName": "UNC_C_TOR_INSERTS.MISS_LOCAL",
1673    "BriefDescription": "TOR Inserts; Misses to Local Memory",
1674    "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Miss transactions inserted into the TOR that are satisifed by locally HOMed memory.",
1675    "Counter": "0,1,2,3",
1676    "MSRValue": "0x00",
1677    "ELLC": "0",
1678    "Filter": "na",
1679    "ExtSel": "0",
1680    "EVENT_STATUS": "0"
1681  },
1682  {
1683    "Unit": "CBO",
1684    "EventCode": "0x35",
1685    "UMask": "0x8A",
1686    "EventName": "UNC_C_TOR_INSERTS.MISS_REMOTE",
1687    "BriefDescription": "TOR Inserts; Misses to Remote Memory",
1688    "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Miss transactions inserted into the TOR that are satisifed by remote caches or remote memory.",
1689    "Counter": "0,1,2,3",
1690    "MSRValue": "0x00",
1691    "ELLC": "0",
1692    "Filter": "na",
1693    "ExtSel": "0",
1694    "EVENT_STATUS": "0"
1695  },
1696  {
1697    "Unit": "CBO",
1698    "EventCode": "0x35",
1699    "UMask": "0x28",
1700    "EventName": "UNC_C_TOR_INSERTS.LOCAL",
1701    "BriefDescription": "TOR Inserts; Local Memory",
1702    "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; All transactions inserted into the TOR that are satisifed by locally HOMed memory.",
1703    "Counter": "0,1,2,3",
1704    "MSRValue": "0x00",
1705    "ELLC": "0",
1706    "Filter": "na",
1707    "ExtSel": "0",
1708    "EVENT_STATUS": "0"
1709  },
1710  {
1711    "Unit": "CBO",
1712    "EventCode": "0x35",
1713    "UMask": "0x88",
1714    "EventName": "UNC_C_TOR_INSERTS.REMOTE",
1715    "BriefDescription": "TOR Inserts; Remote Memory",
1716    "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; All transactions inserted into the TOR that are satisifed by remote caches or remote memory.",
1717    "Counter": "0,1,2,3",
1718    "MSRValue": "0x00",
1719    "ELLC": "0",
1720    "Filter": "na",
1721    "ExtSel": "0",
1722    "EVENT_STATUS": "0"
1723  },
1724  {
1725    "Unit": "CBO",
1726    "EventCode": "0x35",
1727    "UMask": "0x23",
1728    "EventName": "UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE",
1729    "BriefDescription": "TOR Inserts; Misses to Local Memory - Opcode Matched",
1730    "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Miss transactions, satisifed by an opcode, inserted into the TOR that are satisifed by locally HOMed memory.",
1731    "Counter": "0,1,2,3",
1732    "MSRValue": "0x00",
1733    "ELLC": "0",
1734    "Filter": "CBoFilter1[28:20]",
1735    "ExtSel": "0",
1736    "EVENT_STATUS": "0"
1737  },
1738  {
1739    "Unit": "CBO",
1740    "EventCode": "0x35",
1741    "UMask": "0x83",
1742    "EventName": "UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE",
1743    "BriefDescription": "TOR Inserts; Misses to Remote Memory - Opcode Matched",
1744    "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Miss transactions, satisifed by an opcode,  inserted into the TOR that are satisifed by remote caches or remote memory.",
1745    "Counter": "0,1,2,3",
1746    "MSRValue": "0x00",
1747    "ELLC": "0",
1748    "Filter": "CBoFilter1[28:20]",
1749    "ExtSel": "0",
1750    "EVENT_STATUS": "0"
1751  },
1752  {
1753    "Unit": "CBO",
1754    "EventCode": "0x35",
1755    "UMask": "0x21",
1756    "EventName": "UNC_C_TOR_INSERTS.LOCAL_OPCODE",
1757    "BriefDescription": "TOR Inserts; Local Memory - Opcode Matched",
1758    "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; All transactions, satisifed by an opcode,  inserted into the TOR that are satisifed by locally HOMed memory.",
1759    "Counter": "0,1,2,3",
1760    "MSRValue": "0x00",
1761    "ELLC": "0",
1762    "Filter": "CBoFilter1[28:20]",
1763    "ExtSel": "0",
1764    "EVENT_STATUS": "0"
1765  },
1766  {
1767    "Unit": "CBO",
1768    "EventCode": "0x35",
1769    "UMask": "0x81",
1770    "EventName": "UNC_C_TOR_INSERTS.REMOTE_OPCODE",
1771    "BriefDescription": "TOR Inserts; Remote Memory - Opcode Matched",
1772    "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; All transactions, satisifed by an opcode,  inserted into the TOR that are satisifed by remote caches or remote memory.",
1773    "Counter": "0,1,2,3",
1774    "MSRValue": "0x00",
1775    "ELLC": "0",
1776    "Filter": "CBoFilter1[28:20]",
1777    "ExtSel": "0",
1778    "EVENT_STATUS": "0"
1779  },
1780  {
1781    "Unit": "CBO",
1782    "EventCode": "0x36",
1783    "UMask": "0x1",
1784    "EventName": "UNC_C_TOR_OCCUPANCY.OPCODE",
1785    "BriefDescription": "TOR Occupancy; Opcode Match",
1786    "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); TOR entries that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc).",
1787    "Counter": "0",
1788    "MSRValue": "0x00",
1789    "ELLC": "0",
1790    "Filter": "CBoFilter1[28:20]",
1791    "ExtSel": "0",
1792    "EVENT_STATUS": "0"
1793  },
1794  {
1795    "Unit": "CBO",
1796    "EventCode": "0x36",
1797    "UMask": "0x4",
1798    "EventName": "UNC_C_TOR_OCCUPANCY.EVICTION",
1799    "BriefDescription": "TOR Occupancy; Evictions",
1800    "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding eviction transactions in the TOR.  Evictions can be quick, such as when the line is in the F, S, or E states and no core valid bits are set.  They can also be longer if either CV bits are set (so the cores need to be snooped) and/or if there is a HitM (in which case it is necessary to write the request out to memory).",
1801    "Counter": "0",
1802    "MSRValue": "0x00",
1803    "ELLC": "0",
1804    "Filter": "na",
1805    "ExtSel": "0",
1806    "EVENT_STATUS": "0"
1807  },
1808  {
1809    "Unit": "CBO",
1810    "EventCode": "0x36",
1811    "UMask": "0x8",
1812    "EventName": "UNC_C_TOR_OCCUPANCY.ALL",
1813    "BriefDescription": "TOR Occupancy; Any",
1814    "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); All valid TOR entries.  This includes requests that reside in the TOR for a short time, such as LLC Hits that do not need to snoop cores or requests that get rejected and have to be retried through one of the ingress queues.  The TOR is more commonly a bottleneck in skews with smaller core counts, where the ratio of RTIDs to TOR entries is larger.  Note that there are reserved TOR entries for various request types, so it is possible that a given request type be blocked with an occupancy that is less than 20.  Also note that generally requests will not be able to arbitrate into the TOR pipeline if there are no available TOR slots.",
1815    "Counter": "0",
1816    "MSRValue": "0x00",
1817    "ELLC": "0",
1818    "Filter": "na",
1819    "ExtSel": "0",
1820    "EVENT_STATUS": "0"
1821  },
1822  {
1823    "Unit": "CBO",
1824    "EventCode": "0x36",
1825    "UMask": "0x3",
1826    "EventName": "UNC_C_TOR_OCCUPANCY.MISS_OPCODE",
1827    "BriefDescription": "TOR Occupancy; Miss Opcode Match",
1828    "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); TOR entries for miss transactions that match an opcode. This generally means that the request was sent to memory or MMIO.",
1829    "Counter": "0",
1830    "MSRValue": "0x00",
1831    "ELLC": "0",
1832    "Filter": "CBoFilter1[28:20]",
1833    "ExtSel": "0",
1834    "EVENT_STATUS": "0"
1835  },
1836  {
1837    "Unit": "CBO",
1838    "EventCode": "0x36",
1839    "UMask": "0xA",
1840    "EventName": "UNC_C_TOR_OCCUPANCY.MISS_ALL",
1841    "BriefDescription": "TOR Occupancy; Miss All",
1842    "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding miss requests in the TOR.  'Miss' means the allocation requires an RTID.  This generally means that the request was sent to memory or MMIO.",
1843    "Counter": "0",
1844    "MSRValue": "0x00",
1845    "ELLC": "0",
1846    "Filter": "na",
1847    "ExtSel": "0",
1848    "EVENT_STATUS": "0"
1849  },
1850  {
1851    "Unit": "CBO",
1852    "EventCode": "0x36",
1853    "UMask": "0x41",
1854    "EventName": "UNC_C_TOR_OCCUPANCY.NID_OPCODE",
1855    "BriefDescription": "TOR Occupancy; NID and Opcode Matched",
1856    "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); TOR entries that match a NID and an opcode.",
1857    "Counter": "0",
1858    "MSRValue": "0x00",
1859    "ELLC": "0",
1860    "Filter": "CBoFilter1[28:20], CBoFilter1[15:0]",
1861    "ExtSel": "0",
1862    "EVENT_STATUS": "0"
1863  },
1864  {
1865    "Unit": "CBO",
1866    "EventCode": "0x36",
1867    "UMask": "0x44",
1868    "EventName": "UNC_C_TOR_OCCUPANCY.NID_EVICTION",
1869    "BriefDescription": "TOR Occupancy; NID Matched Evictions",
1870    "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding NID matched eviction transactions in the TOR .",
1871    "Counter": "0",
1872    "MSRValue": "0x00",
1873    "ELLC": "0",
1874    "Filter": "CBoFilter1[15:0]",
1875    "ExtSel": "0",
1876    "EVENT_STATUS": "0"
1877  },
1878  {
1879    "Unit": "CBO",
1880    "EventCode": "0x36",
1881    "UMask": "0x48",
1882    "EventName": "UNC_C_TOR_OCCUPANCY.NID_ALL",
1883    "BriefDescription": "TOR Occupancy; NID Matched",
1884    "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of NID matched outstanding requests in the TOR.  The NID is programmed in Cn_MSR_PMON_BOX_FILTER.nid.In conjunction with STATE = I, it is possible to monitor misses to specific NIDs in the system.",
1885    "Counter": "0",
1886    "MSRValue": "0x00",
1887    "ELLC": "0",
1888    "Filter": "CBoFilter1[15:0]",
1889    "ExtSel": "0",
1890    "EVENT_STATUS": "0"
1891  },
1892  {
1893    "Unit": "CBO",
1894    "EventCode": "0x36",
1895    "UMask": "0x43",
1896    "EventName": "UNC_C_TOR_OCCUPANCY.NID_MISS_OPCODE",
1897    "BriefDescription": "TOR Occupancy; NID and Opcode Matched Miss",
1898    "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding Miss requests in the TOR that match a NID and an opcode.",
1899    "Counter": "0",
1900    "MSRValue": "0x00",
1901    "ELLC": "0",
1902    "Filter": "CBoFilter1[28:20], CBoFilter1[15:0]",
1903    "ExtSel": "0",
1904    "EVENT_STATUS": "0"
1905  },
1906  {
1907    "Unit": "CBO",
1908    "EventCode": "0x36",
1909    "UMask": "0x4A",
1910    "EventName": "UNC_C_TOR_OCCUPANCY.NID_MISS_ALL",
1911    "BriefDescription": "TOR Occupancy; NID Matched",
1912    "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding Miss requests in the TOR that match a NID.",
1913    "Counter": "0",
1914    "MSRValue": "0x00",
1915    "ELLC": "0",
1916    "Filter": "CBoFilter1[15:0]",
1917    "ExtSel": "0",
1918    "EVENT_STATUS": "0"
1919  },
1920  {
1921    "Unit": "CBO",
1922    "EventCode": "0x36",
1923    "UMask": "0x2A",
1924    "EventName": "UNC_C_TOR_OCCUPANCY.MISS_LOCAL",
1925    "BriefDescription": "TOR Occupancy",
1926    "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)",
1927    "Counter": "0",
1928    "MSRValue": "0x00",
1929    "ELLC": "0",
1930    "Filter": "na",
1931    "ExtSel": "0",
1932    "EVENT_STATUS": "0"
1933  },
1934  {
1935    "Unit": "CBO",
1936    "EventCode": "0x36",
1937    "UMask": "0x8A",
1938    "EventName": "UNC_C_TOR_OCCUPANCY.MISS_REMOTE",
1939    "BriefDescription": "TOR Occupancy",
1940    "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)",
1941    "Counter": "0",
1942    "MSRValue": "0x00",
1943    "ELLC": "0",
1944    "Filter": "na",
1945    "ExtSel": "0",
1946    "EVENT_STATUS": "0"
1947  },
1948  {
1949    "Unit": "CBO",
1950    "EventCode": "0x36",
1951    "UMask": "0x28",
1952    "EventName": "UNC_C_TOR_OCCUPANCY.LOCAL",
1953    "BriefDescription": "TOR Occupancy",
1954    "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)",
1955    "Counter": "0",
1956    "MSRValue": "0x00",
1957    "ELLC": "0",
1958    "Filter": "na",
1959    "ExtSel": "0",
1960    "EVENT_STATUS": "0"
1961  },
1962  {
1963    "Unit": "CBO",
1964    "EventCode": "0x36",
1965    "UMask": "0x88",
1966    "EventName": "UNC_C_TOR_OCCUPANCY.REMOTE",
1967    "BriefDescription": "TOR Occupancy",
1968    "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)",
1969    "Counter": "0",
1970    "MSRValue": "0x00",
1971    "ELLC": "0",
1972    "Filter": "na",
1973    "ExtSel": "0",
1974    "EVENT_STATUS": "0"
1975  },
1976  {
1977    "Unit": "CBO",
1978    "EventCode": "0x36",
1979    "UMask": "0x23",
1980    "EventName": "UNC_C_TOR_OCCUPANCY.MISS_LOCAL_OPCODE",
1981    "BriefDescription": "TOR Occupancy; Misses to Local Memory - Opcode Matched",
1982    "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding Miss transactions, satisifed by an opcode, in the TOR that are satisifed by locally HOMed memory.",
1983    "Counter": "0",
1984    "MSRValue": "0x00",
1985    "ELLC": "0",
1986    "Filter": "CBoFilter1[28:20]",
1987    "ExtSel": "0",
1988    "EVENT_STATUS": "0"
1989  },
1990  {
1991    "Unit": "CBO",
1992    "EventCode": "0x36",
1993    "UMask": "0x83",
1994    "EventName": "UNC_C_TOR_OCCUPANCY.MISS_REMOTE_OPCODE",
1995    "BriefDescription": "TOR Occupancy; Misses to Remote Memory - Opcode Matched",
1996    "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding Miss transactions, satisifed by an opcode, in the TOR that are satisifed by remote caches or remote memory.",
1997    "Counter": "0",
1998    "MSRValue": "0x00",
1999    "ELLC": "0",
2000    "Filter": "CBoFilter1[28:20]",
2001    "ExtSel": "0",
2002    "EVENT_STATUS": "0"
2003  },
2004  {
2005    "Unit": "CBO",
2006    "EventCode": "0x36",
2007    "UMask": "0x21",
2008    "EventName": "UNC_C_TOR_OCCUPANCY.LOCAL_OPCODE",
2009    "BriefDescription": "TOR Occupancy; Local Memory - Opcode Matched",
2010    "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding  transactions, satisifed by an opcode,  in the TOR that are satisifed by locally HOMed memory.",
2011    "Counter": "0",
2012    "MSRValue": "0x00",
2013    "ELLC": "0",
2014    "Filter": "CBoFilter1[28:20]",
2015    "ExtSel": "0",
2016    "EVENT_STATUS": "0"
2017  },
2018  {
2019    "Unit": "CBO",
2020    "EventCode": "0x36",
2021    "UMask": "0x81",
2022    "EventName": "UNC_C_TOR_OCCUPANCY.REMOTE_OPCODE",
2023    "BriefDescription": "TOR Occupancy; Remote Memory - Opcode Matched",
2024    "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding  transactions, satisifed by an opcode,  in the TOR that are satisifed by remote caches or remote memory.",
2025    "Counter": "0",
2026    "MSRValue": "0x00",
2027    "ELLC": "0",
2028    "Filter": "CBoFilter1[28:20]",
2029    "ExtSel": "0",
2030    "EVENT_STATUS": "0"
2031  },
2032  {
2033    "Unit": "CBO",
2034    "EventCode": "0x36",
2035    "UMask": "0x10",
2036    "EventName": "UNC_C_TOR_OCCUPANCY.WB",
2037    "BriefDescription": "TOR Occupancy; Writebacks",
2038    "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Write transactions in the TOR.   This does not include RFO, but actual operations that contain data being sent from the core.",
2039    "Counter": "0",
2040    "MSRValue": "0x00",
2041    "ELLC": "0",
2042    "Filter": "na",
2043    "ExtSel": "0",
2044    "EVENT_STATUS": "0"
2045  },
2046  {
2047    "Unit": "CBO",
2048    "EventCode": "0x36",
2049    "UMask": "0x50",
2050    "EventName": "UNC_C_TOR_OCCUPANCY.NID_WB",
2051    "BriefDescription": "TOR Occupancy; NID Matched Writebacks",
2052    "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); NID matched write transactions int the TOR.",
2053    "Counter": "0",
2054    "MSRValue": "0x00",
2055    "ELLC": "0",
2056    "Filter": "CBoFilter1[15:0]",
2057    "ExtSel": "0",
2058    "EVENT_STATUS": "0"
2059  },
2060  {
2061    "Unit": "CBO",
2062    "EventCode": "0x4",
2063    "UMask": "0x1",
2064    "EventName": "UNC_C_TxR_ADS_USED.AD",
2065    "BriefDescription": "Onto AD Ring",
2066    "PublicDescription": "tbd",
2067    "Counter": "0,1,2,3",
2068    "MSRValue": "0x00",
2069    "ELLC": "0",
2070    "Filter": "na",
2071    "ExtSel": "0",
2072    "EVENT_STATUS": "0"
2073  },
2074  {
2075    "Unit": "CBO",
2076    "EventCode": "0x4",
2077    "UMask": "0x2",
2078    "EventName": "UNC_C_TxR_ADS_USED.AK",
2079    "BriefDescription": "Onto AK Ring",
2080    "PublicDescription": "tbd",
2081    "Counter": "0,1,2,3",
2082    "MSRValue": "0x00",
2083    "ELLC": "0",
2084    "Filter": "na",
2085    "ExtSel": "0",
2086    "EVENT_STATUS": "0"
2087  },
2088  {
2089    "Unit": "CBO",
2090    "EventCode": "0x4",
2091    "UMask": "0x4",
2092    "EventName": "UNC_C_TxR_ADS_USED.BL",
2093    "BriefDescription": "Onto BL Ring",
2094    "PublicDescription": "tbd",
2095    "Counter": "0,1,2,3",
2096    "MSRValue": "0x00",
2097    "ELLC": "0",
2098    "Filter": "na",
2099    "ExtSel": "0",
2100    "EVENT_STATUS": "0"
2101  },
2102  {
2103    "Unit": "CBO",
2104    "EventCode": "0x2",
2105    "UMask": "0x1",
2106    "EventName": "UNC_C_TxR_INSERTS.AD_CACHE",
2107    "BriefDescription": "Egress Allocations; AD - Cachebo",
2108    "PublicDescription": "Number of allocations into the Cbo Egress.  The Egress is used to queue up requests destined for the ring.; Ring transactions from the Cachebo destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses.",
2109    "Counter": "0,1,2,3",
2110    "MSRValue": "0x00",
2111    "ELLC": "0",
2112    "Filter": "na",
2113    "ExtSel": "0",
2114    "EVENT_STATUS": "0"
2115  },
2116  {
2117    "Unit": "CBO",
2118    "EventCode": "0x2",
2119    "UMask": "0x2",
2120    "EventName": "UNC_C_TxR_INSERTS.AK_CACHE",
2121    "BriefDescription": "Egress Allocations; AK - Cachebo",
2122    "PublicDescription": "Number of allocations into the Cbo Egress.  The Egress is used to queue up requests destined for the ring.; Ring transactions from the Cachebo destined for the AK ring.  This is commonly used for credit returns and GO responses.",
2123    "Counter": "0,1,2,3",
2124    "MSRValue": "0x00",
2125    "ELLC": "0",
2126    "Filter": "na",
2127    "ExtSel": "0",
2128    "EVENT_STATUS": "0"
2129  },
2130  {
2131    "Unit": "CBO",
2132    "EventCode": "0x2",
2133    "UMask": "0x4",
2134    "EventName": "UNC_C_TxR_INSERTS.BL_CACHE",
2135    "BriefDescription": "Egress Allocations; BL - Cacheno",
2136    "PublicDescription": "Number of allocations into the Cbo Egress.  The Egress is used to queue up requests destined for the ring.; Ring transactions from the Cachebo destined for the BL ring.  This is commonly used to send data from the cache to various destinations.",
2137    "Counter": "0,1,2,3",
2138    "MSRValue": "0x00",
2139    "ELLC": "0",
2140    "Filter": "na",
2141    "ExtSel": "0",
2142    "EVENT_STATUS": "0"
2143  },
2144  {
2145    "Unit": "CBO",
2146    "EventCode": "0x2",
2147    "UMask": "0x8",
2148    "EventName": "UNC_C_TxR_INSERTS.IV_CACHE",
2149    "BriefDescription": "Egress Allocations; IV - Cachebo",
2150    "PublicDescription": "Number of allocations into the Cbo Egress.  The Egress is used to queue up requests destined for the ring.; Ring transactions from the Cachebo destined for the IV ring.  This is commonly used for snoops to the cores.",
2151    "Counter": "0,1,2,3",
2152    "MSRValue": "0x00",
2153    "ELLC": "0",
2154    "Filter": "na",
2155    "ExtSel": "0",
2156    "EVENT_STATUS": "0"
2157  },
2158  {
2159    "Unit": "CBO",
2160    "EventCode": "0x2",
2161    "UMask": "0x10",
2162    "EventName": "UNC_C_TxR_INSERTS.AD_CORE",
2163    "BriefDescription": "Egress Allocations; AD - Corebo",
2164    "PublicDescription": "Number of allocations into the Cbo Egress.  The Egress is used to queue up requests destined for the ring.; Ring transactions from the Corebo destined for the AD ring.  This is commonly used for outbound requests.",
2165    "Counter": "0,1,2,3",
2166    "MSRValue": "0x00",
2167    "ELLC": "0",
2168    "Filter": "na",
2169    "ExtSel": "0",
2170    "EVENT_STATUS": "0"
2171  },
2172  {
2173    "Unit": "CBO",
2174    "EventCode": "0x2",
2175    "UMask": "0x20",
2176    "EventName": "UNC_C_TxR_INSERTS.AK_CORE",
2177    "BriefDescription": "Egress Allocations; AK - Corebo",
2178    "PublicDescription": "Number of allocations into the Cbo Egress.  The Egress is used to queue up requests destined for the ring.; Ring transactions from the Corebo destined for the AK ring.  This is commonly used for snoop responses coming from the core and destined for a Cachebo.",
2179    "Counter": "0,1,2,3",
2180    "MSRValue": "0x00",
2181    "ELLC": "0",
2182    "Filter": "na",
2183    "ExtSel": "0",
2184    "EVENT_STATUS": "0"
2185  },
2186  {
2187    "Unit": "CBO",
2188    "EventCode": "0x2",
2189    "UMask": "0x40",
2190    "EventName": "UNC_C_TxR_INSERTS.BL_CORE",
2191    "BriefDescription": "Egress Allocations; BL - Corebo",
2192    "PublicDescription": "Number of allocations into the Cbo Egress.  The Egress is used to queue up requests destined for the ring.; Ring transactions from the Corebo destined for the BL ring.  This is commonly used for transfering writeback data to the cache.",
2193    "Counter": "0,1,2,3",
2194    "MSRValue": "0x00",
2195    "ELLC": "0",
2196    "Filter": "na",
2197    "ExtSel": "0",
2198    "EVENT_STATUS": "0"
2199  },
2200  {
2201    "Unit": "CBO",
2202    "EventCode": "0x3",
2203    "UMask": "0x2",
2204    "EventName": "UNC_C_TxR_STARVED.AK_BOTH",
2205    "BriefDescription": "Injection Starvation; Onto AK Ring",
2206    "PublicDescription": "Counts injection starvation.  This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.; cycles that both AK egresses spent in starvation",
2207    "Counter": "0,1,2,3",
2208    "MSRValue": "0x00",
2209    "ELLC": "0",
2210    "Filter": "na",
2211    "ExtSel": "0",
2212    "EVENT_STATUS": "0"
2213  },
2214  {
2215    "Unit": "CBO",
2216    "EventCode": "0x3",
2217    "UMask": "0x4",
2218    "EventName": "UNC_C_TxR_STARVED.BL_BOTH",
2219    "BriefDescription": "Injection Starvation; Onto BL Ring",
2220    "PublicDescription": "Counts injection starvation.  This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.; cycles that both BL egresses spent in starvation",
2221    "Counter": "0,1,2,3",
2222    "MSRValue": "0x00",
2223    "ELLC": "0",
2224    "Filter": "na",
2225    "ExtSel": "0",
2226    "EVENT_STATUS": "0"
2227  },
2228  {
2229    "Unit": "CBO",
2230    "EventCode": "0x3",
2231    "UMask": "0x8",
2232    "EventName": "UNC_C_TxR_STARVED.IV",
2233    "BriefDescription": "Injection Starvation; Onto IV Ring",
2234    "PublicDescription": "Counts injection starvation.  This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.; cycles that the cachebo IV egress spent in starvation",
2235    "Counter": "0,1,2,3",
2236    "MSRValue": "0x00",
2237    "ELLC": "0",
2238    "Filter": "na",
2239    "ExtSel": "0",
2240    "EVENT_STATUS": "0"
2241  },
2242  {
2243    "Unit": "CBO",
2244    "EventCode": "0x3",
2245    "UMask": "0x10",
2246    "EventName": "UNC_C_TxR_STARVED.AD_CORE",
2247    "BriefDescription": "Injection Starvation; Onto AD Ring (to core)",
2248    "PublicDescription": "Counts injection starvation.  This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.; cycles that the core AD egress spent in starvation",
2249    "Counter": "0,1,2,3",
2250    "MSRValue": "0x00",
2251    "ELLC": "0",
2252    "Filter": "na",
2253    "ExtSel": "0",
2254    "EVENT_STATUS": "0"
2255  },
2256  {
2257    "Unit": "CBO",
2258    "EventCode": "0x11",
2259    "UMask": "0x2",
2260    "EventName": "UNC_C_RxR_OCCUPANCY.IRQ_REJ",
2261    "BriefDescription": "Ingress Occupancy; IRQ Rejected",
2262    "PublicDescription": "Counts number of entries in the specified Ingress queue in each cycle.",
2263    "Counter": "0",
2264    "MSRValue": "0x00",
2265    "ELLC": "0",
2266    "Filter": "na",
2267    "ExtSel": "0",
2268    "EVENT_STATUS": "0"
2269  },
2270  {
2271    "Unit": "CBO",
2272    "EventCode": "0x37",
2273    "UMask": "0x4",
2274    "EventName": "UNC_C_LLC_VICTIMS.I_STATE",
2275    "BriefDescription": "Lines Victimized; Lines in S State",
2276    "PublicDescription": "Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
2277    "Counter": "0,1,2,3",
2278    "MSRValue": "0x00",
2279    "ELLC": "0",
2280    "Filter": "na",
2281    "ExtSel": "0",
2282    "EVENT_STATUS": "0"
2283  },
2284  {
2285    "Unit": "HA",
2286    "EventCode": "0x20",
2287    "UMask": "0x3",
2288    "EventName": "UNC_H_ADDR_OPC_MATCH.FILT",
2289    "BriefDescription": "QPI Address/Opcode Match; Address & Opcode Match",
2290    "PublicDescription": "tbd",
2291    "Counter": "0,1,2,3",
2292    "MSRValue": "0x00",
2293    "ELLC": "0",
2294    "Filter": "HA_AddrMatch0[31:6], HA_AddrMatch1[13:0], HA_OpcodeMatch[5:0]",
2295    "ExtSel": "0",
2296    "EVENT_STATUS": "0"
2297  },
2298  {
2299    "Unit": "HA",
2300    "EventCode": "0x20",
2301    "UMask": "0x1",
2302    "EventName": "UNC_H_ADDR_OPC_MATCH.ADDR",
2303    "BriefDescription": "QPI Address/Opcode Match; Address",
2304    "PublicDescription": "tbd",
2305    "Counter": "0,1,2,3",
2306    "MSRValue": "0x00",
2307    "ELLC": "0",
2308    "Filter": "HA_AddrMatch0[31:6], HA_AddrMatch1[13:0]",
2309    "ExtSel": "0",
2310    "EVENT_STATUS": "0"
2311  },
2312  {
2313    "Unit": "HA",
2314    "EventCode": "0x20",
2315    "UMask": "0x2",
2316    "EventName": "UNC_H_ADDR_OPC_MATCH.OPC",
2317    "BriefDescription": "QPI Address/Opcode Match; Opcode",
2318    "PublicDescription": "tbd",
2319    "Counter": "0,1,2,3",
2320    "MSRValue": "0x00",
2321    "ELLC": "0",
2322    "Filter": "HA_OpcodeMatch[5:0]",
2323    "ExtSel": "0",
2324    "EVENT_STATUS": "0"
2325  },
2326  {
2327    "Unit": "HA",
2328    "EventCode": "0x20",
2329    "UMask": "0x4",
2330    "EventName": "UNC_H_ADDR_OPC_MATCH.AD",
2331    "BriefDescription": "QPI Address/Opcode Match; AD Opcodes",
2332    "PublicDescription": "tbd",
2333    "Counter": "0,1,2,3",
2334    "MSRValue": "0x00",
2335    "ELLC": "0",
2336    "Filter": "HA_OpcodeMatch[5:0]",
2337    "ExtSel": "0",
2338    "EVENT_STATUS": "0"
2339  },
2340  {
2341    "Unit": "HA",
2342    "EventCode": "0x20",
2343    "UMask": "0x8",
2344    "EventName": "UNC_H_ADDR_OPC_MATCH.BL",
2345    "BriefDescription": "QPI Address/Opcode Match; BL Opcodes",
2346    "PublicDescription": "tbd",
2347    "Counter": "0,1,2,3",
2348    "MSRValue": "0x00",
2349    "ELLC": "0",
2350    "Filter": "HA_OpcodeMatch[5:0]",
2351    "ExtSel": "0",
2352    "EVENT_STATUS": "0"
2353  },
2354  {
2355    "Unit": "HA",
2356    "EventCode": "0x20",
2357    "UMask": "0x10",
2358    "EventName": "UNC_H_ADDR_OPC_MATCH.AK",
2359    "BriefDescription": "QPI Address/Opcode Match; AK Opcodes",
2360    "PublicDescription": "tbd",
2361    "Counter": "0,1,2,3",
2362    "MSRValue": "0x00",
2363    "ELLC": "0",
2364    "Filter": "HA_OpcodeMatch[5:0]",
2365    "ExtSel": "0",
2366    "EVENT_STATUS": "0"
2367  },
2368  {
2369    "Unit": "HA",
2370    "EventCode": "0x42",
2371    "UMask": "0x0",
2372    "EventName": "UNC_H_BT_CYCLES_NE",
2373    "BriefDescription": "BT Cycles Not Empty",
2374    "PublicDescription": "Cycles the Backup Tracker (BT) is not empty. The BT is the actual HOM tracker in IVT.",
2375    "Counter": "0,1,2,3",
2376    "MSRValue": "0x00",
2377    "ELLC": "0",
2378    "Filter": "na",
2379    "ExtSel": "0",
2380    "EVENT_STATUS": "0"
2381  },
2382  {
2383    "Unit": "HA",
2384    "EventCode": "0x51",
2385    "UMask": "0x2",
2386    "EventName": "UNC_H_BT_TO_HT_NOT_ISSUED.INCOMING_SNP_HAZARD",
2387    "BriefDescription": "BT to HT Not Issued; Incoming Snoop Hazard",
2388    "PublicDescription": "Counts the number of cycles when the HA does not issue transaction from BT to HT.; Cycles unable to issue from BT due to incoming snoop hazard",
2389    "Counter": "0,1,2,3",
2390    "MSRValue": "0x00",
2391    "ELLC": "0",
2392    "Filter": "na",
2393    "ExtSel": "0",
2394    "EVENT_STATUS": "0"
2395  },
2396  {
2397    "Unit": "HA",
2398    "EventCode": "0x51",
2399    "UMask": "0x4",
2400    "EventName": "UNC_H_BT_TO_HT_NOT_ISSUED.INCOMING_BL_HAZARD",
2401    "BriefDescription": "BT to HT Not Issued; Incoming Data Hazard",
2402    "PublicDescription": "Counts the number of cycles when the HA does not issue transaction from BT to HT.; Cycles unable to issue from BT due to incoming BL data hazard",
2403    "Counter": "0,1,2,3",
2404    "MSRValue": "0x00",
2405    "ELLC": "0",
2406    "Filter": "na",
2407    "ExtSel": "0",
2408    "EVENT_STATUS": "0"
2409  },
2410  {
2411    "Unit": "HA",
2412    "EventCode": "0x51",
2413    "UMask": "0x8",
2414    "EventName": "UNC_H_BT_TO_HT_NOT_ISSUED.RSPACKCFLT_HAZARD",
2415    "BriefDescription": "BT to HT Not Issued; Incoming Data Hazard",
2416    "PublicDescription": "Counts the number of cycles when the HA does not issue transaction from BT to HT.; Cycles unable to issue from BT due to incoming BL data hazard",
2417    "Counter": "0,1,2,3",
2418    "MSRValue": "0x00",
2419    "ELLC": "0",
2420    "Filter": "na",
2421    "ExtSel": "0",
2422    "EVENT_STATUS": "0"
2423  },
2424  {
2425    "Unit": "HA",
2426    "EventCode": "0x51",
2427    "UMask": "0x10",
2428    "EventName": "UNC_H_BT_TO_HT_NOT_ISSUED.WBMDATA_HAZARD",
2429    "BriefDescription": "BT to HT Not Issued; Incoming Data Hazard",
2430    "PublicDescription": "Counts the number of cycles when the HA does not issue transaction from BT to HT.; Cycles unable to issue from BT due to incoming BL data hazard",
2431    "Counter": "0,1,2,3",
2432    "MSRValue": "0x00",
2433    "ELLC": "0",
2434    "Filter": "na",
2435    "ExtSel": "0",
2436    "EVENT_STATUS": "0"
2437  },
2438  {
2439    "Unit": "HA",
2440    "EventCode": "0x14",
2441    "UMask": "0x1",
2442    "EventName": "UNC_H_BYPASS_IMC.TAKEN",
2443    "BriefDescription": "HA to iMC Bypass; Taken",
2444    "PublicDescription": "Counts the number of times when the HA was able to bypass was attempted.  This is a latency optimization for situations when there is light loadings on the memory subsystem.  This can be filted by when the bypass was taken and when it was not.; Filter for transactions that succeeded in taking the bypass.",
2445    "Counter": "0,1,2,3",
2446    "MSRValue": "0x00",
2447    "ELLC": "0",
2448    "Filter": "na",
2449    "ExtSel": "0",
2450    "EVENT_STATUS": "0"
2451  },
2452  {
2453    "Unit": "HA",
2454    "EventCode": "0x14",
2455    "UMask": "0x2",
2456    "EventName": "UNC_H_BYPASS_IMC.NOT_TAKEN",
2457    "BriefDescription": "HA to iMC Bypass; Not Taken",
2458    "PublicDescription": "Counts the number of times when the HA was able to bypass was attempted.  This is a latency optimization for situations when there is light loadings on the memory subsystem.  This can be filted by when the bypass was taken and when it was not.; Filter for transactions that could not take the bypass.",
2459    "Counter": "0,1,2,3",
2460    "MSRValue": "0x00",
2461    "ELLC": "0",
2462    "Filter": "na",
2463    "ExtSel": "0",
2464    "EVENT_STATUS": "0"
2465  },
2466  {
2467    "Unit": "HA",
2468    "EventCode": "0x0",
2469    "UMask": "0x0",
2470    "EventName": "UNC_H_CLOCKTICKS",
2471    "BriefDescription": "uclks",
2472    "PublicDescription": "Counts the number of uclks in the HA.  This will be slightly different than the count in the Ubox because of enable/freeze delays.  The HA is on the other side of the die from the fixed Ubox uclk counter, so the drift could be somewhat larger than in units that are closer like the QPI Agent.",
2473    "Counter": "0,1,2,3",
2474    "MSRValue": "0x00",
2475    "ELLC": "0",
2476    "Filter": "na",
2477    "ExtSel": "0",
2478    "EVENT_STATUS": "0"
2479  },
2480  {
2481    "Unit": "HA",
2482    "EventCode": "0x11",
2483    "UMask": "0x0",
2484    "EventName": "UNC_H_DIRECT2CORE_COUNT",
2485    "BriefDescription": "Direct2Core Messages Sent",
2486    "PublicDescription": "Number of Direct2Core messages sent",
2487    "Counter": "0,1,2,3",
2488    "MSRValue": "0x00",
2489    "ELLC": "0",
2490    "Filter": "na",
2491    "ExtSel": "0",
2492    "EVENT_STATUS": "0"
2493  },
2494  {
2495    "Unit": "HA",
2496    "EventCode": "0x12",
2497    "UMask": "0x0",
2498    "EventName": "UNC_H_DIRECT2CORE_CYCLES_DISABLED",
2499    "BriefDescription": "Cycles when Direct2Core was Disabled",
2500    "PublicDescription": "Number of cycles in which Direct2Core was disabled",
2501    "Counter": "0,1,2,3",
2502    "MSRValue": "0x00",
2503    "ELLC": "0",
2504    "Filter": "na",
2505    "ExtSel": "0",
2506    "EVENT_STATUS": "0"
2507  },
2508  {
2509    "Unit": "HA",
2510    "EventCode": "0x13",
2511    "UMask": "0x0",
2512    "EventName": "UNC_H_DIRECT2CORE_TXN_OVERRIDE",
2513    "BriefDescription": "Number of Reads that had Direct2Core Overridden",
2514    "PublicDescription": "Number of Reads where Direct2Core overridden",
2515    "Counter": "0,1,2,3",
2516    "MSRValue": "0x00",
2517    "ELLC": "0",
2518    "Filter": "na",
2519    "ExtSel": "0",
2520    "EVENT_STATUS": "0"
2521  },
2522  {
2523    "Unit": "HA",
2524    "EventCode": "0x41",
2525    "UMask": "0x0",
2526    "EventName": "UNC_H_DIRECTORY_LAT_OPT",
2527    "BriefDescription": "Directory Lat Opt Return",
2528    "PublicDescription": "Directory Latency Optimization Data Return Path Taken. When directory mode is enabled and the directory retuned for a read is Dir=I, then data can be returned using a faster path if certain conditions are met (credits, free pipeline, etc).",
2529    "Counter": "0,1,2,3",
2530    "MSRValue": "0x00",
2531    "ELLC": "0",
2532    "Filter": "na",
2533    "ExtSel": "0",
2534    "EVENT_STATUS": "0"
2535  },
2536  {
2537    "Unit": "HA",
2538    "EventCode": "0xC",
2539    "UMask": "0x1",
2540    "EventName": "UNC_H_DIRECTORY_LOOKUP.SNP",
2541    "BriefDescription": "Directory Lookups; Snoop Needed",
2542    "PublicDescription": "Counts the number of transactions that looked up the directory.  Can be filtered by requests that had to snoop and those that did not have to.; Filters for transactions that had to send one or more snoops because the directory bit was set.",
2543    "Counter": "0,1,2,3",
2544    "MSRValue": "0x00",
2545    "ELLC": "0",
2546    "Filter": "na",
2547    "ExtSel": "0",
2548    "EVENT_STATUS": "0"
2549  },
2550  {
2551    "Unit": "HA",
2552    "EventCode": "0xC",
2553    "UMask": "0x2",
2554    "EventName": "UNC_H_DIRECTORY_LOOKUP.NO_SNP",
2555    "BriefDescription": "Directory Lookups; Snoop Not Needed",
2556    "PublicDescription": "Counts the number of transactions that looked up the directory.  Can be filtered by requests that had to snoop and those that did not have to.; Filters for transactions that did not have to send any snoops because the directory bit was clear.",
2557    "Counter": "0,1,2,3",
2558    "MSRValue": "0x00",
2559    "ELLC": "0",
2560    "Filter": "na",
2561    "ExtSel": "0",
2562    "EVENT_STATUS": "0"
2563  },
2564  {
2565    "Unit": "HA",
2566    "EventCode": "0xD",
2567    "UMask": "0x1",
2568    "EventName": "UNC_H_DIRECTORY_UPDATE.SET",
2569    "BriefDescription": "Directory Updates; Directory Set",
2570    "PublicDescription": "Counts the number of directory updates that were required.  These result in writes to the memory controller.  This can be filtered by directory sets and directory clears.; Filter for directory sets.  This occurs when a remote read transaction requests memory, bringing it to a remote cache.",
2571    "Counter": "0,1,2,3",
2572    "MSRValue": "0x00",
2573    "ELLC": "0",
2574    "Filter": "na",
2575    "ExtSel": "0",
2576    "EVENT_STATUS": "0"
2577  },
2578  {
2579    "Unit": "HA",
2580    "EventCode": "0xD",
2581    "UMask": "0x2",
2582    "EventName": "UNC_H_DIRECTORY_UPDATE.CLEAR",
2583    "BriefDescription": "Directory Updates; Directory Clear",
2584    "PublicDescription": "Counts the number of directory updates that were required.  These result in writes to the memory controller.  This can be filtered by directory sets and directory clears.; Filter for directory clears.  This occurs when snoops were sent and all returned with RspI.",
2585    "Counter": "0,1,2,3",
2586    "MSRValue": "0x00",
2587    "ELLC": "0",
2588    "Filter": "na",
2589    "ExtSel": "0",
2590    "EVENT_STATUS": "0"
2591  },
2592  {
2593    "Unit": "HA",
2594    "EventCode": "0xD",
2595    "UMask": "0x3",
2596    "EventName": "UNC_H_DIRECTORY_UPDATE.ANY",
2597    "BriefDescription": "Directory Updates; Any Directory Update",
2598    "PublicDescription": "Counts the number of directory updates that were required.  These result in writes to the memory controller.  This can be filtered by directory sets and directory clears.",
2599    "Counter": "0,1,2,3",
2600    "MSRValue": "0x00",
2601    "ELLC": "0",
2602    "Filter": "na",
2603    "ExtSel": "0",
2604    "EVENT_STATUS": "0"
2605  },
2606  {
2607    "Unit": "HA",
2608    "EventCode": "0x71",
2609    "UMask": "0x1",
2610    "EventName": "UNC_H_HITME_HIT.READ_OR_INVITOE",
2611    "BriefDescription": "Counts Number of Hits in HitMe Cache; op is RdCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvItoE",
2612    "PublicDescription": "tbd",
2613    "Counter": "0,1,2,3",
2614    "MSRValue": "0x00",
2615    "ELLC": "0",
2616    "Filter": "na",
2617    "ExtSel": "0",
2618    "EVENT_STATUS": "0"
2619  },
2620  {
2621    "Unit": "HA",
2622    "EventCode": "0x71",
2623    "UMask": "0x2",
2624    "EventName": "UNC_H_HITME_HIT.WBMTOI",
2625    "BriefDescription": "Counts Number of Hits in HitMe Cache; op is WbMtoI",
2626    "PublicDescription": "tbd",
2627    "Counter": "0,1,2,3",
2628    "MSRValue": "0x00",
2629    "ELLC": "0",
2630    "Filter": "na",
2631    "ExtSel": "0",
2632    "EVENT_STATUS": "0"
2633  },
2634  {
2635    "Unit": "HA",
2636    "EventCode": "0x71",
2637    "UMask": "0x4",
2638    "EventName": "UNC_H_HITME_HIT.ACKCNFLTWBI",
2639    "BriefDescription": "Counts Number of Hits in HitMe Cache; op is AckCnfltWbI",
2640    "PublicDescription": "tbd",
2641    "Counter": "0,1,2,3",
2642    "MSRValue": "0x00",
2643    "ELLC": "0",
2644    "Filter": "na",
2645    "ExtSel": "0",
2646    "EVENT_STATUS": "0"
2647  },
2648  {
2649    "Unit": "HA",
2650    "EventCode": "0x71",
2651    "UMask": "0x8",
2652    "EventName": "UNC_H_HITME_HIT.WBMTOE_OR_S",
2653    "BriefDescription": "Counts Number of Hits in HitMe Cache; op is WbMtoE or WbMtoS",
2654    "PublicDescription": "tbd",
2655    "Counter": "0,1,2,3",
2656    "MSRValue": "0x00",
2657    "ELLC": "0",
2658    "Filter": "na",
2659    "ExtSel": "0",
2660    "EVENT_STATUS": "0"
2661  },
2662  {
2663    "Unit": "HA",
2664    "EventCode": "0x71",
2665    "UMask": "0x10",
2666    "EventName": "UNC_H_HITME_HIT.RSPFWDI_REMOTE",
2667    "BriefDescription": "Counts Number of Hits in HitMe Cache; op is RspIFwd or RspIFwdWb for a remote request",
2668    "PublicDescription": "tbd",
2669    "Counter": "0,1,2,3",
2670    "MSRValue": "0x00",
2671    "ELLC": "0",
2672    "Filter": "na",
2673    "ExtSel": "0",
2674    "EVENT_STATUS": "0"
2675  },
2676  {
2677    "Unit": "HA",
2678    "EventCode": "0x71",
2679    "UMask": "0x20",
2680    "EventName": "UNC_H_HITME_HIT.RSPFWDI_LOCAL",
2681    "BriefDescription": "Counts Number of Hits in HitMe Cache; op is RspIFwd or RspIFwdWb for a local request",
2682    "PublicDescription": "tbd",
2683    "Counter": "0,1,2,3",
2684    "MSRValue": "0x00",
2685    "ELLC": "0",
2686    "Filter": "na",
2687    "ExtSel": "0",
2688    "EVENT_STATUS": "0"
2689  },
2690  {
2691    "Unit": "HA",
2692    "EventCode": "0x71",
2693    "UMask": "0x40",
2694    "EventName": "UNC_H_HITME_HIT.RSPFWDS",
2695    "BriefDescription": "Counts Number of Hits in HitMe Cache; op is RsSFwd or RspSFwdWb",
2696    "PublicDescription": "tbd",
2697    "Counter": "0,1,2,3",
2698    "MSRValue": "0x00",
2699    "ELLC": "0",
2700    "Filter": "na",
2701    "ExtSel": "0",
2702    "EVENT_STATUS": "0"
2703  },
2704  {
2705    "Unit": "HA",
2706    "EventCode": "0x71",
2707    "UMask": "0x80",
2708    "EventName": "UNC_H_HITME_HIT.RSP",
2709    "BriefDescription": "Counts Number of Hits in HitMe Cache; op is RspI, RspIWb, RspS, RspSWb, RspCnflt or RspCnfltWbI",
2710    "PublicDescription": "tbd",
2711    "Counter": "0,1,2,3",
2712    "MSRValue": "0x00",
2713    "ELLC": "0",
2714    "Filter": "na",
2715    "ExtSel": "0",
2716    "EVENT_STATUS": "0"
2717  },
2718  {
2719    "Unit": "HA",
2720    "EventCode": "0x71",
2721    "UMask": "0x70",
2722    "EventName": "UNC_H_HITME_HIT.ALLOCS",
2723    "BriefDescription": "Counts Number of Hits in HitMe Cache; Allocations",
2724    "PublicDescription": "tbd",
2725    "Counter": "0,1,2,3",
2726    "MSRValue": "0x00",
2727    "ELLC": "0",
2728    "Filter": "na",
2729    "ExtSel": "0",
2730    "EVENT_STATUS": "0"
2731  },
2732  {
2733    "Unit": "HA",
2734    "EventCode": "0x71",
2735    "UMask": "0x42",
2736    "EventName": "UNC_H_HITME_HIT.EVICTS",
2737    "BriefDescription": "Counts Number of Hits in HitMe Cache; Allocations",
2738    "PublicDescription": "tbd",
2739    "Counter": "0,1,2,3",
2740    "MSRValue": "0x00",
2741    "ELLC": "0",
2742    "Filter": "na",
2743    "ExtSel": "0",
2744    "EVENT_STATUS": "0"
2745  },
2746  {
2747    "Unit": "HA",
2748    "EventCode": "0x71",
2749    "UMask": "0x26",
2750    "EventName": "UNC_H_HITME_HIT.INVALS",
2751    "BriefDescription": "Counts Number of Hits in HitMe Cache; Invalidations",
2752    "PublicDescription": "tbd",
2753    "Counter": "0,1,2,3",
2754    "MSRValue": "0x00",
2755    "ELLC": "0",
2756    "Filter": "na",
2757    "ExtSel": "0",
2758    "EVENT_STATUS": "0"
2759  },
2760  {
2761    "Unit": "HA",
2762    "EventCode": "0x71",
2763    "UMask": "0xFF",
2764    "EventName": "UNC_H_HITME_HIT.ALL",
2765    "BriefDescription": "Counts Number of Hits in HitMe Cache; All Requests",
2766    "PublicDescription": "tbd",
2767    "Counter": "0,1,2,3",
2768    "MSRValue": "0x00",
2769    "ELLC": "0",
2770    "Filter": "na",
2771    "ExtSel": "0",
2772    "EVENT_STATUS": "0"
2773  },
2774  {
2775    "Unit": "HA",
2776    "EventCode": "0x71",
2777    "UMask": "0xF",
2778    "EventName": "UNC_H_HITME_HIT.HOM",
2779    "BriefDescription": "Counts Number of Hits in HitMe Cache; HOM Requests",
2780    "PublicDescription": "tbd",
2781    "Counter": "0,1,2,3",
2782    "MSRValue": "0x00",
2783    "ELLC": "0",
2784    "Filter": "na",
2785    "ExtSel": "0",
2786    "EVENT_STATUS": "0"
2787  },
2788  {
2789    "Unit": "HA",
2790    "EventCode": "0x72",
2791    "UMask": "0x1",
2792    "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.READ_OR_INVITOE",
2793    "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is RdCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvItoE",
2794    "PublicDescription": "tbd",
2795    "Counter": "0,1,2,3",
2796    "MSRValue": "0x00",
2797    "ELLC": "0",
2798    "Filter": "na",
2799    "ExtSel": "0",
2800    "EVENT_STATUS": "0"
2801  },
2802  {
2803    "Unit": "HA",
2804    "EventCode": "0x72",
2805    "UMask": "0x2",
2806    "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.WBMTOI",
2807    "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is WbMtoI",
2808    "PublicDescription": "tbd",
2809    "Counter": "0,1,2,3",
2810    "MSRValue": "0x00",
2811    "ELLC": "0",
2812    "Filter": "na",
2813    "ExtSel": "0",
2814    "EVENT_STATUS": "0"
2815  },
2816  {
2817    "Unit": "HA",
2818    "EventCode": "0x72",
2819    "UMask": "0x4",
2820    "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.ACKCNFLTWBI",
2821    "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is AckCnfltWbI",
2822    "PublicDescription": "tbd",
2823    "Counter": "0,1,2,3",
2824    "MSRValue": "0x00",
2825    "ELLC": "0",
2826    "Filter": "na",
2827    "ExtSel": "0",
2828    "EVENT_STATUS": "0"
2829  },
2830  {
2831    "Unit": "HA",
2832    "EventCode": "0x72",
2833    "UMask": "0x8",
2834    "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.WBMTOE_OR_S",
2835    "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is WbMtoE or WbMtoS",
2836    "PublicDescription": "tbd",
2837    "Counter": "0,1,2,3",
2838    "MSRValue": "0x00",
2839    "ELLC": "0",
2840    "Filter": "na",
2841    "ExtSel": "0",
2842    "EVENT_STATUS": "0"
2843  },
2844  {
2845    "Unit": "HA",
2846    "EventCode": "0x72",
2847    "UMask": "0x10",
2848    "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.RSPFWDI_REMOTE",
2849    "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is RspIFwd or RspIFwdWb for a remote request",
2850    "PublicDescription": "tbd",
2851    "Counter": "0,1,2,3",
2852    "MSRValue": "0x00",
2853    "ELLC": "0",
2854    "Filter": "na",
2855    "ExtSel": "0",
2856    "EVENT_STATUS": "0"
2857  },
2858  {
2859    "Unit": "HA",
2860    "EventCode": "0x72",
2861    "UMask": "0x20",
2862    "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.RSPFWDI_LOCAL",
2863    "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is RspIFwd or RspIFwdWb for a local request",
2864    "PublicDescription": "tbd",
2865    "Counter": "0,1,2,3",
2866    "MSRValue": "0x00",
2867    "ELLC": "0",
2868    "Filter": "na",
2869    "ExtSel": "0",
2870    "EVENT_STATUS": "0"
2871  },
2872  {
2873    "Unit": "HA",
2874    "EventCode": "0x72",
2875    "UMask": "0x40",
2876    "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.RSPFWDS",
2877    "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is RsSFwd or RspSFwdWb",
2878    "PublicDescription": "tbd",
2879    "Counter": "0,1,2,3",
2880    "MSRValue": "0x00",
2881    "ELLC": "0",
2882    "Filter": "na",
2883    "ExtSel": "0",
2884    "EVENT_STATUS": "0"
2885  },
2886  {
2887    "Unit": "HA",
2888    "EventCode": "0x72",
2889    "UMask": "0x80",
2890    "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.RSP",
2891    "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is RspI, RspIWb, RspS, RspSWb, RspCnflt or RspCnfltWbI",
2892    "PublicDescription": "tbd",
2893    "Counter": "0,1,2,3",
2894    "MSRValue": "0x00",
2895    "ELLC": "0",
2896    "Filter": "na",
2897    "ExtSel": "0",
2898    "EVENT_STATUS": "0"
2899  },
2900  {
2901    "Unit": "HA",
2902    "EventCode": "0x72",
2903    "UMask": "0xFF",
2904    "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.ALL",
2905    "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; All Requests",
2906    "PublicDescription": "tbd",
2907    "Counter": "0,1,2,3",
2908    "MSRValue": "0x00",
2909    "ELLC": "0",
2910    "Filter": "na",
2911    "ExtSel": "0",
2912    "EVENT_STATUS": "0"
2913  },
2914  {
2915    "Unit": "HA",
2916    "EventCode": "0x72",
2917    "UMask": "0xF",
2918    "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.HOM",
2919    "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; HOM Requests",
2920    "PublicDescription": "tbd",
2921    "Counter": "0,1,2,3",
2922    "MSRValue": "0x00",
2923    "ELLC": "0",
2924    "Filter": "na",
2925    "ExtSel": "0",
2926    "EVENT_STATUS": "0"
2927  },
2928  {
2929    "Unit": "HA",
2930    "EventCode": "0x70",
2931    "UMask": "0x1",
2932    "EventName": "UNC_H_HITME_LOOKUP.READ_OR_INVITOE",
2933    "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is RdCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvItoE",
2934    "PublicDescription": "tbd",
2935    "Counter": "0,1,2,3",
2936    "MSRValue": "0x00",
2937    "ELLC": "0",
2938    "Filter": "na",
2939    "ExtSel": "0",
2940    "EVENT_STATUS": "0"
2941  },
2942  {
2943    "Unit": "HA",
2944    "EventCode": "0x70",
2945    "UMask": "0x2",
2946    "EventName": "UNC_H_HITME_LOOKUP.WBMTOI",
2947    "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is WbMtoI",
2948    "PublicDescription": "tbd",
2949    "Counter": "0,1,2,3",
2950    "MSRValue": "0x00",
2951    "ELLC": "0",
2952    "Filter": "na",
2953    "ExtSel": "0",
2954    "EVENT_STATUS": "0"
2955  },
2956  {
2957    "Unit": "HA",
2958    "EventCode": "0x70",
2959    "UMask": "0x4",
2960    "EventName": "UNC_H_HITME_LOOKUP.ACKCNFLTWBI",
2961    "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is AckCnfltWbI",
2962    "PublicDescription": "tbd",
2963    "Counter": "0,1,2,3",
2964    "MSRValue": "0x00",
2965    "ELLC": "0",
2966    "Filter": "na",
2967    "ExtSel": "0",
2968    "EVENT_STATUS": "0"
2969  },
2970  {
2971    "Unit": "HA",
2972    "EventCode": "0x70",
2973    "UMask": "0x8",
2974    "EventName": "UNC_H_HITME_LOOKUP.WBMTOE_OR_S",
2975    "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is WbMtoE or WbMtoS",
2976    "PublicDescription": "tbd",
2977    "Counter": "0,1,2,3",
2978    "MSRValue": "0x00",
2979    "ELLC": "0",
2980    "Filter": "na",
2981    "ExtSel": "0",
2982    "EVENT_STATUS": "0"
2983  },
2984  {
2985    "Unit": "HA",
2986    "EventCode": "0x70",
2987    "UMask": "0x10",
2988    "EventName": "UNC_H_HITME_LOOKUP.RSPFWDI_REMOTE",
2989    "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is RspIFwd or RspIFwdWb for a remote request",
2990    "PublicDescription": "tbd",
2991    "Counter": "0,1,2,3",
2992    "MSRValue": "0x00",
2993    "ELLC": "0",
2994    "Filter": "na",
2995    "ExtSel": "0",
2996    "EVENT_STATUS": "0"
2997  },
2998  {
2999    "Unit": "HA",
3000    "EventCode": "0x70",
3001    "UMask": "0x20",
3002    "EventName": "UNC_H_HITME_LOOKUP.RSPFWDI_LOCAL",
3003    "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is RspIFwd or RspIFwdWb for a local request",
3004    "PublicDescription": "tbd",
3005    "Counter": "0,1,2,3",
3006    "MSRValue": "0x00",
3007    "ELLC": "0",
3008    "Filter": "na",
3009    "ExtSel": "0",
3010    "EVENT_STATUS": "0"
3011  },
3012  {
3013    "Unit": "HA",
3014    "EventCode": "0x70",
3015    "UMask": "0x40",
3016    "EventName": "UNC_H_HITME_LOOKUP.RSPFWDS",
3017    "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is RsSFwd or RspSFwdWb",
3018    "PublicDescription": "tbd",
3019    "Counter": "0,1,2,3",
3020    "MSRValue": "0x00",
3021    "ELLC": "0",
3022    "Filter": "na",
3023    "ExtSel": "0",
3024    "EVENT_STATUS": "0"
3025  },
3026  {
3027    "Unit": "HA",
3028    "EventCode": "0x70",
3029    "UMask": "0x80",
3030    "EventName": "UNC_H_HITME_LOOKUP.RSP",
3031    "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is RspI, RspIWb, RspS, RspSWb, RspCnflt or RspCnfltWbI",
3032    "PublicDescription": "tbd",
3033    "Counter": "0,1,2,3",
3034    "MSRValue": "0x00",
3035    "ELLC": "0",
3036    "Filter": "na",
3037    "ExtSel": "0",
3038    "EVENT_STATUS": "0"
3039  },
3040  {
3041    "Unit": "HA",
3042    "EventCode": "0x70",
3043    "UMask": "0x70",
3044    "EventName": "UNC_H_HITME_LOOKUP.ALLOCS",
3045    "BriefDescription": "Counts Number of times HitMe Cache is accessed; Allocations",
3046    "PublicDescription": "tbd",
3047    "Counter": "0,1,2,3",
3048    "MSRValue": "0x00",
3049    "ELLC": "0",
3050    "Filter": "na",
3051    "ExtSel": "0",
3052    "EVENT_STATUS": "0"
3053  },
3054  {
3055    "Unit": "HA",
3056    "EventCode": "0x70",
3057    "UMask": "0x26",
3058    "EventName": "UNC_H_HITME_LOOKUP.INVALS",
3059    "BriefDescription": "Counts Number of times HitMe Cache is accessed; Invalidations",
3060    "PublicDescription": "tbd",
3061    "Counter": "0,1,2,3",
3062    "MSRValue": "0x00",
3063    "ELLC": "0",
3064    "Filter": "na",
3065    "ExtSel": "0",
3066    "EVENT_STATUS": "0"
3067  },
3068  {
3069    "Unit": "HA",
3070    "EventCode": "0x70",
3071    "UMask": "0xFF",
3072    "EventName": "UNC_H_HITME_LOOKUP.ALL",
3073    "BriefDescription": "Counts Number of times HitMe Cache is accessed; All Requests",
3074    "PublicDescription": "tbd",
3075    "Counter": "0,1,2,3",
3076    "MSRValue": "0x00",
3077    "ELLC": "0",
3078    "Filter": "na",
3079    "ExtSel": "0",
3080    "EVENT_STATUS": "0"
3081  },
3082  {
3083    "Unit": "HA",
3084    "EventCode": "0x70",
3085    "UMask": "0xF",
3086    "EventName": "UNC_H_HITME_LOOKUP.HOM",
3087    "BriefDescription": "Counts Number of times HitMe Cache is accessed; HOM Requests",
3088    "PublicDescription": "tbd",
3089    "Counter": "0,1,2,3",
3090    "MSRValue": "0x00",
3091    "ELLC": "0",
3092    "Filter": "na",
3093    "ExtSel": "0",
3094    "EVENT_STATUS": "0"
3095  },
3096  {
3097    "Unit": "HA",
3098    "EventCode": "0x22",
3099    "UMask": "0x1",
3100    "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI0",
3101    "BriefDescription": "Cycles without QPI Ingress Credits; AD to QPI Link 0",
3102    "PublicDescription": "Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent.  This can be filtered by the different credit pools and the different links.",
3103    "Counter": "0,1,2,3",
3104    "MSRValue": "0x00",
3105    "ELLC": "0",
3106    "Filter": "na",
3107    "ExtSel": "0",
3108    "EVENT_STATUS": "0"
3109  },
3110  {
3111    "Unit": "HA",
3112    "EventCode": "0x22",
3113    "UMask": "0x2",
3114    "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI1",
3115    "BriefDescription": "Cycles without QPI Ingress Credits; AD to QPI Link 1",
3116    "PublicDescription": "Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent.  This can be filtered by the different credit pools and the different links.",
3117    "Counter": "0,1,2,3",
3118    "MSRValue": "0x00",
3119    "ELLC": "0",
3120    "Filter": "na",
3121    "ExtSel": "0",
3122    "EVENT_STATUS": "0"
3123  },
3124  {
3125    "Unit": "HA",
3126    "EventCode": "0x22",
3127    "UMask": "0x4",
3128    "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI0",
3129    "BriefDescription": "Cycles without QPI Ingress Credits; BL to QPI Link 0",
3130    "PublicDescription": "Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent.  This can be filtered by the different credit pools and the different links.",
3131    "Counter": "0,1,2,3",
3132    "MSRValue": "0x00",
3133    "ELLC": "0",
3134    "Filter": "na",
3135    "ExtSel": "0",
3136    "EVENT_STATUS": "0"
3137  },
3138  {
3139    "Unit": "HA",
3140    "EventCode": "0x22",
3141    "UMask": "0x8",
3142    "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI1",
3143    "BriefDescription": "Cycles without QPI Ingress Credits; BL to QPI Link 1",
3144    "PublicDescription": "Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent.  This can be filtered by the different credit pools and the different links.",
3145    "Counter": "0,1,2,3",
3146    "MSRValue": "0x00",
3147    "ELLC": "0",
3148    "Filter": "na",
3149    "ExtSel": "0",
3150    "EVENT_STATUS": "0"
3151  },
3152  {
3153    "Unit": "HA",
3154    "EventCode": "0x22",
3155    "UMask": "0x10",
3156    "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI2",
3157    "BriefDescription": "Cycles without QPI Ingress Credits; BL to QPI Link 0",
3158    "PublicDescription": "Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent.  This can be filtered by the different credit pools and the different links.",
3159    "Counter": "0,1,2,3",
3160    "MSRValue": "0x00",
3161    "ELLC": "0",
3162    "Filter": "na",
3163    "ExtSel": "0",
3164    "EVENT_STATUS": "0"
3165  },
3166  {
3167    "Unit": "HA",
3168    "EventCode": "0x22",
3169    "UMask": "0x20",
3170    "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI2",
3171    "BriefDescription": "Cycles without QPI Ingress Credits; BL to QPI Link 1",
3172    "PublicDescription": "Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent.  This can be filtered by the different credit pools and the different links.",
3173    "Counter": "0,1,2,3",
3174    "MSRValue": "0x00",
3175    "ELLC": "0",
3176    "Filter": "na",
3177    "ExtSel": "0",
3178    "EVENT_STATUS": "0"
3179  },
3180  {
3181    "Unit": "HA",
3182    "EventCode": "0x17",
3183    "UMask": "0x1",
3184    "EventName": "UNC_H_IMC_READS.NORMAL",
3185    "BriefDescription": "HA to iMC Normal Priority Reads Issued; Normal Priority",
3186    "PublicDescription": "Count of the number of reads issued to any of the memory controller channels.  This can be filtered by the priority of the reads.",
3187    "Counter": "0,1,2,3",
3188    "MSRValue": "0x00",
3189    "ELLC": "0",
3190    "Filter": "na",
3191    "ExtSel": "0",
3192    "EVENT_STATUS": "0"
3193  },
3194  {
3195    "Unit": "HA",
3196    "EventCode": "0x1E",
3197    "UMask": "0x0",
3198    "EventName": "UNC_H_IMC_RETRY",
3199    "BriefDescription": "Retry Events",
3200    "PublicDescription": "tbd",
3201    "Counter": "0,1,2,3",
3202    "MSRValue": "0x00",
3203    "ELLC": "0",
3204    "Filter": "na",
3205    "ExtSel": "0",
3206    "EVENT_STATUS": "0"
3207  },
3208  {
3209    "Unit": "HA",
3210    "EventCode": "0x1A",
3211    "UMask": "0x1",
3212    "EventName": "UNC_H_IMC_WRITES.FULL",
3213    "BriefDescription": "HA to iMC Full Line Writes Issued; Full Line Non-ISOCH",
3214    "PublicDescription": "Counts the total number of full line writes issued from the HA into the memory controller.  This counts for all four channels.  It can be filtered by full/partial and ISOCH/non-ISOCH.",
3215    "Counter": "0,1,2,3",
3216    "MSRValue": "0x00",
3217    "ELLC": "0",
3218    "Filter": "na",
3219    "ExtSel": "0",
3220    "EVENT_STATUS": "0"
3221  },
3222  {
3223    "Unit": "HA",
3224    "EventCode": "0x1A",
3225    "UMask": "0x2",
3226    "EventName": "UNC_H_IMC_WRITES.PARTIAL",
3227    "BriefDescription": "HA to iMC Full Line Writes Issued; Partial Non-ISOCH",
3228    "PublicDescription": "Counts the total number of full line writes issued from the HA into the memory controller.  This counts for all four channels.  It can be filtered by full/partial and ISOCH/non-ISOCH.",
3229    "Counter": "0,1,2,3",
3230    "MSRValue": "0x00",
3231    "ELLC": "0",
3232    "Filter": "na",
3233    "ExtSel": "0",
3234    "EVENT_STATUS": "0"
3235  },
3236  {
3237    "Unit": "HA",
3238    "EventCode": "0x1A",
3239    "UMask": "0x4",
3240    "EventName": "UNC_H_IMC_WRITES.FULL_ISOCH",
3241    "BriefDescription": "HA to iMC Full Line Writes Issued; ISOCH Full Line",
3242    "PublicDescription": "Counts the total number of full line writes issued from the HA into the memory controller.  This counts for all four channels.  It can be filtered by full/partial and ISOCH/non-ISOCH.",
3243    "Counter": "0,1,2,3",
3244    "MSRValue": "0x00",
3245    "ELLC": "0",
3246    "Filter": "na",
3247    "ExtSel": "0",
3248    "EVENT_STATUS": "0"
3249  },
3250  {
3251    "Unit": "HA",
3252    "EventCode": "0x1A",
3253    "UMask": "0x8",
3254    "EventName": "UNC_H_IMC_WRITES.PARTIAL_ISOCH",
3255    "BriefDescription": "HA to iMC Full Line Writes Issued; ISOCH Partial",
3256    "PublicDescription": "Counts the total number of full line writes issued from the HA into the memory controller.  This counts for all four channels.  It can be filtered by full/partial and ISOCH/non-ISOCH.",
3257    "Counter": "0,1,2,3",
3258    "MSRValue": "0x00",
3259    "ELLC": "0",
3260    "Filter": "na",
3261    "ExtSel": "0",
3262    "EVENT_STATUS": "0"
3263  },
3264  {
3265    "Unit": "HA",
3266    "EventCode": "0x1A",
3267    "UMask": "0xF",
3268    "EventName": "UNC_H_IMC_WRITES.ALL",
3269    "BriefDescription": "HA to iMC Full Line Writes Issued; All Writes",
3270    "PublicDescription": "Counts the total number of full line writes issued from the HA into the memory controller.  This counts for all four channels.  It can be filtered by full/partial and ISOCH/non-ISOCH.",
3271    "Counter": "0,1,2,3",
3272    "MSRValue": "0x00",
3273    "ELLC": "0",
3274    "Filter": "na",
3275    "ExtSel": "0",
3276    "EVENT_STATUS": "0"
3277  },
3278  {
3279    "Unit": "HA",
3280    "EventCode": "0x61",
3281    "UMask": "0x1",
3282    "EventName": "UNC_H_IOT_BACKPRESSURE.SAT",
3283    "BriefDescription": "IOT Backpressure",
3284    "PublicDescription": "tbd",
3285    "Counter": "0,1,2",
3286    "MSRValue": "0x00",
3287    "ELLC": "0",
3288    "Filter": "na",
3289    "ExtSel": "0",
3290    "EVENT_STATUS": "0"
3291  },
3292  {
3293    "Unit": "HA",
3294    "EventCode": "0x61",
3295    "UMask": "0x2",
3296    "EventName": "UNC_H_IOT_BACKPRESSURE.HUB",
3297    "BriefDescription": "IOT Backpressure",
3298    "PublicDescription": "tbd",
3299    "Counter": "0,1,2",
3300    "MSRValue": "0x00",
3301    "ELLC": "0",
3302    "Filter": "na",
3303    "ExtSel": "0",
3304    "EVENT_STATUS": "0"
3305  },
3306  {
3307    "Unit": "HA",
3308    "EventCode": "0x64",
3309    "UMask": "0x1",
3310    "EventName": "UNC_H_IOT_CTS_EAST_LO.CTS0",
3311    "BriefDescription": "IOT Common Trigger Sequencer - Lo",
3312    "PublicDescription": "Debug Mask/Match Tie-Ins",
3313    "Counter": "0,1,2",
3314    "MSRValue": "0x00",
3315    "ELLC": "0",
3316    "Filter": "na",
3317    "ExtSel": "0",
3318    "EVENT_STATUS": "0"
3319  },
3320  {
3321    "Unit": "HA",
3322    "EventCode": "0x64",
3323    "UMask": "0x2",
3324    "EventName": "UNC_H_IOT_CTS_EAST_LO.CTS1",
3325    "BriefDescription": "IOT Common Trigger Sequencer - Lo",
3326    "PublicDescription": "Debug Mask/Match Tie-Ins",
3327    "Counter": "0,1,2",
3328    "MSRValue": "0x00",
3329    "ELLC": "0",
3330    "Filter": "na",
3331    "ExtSel": "0",
3332    "EVENT_STATUS": "0"
3333  },
3334  {
3335    "Unit": "HA",
3336    "EventCode": "0x65",
3337    "UMask": "0x1",
3338    "EventName": "UNC_H_IOT_CTS_HI.CTS2",
3339    "BriefDescription": "IOT Common Trigger Sequencer - Hi",
3340    "PublicDescription": "Debug Mask/Match Tie-Ins",
3341    "Counter": "0,1,2",
3342    "MSRValue": "0x00",
3343    "ELLC": "0",
3344    "Filter": "na",
3345    "ExtSel": "0",
3346    "EVENT_STATUS": "0"
3347  },
3348  {
3349    "Unit": "HA",
3350    "EventCode": "0x65",
3351    "UMask": "0x2",
3352    "EventName": "UNC_H_IOT_CTS_HI.CTS3",
3353    "BriefDescription": "IOT Common Trigger Sequencer - Hi",
3354    "PublicDescription": "Debug Mask/Match Tie-Ins",
3355    "Counter": "0,1,2",
3356    "MSRValue": "0x00",
3357    "ELLC": "0",
3358    "Filter": "na",
3359    "ExtSel": "0",
3360    "EVENT_STATUS": "0"
3361  },
3362  {
3363    "Unit": "HA",
3364    "EventCode": "0x62",
3365    "UMask": "0x1",
3366    "EventName": "UNC_H_IOT_CTS_WEST_LO.CTS0",
3367    "BriefDescription": "IOT Common Trigger Sequencer - Lo",
3368    "PublicDescription": "Debug Mask/Match Tie-Ins",
3369    "Counter": "0,1,2",
3370    "MSRValue": "0x00",
3371    "ELLC": "0",
3372    "Filter": "na",
3373    "ExtSel": "0",
3374    "EVENT_STATUS": "0"
3375  },
3376  {
3377    "Unit": "HA",
3378    "EventCode": "0x62",
3379    "UMask": "0x2",
3380    "EventName": "UNC_H_IOT_CTS_WEST_LO.CTS1",
3381    "BriefDescription": "IOT Common Trigger Sequencer - Lo",
3382    "PublicDescription": "Debug Mask/Match Tie-Ins",
3383    "Counter": "0,1,2",
3384    "MSRValue": "0x00",
3385    "ELLC": "0",
3386    "Filter": "na",
3387    "ExtSel": "0",
3388    "EVENT_STATUS": "0"
3389  },
3390  {
3391    "Unit": "HA",
3392    "EventCode": "0x53",
3393    "UMask": "0x2",
3394    "EventName": "UNC_H_OSB.READS_LOCAL",
3395    "BriefDescription": "OSB Snoop Broadcast; Local Reads",
3396    "PublicDescription": "Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.",
3397    "Counter": "0,1,2,3",
3398    "MSRValue": "0x00",
3399    "ELLC": "0",
3400    "Filter": "na",
3401    "ExtSel": "0",
3402    "EVENT_STATUS": "0"
3403  },
3404  {
3405    "Unit": "HA",
3406    "EventCode": "0x53",
3407    "UMask": "0x4",
3408    "EventName": "UNC_H_OSB.INVITOE_LOCAL",
3409    "BriefDescription": "OSB Snoop Broadcast; Local InvItoE",
3410    "PublicDescription": "Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.",
3411    "Counter": "0,1,2,3",
3412    "MSRValue": "0x00",
3413    "ELLC": "0",
3414    "Filter": "na",
3415    "ExtSel": "0",
3416    "EVENT_STATUS": "0"
3417  },
3418  {
3419    "Unit": "HA",
3420    "EventCode": "0x53",
3421    "UMask": "0x8",
3422    "EventName": "UNC_H_OSB.REMOTE",
3423    "BriefDescription": "OSB Snoop Broadcast; Remote",
3424    "PublicDescription": "Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.",
3425    "Counter": "0,1,2,3",
3426    "MSRValue": "0x00",
3427    "ELLC": "0",
3428    "Filter": "na",
3429    "ExtSel": "0",
3430    "EVENT_STATUS": "0"
3431  },
3432  {
3433    "Unit": "HA",
3434    "EventCode": "0x53",
3435    "UMask": "0x10",
3436    "EventName": "UNC_H_OSB.CANCELLED",
3437    "BriefDescription": "OSB Snoop Broadcast; Cancelled",
3438    "PublicDescription": "Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.; OSB Snoop broadcast cancelled due to D2C or Other. OSB cancel is counted when OSB local read is not allowed even when the transaction in local InItoE. It also counts D2C OSB cancel, but also includes the cases were D2C was not set in the first place for the transaction coming from the ring.",
3439    "Counter": "0,1,2,3",
3440    "MSRValue": "0x00",
3441    "ELLC": "0",
3442    "Filter": "na",
3443    "ExtSel": "0",
3444    "EVENT_STATUS": "0"
3445  },
3446  {
3447    "Unit": "HA",
3448    "EventCode": "0x53",
3449    "UMask": "0x20",
3450    "EventName": "UNC_H_OSB.READS_LOCAL_USEFUL",
3451    "BriefDescription": "OSB Snoop Broadcast; Reads Local -  Useful",
3452    "PublicDescription": "Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.",
3453    "Counter": "0,1,2,3",
3454    "MSRValue": "0x00",
3455    "ELLC": "0",
3456    "Filter": "na",
3457    "ExtSel": "0",
3458    "EVENT_STATUS": "0"
3459  },
3460  {
3461    "Unit": "HA",
3462    "EventCode": "0x53",
3463    "UMask": "0x40",
3464    "EventName": "UNC_H_OSB.REMOTE_USEFUL",
3465    "BriefDescription": "OSB Snoop Broadcast; Remote - Useful",
3466    "PublicDescription": "Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.",
3467    "Counter": "0,1,2,3",
3468    "MSRValue": "0x00",
3469    "ELLC": "0",
3470    "Filter": "na",
3471    "ExtSel": "0",
3472    "EVENT_STATUS": "0"
3473  },
3474  {
3475    "Unit": "HA",
3476    "EventCode": "0x54",
3477    "UMask": "0x1",
3478    "EventName": "UNC_H_OSB_EDR.ALL",
3479    "BriefDescription": "OSB Early Data Return; All",
3480    "PublicDescription": "Counts the number of transactions that broadcast snoop due to OSB, but found clean data in memory and was able to do early data return",
3481    "Counter": "0,1,2,3",
3482    "MSRValue": "0x00",
3483    "ELLC": "0",
3484    "Filter": "na",
3485    "ExtSel": "0",
3486    "EVENT_STATUS": "0"
3487  },
3488  {
3489    "Unit": "HA",
3490    "EventCode": "0x54",
3491    "UMask": "0x2",
3492    "EventName": "UNC_H_OSB_EDR.READS_LOCAL_I",
3493    "BriefDescription": "OSB Early Data Return; Reads to Local  I",
3494    "PublicDescription": "Counts the number of transactions that broadcast snoop due to OSB, but found clean data in memory and was able to do early data return",
3495    "Counter": "0,1,2,3",
3496    "MSRValue": "0x00",
3497    "ELLC": "0",
3498    "Filter": "na",
3499    "ExtSel": "0",
3500    "EVENT_STATUS": "0"
3501  },
3502  {
3503    "Unit": "HA",
3504    "EventCode": "0x54",
3505    "UMask": "0x4",
3506    "EventName": "UNC_H_OSB_EDR.READS_REMOTE_I",
3507    "BriefDescription": "OSB Early Data Return; Reads to Remote I",
3508    "PublicDescription": "Counts the number of transactions that broadcast snoop due to OSB, but found clean data in memory and was able to do early data return",
3509    "Counter": "0,1,2,3",
3510    "MSRValue": "0x00",
3511    "ELLC": "0",
3512    "Filter": "na",
3513    "ExtSel": "0",
3514    "EVENT_STATUS": "0"
3515  },
3516  {
3517    "Unit": "HA",
3518    "EventCode": "0x54",
3519    "UMask": "0x8",
3520    "EventName": "UNC_H_OSB_EDR.READS_LOCAL_S",
3521    "BriefDescription": "OSB Early Data Return; Reads to Local S",
3522    "PublicDescription": "Counts the number of transactions that broadcast snoop due to OSB, but found clean data in memory and was able to do early data return",
3523    "Counter": "0,1,2,3",
3524    "MSRValue": "0x00",
3525    "ELLC": "0",
3526    "Filter": "na",
3527    "ExtSel": "0",
3528    "EVENT_STATUS": "0"
3529  },
3530  {
3531    "Unit": "HA",
3532    "EventCode": "0x54",
3533    "UMask": "0x10",
3534    "EventName": "UNC_H_OSB_EDR.READS_REMOTE_S",
3535    "BriefDescription": "OSB Early Data Return; Reads to Remote S",
3536    "PublicDescription": "Counts the number of transactions that broadcast snoop due to OSB, but found clean data in memory and was able to do early data return",
3537    "Counter": "0,1,2,3",
3538    "MSRValue": "0x00",
3539    "ELLC": "0",
3540    "Filter": "na",
3541    "ExtSel": "0",
3542    "EVENT_STATUS": "0"
3543  },
3544  {
3545    "Unit": "HA",
3546    "EventCode": "0x1",
3547    "UMask": "0x3",
3548    "EventName": "UNC_H_REQUESTS.READS",
3549    "BriefDescription": "Read and Write Requests; Reads",
3550    "PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO).  Writes include all writes (streaming, evictions, HitM, etc).; Incoming ead requests.  This is a good proxy for LLC Read Misses (including RFOs).",
3551    "Counter": "0,1,2,3",
3552    "MSRValue": "0x00",
3553    "ELLC": "0",
3554    "Filter": "na",
3555    "ExtSel": "0",
3556    "EVENT_STATUS": "0"
3557  },
3558  {
3559    "Unit": "HA",
3560    "EventCode": "0x1",
3561    "UMask": "0xC",
3562    "EventName": "UNC_H_REQUESTS.WRITES",
3563    "BriefDescription": "Read and Write Requests; Writes",
3564    "PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO).  Writes include all writes (streaming, evictions, HitM, etc).; Incoming write requests.",
3565    "Counter": "0,1,2,3",
3566    "MSRValue": "0x00",
3567    "ELLC": "0",
3568    "Filter": "na",
3569    "ExtSel": "0",
3570    "EVENT_STATUS": "0"
3571  },
3572  {
3573    "Unit": "HA",
3574    "EventCode": "0x1",
3575    "UMask": "0x1",
3576    "EventName": "UNC_H_REQUESTS.READS_LOCAL",
3577    "BriefDescription": "Read and Write Requests; Local Reads",
3578    "PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO).  Writes include all writes (streaming, evictions, HitM, etc).; This filter includes only read requests coming from the local socket.  This is a good proxy for LLC Read Misses (including RFOs) from the local socket.",
3579    "Counter": "0,1,2,3",
3580    "MSRValue": "0x00",
3581    "ELLC": "0",
3582    "Filter": "na",
3583    "ExtSel": "0",
3584    "EVENT_STATUS": "0"
3585  },
3586  {
3587    "Unit": "HA",
3588    "EventCode": "0x1",
3589    "UMask": "0x2",
3590    "EventName": "UNC_H_REQUESTS.READS_REMOTE",
3591    "BriefDescription": "Read and Write Requests; Remote Reads",
3592    "PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO).  Writes include all writes (streaming, evictions, HitM, etc).; This filter includes only read requests coming from the remote socket.  This is a good proxy for LLC Read Misses (including RFOs) from the remote socket.",
3593    "Counter": "0,1,2,3",
3594    "MSRValue": "0x00",
3595    "ELLC": "0",
3596    "Filter": "na",
3597    "ExtSel": "0",
3598    "EVENT_STATUS": "0"
3599  },
3600  {
3601    "Unit": "HA",
3602    "EventCode": "0x1",
3603    "UMask": "0x4",
3604    "EventName": "UNC_H_REQUESTS.WRITES_LOCAL",
3605    "BriefDescription": "Read and Write Requests; Local Writes",
3606    "PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO).  Writes include all writes (streaming, evictions, HitM, etc).; This filter includes only writes coming from the local socket.",
3607    "Counter": "0,1,2,3",
3608    "MSRValue": "0x00",
3609    "ELLC": "0",
3610    "Filter": "na",
3611    "ExtSel": "0",
3612    "EVENT_STATUS": "0"
3613  },
3614  {
3615    "Unit": "HA",
3616    "EventCode": "0x1",
3617    "UMask": "0x8",
3618    "EventName": "UNC_H_REQUESTS.WRITES_REMOTE",
3619    "BriefDescription": "Read and Write Requests; Remote Writes",
3620    "PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO).  Writes include all writes (streaming, evictions, HitM, etc).; This filter includes only writes coming from remote sockets.",
3621    "Counter": "0,1,2,3",
3622    "MSRValue": "0x00",
3623    "ELLC": "0",
3624    "Filter": "na",
3625    "ExtSel": "0",
3626    "EVENT_STATUS": "0"
3627  },
3628  {
3629    "Unit": "HA",
3630    "EventCode": "0x1",
3631    "UMask": "0x10",
3632    "EventName": "UNC_H_REQUESTS.INVITOE_LOCAL",
3633    "BriefDescription": "Read and Write Requests; Local InvItoEs",
3634    "PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO).  Writes include all writes (streaming, evictions, HitM, etc).; This filter includes only InvItoEs coming from the local socket.",
3635    "Counter": "0,1,2,3",
3636    "MSRValue": "0x00",
3637    "ELLC": "0",
3638    "Filter": "na",
3639    "ExtSel": "0",
3640    "EVENT_STATUS": "0"
3641  },
3642  {
3643    "Unit": "HA",
3644    "EventCode": "0x1",
3645    "UMask": "0x20",
3646    "EventName": "UNC_H_REQUESTS.INVITOE_REMOTE",
3647    "BriefDescription": "Read and Write Requests; Remote InvItoEs",
3648    "PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO).  Writes include all writes (streaming, evictions, HitM, etc).; This filter includes only InvItoEs coming from remote sockets.",
3649    "Counter": "0,1,2,3",
3650    "MSRValue": "0x00",
3651    "ELLC": "0",
3652    "Filter": "na",
3653    "ExtSel": "0",
3654    "EVENT_STATUS": "0"
3655  },
3656  {
3657    "Unit": "HA",
3658    "EventCode": "0x3E",
3659    "UMask": "0x1",
3660    "EventName": "UNC_H_RING_AD_USED.CW_EVEN",
3661    "BriefDescription": "HA AD Ring in Use; Clockwise and Even",
3662    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity.",
3663    "Counter": "0,1,2,3",
3664    "MSRValue": "0x00",
3665    "ELLC": "0",
3666    "Filter": "na",
3667    "ExtSel": "0",
3668    "EVENT_STATUS": "0"
3669  },
3670  {
3671    "Unit": "HA",
3672    "EventCode": "0x3E",
3673    "UMask": "0x2",
3674    "EventName": "UNC_H_RING_AD_USED.CW_ODD",
3675    "BriefDescription": "HA AD Ring in Use; Clockwise and Odd",
3676    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity.",
3677    "Counter": "0,1,2,3",
3678    "MSRValue": "0x00",
3679    "ELLC": "0",
3680    "Filter": "na",
3681    "ExtSel": "0",
3682    "EVENT_STATUS": "0"
3683  },
3684  {
3685    "Unit": "HA",
3686    "EventCode": "0x3E",
3687    "UMask": "0x4",
3688    "EventName": "UNC_H_RING_AD_USED.CCW_EVEN",
3689    "BriefDescription": "HA AD Ring in Use; Counterclockwise and Even",
3690    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity.",
3691    "Counter": "0,1,2,3",
3692    "MSRValue": "0x00",
3693    "ELLC": "0",
3694    "Filter": "na",
3695    "ExtSel": "0",
3696    "EVENT_STATUS": "0"
3697  },
3698  {
3699    "Unit": "HA",
3700    "EventCode": "0x3E",
3701    "UMask": "0x8",
3702    "EventName": "UNC_H_RING_AD_USED.CCW_ODD",
3703    "BriefDescription": "HA AD Ring in Use; Counterclockwise and Odd",
3704    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity.",
3705    "Counter": "0,1,2,3",
3706    "MSRValue": "0x00",
3707    "ELLC": "0",
3708    "Filter": "na",
3709    "ExtSel": "0",
3710    "EVENT_STATUS": "0"
3711  },
3712  {
3713    "Unit": "HA",
3714    "EventCode": "0x3E",
3715    "UMask": "0x3",
3716    "EventName": "UNC_H_RING_AD_USED.CW",
3717    "BriefDescription": "HA AD Ring in Use; Clockwise",
3718    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
3719    "Counter": "0,1,2,3",
3720    "MSRValue": "0x00",
3721    "ELLC": "0",
3722    "Filter": "na",
3723    "ExtSel": "0",
3724    "EVENT_STATUS": "0"
3725  },
3726  {
3727    "Unit": "HA",
3728    "EventCode": "0x3E",
3729    "UMask": "0xC",
3730    "EventName": "UNC_H_RING_AD_USED.CCW",
3731    "BriefDescription": "HA AD Ring in Use; Counterclockwise",
3732    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
3733    "Counter": "0,1,2,3",
3734    "MSRValue": "0x00",
3735    "ELLC": "0",
3736    "Filter": "na",
3737    "ExtSel": "0",
3738    "EVENT_STATUS": "0"
3739  },
3740  {
3741    "Unit": "HA",
3742    "EventCode": "0x3F",
3743    "UMask": "0x1",
3744    "EventName": "UNC_H_RING_AK_USED.CW_EVEN",
3745    "BriefDescription": "HA AK Ring in Use; Clockwise and Even",
3746    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity.",
3747    "Counter": "0,1,2,3",
3748    "MSRValue": "0x00",
3749    "ELLC": "0",
3750    "Filter": "na",
3751    "ExtSel": "0",
3752    "EVENT_STATUS": "0"
3753  },
3754  {
3755    "Unit": "HA",
3756    "EventCode": "0x3F",
3757    "UMask": "0x2",
3758    "EventName": "UNC_H_RING_AK_USED.CW_ODD",
3759    "BriefDescription": "HA AK Ring in Use; Clockwise and Odd",
3760    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity.",
3761    "Counter": "0,1,2,3",
3762    "MSRValue": "0x00",
3763    "ELLC": "0",
3764    "Filter": "na",
3765    "ExtSel": "0",
3766    "EVENT_STATUS": "0"
3767  },
3768  {
3769    "Unit": "HA",
3770    "EventCode": "0x3F",
3771    "UMask": "0x4",
3772    "EventName": "UNC_H_RING_AK_USED.CCW_EVEN",
3773    "BriefDescription": "HA AK Ring in Use; Counterclockwise and Even",
3774    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity.",
3775    "Counter": "0,1,2,3",
3776    "MSRValue": "0x00",
3777    "ELLC": "0",
3778    "Filter": "na",
3779    "ExtSel": "0",
3780    "EVENT_STATUS": "0"
3781  },
3782  {
3783    "Unit": "HA",
3784    "EventCode": "0x3F",
3785    "UMask": "0x8",
3786    "EventName": "UNC_H_RING_AK_USED.CCW_ODD",
3787    "BriefDescription": "HA AK Ring in Use; Counterclockwise and Odd",
3788    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity.",
3789    "Counter": "0,1,2,3",
3790    "MSRValue": "0x00",
3791    "ELLC": "0",
3792    "Filter": "na",
3793    "ExtSel": "0",
3794    "EVENT_STATUS": "0"
3795  },
3796  {
3797    "Unit": "HA",
3798    "EventCode": "0x3F",
3799    "UMask": "0x3",
3800    "EventName": "UNC_H_RING_AK_USED.CW",
3801    "BriefDescription": "HA AK Ring in Use; Clockwise",
3802    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
3803    "Counter": "0,1,2,3",
3804    "MSRValue": "0x00",
3805    "ELLC": "0",
3806    "Filter": "na",
3807    "ExtSel": "0",
3808    "EVENT_STATUS": "0"
3809  },
3810  {
3811    "Unit": "HA",
3812    "EventCode": "0x3F",
3813    "UMask": "0xC",
3814    "EventName": "UNC_H_RING_AK_USED.CCW",
3815    "BriefDescription": "HA AK Ring in Use; Counterclockwise",
3816    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
3817    "Counter": "0,1,2,3",
3818    "MSRValue": "0x00",
3819    "ELLC": "0",
3820    "Filter": "na",
3821    "ExtSel": "0",
3822    "EVENT_STATUS": "0"
3823  },
3824  {
3825    "Unit": "HA",
3826    "EventCode": "0x40",
3827    "UMask": "0x1",
3828    "EventName": "UNC_H_RING_BL_USED.CW_EVEN",
3829    "BriefDescription": "HA BL Ring in Use; Clockwise and Even",
3830    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity.",
3831    "Counter": "0,1,2,3",
3832    "MSRValue": "0x00",
3833    "ELLC": "0",
3834    "Filter": "na",
3835    "ExtSel": "0",
3836    "EVENT_STATUS": "0"
3837  },
3838  {
3839    "Unit": "HA",
3840    "EventCode": "0x40",
3841    "UMask": "0x2",
3842    "EventName": "UNC_H_RING_BL_USED.CW_ODD",
3843    "BriefDescription": "HA BL Ring in Use; Clockwise and Odd",
3844    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity.",
3845    "Counter": "0,1,2,3",
3846    "MSRValue": "0x00",
3847    "ELLC": "0",
3848    "Filter": "na",
3849    "ExtSel": "0",
3850    "EVENT_STATUS": "0"
3851  },
3852  {
3853    "Unit": "HA",
3854    "EventCode": "0x40",
3855    "UMask": "0x4",
3856    "EventName": "UNC_H_RING_BL_USED.CCW_EVEN",
3857    "BriefDescription": "HA BL Ring in Use; Counterclockwise and Even",
3858    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity.",
3859    "Counter": "0,1,2,3",
3860    "MSRValue": "0x00",
3861    "ELLC": "0",
3862    "Filter": "na",
3863    "ExtSel": "0",
3864    "EVENT_STATUS": "0"
3865  },
3866  {
3867    "Unit": "HA",
3868    "EventCode": "0x40",
3869    "UMask": "0x8",
3870    "EventName": "UNC_H_RING_BL_USED.CCW_ODD",
3871    "BriefDescription": "HA BL Ring in Use; Counterclockwise and Odd",
3872    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity.",
3873    "Counter": "0,1,2,3",
3874    "MSRValue": "0x00",
3875    "ELLC": "0",
3876    "Filter": "na",
3877    "ExtSel": "0",
3878    "EVENT_STATUS": "0"
3879  },
3880  {
3881    "Unit": "HA",
3882    "EventCode": "0x40",
3883    "UMask": "0x3",
3884    "EventName": "UNC_H_RING_BL_USED.CW",
3885    "BriefDescription": "HA BL Ring in Use; Clockwise",
3886    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
3887    "Counter": "0,1,2,3",
3888    "MSRValue": "0x00",
3889    "ELLC": "0",
3890    "Filter": "na",
3891    "ExtSel": "0",
3892    "EVENT_STATUS": "0"
3893  },
3894  {
3895    "Unit": "HA",
3896    "EventCode": "0x40",
3897    "UMask": "0xC",
3898    "EventName": "UNC_H_RING_BL_USED.CCW",
3899    "BriefDescription": "HA BL Ring in Use; Counterclockwise",
3900    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
3901    "Counter": "0,1,2,3",
3902    "MSRValue": "0x00",
3903    "ELLC": "0",
3904    "Filter": "na",
3905    "ExtSel": "0",
3906    "EVENT_STATUS": "0"
3907  },
3908  {
3909    "Unit": "HA",
3910    "EventCode": "0x15",
3911    "UMask": "0x1",
3912    "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN0",
3913    "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 0",
3914    "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting reads from the HA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue).  This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads.  This count only tracks the regular credits  Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 0 only.",
3915    "Counter": "0,1,2,3",
3916    "MSRValue": "0x00",
3917    "ELLC": "0",
3918    "Filter": "na",
3919    "ExtSel": "0",
3920    "EVENT_STATUS": "0"
3921  },
3922  {
3923    "Unit": "HA",
3924    "EventCode": "0x15",
3925    "UMask": "0x2",
3926    "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN1",
3927    "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 1",
3928    "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting reads from the HA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue).  This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads.  This count only tracks the regular credits  Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 1 only.",
3929    "Counter": "0,1,2,3",
3930    "MSRValue": "0x00",
3931    "ELLC": "0",
3932    "Filter": "na",
3933    "ExtSel": "0",
3934    "EVENT_STATUS": "0"
3935  },
3936  {
3937    "Unit": "HA",
3938    "EventCode": "0x15",
3939    "UMask": "0x4",
3940    "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN2",
3941    "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 2",
3942    "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting reads from the HA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue).  This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads.  This count only tracks the regular credits  Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 2 only.",
3943    "Counter": "0,1,2,3",
3944    "MSRValue": "0x00",
3945    "ELLC": "0",
3946    "Filter": "na",
3947    "ExtSel": "0",
3948    "EVENT_STATUS": "0"
3949  },
3950  {
3951    "Unit": "HA",
3952    "EventCode": "0x15",
3953    "UMask": "0x8",
3954    "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN3",
3955    "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 3",
3956    "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting reads from the HA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue).  This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads.  This count only tracks the regular credits  Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 3 only.",
3957    "Counter": "0,1,2,3",
3958    "MSRValue": "0x00",
3959    "ELLC": "0",
3960    "Filter": "na",
3961    "ExtSel": "0",
3962    "EVENT_STATUS": "0"
3963  },
3964  {
3965    "Unit": "HA",
3966    "EventCode": "0x16",
3967    "UMask": "0x1",
3968    "EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN0",
3969    "BriefDescription": "iMC RPQ Credits Empty - Special; Channel 0",
3970    "PublicDescription": "Counts the number of cycles when there are no special credits available for posting reads from the HA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue).  This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads.  This count only tracks the special credits.  This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 0 only.",
3971    "Counter": "0,1,2,3",
3972    "MSRValue": "0x00",
3973    "ELLC": "0",
3974    "Filter": "na",
3975    "ExtSel": "0",
3976    "EVENT_STATUS": "0"
3977  },
3978  {
3979    "Unit": "HA",
3980    "EventCode": "0x16",
3981    "UMask": "0x2",
3982    "EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN1",
3983    "BriefDescription": "iMC RPQ Credits Empty - Special; Channel 1",
3984    "PublicDescription": "Counts the number of cycles when there are no special credits available for posting reads from the HA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue).  This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads.  This count only tracks the special credits.  This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 1 only.",
3985    "Counter": "0,1,2,3",
3986    "MSRValue": "0x00",
3987    "ELLC": "0",
3988    "Filter": "na",
3989    "ExtSel": "0",
3990    "EVENT_STATUS": "0"
3991  },
3992  {
3993    "Unit": "HA",
3994    "EventCode": "0x16",
3995    "UMask": "0x4",
3996    "EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN2",
3997    "BriefDescription": "iMC RPQ Credits Empty - Special; Channel 2",
3998    "PublicDescription": "Counts the number of cycles when there are no special credits available for posting reads from the HA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue).  This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads.  This count only tracks the special credits.  This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 2 only.",
3999    "Counter": "0,1,2,3",
4000    "MSRValue": "0x00",
4001    "ELLC": "0",
4002    "Filter": "na",
4003    "ExtSel": "0",
4004    "EVENT_STATUS": "0"
4005  },
4006  {
4007    "Unit": "HA",
4008    "EventCode": "0x16",
4009    "UMask": "0x8",
4010    "EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN3",
4011    "BriefDescription": "iMC RPQ Credits Empty - Special; Channel 3",
4012    "PublicDescription": "Counts the number of cycles when there are no special credits available for posting reads from the HA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue).  This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads.  This count only tracks the special credits.  This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 3 only.",
4013    "Counter": "0,1,2,3",
4014    "MSRValue": "0x00",
4015    "ELLC": "0",
4016    "Filter": "na",
4017    "ExtSel": "0",
4018    "EVENT_STATUS": "0"
4019  },
4020  {
4021    "Unit": "HA",
4022    "EventCode": "0x68",
4023    "UMask": "0x1",
4024    "EventName": "UNC_H_SBO0_CREDITS_ACQUIRED.AD",
4025    "BriefDescription": "SBo0 Credits Acquired; For AD Ring",
4026    "PublicDescription": "Number of Sbo 0 credits acquired in a given cycle, per ring.",
4027    "Counter": "0,1,2,3",
4028    "MSRValue": "0x00",
4029    "ELLC": "0",
4030    "Filter": "na",
4031    "ExtSel": "0",
4032    "EVENT_STATUS": "0"
4033  },
4034  {
4035    "Unit": "HA",
4036    "EventCode": "0x68",
4037    "UMask": "0x2",
4038    "EventName": "UNC_H_SBO0_CREDITS_ACQUIRED.BL",
4039    "BriefDescription": "SBo0 Credits Acquired; For BL Ring",
4040    "PublicDescription": "Number of Sbo 0 credits acquired in a given cycle, per ring.",
4041    "Counter": "0,1,2,3",
4042    "MSRValue": "0x00",
4043    "ELLC": "0",
4044    "Filter": "na",
4045    "ExtSel": "0",
4046    "EVENT_STATUS": "0"
4047  },
4048  {
4049    "Unit": "HA",
4050    "EventCode": "0x6A",
4051    "UMask": "0x1",
4052    "EventName": "UNC_H_SBO0_CREDIT_OCCUPANCY.AD",
4053    "BriefDescription": "SBo0 Credits Occupancy; For AD Ring",
4054    "PublicDescription": "Number of Sbo 0 credits in use in a given cycle, per ring.",
4055    "Counter": "0,1,2,3",
4056    "MSRValue": "0x00",
4057    "ELLC": "0",
4058    "Filter": "na",
4059    "ExtSel": "0",
4060    "EVENT_STATUS": "0"
4061  },
4062  {
4063    "Unit": "HA",
4064    "EventCode": "0x6A",
4065    "UMask": "0x2",
4066    "EventName": "UNC_H_SBO0_CREDIT_OCCUPANCY.BL",
4067    "BriefDescription": "SBo0 Credits Occupancy; For BL Ring",
4068    "PublicDescription": "Number of Sbo 0 credits in use in a given cycle, per ring.",
4069    "Counter": "0,1,2,3",
4070    "MSRValue": "0x00",
4071    "ELLC": "0",
4072    "Filter": "na",
4073    "ExtSel": "0",
4074    "EVENT_STATUS": "0"
4075  },
4076  {
4077    "Unit": "HA",
4078    "EventCode": "0x69",
4079    "UMask": "0x1",
4080    "EventName": "UNC_H_SBO1_CREDITS_ACQUIRED.AD",
4081    "BriefDescription": "SBo1 Credits Acquired; For AD Ring",
4082    "PublicDescription": "Number of Sbo 1 credits acquired in a given cycle, per ring.",
4083    "Counter": "0,1,2,3",
4084    "MSRValue": "0x00",
4085    "ELLC": "0",
4086    "Filter": "na",
4087    "ExtSel": "0",
4088    "EVENT_STATUS": "0"
4089  },
4090  {
4091    "Unit": "HA",
4092    "EventCode": "0x69",
4093    "UMask": "0x2",
4094    "EventName": "UNC_H_SBO1_CREDITS_ACQUIRED.BL",
4095    "BriefDescription": "SBo1 Credits Acquired; For BL Ring",
4096    "PublicDescription": "Number of Sbo 1 credits acquired in a given cycle, per ring.",
4097    "Counter": "0,1,2,3",
4098    "MSRValue": "0x00",
4099    "ELLC": "0",
4100    "Filter": "na",
4101    "ExtSel": "0",
4102    "EVENT_STATUS": "0"
4103  },
4104  {
4105    "Unit": "HA",
4106    "EventCode": "0x6B",
4107    "UMask": "0x1",
4108    "EventName": "UNC_H_SBO1_CREDIT_OCCUPANCY.AD",
4109    "BriefDescription": "SBo1 Credits Occupancy; For AD Ring",
4110    "PublicDescription": "Number of Sbo 1 credits in use in a given cycle, per ring.",
4111    "Counter": "0,1,2,3",
4112    "MSRValue": "0x00",
4113    "ELLC": "0",
4114    "Filter": "na",
4115    "ExtSel": "0",
4116    "EVENT_STATUS": "0"
4117  },
4118  {
4119    "Unit": "HA",
4120    "EventCode": "0x6B",
4121    "UMask": "0x2",
4122    "EventName": "UNC_H_SBO1_CREDIT_OCCUPANCY.BL",
4123    "BriefDescription": "SBo1 Credits Occupancy; For BL Ring",
4124    "PublicDescription": "Number of Sbo 1 credits in use in a given cycle, per ring.",
4125    "Counter": "0,1,2,3",
4126    "MSRValue": "0x00",
4127    "ELLC": "0",
4128    "Filter": "na",
4129    "ExtSel": "0",
4130    "EVENT_STATUS": "0"
4131  },
4132  {
4133    "Unit": "HA",
4134    "EventCode": "0xA",
4135    "UMask": "0x1",
4136    "EventName": "UNC_H_SNOOPS_RSP_AFTER_DATA.LOCAL",
4137    "BriefDescription": "Data beat the Snoop Responses; Local Requests",
4138    "PublicDescription": "Counts the number of reads when the snoop was on the critical path to the data return.; This filter includes only requests coming from the local socket.",
4139    "Counter": "0,1,2,3",
4140    "MSRValue": "0x00",
4141    "ELLC": "0",
4142    "Filter": "na",
4143    "ExtSel": "0",
4144    "EVENT_STATUS": "0"
4145  },
4146  {
4147    "Unit": "HA",
4148    "EventCode": "0xA",
4149    "UMask": "0x2",
4150    "EventName": "UNC_H_SNOOPS_RSP_AFTER_DATA.REMOTE",
4151    "BriefDescription": "Data beat the Snoop Responses; Remote Requests",
4152    "PublicDescription": "Counts the number of reads when the snoop was on the critical path to the data return.; This filter includes only requests coming from remote sockets.",
4153    "Counter": "0,1,2,3",
4154    "MSRValue": "0x00",
4155    "ELLC": "0",
4156    "Filter": "na",
4157    "ExtSel": "0",
4158    "EVENT_STATUS": "0"
4159  },
4160  {
4161    "Unit": "HA",
4162    "EventCode": "0x8",
4163    "UMask": "0x1",
4164    "EventName": "UNC_H_SNOOP_CYCLES_NE.LOCAL",
4165    "BriefDescription": "Cycles with Snoops Outstanding; Local Requests",
4166    "PublicDescription": "Counts cycles when one or more snoops are outstanding.; This filter includes only requests coming from the local socket.",
4167    "Counter": "0,1,2,3",
4168    "MSRValue": "0x00",
4169    "ELLC": "0",
4170    "Filter": "na",
4171    "ExtSel": "0",
4172    "EVENT_STATUS": "0"
4173  },
4174  {
4175    "Unit": "HA",
4176    "EventCode": "0x8",
4177    "UMask": "0x2",
4178    "EventName": "UNC_H_SNOOP_CYCLES_NE.REMOTE",
4179    "BriefDescription": "Cycles with Snoops Outstanding; Remote Requests",
4180    "PublicDescription": "Counts cycles when one or more snoops are outstanding.; This filter includes only requests coming from remote sockets.",
4181    "Counter": "0,1,2,3",
4182    "MSRValue": "0x00",
4183    "ELLC": "0",
4184    "Filter": "na",
4185    "ExtSel": "0",
4186    "EVENT_STATUS": "0"
4187  },
4188  {
4189    "Unit": "HA",
4190    "EventCode": "0x8",
4191    "UMask": "0x3",
4192    "EventName": "UNC_H_SNOOP_CYCLES_NE.ALL",
4193    "BriefDescription": "Cycles with Snoops Outstanding; All Requests",
4194    "PublicDescription": "Counts cycles when one or more snoops are outstanding.; Tracked for snoops from both local and remote sockets.",
4195    "Counter": "0,1,2,3",
4196    "MSRValue": "0x00",
4197    "ELLC": "0",
4198    "Filter": "na",
4199    "ExtSel": "0",
4200    "EVENT_STATUS": "0"
4201  },
4202  {
4203    "Unit": "HA",
4204    "EventCode": "0x9",
4205    "UMask": "0x1",
4206    "EventName": "UNC_H_SNOOP_OCCUPANCY.LOCAL",
4207    "BriefDescription": "Tracker Snoops Outstanding Accumulator; Local Requests",
4208    "PublicDescription": "Accumulates the occupancy of either the local HA tracker pool that have snoops pending in every cycle.    This can be used in conjection with the not empty stat to calculate average queue occupancy or the allocations stat in order to calculate average queue latency.  HA trackers are allocated as soon as a request enters the HA if an HT (HomeTracker) entry is available and this occupancy is decremented when all the snoop responses have returned.; This filter includes only requests coming from the local socket.",
4209    "Counter": "0,1,2,3",
4210    "MSRValue": "0x00",
4211    "ELLC": "0",
4212    "Filter": "na",
4213    "ExtSel": "0",
4214    "EVENT_STATUS": "0"
4215  },
4216  {
4217    "Unit": "HA",
4218    "EventCode": "0x9",
4219    "UMask": "0x2",
4220    "EventName": "UNC_H_SNOOP_OCCUPANCY.REMOTE",
4221    "BriefDescription": "Tracker Snoops Outstanding Accumulator; Remote Requests",
4222    "PublicDescription": "Accumulates the occupancy of either the local HA tracker pool that have snoops pending in every cycle.    This can be used in conjection with the not empty stat to calculate average queue occupancy or the allocations stat in order to calculate average queue latency.  HA trackers are allocated as soon as a request enters the HA if an HT (HomeTracker) entry is available and this occupancy is decremented when all the snoop responses have returned.; This filter includes only requests coming from remote sockets.",
4223    "Counter": "0,1,2,3",
4224    "MSRValue": "0x00",
4225    "ELLC": "0",
4226    "Filter": "na",
4227    "ExtSel": "0",
4228    "EVENT_STATUS": "0"
4229  },
4230  {
4231    "Unit": "HA",
4232    "EventCode": "0x21",
4233    "UMask": "0x1",
4234    "EventName": "UNC_H_SNOOP_RESP.RSPI",
4235    "BriefDescription": "Snoop Responses Received; RspI",
4236    "PublicDescription": "Counts the total number of RspI snoop responses received.  Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system.   In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received.  For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for snoops responses of RspI.  RspI is returned when the remote cache does not have the data, or when the remote cache silently evicts data (such as when an RFO hits non-modified data).",
4237    "Counter": "0,1,2,3",
4238    "MSRValue": "0x00",
4239    "ELLC": "0",
4240    "Filter": "na",
4241    "ExtSel": "0",
4242    "EVENT_STATUS": "0"
4243  },
4244  {
4245    "Unit": "HA",
4246    "EventCode": "0x21",
4247    "UMask": "0x2",
4248    "EventName": "UNC_H_SNOOP_RESP.RSPS",
4249    "BriefDescription": "Snoop Responses Received; RspS",
4250    "PublicDescription": "Counts the total number of RspI snoop responses received.  Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system.   In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received.  For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for snoop responses of RspS.  RspS is returned when a remote cache has data but is not forwarding it.  It is a way to let the requesting socket know that it cannot allocate the data in E state.  No data is sent with S RspS.",
4251    "Counter": "0,1,2,3",
4252    "MSRValue": "0x00",
4253    "ELLC": "0",
4254    "Filter": "na",
4255    "ExtSel": "0",
4256    "EVENT_STATUS": "0"
4257  },
4258  {
4259    "Unit": "HA",
4260    "EventCode": "0x21",
4261    "UMask": "0x4",
4262    "EventName": "UNC_H_SNOOP_RESP.RSPIFWD",
4263    "BriefDescription": "Snoop Responses Received; RspIFwd",
4264    "PublicDescription": "Counts the total number of RspI snoop responses received.  Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system.   In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received.  For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for snoop responses of RspIFwd.  This is returned when a remote caching agent forwards data and the requesting agent is able to acquire the data in E or M states.  This is commonly returned with RFO transactions.  It can be either a HitM or a HitFE.",
4265    "Counter": "0,1,2,3",
4266    "MSRValue": "0x00",
4267    "ELLC": "0",
4268    "Filter": "na",
4269    "ExtSel": "0",
4270    "EVENT_STATUS": "0"
4271  },
4272  {
4273    "Unit": "HA",
4274    "EventCode": "0x21",
4275    "UMask": "0x8",
4276    "EventName": "UNC_H_SNOOP_RESP.RSPSFWD",
4277    "BriefDescription": "Snoop Responses Received; RspSFwd",
4278    "PublicDescription": "Counts the total number of RspI snoop responses received.  Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system.   In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received.  For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for a snoop response of RspSFwd.  This is returned when a remote caching agent forwards data but holds on to its currentl copy.  This is common for data and code reads that hit in a remote socket in E or F state.",
4279    "Counter": "0,1,2,3",
4280    "MSRValue": "0x00",
4281    "ELLC": "0",
4282    "Filter": "na",
4283    "ExtSel": "0",
4284    "EVENT_STATUS": "0"
4285  },
4286  {
4287    "Unit": "HA",
4288    "EventCode": "0x21",
4289    "UMask": "0x10",
4290    "EventName": "UNC_H_SNOOP_RESP.RSP_WB",
4291    "BriefDescription": "Snoop Responses Received; Rsp*WB",
4292    "PublicDescription": "Counts the total number of RspI snoop responses received.  Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system.   In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received.  For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for a snoop response of RspIWB or RspSWB.  This is returned when a non-RFO request hits in M state.  Data and Code Reads can return either RspIWB or RspSWB depending on how the system has been configured.  InvItoE transactions will also return RspIWB because they must acquire ownership.",
4293    "Counter": "0,1,2,3",
4294    "MSRValue": "0x00",
4295    "ELLC": "0",
4296    "Filter": "na",
4297    "ExtSel": "0",
4298    "EVENT_STATUS": "0"
4299  },
4300  {
4301    "Unit": "HA",
4302    "EventCode": "0x21",
4303    "UMask": "0x20",
4304    "EventName": "UNC_H_SNOOP_RESP.RSP_FWD_WB",
4305    "BriefDescription": "Snoop Responses Received; Rsp*Fwd*WB",
4306    "PublicDescription": "Counts the total number of RspI snoop responses received.  Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system.   In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received.  For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for a snoop response of Rsp*Fwd*WB.  This snoop response is only used in 4s systems.  It is used when a snoop HITM's in a remote caching agent and it directly forwards data to a requestor, and simultaneously returns data to the home to be written back to memory.",
4307    "Counter": "0,1,2,3",
4308    "MSRValue": "0x00",
4309    "ELLC": "0",
4310    "Filter": "na",
4311    "ExtSel": "0",
4312    "EVENT_STATUS": "0"
4313  },
4314  {
4315    "Unit": "HA",
4316    "EventCode": "0x21",
4317    "UMask": "0x40",
4318    "EventName": "UNC_H_SNOOP_RESP.RSPCNFLCT",
4319    "BriefDescription": "Snoop Responses Received; RSPCNFLCT*",
4320    "PublicDescription": "Counts the total number of RspI snoop responses received.  Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system.   In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received.  For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for snoops responses of RspConflict.  This is returned when a snoop finds an existing outstanding transaction in a remote caching agent when it CAMs that caching agent.  This triggers conflict resolution hardware.  This covers both RspCnflct and RspCnflctWbI.",
4321    "Counter": "0,1,2,3",
4322    "MSRValue": "0x00",
4323    "ELLC": "0",
4324    "Filter": "na",
4325    "ExtSel": "0",
4326    "EVENT_STATUS": "0"
4327  },
4328  {
4329    "Unit": "HA",
4330    "EventCode": "0x60",
4331    "UMask": "0x1",
4332    "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPI",
4333    "BriefDescription": "Snoop Responses Received Local; RspI",
4334    "PublicDescription": "Number of snoop responses received for a Local  request; Filters for snoops responses of RspI.  RspI is returned when the remote cache does not have the data, or when the remote cache silently evicts data (such as when an RFO hits non-modified data).",
4335    "Counter": "0,1,2,3",
4336    "MSRValue": "0x00",
4337    "ELLC": "0",
4338    "Filter": "na",
4339    "ExtSel": "0",
4340    "EVENT_STATUS": "0"
4341  },
4342  {
4343    "Unit": "HA",
4344    "EventCode": "0x60",
4345    "UMask": "0x2",
4346    "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPS",
4347    "BriefDescription": "Snoop Responses Received Local; RspS",
4348    "PublicDescription": "Number of snoop responses received for a Local  request; Filters for snoop responses of RspS.  RspS is returned when a remote cache has data but is not forwarding it.  It is a way to let the requesting socket know that it cannot allocate the data in E state.  No data is sent with S RspS.",
4349    "Counter": "0,1,2,3",
4350    "MSRValue": "0x00",
4351    "ELLC": "0",
4352    "Filter": "na",
4353    "ExtSel": "0",
4354    "EVENT_STATUS": "0"
4355  },
4356  {
4357    "Unit": "HA",
4358    "EventCode": "0x60",
4359    "UMask": "0x4",
4360    "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPIFWD",
4361    "BriefDescription": "Snoop Responses Received Local; RspIFwd",
4362    "PublicDescription": "Number of snoop responses received for a Local  request; Filters for snoop responses of RspIFwd.  This is returned when a remote caching agent forwards data and the requesting agent is able to acquire the data in E or M states.  This is commonly returned with RFO transactions.  It can be either a HitM or a HitFE.",
4363    "Counter": "0,1,2,3",
4364    "MSRValue": "0x00",
4365    "ELLC": "0",
4366    "Filter": "na",
4367    "ExtSel": "0",
4368    "EVENT_STATUS": "0"
4369  },
4370  {
4371    "Unit": "HA",
4372    "EventCode": "0x60",
4373    "UMask": "0x8",
4374    "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPSFWD",
4375    "BriefDescription": "Snoop Responses Received Local; RspSFwd",
4376    "PublicDescription": "Number of snoop responses received for a Local  request; Filters for a snoop response of RspSFwd.  This is returned when a remote caching agent forwards data but holds on to its currentl copy.  This is common for data and code reads that hit in a remote socket in E or F state.",
4377    "Counter": "0,1,2,3",
4378    "MSRValue": "0x00",
4379    "ELLC": "0",
4380    "Filter": "na",
4381    "ExtSel": "0",
4382    "EVENT_STATUS": "0"
4383  },
4384  {
4385    "Unit": "HA",
4386    "EventCode": "0x60",
4387    "UMask": "0x10",
4388    "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPxWB",
4389    "BriefDescription": "Snoop Responses Received Local; Rsp*WB",
4390    "PublicDescription": "Number of snoop responses received for a Local  request; Filters for a snoop response of RspIWB or RspSWB.  This is returned when a non-RFO request hits in M state.  Data and Code Reads can return either RspIWB or RspSWB depending on how the system has been configured.  InvItoE transactions will also return RspIWB because they must acquire ownership.",
4391    "Counter": "0,1,2,3",
4392    "MSRValue": "0x00",
4393    "ELLC": "0",
4394    "Filter": "na",
4395    "ExtSel": "0",
4396    "EVENT_STATUS": "0"
4397  },
4398  {
4399    "Unit": "HA",
4400    "EventCode": "0x60",
4401    "UMask": "0x20",
4402    "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPxFWDxWB",
4403    "BriefDescription": "Snoop Responses Received Local; Rsp*FWD*WB",
4404    "PublicDescription": "Number of snoop responses received for a Local  request; Filters for a snoop response of Rsp*Fwd*WB.  This snoop response is only used in 4s systems.  It is used when a snoop HITM's in a remote caching agent and it directly forwards data to a requestor, and simultaneously returns data to the home to be written back to memory.",
4405    "Counter": "0,1,2,3",
4406    "MSRValue": "0x00",
4407    "ELLC": "0",
4408    "Filter": "na",
4409    "ExtSel": "0",
4410    "EVENT_STATUS": "0"
4411  },
4412  {
4413    "Unit": "HA",
4414    "EventCode": "0x60",
4415    "UMask": "0x40",
4416    "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPCNFLCT",
4417    "BriefDescription": "Snoop Responses Received Local; RspCnflct",
4418    "PublicDescription": "Number of snoop responses received for a Local  request; Filters for snoops responses of RspConflict.  This is returned when a snoop finds an existing outstanding transaction in a remote caching agent when it CAMs that caching agent.  This triggers conflict resolution hardware.  This covers both RspCnflct and RspCnflctWbI.",
4419    "Counter": "0,1,2,3",
4420    "MSRValue": "0x00",
4421    "ELLC": "0",
4422    "Filter": "na",
4423    "ExtSel": "0",
4424    "EVENT_STATUS": "0"
4425  },
4426  {
4427    "Unit": "HA",
4428    "EventCode": "0x60",
4429    "UMask": "0x80",
4430    "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.OTHER",
4431    "BriefDescription": "Snoop Responses Received Local; Other",
4432    "PublicDescription": "Number of snoop responses received for a Local  request; Filters for all other snoop responses.",
4433    "Counter": "0,1,2,3",
4434    "MSRValue": "0x00",
4435    "ELLC": "0",
4436    "Filter": "na",
4437    "ExtSel": "0",
4438    "EVENT_STATUS": "0"
4439  },
4440  {
4441    "Unit": "HA",
4442    "EventCode": "0x6C",
4443    "UMask": "0x1",
4444    "EventName": "UNC_H_STALL_NO_SBO_CREDIT.SBO0_AD",
4445    "BriefDescription": "Stall on No Sbo Credits; For SBo0, AD Ring",
4446    "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available.  Per Sbo, per Ring.",
4447    "Counter": "0,1,2,3",
4448    "MSRValue": "0x00",
4449    "ELLC": "0",
4450    "Filter": "na",
4451    "ExtSel": "0",
4452    "EVENT_STATUS": "0"
4453  },
4454  {
4455    "Unit": "HA",
4456    "EventCode": "0x6C",
4457    "UMask": "0x2",
4458    "EventName": "UNC_H_STALL_NO_SBO_CREDIT.SBO1_AD",
4459    "BriefDescription": "Stall on No Sbo Credits; For SBo1, AD Ring",
4460    "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available.  Per Sbo, per Ring.",
4461    "Counter": "0,1,2,3",
4462    "MSRValue": "0x00",
4463    "ELLC": "0",
4464    "Filter": "na",
4465    "ExtSel": "0",
4466    "EVENT_STATUS": "0"
4467  },
4468  {
4469    "Unit": "HA",
4470    "EventCode": "0x6C",
4471    "UMask": "0x4",
4472    "EventName": "UNC_H_STALL_NO_SBO_CREDIT.SBO0_BL",
4473    "BriefDescription": "Stall on No Sbo Credits; For SBo0, BL Ring",
4474    "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available.  Per Sbo, per Ring.",
4475    "Counter": "0,1,2,3",
4476    "MSRValue": "0x00",
4477    "ELLC": "0",
4478    "Filter": "na",
4479    "ExtSel": "0",
4480    "EVENT_STATUS": "0"
4481  },
4482  {
4483    "Unit": "HA",
4484    "EventCode": "0x6C",
4485    "UMask": "0x8",
4486    "EventName": "UNC_H_STALL_NO_SBO_CREDIT.SBO1_BL",
4487    "BriefDescription": "Stall on No Sbo Credits; For SBo1, BL Ring",
4488    "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available.  Per Sbo, per Ring.",
4489    "Counter": "0,1,2,3",
4490    "MSRValue": "0x00",
4491    "ELLC": "0",
4492    "Filter": "na",
4493    "ExtSel": "0",
4494    "EVENT_STATUS": "0"
4495  },
4496  {
4497    "Unit": "HA",
4498    "EventCode": "0x1B",
4499    "UMask": "0x1",
4500    "EventName": "UNC_H_TAD_REQUESTS_G0.REGION0",
4501    "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 0",
4502    "PublicDescription": "Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 0 to 7.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 0",
4503    "Counter": "0,1,2,3",
4504    "MSRValue": "0x00",
4505    "ELLC": "0",
4506    "Filter": "na",
4507    "ExtSel": "0",
4508    "EVENT_STATUS": "0"
4509  },
4510  {
4511    "Unit": "HA",
4512    "EventCode": "0x1B",
4513    "UMask": "0x2",
4514    "EventName": "UNC_H_TAD_REQUESTS_G0.REGION1",
4515    "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 1",
4516    "PublicDescription": "Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 0 to 7.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 1",
4517    "Counter": "0,1,2,3",
4518    "MSRValue": "0x00",
4519    "ELLC": "0",
4520    "Filter": "na",
4521    "ExtSel": "0",
4522    "EVENT_STATUS": "0"
4523  },
4524  {
4525    "Unit": "HA",
4526    "EventCode": "0x1B",
4527    "UMask": "0x4",
4528    "EventName": "UNC_H_TAD_REQUESTS_G0.REGION2",
4529    "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 2",
4530    "PublicDescription": "Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 0 to 7.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 2",
4531    "Counter": "0,1,2,3",
4532    "MSRValue": "0x00",
4533    "ELLC": "0",
4534    "Filter": "na",
4535    "ExtSel": "0",
4536    "EVENT_STATUS": "0"
4537  },
4538  {
4539    "Unit": "HA",
4540    "EventCode": "0x1B",
4541    "UMask": "0x8",
4542    "EventName": "UNC_H_TAD_REQUESTS_G0.REGION3",
4543    "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 3",
4544    "PublicDescription": "Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 0 to 7.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 3",
4545    "Counter": "0,1,2,3",
4546    "MSRValue": "0x00",
4547    "ELLC": "0",
4548    "Filter": "na",
4549    "ExtSel": "0",
4550    "EVENT_STATUS": "0"
4551  },
4552  {
4553    "Unit": "HA",
4554    "EventCode": "0x1B",
4555    "UMask": "0x10",
4556    "EventName": "UNC_H_TAD_REQUESTS_G0.REGION4",
4557    "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 4",
4558    "PublicDescription": "Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 0 to 7.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 4",
4559    "Counter": "0,1,2,3",
4560    "MSRValue": "0x00",
4561    "ELLC": "0",
4562    "Filter": "na",
4563    "ExtSel": "0",
4564    "EVENT_STATUS": "0"
4565  },
4566  {
4567    "Unit": "HA",
4568    "EventCode": "0x1B",
4569    "UMask": "0x20",
4570    "EventName": "UNC_H_TAD_REQUESTS_G0.REGION5",
4571    "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 5",
4572    "PublicDescription": "Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 0 to 7.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 5",
4573    "Counter": "0,1,2,3",
4574    "MSRValue": "0x00",
4575    "ELLC": "0",
4576    "Filter": "na",
4577    "ExtSel": "0",
4578    "EVENT_STATUS": "0"
4579  },
4580  {
4581    "Unit": "HA",
4582    "EventCode": "0x1B",
4583    "UMask": "0x40",
4584    "EventName": "UNC_H_TAD_REQUESTS_G0.REGION6",
4585    "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 6",
4586    "PublicDescription": "Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 0 to 7.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 6",
4587    "Counter": "0,1,2,3",
4588    "MSRValue": "0x00",
4589    "ELLC": "0",
4590    "Filter": "na",
4591    "ExtSel": "0",
4592    "EVENT_STATUS": "0"
4593  },
4594  {
4595    "Unit": "HA",
4596    "EventCode": "0x1B",
4597    "UMask": "0x80",
4598    "EventName": "UNC_H_TAD_REQUESTS_G0.REGION7",
4599    "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 7",
4600    "PublicDescription": "Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 0 to 7.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 7",
4601    "Counter": "0,1,2,3",
4602    "MSRValue": "0x00",
4603    "ELLC": "0",
4604    "Filter": "na",
4605    "ExtSel": "0",
4606    "EVENT_STATUS": "0"
4607  },
4608  {
4609    "Unit": "HA",
4610    "EventCode": "0x1C",
4611    "UMask": "0x1",
4612    "EventName": "UNC_H_TAD_REQUESTS_G1.REGION8",
4613    "BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Region 8",
4614    "PublicDescription": "Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 8 to 10.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 8",
4615    "Counter": "0,1,2,3",
4616    "MSRValue": "0x00",
4617    "ELLC": "0",
4618    "Filter": "na",
4619    "ExtSel": "0",
4620    "EVENT_STATUS": "0"
4621  },
4622  {
4623    "Unit": "HA",
4624    "EventCode": "0x1C",
4625    "UMask": "0x2",
4626    "EventName": "UNC_H_TAD_REQUESTS_G1.REGION9",
4627    "BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Region 9",
4628    "PublicDescription": "Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 8 to 10.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 9",
4629    "Counter": "0,1,2,3",
4630    "MSRValue": "0x00",
4631    "ELLC": "0",
4632    "Filter": "na",
4633    "ExtSel": "0",
4634    "EVENT_STATUS": "0"
4635  },
4636  {
4637    "Unit": "HA",
4638    "EventCode": "0x1C",
4639    "UMask": "0x4",
4640    "EventName": "UNC_H_TAD_REQUESTS_G1.REGION10",
4641    "BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Region 10",
4642    "PublicDescription": "Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 8 to 10.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 10",
4643    "Counter": "0,1,2,3",
4644    "MSRValue": "0x00",
4645    "ELLC": "0",
4646    "Filter": "na",
4647    "ExtSel": "0",
4648    "EVENT_STATUS": "0"
4649  },
4650  {
4651    "Unit": "HA",
4652    "EventCode": "0x1C",
4653    "UMask": "0x8",
4654    "EventName": "UNC_H_TAD_REQUESTS_G1.REGION11",
4655    "BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Region 11",
4656    "PublicDescription": "Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 8 to 10.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 11",
4657    "Counter": "0,1,2,3",
4658    "MSRValue": "0x00",
4659    "ELLC": "0",
4660    "Filter": "na",
4661    "ExtSel": "0",
4662    "EVENT_STATUS": "0"
4663  },
4664  {
4665    "Unit": "HA",
4666    "EventCode": "0x2",
4667    "UMask": "0x1",
4668    "EventName": "UNC_H_TRACKER_CYCLES_FULL.GP",
4669    "BriefDescription": "Tracker Cycles Full; Cycles GP Completely Used",
4670    "PublicDescription": "Counts the number of cycles when the local HA tracker pool is completely used.  This can be used with edge detect to identify the number of situations when the pool became fully utilized.  This should not be confused with RTID credit usage -- which must be tracked inside each cbo individually -- but represents the actual tracker buffer structure.  In other words, the system could be starved for RTIDs but not fill up the HA trackers.  HA trackers are allocated as soon as a request enters the HA and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.; Counts the number of cycles when the general purpose (GP) HA tracker pool (HT) is completely used.  It will not return valid count when BT is disabled.",
4671    "Counter": "0,1,2,3",
4672    "MSRValue": "0x00",
4673    "ELLC": "0",
4674    "Filter": "na",
4675    "ExtSel": "0",
4676    "EVENT_STATUS": "0"
4677  },
4678  {
4679    "Unit": "HA",
4680    "EventCode": "0x2",
4681    "UMask": "0x2",
4682    "EventName": "UNC_H_TRACKER_CYCLES_FULL.ALL",
4683    "BriefDescription": "Tracker Cycles Full; Cycles Completely Used",
4684    "PublicDescription": "Counts the number of cycles when the local HA tracker pool is completely used.  This can be used with edge detect to identify the number of situations when the pool became fully utilized.  This should not be confused with RTID credit usage -- which must be tracked inside each cbo individually -- but represents the actual tracker buffer structure.  In other words, the system could be starved for RTIDs but not fill up the HA trackers.  HA trackers are allocated as soon as a request enters the HA and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.; Counts the number of cycles when the HA tracker pool (HT) is completely used including reserved HT entries.  It will not return valid count when BT is disabled.",
4685    "Counter": "0,1,2,3",
4686    "MSRValue": "0x00",
4687    "ELLC": "0",
4688    "Filter": "na",
4689    "ExtSel": "0",
4690    "EVENT_STATUS": "0"
4691  },
4692  {
4693    "Unit": "HA",
4694    "EventCode": "0x4",
4695    "UMask": "0x4",
4696    "EventName": "UNC_H_TRACKER_OCCUPANCY.READS_LOCAL",
4697    "BriefDescription": "Tracker Occupancy Accumultor; Local Read Requests",
4698    "PublicDescription": "Accumulates the occupancy of the local HA tracker pool in every cycle.  This can be used in conjection with the not empty stat to calculate average queue occupancy or the allocations stat in order to calculate average queue latency.  HA trackers are allocated as soon as a request enters the HA if a HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.",
4699    "Counter": "0,1,2,3",
4700    "MSRValue": "0x00",
4701    "ELLC": "0",
4702    "Filter": "na",
4703    "ExtSel": "0",
4704    "EVENT_STATUS": "0"
4705  },
4706  {
4707    "Unit": "HA",
4708    "EventCode": "0x4",
4709    "UMask": "0x8",
4710    "EventName": "UNC_H_TRACKER_OCCUPANCY.READS_REMOTE",
4711    "BriefDescription": "Tracker Occupancy Accumultor; Remote Read Requests",
4712    "PublicDescription": "Accumulates the occupancy of the local HA tracker pool in every cycle.  This can be used in conjection with the not empty stat to calculate average queue occupancy or the allocations stat in order to calculate average queue latency.  HA trackers are allocated as soon as a request enters the HA if a HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.",
4713    "Counter": "0,1,2,3",
4714    "MSRValue": "0x00",
4715    "ELLC": "0",
4716    "Filter": "na",
4717    "ExtSel": "0",
4718    "EVENT_STATUS": "0"
4719  },
4720  {
4721    "Unit": "HA",
4722    "EventCode": "0x4",
4723    "UMask": "0x10",
4724    "EventName": "UNC_H_TRACKER_OCCUPANCY.WRITES_LOCAL",
4725    "BriefDescription": "Tracker Occupancy Accumultor; Local Write Requests",
4726    "PublicDescription": "Accumulates the occupancy of the local HA tracker pool in every cycle.  This can be used in conjection with the not empty stat to calculate average queue occupancy or the allocations stat in order to calculate average queue latency.  HA trackers are allocated as soon as a request enters the HA if a HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.",
4727    "Counter": "0,1,2,3",
4728    "MSRValue": "0x00",
4729    "ELLC": "0",
4730    "Filter": "na",
4731    "ExtSel": "0",
4732    "EVENT_STATUS": "0"
4733  },
4734  {
4735    "Unit": "HA",
4736    "EventCode": "0x4",
4737    "UMask": "0x20",
4738    "EventName": "UNC_H_TRACKER_OCCUPANCY.WRITES_REMOTE",
4739    "BriefDescription": "Tracker Occupancy Accumultor; Remote Write Requests",
4740    "PublicDescription": "Accumulates the occupancy of the local HA tracker pool in every cycle.  This can be used in conjection with the not empty stat to calculate average queue occupancy or the allocations stat in order to calculate average queue latency.  HA trackers are allocated as soon as a request enters the HA if a HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.",
4741    "Counter": "0,1,2,3",
4742    "MSRValue": "0x00",
4743    "ELLC": "0",
4744    "Filter": "na",
4745    "ExtSel": "0",
4746    "EVENT_STATUS": "0"
4747  },
4748  {
4749    "Unit": "HA",
4750    "EventCode": "0x4",
4751    "UMask": "0x40",
4752    "EventName": "UNC_H_TRACKER_OCCUPANCY.INVITOE_LOCAL",
4753    "BriefDescription": "Tracker Occupancy Accumultor; Local InvItoE Requests",
4754    "PublicDescription": "Accumulates the occupancy of the local HA tracker pool in every cycle.  This can be used in conjection with the not empty stat to calculate average queue occupancy or the allocations stat in order to calculate average queue latency.  HA trackers are allocated as soon as a request enters the HA if a HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.",
4755    "Counter": "0,1,2,3",
4756    "MSRValue": "0x00",
4757    "ELLC": "0",
4758    "Filter": "na",
4759    "ExtSel": "0",
4760    "EVENT_STATUS": "0"
4761  },
4762  {
4763    "Unit": "HA",
4764    "EventCode": "0x4",
4765    "UMask": "0x80",
4766    "EventName": "UNC_H_TRACKER_OCCUPANCY.INVITOE_REMOTE",
4767    "BriefDescription": "Tracker Occupancy Accumultor; Remote InvItoE Requests",
4768    "PublicDescription": "Accumulates the occupancy of the local HA tracker pool in every cycle.  This can be used in conjection with the not empty stat to calculate average queue occupancy or the allocations stat in order to calculate average queue latency.  HA trackers are allocated as soon as a request enters the HA if a HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.",
4769    "Counter": "0,1,2,3",
4770    "MSRValue": "0x00",
4771    "ELLC": "0",
4772    "Filter": "na",
4773    "ExtSel": "0",
4774    "EVENT_STATUS": "0"
4775  },
4776  {
4777    "Unit": "HA",
4778    "EventCode": "0x5",
4779    "UMask": "0x1",
4780    "EventName": "UNC_H_TRACKER_PENDING_OCCUPANCY.LOCAL",
4781    "BriefDescription": "Data Pending Occupancy Accumultor; Local Requests",
4782    "PublicDescription": "Accumulates the number of transactions that have data from the memory controller until they get scheduled to the Egress.  This can be used to calculate the queuing latency for two things.  (1) If the system is waiting for snoops, this will increase.  (2) If the system can't schedule to the Egress because of either (a) Egress Credits or (b) QPI BL IGR credits for remote requests.; This filter includes only requests coming from the local socket.",
4783    "Counter": "0,1,2,3",
4784    "MSRValue": "0x00",
4785    "ELLC": "0",
4786    "Filter": "na",
4787    "ExtSel": "0",
4788    "EVENT_STATUS": "0"
4789  },
4790  {
4791    "Unit": "HA",
4792    "EventCode": "0x5",
4793    "UMask": "0x2",
4794    "EventName": "UNC_H_TRACKER_PENDING_OCCUPANCY.REMOTE",
4795    "BriefDescription": "Data Pending Occupancy Accumultor; Remote Requests",
4796    "PublicDescription": "Accumulates the number of transactions that have data from the memory controller until they get scheduled to the Egress.  This can be used to calculate the queuing latency for two things.  (1) If the system is waiting for snoops, this will increase.  (2) If the system can't schedule to the Egress because of either (a) Egress Credits or (b) QPI BL IGR credits for remote requests.; This filter includes only requests coming from remote sockets.",
4797    "Counter": "0,1,2,3",
4798    "MSRValue": "0x00",
4799    "ELLC": "0",
4800    "Filter": "na",
4801    "ExtSel": "0",
4802    "EVENT_STATUS": "0"
4803  },
4804  {
4805    "Unit": "HA",
4806    "EventCode": "0xF",
4807    "UMask": "0x4",
4808    "EventName": "UNC_H_TxR_AD.HOM",
4809    "BriefDescription": "Outbound NDR Ring Transactions; Non-data Responses",
4810    "PublicDescription": "Counts the number of outbound transactions on the AD ring.  This can be filtered by the NDR and SNP message classes.  See the filter descriptions for more details.; Filter for outbound NDR transactions sent on the AD ring.  NDR stands for non-data response and is generally used for completions that do not include data.  AD NDR is used for transactions to remote sockets.",
4811    "Counter": "0,1,2,3",
4812    "MSRValue": "0x00",
4813    "ELLC": "0",
4814    "Filter": "na",
4815    "ExtSel": "0",
4816    "EVENT_STATUS": "0"
4817  },
4818  {
4819    "Unit": "HA",
4820    "EventCode": "0x2A",
4821    "UMask": "0x1",
4822    "EventName": "UNC_H_TxR_AD_CYCLES_FULL.SCHED0",
4823    "BriefDescription": "AD Egress Full; Scheduler 0",
4824    "PublicDescription": "AD Egress Full; Filter for cycles full  from scheduler bank 0",
4825    "Counter": "0,1,2,3",
4826    "MSRValue": "0x00",
4827    "ELLC": "0",
4828    "Filter": "na",
4829    "ExtSel": "0",
4830    "EVENT_STATUS": "0"
4831  },
4832  {
4833    "Unit": "HA",
4834    "EventCode": "0x2A",
4835    "UMask": "0x2",
4836    "EventName": "UNC_H_TxR_AD_CYCLES_FULL.SCHED1",
4837    "BriefDescription": "AD Egress Full; Scheduler 1",
4838    "PublicDescription": "AD Egress Full; Filter for cycles full  from scheduler bank 1",
4839    "Counter": "0,1,2,3",
4840    "MSRValue": "0x00",
4841    "ELLC": "0",
4842    "Filter": "na",
4843    "ExtSel": "0",
4844    "EVENT_STATUS": "0"
4845  },
4846  {
4847    "Unit": "HA",
4848    "EventCode": "0x2A",
4849    "UMask": "0x3",
4850    "EventName": "UNC_H_TxR_AD_CYCLES_FULL.ALL",
4851    "BriefDescription": "AD Egress Full; All",
4852    "PublicDescription": "AD Egress Full; Cycles full from both schedulers",
4853    "Counter": "0,1,2,3",
4854    "MSRValue": "0x00",
4855    "ELLC": "0",
4856    "Filter": "na",
4857    "ExtSel": "0",
4858    "EVENT_STATUS": "0"
4859  },
4860  {
4861    "Unit": "HA",
4862    "EventCode": "0x29",
4863    "UMask": "0x1",
4864    "EventName": "UNC_H_TxR_AD_CYCLES_NE.SCHED0",
4865    "BriefDescription": "AD Egress Not Empty; Scheduler 0",
4866    "PublicDescription": "AD Egress Not Empty; Filter for cycles not empty  from scheduler bank 0",
4867    "Counter": "0,1,2,3",
4868    "MSRValue": "0x00",
4869    "ELLC": "0",
4870    "Filter": "na",
4871    "ExtSel": "0",
4872    "EVENT_STATUS": "0"
4873  },
4874  {
4875    "Unit": "HA",
4876    "EventCode": "0x29",
4877    "UMask": "0x2",
4878    "EventName": "UNC_H_TxR_AD_CYCLES_NE.SCHED1",
4879    "BriefDescription": "AD Egress Not Empty; Scheduler 1",
4880    "PublicDescription": "AD Egress Not Empty; Filter for cycles not empty from scheduler bank 1",
4881    "Counter": "0,1,2,3",
4882    "MSRValue": "0x00",
4883    "ELLC": "0",
4884    "Filter": "na",
4885    "ExtSel": "0",
4886    "EVENT_STATUS": "0"
4887  },
4888  {
4889    "Unit": "HA",
4890    "EventCode": "0x29",
4891    "UMask": "0x3",
4892    "EventName": "UNC_H_TxR_AD_CYCLES_NE.ALL",
4893    "BriefDescription": "AD Egress Not Empty; All",
4894    "PublicDescription": "AD Egress Not Empty; Cycles full from both schedulers",
4895    "Counter": "0,1,2,3",
4896    "MSRValue": "0x00",
4897    "ELLC": "0",
4898    "Filter": "na",
4899    "ExtSel": "0",
4900    "EVENT_STATUS": "0"
4901  },
4902  {
4903    "Unit": "HA",
4904    "EventCode": "0x27",
4905    "UMask": "0x1",
4906    "EventName": "UNC_H_TxR_AD_INSERTS.SCHED0",
4907    "BriefDescription": "AD Egress Allocations; Scheduler 0",
4908    "PublicDescription": "AD Egress Allocations; Filter for allocations from scheduler bank 0",
4909    "Counter": "0,1,2,3",
4910    "MSRValue": "0x00",
4911    "ELLC": "0",
4912    "Filter": "na",
4913    "ExtSel": "0",
4914    "EVENT_STATUS": "0"
4915  },
4916  {
4917    "Unit": "HA",
4918    "EventCode": "0x27",
4919    "UMask": "0x2",
4920    "EventName": "UNC_H_TxR_AD_INSERTS.SCHED1",
4921    "BriefDescription": "AD Egress Allocations; Scheduler 1",
4922    "PublicDescription": "AD Egress Allocations; Filter for allocations from scheduler bank 1",
4923    "Counter": "0,1,2,3",
4924    "MSRValue": "0x00",
4925    "ELLC": "0",
4926    "Filter": "na",
4927    "ExtSel": "0",
4928    "EVENT_STATUS": "0"
4929  },
4930  {
4931    "Unit": "HA",
4932    "EventCode": "0x27",
4933    "UMask": "0x3",
4934    "EventName": "UNC_H_TxR_AD_INSERTS.ALL",
4935    "BriefDescription": "AD Egress Allocations; All",
4936    "PublicDescription": "AD Egress Allocations; Allocations from both schedulers",
4937    "Counter": "0,1,2,3",
4938    "MSRValue": "0x00",
4939    "ELLC": "0",
4940    "Filter": "na",
4941    "ExtSel": "0",
4942    "EVENT_STATUS": "0"
4943  },
4944  {
4945    "Unit": "HA",
4946    "EventCode": "0x32",
4947    "UMask": "0x1",
4948    "EventName": "UNC_H_TxR_AK_CYCLES_FULL.SCHED0",
4949    "BriefDescription": "AK Egress Full; Scheduler 0",
4950    "PublicDescription": "AK Egress Full; Filter for cycles full  from scheduler bank 0",
4951    "Counter": "0,1,2,3",
4952    "MSRValue": "0x00",
4953    "ELLC": "0",
4954    "Filter": "na",
4955    "ExtSel": "0",
4956    "EVENT_STATUS": "0"
4957  },
4958  {
4959    "Unit": "HA",
4960    "EventCode": "0x32",
4961    "UMask": "0x2",
4962    "EventName": "UNC_H_TxR_AK_CYCLES_FULL.SCHED1",
4963    "BriefDescription": "AK Egress Full; Scheduler 1",
4964    "PublicDescription": "AK Egress Full; Filter for cycles full  from scheduler bank 1",
4965    "Counter": "0,1,2,3",
4966    "MSRValue": "0x00",
4967    "ELLC": "0",
4968    "Filter": "na",
4969    "ExtSel": "0",
4970    "EVENT_STATUS": "0"
4971  },
4972  {
4973    "Unit": "HA",
4974    "EventCode": "0x32",
4975    "UMask": "0x3",
4976    "EventName": "UNC_H_TxR_AK_CYCLES_FULL.ALL",
4977    "BriefDescription": "AK Egress Full; All",
4978    "PublicDescription": "AK Egress Full; Cycles full from both schedulers",
4979    "Counter": "0,1,2,3",
4980    "MSRValue": "0x00",
4981    "ELLC": "0",
4982    "Filter": "na",
4983    "ExtSel": "0",
4984    "EVENT_STATUS": "0"
4985  },
4986  {
4987    "Unit": "HA",
4988    "EventCode": "0x31",
4989    "UMask": "0x1",
4990    "EventName": "UNC_H_TxR_AK_CYCLES_NE.SCHED0",
4991    "BriefDescription": "AK Egress Not Empty; Scheduler 0",
4992    "PublicDescription": "AK Egress Not Empty; Filter for cycles not empty  from scheduler bank 0",
4993    "Counter": "0,1,2,3",
4994    "MSRValue": "0x00",
4995    "ELLC": "0",
4996    "Filter": "na",
4997    "ExtSel": "0",
4998    "EVENT_STATUS": "0"
4999  },
5000  {
5001    "Unit": "HA",
5002    "EventCode": "0x31",
5003    "UMask": "0x2",
5004    "EventName": "UNC_H_TxR_AK_CYCLES_NE.SCHED1",
5005    "BriefDescription": "AK Egress Not Empty; Scheduler 1",
5006    "PublicDescription": "AK Egress Not Empty; Filter for cycles not empty from scheduler bank 1",
5007    "Counter": "0,1,2,3",
5008    "MSRValue": "0x00",
5009    "ELLC": "0",
5010    "Filter": "na",
5011    "ExtSel": "0",
5012    "EVENT_STATUS": "0"
5013  },
5014  {
5015    "Unit": "HA",
5016    "EventCode": "0x31",
5017    "UMask": "0x3",
5018    "EventName": "UNC_H_TxR_AK_CYCLES_NE.ALL",
5019    "BriefDescription": "AK Egress Not Empty; All",
5020    "PublicDescription": "AK Egress Not Empty; Cycles full from both schedulers",
5021    "Counter": "0,1,2,3",
5022    "MSRValue": "0x00",
5023    "ELLC": "0",
5024    "Filter": "na",
5025    "ExtSel": "0",
5026    "EVENT_STATUS": "0"
5027  },
5028  {
5029    "Unit": "HA",
5030    "EventCode": "0x2F",
5031    "UMask": "0x1",
5032    "EventName": "UNC_H_TxR_AK_INSERTS.SCHED0",
5033    "BriefDescription": "AK Egress Allocations; Scheduler 0",
5034    "PublicDescription": "AK Egress Allocations; Filter for allocations from scheduler bank 0",
5035    "Counter": "0,1,2,3",
5036    "MSRValue": "0x00",
5037    "ELLC": "0",
5038    "Filter": "na",
5039    "ExtSel": "0",
5040    "EVENT_STATUS": "0"
5041  },
5042  {
5043    "Unit": "HA",
5044    "EventCode": "0x2F",
5045    "UMask": "0x2",
5046    "EventName": "UNC_H_TxR_AK_INSERTS.SCHED1",
5047    "BriefDescription": "AK Egress Allocations; Scheduler 1",
5048    "PublicDescription": "AK Egress Allocations; Filter for allocations from scheduler bank 1",
5049    "Counter": "0,1,2,3",
5050    "MSRValue": "0x00",
5051    "ELLC": "0",
5052    "Filter": "na",
5053    "ExtSel": "0",
5054    "EVENT_STATUS": "0"
5055  },
5056  {
5057    "Unit": "HA",
5058    "EventCode": "0x2F",
5059    "UMask": "0x3",
5060    "EventName": "UNC_H_TxR_AK_INSERTS.ALL",
5061    "BriefDescription": "AK Egress Allocations; All",
5062    "PublicDescription": "AK Egress Allocations; Allocations from both schedulers",
5063    "Counter": "0,1,2,3",
5064    "MSRValue": "0x00",
5065    "ELLC": "0",
5066    "Filter": "na",
5067    "ExtSel": "0",
5068    "EVENT_STATUS": "0"
5069  },
5070  {
5071    "Unit": "HA",
5072    "EventCode": "0x10",
5073    "UMask": "0x1",
5074    "EventName": "UNC_H_TxR_BL.DRS_CACHE",
5075    "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to Cache",
5076    "PublicDescription": "Counts the number of DRS messages sent out on the BL ring.   This can be filtered by the destination.; Filter for data being sent to the cache.",
5077    "Counter": "0,1,2,3",
5078    "MSRValue": "0x00",
5079    "ELLC": "0",
5080    "Filter": "na",
5081    "ExtSel": "0",
5082    "EVENT_STATUS": "0"
5083  },
5084  {
5085    "Unit": "HA",
5086    "EventCode": "0x10",
5087    "UMask": "0x2",
5088    "EventName": "UNC_H_TxR_BL.DRS_CORE",
5089    "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to Core",
5090    "PublicDescription": "Counts the number of DRS messages sent out on the BL ring.   This can be filtered by the destination.; Filter for data being sent directly to the requesting core.",
5091    "Counter": "0,1,2,3",
5092    "MSRValue": "0x00",
5093    "ELLC": "0",
5094    "Filter": "na",
5095    "ExtSel": "0",
5096    "EVENT_STATUS": "0"
5097  },
5098  {
5099    "Unit": "HA",
5100    "EventCode": "0x10",
5101    "UMask": "0x4",
5102    "EventName": "UNC_H_TxR_BL.DRS_QPI",
5103    "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to QPI",
5104    "PublicDescription": "Counts the number of DRS messages sent out on the BL ring.   This can be filtered by the destination.; Filter for data being sent to a remote socket over QPI.",
5105    "Counter": "0,1,2,3",
5106    "MSRValue": "0x00",
5107    "ELLC": "0",
5108    "Filter": "na",
5109    "ExtSel": "0",
5110    "EVENT_STATUS": "0"
5111  },
5112  {
5113    "Unit": "HA",
5114    "EventCode": "0x36",
5115    "UMask": "0x1",
5116    "EventName": "UNC_H_TxR_BL_CYCLES_FULL.SCHED0",
5117    "BriefDescription": "BL Egress Full; Scheduler 0",
5118    "PublicDescription": "BL Egress Full; Filter for cycles full  from scheduler bank 0",
5119    "Counter": "0,1,2,3",
5120    "MSRValue": "0x00",
5121    "ELLC": "0",
5122    "Filter": "na",
5123    "ExtSel": "0",
5124    "EVENT_STATUS": "0"
5125  },
5126  {
5127    "Unit": "HA",
5128    "EventCode": "0x36",
5129    "UMask": "0x2",
5130    "EventName": "UNC_H_TxR_BL_CYCLES_FULL.SCHED1",
5131    "BriefDescription": "BL Egress Full; Scheduler 1",
5132    "PublicDescription": "BL Egress Full; Filter for cycles full  from scheduler bank 1",
5133    "Counter": "0,1,2,3",
5134    "MSRValue": "0x00",
5135    "ELLC": "0",
5136    "Filter": "na",
5137    "ExtSel": "0",
5138    "EVENT_STATUS": "0"
5139  },
5140  {
5141    "Unit": "HA",
5142    "EventCode": "0x36",
5143    "UMask": "0x3",
5144    "EventName": "UNC_H_TxR_BL_CYCLES_FULL.ALL",
5145    "BriefDescription": "BL Egress Full; All",
5146    "PublicDescription": "BL Egress Full; Cycles full from both schedulers",
5147    "Counter": "0,1,2,3",
5148    "MSRValue": "0x00",
5149    "ELLC": "0",
5150    "Filter": "na",
5151    "ExtSel": "0",
5152    "EVENT_STATUS": "0"
5153  },
5154  {
5155    "Unit": "HA",
5156    "EventCode": "0x35",
5157    "UMask": "0x1",
5158    "EventName": "UNC_H_TxR_BL_CYCLES_NE.SCHED0",
5159    "BriefDescription": "BL Egress Not Empty; Scheduler 0",
5160    "PublicDescription": "BL Egress Not Empty; Filter for cycles not empty  from scheduler bank 0",
5161    "Counter": "0,1,2,3",
5162    "MSRValue": "0x00",
5163    "ELLC": "0",
5164    "Filter": "na",
5165    "ExtSel": "0",
5166    "EVENT_STATUS": "0"
5167  },
5168  {
5169    "Unit": "HA",
5170    "EventCode": "0x35",
5171    "UMask": "0x2",
5172    "EventName": "UNC_H_TxR_BL_CYCLES_NE.SCHED1",
5173    "BriefDescription": "BL Egress Not Empty; Scheduler 1",
5174    "PublicDescription": "BL Egress Not Empty; Filter for cycles not empty from scheduler bank 1",
5175    "Counter": "0,1,2,3",
5176    "MSRValue": "0x00",
5177    "ELLC": "0",
5178    "Filter": "na",
5179    "ExtSel": "0",
5180    "EVENT_STATUS": "0"
5181  },
5182  {
5183    "Unit": "HA",
5184    "EventCode": "0x35",
5185    "UMask": "0x3",
5186    "EventName": "UNC_H_TxR_BL_CYCLES_NE.ALL",
5187    "BriefDescription": "BL Egress Not Empty; All",
5188    "PublicDescription": "BL Egress Not Empty; Cycles full from both schedulers",
5189    "Counter": "0,1,2,3",
5190    "MSRValue": "0x00",
5191    "ELLC": "0",
5192    "Filter": "na",
5193    "ExtSel": "0",
5194    "EVENT_STATUS": "0"
5195  },
5196  {
5197    "Unit": "HA",
5198    "EventCode": "0x33",
5199    "UMask": "0x1",
5200    "EventName": "UNC_H_TxR_BL_INSERTS.SCHED0",
5201    "BriefDescription": "BL Egress Allocations; Scheduler 0",
5202    "PublicDescription": "BL Egress Allocations; Filter for allocations from scheduler bank 0",
5203    "Counter": "0,1,2,3",
5204    "MSRValue": "0x00",
5205    "ELLC": "0",
5206    "Filter": "na",
5207    "ExtSel": "0",
5208    "EVENT_STATUS": "0"
5209  },
5210  {
5211    "Unit": "HA",
5212    "EventCode": "0x33",
5213    "UMask": "0x2",
5214    "EventName": "UNC_H_TxR_BL_INSERTS.SCHED1",
5215    "BriefDescription": "BL Egress Allocations; Scheduler 1",
5216    "PublicDescription": "BL Egress Allocations; Filter for allocations from scheduler bank 1",
5217    "Counter": "0,1,2,3",
5218    "MSRValue": "0x00",
5219    "ELLC": "0",
5220    "Filter": "na",
5221    "ExtSel": "0",
5222    "EVENT_STATUS": "0"
5223  },
5224  {
5225    "Unit": "HA",
5226    "EventCode": "0x33",
5227    "UMask": "0x3",
5228    "EventName": "UNC_H_TxR_BL_INSERTS.ALL",
5229    "BriefDescription": "BL Egress Allocations; All",
5230    "PublicDescription": "BL Egress Allocations; Allocations from both schedulers",
5231    "Counter": "0,1,2,3",
5232    "MSRValue": "0x00",
5233    "ELLC": "0",
5234    "Filter": "na",
5235    "ExtSel": "0",
5236    "EVENT_STATUS": "0"
5237  },
5238  {
5239    "Unit": "HA",
5240    "EventCode": "0x6D",
5241    "UMask": "0x1",
5242    "EventName": "UNC_H_TxR_STARVED.AK",
5243    "BriefDescription": "Injection Starvation; For AK Ring",
5244    "PublicDescription": "Counts injection starvation.  This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.",
5245    "Counter": "0,1,2,3",
5246    "MSRValue": "0x00",
5247    "ELLC": "0",
5248    "Filter": "na",
5249    "ExtSel": "0",
5250    "EVENT_STATUS": "0"
5251  },
5252  {
5253    "Unit": "HA",
5254    "EventCode": "0x6D",
5255    "UMask": "0x2",
5256    "EventName": "UNC_H_TxR_STARVED.BL",
5257    "BriefDescription": "Injection Starvation; For BL Ring",
5258    "PublicDescription": "Counts injection starvation.  This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.",
5259    "Counter": "0,1,2,3",
5260    "MSRValue": "0x00",
5261    "ELLC": "0",
5262    "Filter": "na",
5263    "ExtSel": "0",
5264    "EVENT_STATUS": "0"
5265  },
5266  {
5267    "Unit": "HA",
5268    "EventCode": "0x18",
5269    "UMask": "0x1",
5270    "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN0",
5271    "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 0",
5272    "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting writes from the HA into the iMC.  In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue).  This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes.  This count only tracks the regular credits  Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 0 only.",
5273    "Counter": "0,1,2,3",
5274    "MSRValue": "0x00",
5275    "ELLC": "0",
5276    "Filter": "na",
5277    "ExtSel": "0",
5278    "EVENT_STATUS": "0"
5279  },
5280  {
5281    "Unit": "HA",
5282    "EventCode": "0x18",
5283    "UMask": "0x2",
5284    "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN1",
5285    "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 1",
5286    "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting writes from the HA into the iMC.  In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue).  This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes.  This count only tracks the regular credits  Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 1 only.",
5287    "Counter": "0,1,2,3",
5288    "MSRValue": "0x00",
5289    "ELLC": "0",
5290    "Filter": "na",
5291    "ExtSel": "0",
5292    "EVENT_STATUS": "0"
5293  },
5294  {
5295    "Unit": "HA",
5296    "EventCode": "0x18",
5297    "UMask": "0x4",
5298    "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN2",
5299    "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 2",
5300    "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting writes from the HA into the iMC.  In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue).  This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes.  This count only tracks the regular credits  Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 2 only.",
5301    "Counter": "0,1,2,3",
5302    "MSRValue": "0x00",
5303    "ELLC": "0",
5304    "Filter": "na",
5305    "ExtSel": "0",
5306    "EVENT_STATUS": "0"
5307  },
5308  {
5309    "Unit": "HA",
5310    "EventCode": "0x18",
5311    "UMask": "0x8",
5312    "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN3",
5313    "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 3",
5314    "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting writes from the HA into the iMC.  In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue).  This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes.  This count only tracks the regular credits  Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 3 only.",
5315    "Counter": "0,1,2,3",
5316    "MSRValue": "0x00",
5317    "ELLC": "0",
5318    "Filter": "na",
5319    "ExtSel": "0",
5320    "EVENT_STATUS": "0"
5321  },
5322  {
5323    "Unit": "HA",
5324    "EventCode": "0x19",
5325    "UMask": "0x1",
5326    "EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN0",
5327    "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Channel 0",
5328    "PublicDescription": "Counts the number of cycles when there are no special credits available for posting writes from the HA into the iMC.  In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue).  This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes.  This count only tracks the special credits.  This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 0 only.",
5329    "Counter": "0,1,2,3",
5330    "MSRValue": "0x00",
5331    "ELLC": "0",
5332    "Filter": "na",
5333    "ExtSel": "0",
5334    "EVENT_STATUS": "0"
5335  },
5336  {
5337    "Unit": "HA",
5338    "EventCode": "0x19",
5339    "UMask": "0x2",
5340    "EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN1",
5341    "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Channel 1",
5342    "PublicDescription": "Counts the number of cycles when there are no special credits available for posting writes from the HA into the iMC.  In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue).  This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes.  This count only tracks the special credits.  This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 1 only.",
5343    "Counter": "0,1,2,3",
5344    "MSRValue": "0x00",
5345    "ELLC": "0",
5346    "Filter": "na",
5347    "ExtSel": "0",
5348    "EVENT_STATUS": "0"
5349  },
5350  {
5351    "Unit": "HA",
5352    "EventCode": "0x19",
5353    "UMask": "0x4",
5354    "EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN2",
5355    "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Channel 2",
5356    "PublicDescription": "Counts the number of cycles when there are no special credits available for posting writes from the HA into the iMC.  In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue).  This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes.  This count only tracks the special credits.  This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 2 only.",
5357    "Counter": "0,1,2,3",
5358    "MSRValue": "0x00",
5359    "ELLC": "0",
5360    "Filter": "na",
5361    "ExtSel": "0",
5362    "EVENT_STATUS": "0"
5363  },
5364  {
5365    "Unit": "HA",
5366    "EventCode": "0x19",
5367    "UMask": "0x8",
5368    "EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN3",
5369    "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Channel 3",
5370    "PublicDescription": "Counts the number of cycles when there are no special credits available for posting writes from the HA into the iMC.  In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue).  This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes.  This count only tracks the special credits.  This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 3 only.",
5371    "Counter": "0,1,2,3",
5372    "MSRValue": "0x00",
5373    "ELLC": "0",
5374    "Filter": "na",
5375    "ExtSel": "0",
5376    "EVENT_STATUS": "0"
5377  },
5378  {
5379    "Unit": "HA",
5380    "EventCode": "0x3",
5381    "UMask": "0x1",
5382    "EventName": "UNC_H_TRACKER_CYCLES_NE.LOCAL",
5383    "BriefDescription": "Tracker Cycles Not Empty; Local Requests",
5384    "PublicDescription": "Counts the number of cycles when the local HA tracker pool is not empty.  This can be used with edge detect to identify the number of situations when the pool became empty.  This should not be confused with RTID credit usage -- which must be tracked inside each cbo individually -- but represents the actual tracker buffer structure.  In other words, this buffer could be completely empty, but there may still be credits in use by the CBos.  This stat can be used in conjunction with the occupancy accumulation stat in order to calculate average queue occpancy.  HA trackers are allocated as soon as a request enters the HA if an HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.; This filter includes only requests coming from the local socket.",
5385    "Counter": "0,1,2,3",
5386    "MSRValue": "0x00",
5387    "ELLC": "0",
5388    "Filter": "na",
5389    "ExtSel": "0",
5390    "EVENT_STATUS": "0"
5391  },
5392  {
5393    "Unit": "HA",
5394    "EventCode": "0x3",
5395    "UMask": "0x2",
5396    "EventName": "UNC_H_TRACKER_CYCLES_NE.REMOTE",
5397    "BriefDescription": "Tracker Cycles Not Empty; Remote Requests",
5398    "PublicDescription": "Counts the number of cycles when the local HA tracker pool is not empty.  This can be used with edge detect to identify the number of situations when the pool became empty.  This should not be confused with RTID credit usage -- which must be tracked inside each cbo individually -- but represents the actual tracker buffer structure.  In other words, this buffer could be completely empty, but there may still be credits in use by the CBos.  This stat can be used in conjunction with the occupancy accumulation stat in order to calculate average queue occpancy.  HA trackers are allocated as soon as a request enters the HA if an HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.; This filter includes only requests coming from remote sockets.",
5399    "Counter": "0,1,2,3",
5400    "MSRValue": "0x00",
5401    "ELLC": "0",
5402    "Filter": "na",
5403    "ExtSel": "0",
5404    "EVENT_STATUS": "0"
5405  },
5406  {
5407    "Unit": "HA",
5408    "EventCode": "0x3",
5409    "UMask": "0x3",
5410    "EventName": "UNC_H_TRACKER_CYCLES_NE.ALL",
5411    "BriefDescription": "Tracker Cycles Not Empty; All Requests",
5412    "PublicDescription": "Counts the number of cycles when the local HA tracker pool is not empty.  This can be used with edge detect to identify the number of situations when the pool became empty.  This should not be confused with RTID credit usage -- which must be tracked inside each cbo individually -- but represents the actual tracker buffer structure.  In other words, this buffer could be completely empty, but there may still be credits in use by the CBos.  This stat can be used in conjunction with the occupancy accumulation stat in order to calculate average queue occpancy.  HA trackers are allocated as soon as a request enters the HA if an HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.; Requests coming from both local and remote sockets.",
5413    "Counter": "0,1,2,3",
5414    "MSRValue": "0x00",
5415    "ELLC": "0",
5416    "Filter": "na",
5417    "ExtSel": "0",
5418    "EVENT_STATUS": "0"
5419  },
5420  {
5421    "Unit": "IRP",
5422    "EventCode": "0x12",
5423    "UMask": "0x1",
5424    "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.ANY",
5425    "BriefDescription": "Total Write Cache Occupancy; Any Source",
5426    "PublicDescription": "Accumulates the number of reads and writes that are outstanding in the uncore in each cycle.  This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events.; Tracks all requests from any source port.",
5427    "Counter": "0,1",
5428    "MSRValue": "0x00",
5429    "ELLC": "0",
5430    "Filter": "na",
5431    "ExtSel": "0",
5432    "EVENT_STATUS": "0"
5433  },
5434  {
5435    "Unit": "IRP",
5436    "EventCode": "0x12",
5437    "UMask": "0x2",
5438    "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.SOURCE",
5439    "BriefDescription": "Total Write Cache Occupancy; Select Source",
5440    "PublicDescription": "Accumulates the number of reads and writes that are outstanding in the uncore in each cycle.  This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events.; Tracks only those requests that come from the port specified in the IRP_PmonFilter.OrderingQ register.  This register allows one to select one specific queue.  It is not possible to monitor multiple queues at a time.",
5441    "Counter": "0,1",
5442    "MSRValue": "0x00",
5443    "ELLC": "0",
5444    "Filter": "na",
5445    "ExtSel": "0",
5446    "EVENT_STATUS": "0"
5447  },
5448  {
5449    "Unit": "IRP",
5450    "EventCode": "0x0",
5451    "UMask": "0x0",
5452    "EventName": "UNC_I_CLOCKTICKS",
5453    "BriefDescription": "Clocks in the IRP",
5454    "PublicDescription": "Number of clocks in the IRP.",
5455    "Counter": "0,1",
5456    "MSRValue": "0x00",
5457    "ELLC": "0",
5458    "Filter": "na",
5459    "ExtSel": "0",
5460    "EVENT_STATUS": "0"
5461  },
5462  {
5463    "Unit": "IRP",
5464    "EventCode": "0x13",
5465    "UMask": "0x1",
5466    "EventName": "UNC_I_COHERENT_OPS.PCIRDCUR",
5467    "BriefDescription": "Coherent Ops; PCIRdCur",
5468    "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
5469    "Counter": "0,1",
5470    "MSRValue": "0x00",
5471    "ELLC": "0",
5472    "Filter": "na",
5473    "ExtSel": "0",
5474    "EVENT_STATUS": "0"
5475  },
5476  {
5477    "Unit": "IRP",
5478    "EventCode": "0x13",
5479    "UMask": "0x2",
5480    "EventName": "UNC_I_COHERENT_OPS.CRD",
5481    "BriefDescription": "Coherent Ops; CRd",
5482    "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
5483    "Counter": "0,1",
5484    "MSRValue": "0x00",
5485    "ELLC": "0",
5486    "Filter": "na",
5487    "ExtSel": "0",
5488    "EVENT_STATUS": "0"
5489  },
5490  {
5491    "Unit": "IRP",
5492    "EventCode": "0x13",
5493    "UMask": "0x4",
5494    "EventName": "UNC_I_COHERENT_OPS.DRD",
5495    "BriefDescription": "Coherent Ops; DRd",
5496    "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
5497    "Counter": "0,1",
5498    "MSRValue": "0x00",
5499    "ELLC": "0",
5500    "Filter": "na",
5501    "ExtSel": "0",
5502    "EVENT_STATUS": "0"
5503  },
5504  {
5505    "Unit": "IRP",
5506    "EventCode": "0x13",
5507    "UMask": "0x8",
5508    "EventName": "UNC_I_COHERENT_OPS.RFO",
5509    "BriefDescription": "Coherent Ops; RFO",
5510    "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
5511    "Counter": "0,1",
5512    "MSRValue": "0x00",
5513    "ELLC": "0",
5514    "Filter": "na",
5515    "ExtSel": "0",
5516    "EVENT_STATUS": "0"
5517  },
5518  {
5519    "Unit": "IRP",
5520    "EventCode": "0x13",
5521    "UMask": "0x10",
5522    "EventName": "UNC_I_COHERENT_OPS.PCITOM",
5523    "BriefDescription": "Coherent Ops; PCIItoM",
5524    "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
5525    "Counter": "0,1",
5526    "MSRValue": "0x00",
5527    "ELLC": "0",
5528    "Filter": "na",
5529    "ExtSel": "0",
5530    "EVENT_STATUS": "0"
5531  },
5532  {
5533    "Unit": "IRP",
5534    "EventCode": "0x13",
5535    "UMask": "0x20",
5536    "EventName": "UNC_I_COHERENT_OPS.PCIDCAHINT",
5537    "BriefDescription": "Coherent Ops; PCIDCAHin5t",
5538    "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
5539    "Counter": "0,1",
5540    "MSRValue": "0x00",
5541    "ELLC": "0",
5542    "Filter": "na",
5543    "ExtSel": "0",
5544    "EVENT_STATUS": "0"
5545  },
5546  {
5547    "Unit": "IRP",
5548    "EventCode": "0x13",
5549    "UMask": "0x40",
5550    "EventName": "UNC_I_COHERENT_OPS.WBMTOI",
5551    "BriefDescription": "Coherent Ops; WbMtoI",
5552    "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
5553    "Counter": "0,1",
5554    "MSRValue": "0x00",
5555    "ELLC": "0",
5556    "Filter": "na",
5557    "ExtSel": "0",
5558    "EVENT_STATUS": "0"
5559  },
5560  {
5561    "Unit": "IRP",
5562    "EventCode": "0x13",
5563    "UMask": "0x80",
5564    "EventName": "UNC_I_COHERENT_OPS.CLFLUSH",
5565    "BriefDescription": "Coherent Ops; CLFlush",
5566    "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
5567    "Counter": "0,1",
5568    "MSRValue": "0x00",
5569    "ELLC": "0",
5570    "Filter": "na",
5571    "ExtSel": "0",
5572    "EVENT_STATUS": "0"
5573  },
5574  {
5575    "Unit": "IRP",
5576    "EventCode": "0x14",
5577    "UMask": "0x1",
5578    "EventName": "UNC_I_MISC0.FAST_REQ",
5579    "BriefDescription": "Misc Events - Set 0; Fastpath Requests",
5580    "PublicDescription": "tbd",
5581    "Counter": "0,1",
5582    "MSRValue": "0x00",
5583    "ELLC": "0",
5584    "Filter": "na",
5585    "ExtSel": "0",
5586    "EVENT_STATUS": "0"
5587  },
5588  {
5589    "Unit": "IRP",
5590    "EventCode": "0x14",
5591    "UMask": "0x2",
5592    "EventName": "UNC_I_MISC0.FAST_REJ",
5593    "BriefDescription": "Misc Events - Set 0; Fastpath Rejects",
5594    "PublicDescription": "tbd",
5595    "Counter": "0,1",
5596    "MSRValue": "0x00",
5597    "ELLC": "0",
5598    "Filter": "na",
5599    "ExtSel": "0",
5600    "EVENT_STATUS": "0"
5601  },
5602  {
5603    "Unit": "IRP",
5604    "EventCode": "0x14",
5605    "UMask": "0x4",
5606    "EventName": "UNC_I_MISC0.2ND_RD_INSERT",
5607    "BriefDescription": "Misc Events - Set 0; Cache Inserts of Read Transactions as Secondary",
5608    "PublicDescription": "tbd",
5609    "Counter": "0,1",
5610    "MSRValue": "0x00",
5611    "ELLC": "0",
5612    "Filter": "na",
5613    "ExtSel": "0",
5614    "EVENT_STATUS": "0"
5615  },
5616  {
5617    "Unit": "IRP",
5618    "EventCode": "0x14",
5619    "UMask": "0x8",
5620    "EventName": "UNC_I_MISC0.2ND_WR_INSERT",
5621    "BriefDescription": "Misc Events - Set 0; Cache Inserts of Write Transactions as Secondary",
5622    "PublicDescription": "tbd",
5623    "Counter": "0,1",
5624    "MSRValue": "0x00",
5625    "ELLC": "0",
5626    "Filter": "na",
5627    "ExtSel": "0",
5628    "EVENT_STATUS": "0"
5629  },
5630  {
5631    "Unit": "IRP",
5632    "EventCode": "0x14",
5633    "UMask": "0x10",
5634    "EventName": "UNC_I_MISC0.2ND_ATOMIC_INSERT",
5635    "BriefDescription": "Misc Events - Set 0; Cache Inserts of Atomic Transactions as Secondary",
5636    "PublicDescription": "tbd",
5637    "Counter": "0,1",
5638    "MSRValue": "0x00",
5639    "ELLC": "0",
5640    "Filter": "na",
5641    "ExtSel": "0",
5642    "EVENT_STATUS": "0"
5643  },
5644  {
5645    "Unit": "IRP",
5646    "EventCode": "0x14",
5647    "UMask": "0x20",
5648    "EventName": "UNC_I_MISC0.FAST_XFER",
5649    "BriefDescription": "Misc Events - Set 0; Fastpath Transfers From Primary to Secondary",
5650    "PublicDescription": "tbd",
5651    "Counter": "0,1",
5652    "MSRValue": "0x00",
5653    "ELLC": "0",
5654    "Filter": "na",
5655    "ExtSel": "0",
5656    "EVENT_STATUS": "0"
5657  },
5658  {
5659    "Unit": "IRP",
5660    "EventCode": "0x14",
5661    "UMask": "0x40",
5662    "EventName": "UNC_I_MISC0.PF_ACK_HINT",
5663    "BriefDescription": "Misc Events - Set 0; Prefetch Ack Hints From Primary to Secondary",
5664    "PublicDescription": "tbd",
5665    "Counter": "0,1",
5666    "MSRValue": "0x00",
5667    "ELLC": "0",
5668    "Filter": "na",
5669    "ExtSel": "0",
5670    "EVENT_STATUS": "0"
5671  },
5672  {
5673    "Unit": "IRP",
5674    "EventCode": "0x15",
5675    "UMask": "0x1",
5676    "EventName": "UNC_I_MISC1.SLOW_I",
5677    "BriefDescription": "Misc Events - Set 1; Slow Transfer of I Line",
5678    "PublicDescription": "Snoop took cacheline ownership before write from data was committed.",
5679    "Counter": "0,1",
5680    "MSRValue": "0x00",
5681    "ELLC": "0",
5682    "Filter": "na",
5683    "ExtSel": "0",
5684    "EVENT_STATUS": "0"
5685  },
5686  {
5687    "Unit": "IRP",
5688    "EventCode": "0x15",
5689    "UMask": "0x2",
5690    "EventName": "UNC_I_MISC1.SLOW_S",
5691    "BriefDescription": "Misc Events - Set 1; Slow Transfer of S Line",
5692    "PublicDescription": "Secondary received a transfer that did not have sufficient MESI state",
5693    "Counter": "0,1",
5694    "MSRValue": "0x00",
5695    "ELLC": "0",
5696    "Filter": "na",
5697    "ExtSel": "0",
5698    "EVENT_STATUS": "0"
5699  },
5700  {
5701    "Unit": "IRP",
5702    "EventCode": "0x15",
5703    "UMask": "0x4",
5704    "EventName": "UNC_I_MISC1.SLOW_E",
5705    "BriefDescription": "Misc Events - Set 1; Slow Transfer of E Line",
5706    "PublicDescription": "Secondary received a transfer that did have sufficient MESI state",
5707    "Counter": "0,1",
5708    "MSRValue": "0x00",
5709    "ELLC": "0",
5710    "Filter": "na",
5711    "ExtSel": "0",
5712    "EVENT_STATUS": "0"
5713  },
5714  {
5715    "Unit": "IRP",
5716    "EventCode": "0x15",
5717    "UMask": "0x8",
5718    "EventName": "UNC_I_MISC1.SLOW_M",
5719    "BriefDescription": "Misc Events - Set 1; Slow Transfer of M Line",
5720    "PublicDescription": "Snoop took cacheline ownership before write from data was committed.",
5721    "Counter": "0,1",
5722    "MSRValue": "0x00",
5723    "ELLC": "0",
5724    "Filter": "na",
5725    "ExtSel": "0",
5726    "EVENT_STATUS": "0"
5727  },
5728  {
5729    "Unit": "IRP",
5730    "EventCode": "0x15",
5731    "UMask": "0x10",
5732    "EventName": "UNC_I_MISC1.LOST_FWD",
5733    "BriefDescription": "Misc Events - Set 1",
5734    "PublicDescription": "tbd",
5735    "Counter": "0,1",
5736    "MSRValue": "0x00",
5737    "ELLC": "0",
5738    "Filter": "na",
5739    "ExtSel": "0",
5740    "EVENT_STATUS": "0"
5741  },
5742  {
5743    "Unit": "IRP",
5744    "EventCode": "0x15",
5745    "UMask": "0x20",
5746    "EventName": "UNC_I_MISC1.SEC_RCVD_INVLD",
5747    "BriefDescription": "Misc Events - Set 1; Received Invalid",
5748    "PublicDescription": "Secondary received a transfer that did not have sufficient MESI state",
5749    "Counter": "0,1",
5750    "MSRValue": "0x00",
5751    "ELLC": "0",
5752    "Filter": "na",
5753    "ExtSel": "0",
5754    "EVENT_STATUS": "0"
5755  },
5756  {
5757    "Unit": "IRP",
5758    "EventCode": "0x15",
5759    "UMask": "0x40",
5760    "EventName": "UNC_I_MISC1.SEC_RCVD_VLD",
5761    "BriefDescription": "Misc Events - Set 1; Received Valid",
5762    "PublicDescription": "Secondary received a transfer that did have sufficient MESI state",
5763    "Counter": "0,1",
5764    "MSRValue": "0x00",
5765    "ELLC": "0",
5766    "Filter": "na",
5767    "ExtSel": "0",
5768    "EVENT_STATUS": "0"
5769  },
5770  {
5771    "Unit": "IRP",
5772    "EventCode": "0x15",
5773    "UMask": "0x80",
5774    "EventName": "UNC_I_MISC1.DATA_THROTTLE",
5775    "BriefDescription": "Misc Events - Set 1; Data Throttled",
5776    "PublicDescription": "IRP throttled switch data",
5777    "Counter": "0,1",
5778    "MSRValue": "0x00",
5779    "ELLC": "0",
5780    "Filter": "na",
5781    "ExtSel": "0",
5782    "EVENT_STATUS": "0"
5783  },
5784  {
5785    "Unit": "IRP",
5786    "EventCode": "0xA",
5787    "UMask": "0x0",
5788    "EventName": "UNC_I_RxR_AK_INSERTS",
5789    "BriefDescription": "AK Ingress Occupancy",
5790    "PublicDescription": "Counts the number of allocations into the AK Ingress.  This queue is where the IRP receives responses from R2PCIe (the ring).",
5791    "Counter": "0,1",
5792    "MSRValue": "0x00",
5793    "ELLC": "0",
5794    "Filter": "na",
5795    "ExtSel": "0",
5796    "EVENT_STATUS": "0"
5797  },
5798  {
5799    "Unit": "IRP",
5800    "EventCode": "0x4",
5801    "UMask": "0x0",
5802    "EventName": "UNC_I_RxR_BL_DRS_CYCLES_FULL",
5803    "BriefDescription": "tbd",
5804    "PublicDescription": "Counts the number of cycles when the BL Ingress is full.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requets as well as outbound MMIO writes.",
5805    "Counter": "0,1",
5806    "MSRValue": "0x00",
5807    "ELLC": "0",
5808    "Filter": "na",
5809    "ExtSel": "0",
5810    "EVENT_STATUS": "0"
5811  },
5812  {
5813    "Unit": "IRP",
5814    "EventCode": "0x1",
5815    "UMask": "0x0",
5816    "EventName": "UNC_I_RxR_BL_DRS_INSERTS",
5817    "BriefDescription": "BL Ingress Occupancy - DRS",
5818    "PublicDescription": "Counts the number of allocations into the BL Ingress.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requets as well as outbound MMIO writes.",
5819    "Counter": "0,1",
5820    "MSRValue": "0x00",
5821    "ELLC": "0",
5822    "Filter": "na",
5823    "ExtSel": "0",
5824    "EVENT_STATUS": "0"
5825  },
5826  {
5827    "Unit": "IRP",
5828    "EventCode": "0x7",
5829    "UMask": "0x0",
5830    "EventName": "UNC_I_RxR_BL_DRS_OCCUPANCY",
5831    "BriefDescription": "tbd",
5832    "PublicDescription": "Accumulates the occupancy of the BL Ingress in each cycles.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requets as well as outbound MMIO writes.",
5833    "Counter": "0,1",
5834    "MSRValue": "0x00",
5835    "ELLC": "0",
5836    "Filter": "na",
5837    "ExtSel": "0",
5838    "EVENT_STATUS": "0"
5839  },
5840  {
5841    "Unit": "IRP",
5842    "EventCode": "0x5",
5843    "UMask": "0x0",
5844    "EventName": "UNC_I_RxR_BL_NCB_CYCLES_FULL",
5845    "BriefDescription": "tbd",
5846    "PublicDescription": "Counts the number of cycles when the BL Ingress is full.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requets as well as outbound MMIO writes.",
5847    "Counter": "0,1",
5848    "MSRValue": "0x00",
5849    "ELLC": "0",
5850    "Filter": "na",
5851    "ExtSel": "0",
5852    "EVENT_STATUS": "0"
5853  },
5854  {
5855    "Unit": "IRP",
5856    "EventCode": "0x2",
5857    "UMask": "0x0",
5858    "EventName": "UNC_I_RxR_BL_NCB_INSERTS",
5859    "BriefDescription": "BL Ingress Occupancy - NCB",
5860    "PublicDescription": "Counts the number of allocations into the BL Ingress.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requets as well as outbound MMIO writes.",
5861    "Counter": "0,1",
5862    "MSRValue": "0x00",
5863    "ELLC": "0",
5864    "Filter": "na",
5865    "ExtSel": "0",
5866    "EVENT_STATUS": "0"
5867  },
5868  {
5869    "Unit": "IRP",
5870    "EventCode": "0x8",
5871    "UMask": "0x0",
5872    "EventName": "UNC_I_RxR_BL_NCB_OCCUPANCY",
5873    "BriefDescription": "tbd",
5874    "PublicDescription": "Accumulates the occupancy of the BL Ingress in each cycles.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requets as well as outbound MMIO writes.",
5875    "Counter": "0,1",
5876    "MSRValue": "0x00",
5877    "ELLC": "0",
5878    "Filter": "na",
5879    "ExtSel": "0",
5880    "EVENT_STATUS": "0"
5881  },
5882  {
5883    "Unit": "IRP",
5884    "EventCode": "0x6",
5885    "UMask": "0x0",
5886    "EventName": "UNC_I_RxR_BL_NCS_CYCLES_FULL",
5887    "BriefDescription": "tbd",
5888    "PublicDescription": "Counts the number of cycles when the BL Ingress is full.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requets as well as outbound MMIO writes.",
5889    "Counter": "0,1",
5890    "MSRValue": "0x00",
5891    "ELLC": "0",
5892    "Filter": "na",
5893    "ExtSel": "0",
5894    "EVENT_STATUS": "0"
5895  },
5896  {
5897    "Unit": "IRP",
5898    "EventCode": "0x3",
5899    "UMask": "0x0",
5900    "EventName": "UNC_I_RxR_BL_NCS_INSERTS",
5901    "BriefDescription": "BL Ingress Occupancy - NCS",
5902    "PublicDescription": "Counts the number of allocations into the BL Ingress.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requets as well as outbound MMIO writes.",
5903    "Counter": "0,1",
5904    "MSRValue": "0x00",
5905    "ELLC": "0",
5906    "Filter": "na",
5907    "ExtSel": "0",
5908    "EVENT_STATUS": "0"
5909  },
5910  {
5911    "Unit": "IRP",
5912    "EventCode": "0x9",
5913    "UMask": "0x0",
5914    "EventName": "UNC_I_RxR_BL_NCS_OCCUPANCY",
5915    "BriefDescription": "tbd",
5916    "PublicDescription": "Accumulates the occupancy of the BL Ingress in each cycles.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requets as well as outbound MMIO writes.",
5917    "Counter": "0,1",
5918    "MSRValue": "0x00",
5919    "ELLC": "0",
5920    "Filter": "na",
5921    "ExtSel": "0",
5922    "EVENT_STATUS": "0"
5923  },
5924  {
5925    "Unit": "IRP",
5926    "EventCode": "0x17",
5927    "UMask": "0x1",
5928    "EventName": "UNC_I_SNOOP_RESP.MISS",
5929    "BriefDescription": "Snoop Responses; Miss",
5930    "PublicDescription": "tbd",
5931    "Counter": "0,1",
5932    "MSRValue": "0x00",
5933    "ELLC": "0",
5934    "Filter": "na",
5935    "ExtSel": "0",
5936    "EVENT_STATUS": "0"
5937  },
5938  {
5939    "Unit": "IRP",
5940    "EventCode": "0x17",
5941    "UMask": "0x2",
5942    "EventName": "UNC_I_SNOOP_RESP.HIT_I",
5943    "BriefDescription": "Snoop Responses; Hit I",
5944    "PublicDescription": "tbd",
5945    "Counter": "0,1",
5946    "MSRValue": "0x00",
5947    "ELLC": "0",
5948    "Filter": "na",
5949    "ExtSel": "0",
5950    "EVENT_STATUS": "0"
5951  },
5952  {
5953    "Unit": "IRP",
5954    "EventCode": "0x17",
5955    "UMask": "0x4",
5956    "EventName": "UNC_I_SNOOP_RESP.HIT_ES",
5957    "BriefDescription": "Snoop Responses; Hit E or S",
5958    "PublicDescription": "tbd",
5959    "Counter": "0,1",
5960    "MSRValue": "0x00",
5961    "ELLC": "0",
5962    "Filter": "na",
5963    "ExtSel": "0",
5964    "EVENT_STATUS": "0"
5965  },
5966  {
5967    "Unit": "IRP",
5968    "EventCode": "0x17",
5969    "UMask": "0x8",
5970    "EventName": "UNC_I_SNOOP_RESP.HIT_M",
5971    "BriefDescription": "Snoop Responses; Hit M",
5972    "PublicDescription": "tbd",
5973    "Counter": "0,1",
5974    "MSRValue": "0x00",
5975    "ELLC": "0",
5976    "Filter": "na",
5977    "ExtSel": "0",
5978    "EVENT_STATUS": "0"
5979  },
5980  {
5981    "Unit": "IRP",
5982    "EventCode": "0x17",
5983    "UMask": "0x10",
5984    "EventName": "UNC_I_SNOOP_RESP.SNPCODE",
5985    "BriefDescription": "Snoop Responses; SnpCode",
5986    "PublicDescription": "tbd",
5987    "Counter": "0,1",
5988    "MSRValue": "0x00",
5989    "ELLC": "0",
5990    "Filter": "na",
5991    "ExtSel": "0",
5992    "EVENT_STATUS": "0"
5993  },
5994  {
5995    "Unit": "IRP",
5996    "EventCode": "0x17",
5997    "UMask": "0x20",
5998    "EventName": "UNC_I_SNOOP_RESP.SNPDATA",
5999    "BriefDescription": "Snoop Responses; SnpData",
6000    "PublicDescription": "tbd",
6001    "Counter": "0,1",
6002    "MSRValue": "0x00",
6003    "ELLC": "0",
6004    "Filter": "na",
6005    "ExtSel": "0",
6006    "EVENT_STATUS": "0"
6007  },
6008  {
6009    "Unit": "IRP",
6010    "EventCode": "0x17",
6011    "UMask": "0x40",
6012    "EventName": "UNC_I_SNOOP_RESP.SNPINV",
6013    "BriefDescription": "Snoop Responses; SnpInv",
6014    "PublicDescription": "tbd",
6015    "Counter": "0,1",
6016    "MSRValue": "0x00",
6017    "ELLC": "0",
6018    "Filter": "na",
6019    "ExtSel": "0",
6020    "EVENT_STATUS": "0"
6021  },
6022  {
6023    "Unit": "IRP",
6024    "EventCode": "0x16",
6025    "UMask": "0x1",
6026    "EventName": "UNC_I_TRANSACTIONS.READS",
6027    "BriefDescription": "Inbound Transaction Count; Reads",
6028    "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks only read requests (not including read prefetches).",
6029    "Counter": "0,1",
6030    "MSRValue": "0x00",
6031    "ELLC": "0",
6032    "Filter": "na",
6033    "ExtSel": "0",
6034    "EVENT_STATUS": "0"
6035  },
6036  {
6037    "Unit": "IRP",
6038    "EventCode": "0x16",
6039    "UMask": "0x2",
6040    "EventName": "UNC_I_TRANSACTIONS.WRITES",
6041    "BriefDescription": "Inbound Transaction Count; Writes",
6042    "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Trackes only write requests.  Each write request should have a prefetch, so there is no need to explicitly track these requests.  For writes that are tickled and have to retry, the counter will be incremented for each retry.",
6043    "Counter": "0,1",
6044    "MSRValue": "0x00",
6045    "ELLC": "0",
6046    "Filter": "na",
6047    "ExtSel": "0",
6048    "EVENT_STATUS": "0"
6049  },
6050  {
6051    "Unit": "IRP",
6052    "EventCode": "0x16",
6053    "UMask": "0x4",
6054    "EventName": "UNC_I_TRANSACTIONS.RD_PREF",
6055    "BriefDescription": "Inbound Transaction Count; Read Prefetches",
6056    "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of read prefetches.",
6057    "Counter": "0,1",
6058    "MSRValue": "0x00",
6059    "ELLC": "0",
6060    "Filter": "na",
6061    "ExtSel": "0",
6062    "EVENT_STATUS": "0"
6063  },
6064  {
6065    "Unit": "IRP",
6066    "EventCode": "0x16",
6067    "UMask": "0x8",
6068    "EventName": "UNC_I_TRANSACTIONS.WR_PREF",
6069    "BriefDescription": "Inbound Transaction Count; Write Prefetches",
6070    "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of write prefetches.",
6071    "Counter": "0,1",
6072    "MSRValue": "0x00",
6073    "ELLC": "0",
6074    "Filter": "na",
6075    "ExtSel": "0",
6076    "EVENT_STATUS": "0"
6077  },
6078  {
6079    "Unit": "IRP",
6080    "EventCode": "0x16",
6081    "UMask": "0x10",
6082    "EventName": "UNC_I_TRANSACTIONS.ATOMIC",
6083    "BriefDescription": "Inbound Transaction Count; Atomic",
6084    "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of atomic transactions",
6085    "Counter": "0,1",
6086    "MSRValue": "0x00",
6087    "ELLC": "0",
6088    "Filter": "na",
6089    "ExtSel": "0",
6090    "EVENT_STATUS": "0"
6091  },
6092  {
6093    "Unit": "IRP",
6094    "EventCode": "0x16",
6095    "UMask": "0x20",
6096    "EventName": "UNC_I_TRANSACTIONS.OTHER",
6097    "BriefDescription": "Inbound Transaction Count; Other",
6098    "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of 'other' kinds of transactions.",
6099    "Counter": "0,1",
6100    "MSRValue": "0x00",
6101    "ELLC": "0",
6102    "Filter": "na",
6103    "ExtSel": "0",
6104    "EVENT_STATUS": "0"
6105  },
6106  {
6107    "Unit": "IRP",
6108    "EventCode": "0x16",
6109    "UMask": "0x40",
6110    "EventName": "UNC_I_TRANSACTIONS.ORDERINGQ",
6111    "BriefDescription": "Inbound Transaction Count; Select Source",
6112    "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks only those requests that come from the port specified in the IRP_PmonFilter.OrderingQ register.  This register allows one to select one specific queue.  It is not possible to monitor multiple queues at a time.  If this bit is not set, then requests from all sources will be counted.",
6113    "Counter": "0,1",
6114    "MSRValue": "0x00",
6115    "ELLC": "0",
6116    "Filter": "IRPFilter[4:0]",
6117    "ExtSel": "0",
6118    "EVENT_STATUS": "0"
6119  },
6120  {
6121    "Unit": "IRP",
6122    "EventCode": "0x18",
6123    "UMask": "0x0",
6124    "EventName": "UNC_I_TxR_AD_STALL_CREDIT_CYCLES",
6125    "BriefDescription": "No AD Egress Credit Stalls",
6126    "PublicDescription": "Counts the number times when it is not possible to issue a request to the R2PCIe because there are no AD Egress Credits available.",
6127    "Counter": "0,1",
6128    "MSRValue": "0x00",
6129    "ELLC": "0",
6130    "Filter": "na",
6131    "ExtSel": "0",
6132    "EVENT_STATUS": "0"
6133  },
6134  {
6135    "Unit": "IRP",
6136    "EventCode": "0x19",
6137    "UMask": "0x0",
6138    "EventName": "UNC_I_TxR_BL_STALL_CREDIT_CYCLES",
6139    "BriefDescription": "No BL Egress Credit Stalls",
6140    "PublicDescription": "Counts the number times when it is not possible to issue data to the R2PCIe because there are no BL Egress Credits available.",
6141    "Counter": "0,1",
6142    "MSRValue": "0x00",
6143    "ELLC": "0",
6144    "Filter": "na",
6145    "ExtSel": "0",
6146    "EVENT_STATUS": "0"
6147  },
6148  {
6149    "Unit": "IRP",
6150    "EventCode": "0xE",
6151    "UMask": "0x0",
6152    "EventName": "UNC_I_TxR_DATA_INSERTS_NCB",
6153    "BriefDescription": "Outbound Read Requests",
6154    "PublicDescription": "Counts the number of requests issued to the switch (towards the devices).",
6155    "Counter": "0,1",
6156    "MSRValue": "0x00",
6157    "ELLC": "0",
6158    "Filter": "na",
6159    "ExtSel": "0",
6160    "EVENT_STATUS": "0"
6161  },
6162  {
6163    "Unit": "IRP",
6164    "EventCode": "0xF",
6165    "UMask": "0x0",
6166    "EventName": "UNC_I_TxR_DATA_INSERTS_NCS",
6167    "BriefDescription": "Outbound Read Requests",
6168    "PublicDescription": "Counts the number of requests issued to the switch (towards the devices).",
6169    "Counter": "0,1",
6170    "MSRValue": "0x00",
6171    "ELLC": "0",
6172    "Filter": "na",
6173    "ExtSel": "0",
6174    "EVENT_STATUS": "0"
6175  },
6176  {
6177    "Unit": "IRP",
6178    "EventCode": "0xD",
6179    "UMask": "0x0",
6180    "EventName": "UNC_I_TxR_REQUEST_OCCUPANCY",
6181    "BriefDescription": "Outbound Request Queue Occupancy",
6182    "PublicDescription": "Accumultes the number of outstanding outbound requests from the IRP to the switch (towards the devices).  This can be used in conjuection with the allocations event in order to calculate average latency of outbound requests.",
6183    "Counter": "0,1",
6184    "MSRValue": "0x00",
6185    "ELLC": "0",
6186    "Filter": "na",
6187    "ExtSel": "0",
6188    "EVENT_STATUS": "0"
6189  },
6190  {
6191    "Unit": "IRP",
6192    "EventCode": "0x14",
6193    "UMask": "0x80",
6194    "EventName": "UNC_I_MISC0.PF_TIMEOUT",
6195    "BriefDescription": "Misc Events - Set 0; Prefetch TimeOut",
6196    "PublicDescription": "Indicates the fetch for a previous prefetch wasn't accepted by the prefetch.   This happens in the case of a prefetch TimeOut",
6197    "Counter": "0,1",
6198    "MSRValue": "0x00",
6199    "ELLC": "0",
6200    "Filter": "na",
6201    "ExtSel": "0",
6202    "EVENT_STATUS": "0"
6203  },
6204  {
6205    "Unit": "PCU",
6206    "EventCode": "0x0",
6207    "UMask": "0x0",
6208    "EventName": "UNC_P_CLOCKTICKS",
6209    "BriefDescription": "pclk Cycles",
6210    "PublicDescription": "The PCU runs off a fixed 800 MHz clock.  This event counts the number of pclk cycles measured while the counter was enabled.  The pclk, like the Memory Controller's dclk, counts at a constant rate making it a good measure of actual wall time.",
6211    "Counter": "0,1,2,3",
6212    "MSRValue": "0x00",
6213    "ELLC": "0",
6214    "Filter": "na",
6215    "ExtSel": "0",
6216    "EVENT_STATUS": "0"
6217  },
6218  {
6219    "Unit": "PCU",
6220    "EventCode": "0x60",
6221    "UMask": "0x0",
6222    "EventName": "UNC_P_CORE0_TRANSITION_CYCLES",
6223    "BriefDescription": "Core C State Transition Cycles",
6224    "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
6225    "Counter": "0,1,2,3",
6226    "MSRValue": "0x00",
6227    "ELLC": "0",
6228    "Filter": "na",
6229    "ExtSel": "0",
6230    "EVENT_STATUS": "0"
6231  },
6232  {
6233    "Unit": "PCU",
6234    "EventCode": "0x6A",
6235    "UMask": "0x0",
6236    "EventName": "UNC_P_CORE10_TRANSITION_CYCLES",
6237    "BriefDescription": "Core C State Transition Cycles",
6238    "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
6239    "Counter": "0,1,2,3",
6240    "MSRValue": "0x00",
6241    "ELLC": "0",
6242    "Filter": "na",
6243    "ExtSel": "0",
6244    "EVENT_STATUS": "0"
6245  },
6246  {
6247    "Unit": "PCU",
6248    "EventCode": "0x6B",
6249    "UMask": "0x0",
6250    "EventName": "UNC_P_CORE11_TRANSITION_CYCLES",
6251    "BriefDescription": "Core C State Transition Cycles",
6252    "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
6253    "Counter": "0,1,2,3",
6254    "MSRValue": "0x00",
6255    "ELLC": "0",
6256    "Filter": "na",
6257    "ExtSel": "0",
6258    "EVENT_STATUS": "0"
6259  },
6260  {
6261    "Unit": "PCU",
6262    "EventCode": "0x6C",
6263    "UMask": "0x0",
6264    "EventName": "UNC_P_CORE12_TRANSITION_CYCLES",
6265    "BriefDescription": "Core C State Transition Cycles",
6266    "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
6267    "Counter": "0,1,2,3",
6268    "MSRValue": "0x00",
6269    "ELLC": "0",
6270    "Filter": "na",
6271    "ExtSel": "0",
6272    "EVENT_STATUS": "0"
6273  },
6274  {
6275    "Unit": "PCU",
6276    "EventCode": "0x6D",
6277    "UMask": "0x0",
6278    "EventName": "UNC_P_CORE13_TRANSITION_CYCLES",
6279    "BriefDescription": "Core C State Transition Cycles",
6280    "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
6281    "Counter": "0,1,2,3",
6282    "MSRValue": "0x00",
6283    "ELLC": "0",
6284    "Filter": "na",
6285    "ExtSel": "0",
6286    "EVENT_STATUS": "0"
6287  },
6288  {
6289    "Unit": "PCU",
6290    "EventCode": "0x6E",
6291    "UMask": "0x0",
6292    "EventName": "UNC_P_CORE14_TRANSITION_CYCLES",
6293    "BriefDescription": "Core C State Transition Cycles",
6294    "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
6295    "Counter": "0,1,2,3",
6296    "MSRValue": "0x00",
6297    "ELLC": "0",
6298    "Filter": "na",
6299    "ExtSel": "0",
6300    "EVENT_STATUS": "0"
6301  },
6302  {
6303    "Unit": "PCU",
6304    "EventCode": "0x6F",
6305    "UMask": "0x0",
6306    "EventName": "UNC_P_CORE15_TRANSITION_CYCLES",
6307    "BriefDescription": "Core C State Transition Cycles",
6308    "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
6309    "Counter": "0,1,2,3",
6310    "MSRValue": "0x00",
6311    "ELLC": "0",
6312    "Filter": "na",
6313    "ExtSel": "0",
6314    "EVENT_STATUS": "0"
6315  },
6316  {
6317    "Unit": "PCU",
6318    "EventCode": "0x70",
6319    "UMask": "0x0",
6320    "EventName": "UNC_P_CORE16_TRANSITION_CYCLES",
6321    "BriefDescription": "Core C State Transition Cycles",
6322    "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
6323    "Counter": "0,1,2,3",
6324    "MSRValue": "0x00",
6325    "ELLC": "0",
6326    "Filter": "na",
6327    "ExtSel": "0",
6328    "EVENT_STATUS": "0"
6329  },
6330  {
6331    "Unit": "PCU",
6332    "EventCode": "0x71",
6333    "UMask": "0x0",
6334    "EventName": "UNC_P_CORE17_TRANSITION_CYCLES",
6335    "BriefDescription": "Core C State Transition Cycles",
6336    "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
6337    "Counter": "0,1,2,3",
6338    "MSRValue": "0x00",
6339    "ELLC": "0",
6340    "Filter": "na",
6341    "ExtSel": "0",
6342    "EVENT_STATUS": "0"
6343  },
6344  {
6345    "Unit": "PCU",
6346    "EventCode": "0x61",
6347    "UMask": "0x0",
6348    "EventName": "UNC_P_CORE1_TRANSITION_CYCLES",
6349    "BriefDescription": "Core C State Transition Cycles",
6350    "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
6351    "Counter": "0,1,2,3",
6352    "MSRValue": "0x00",
6353    "ELLC": "0",
6354    "Filter": "na",
6355    "ExtSel": "0",
6356    "EVENT_STATUS": "0"
6357  },
6358  {
6359    "Unit": "PCU",
6360    "EventCode": "0x62",
6361    "UMask": "0x0",
6362    "EventName": "UNC_P_CORE2_TRANSITION_CYCLES",
6363    "BriefDescription": "Core C State Transition Cycles",
6364    "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
6365    "Counter": "0,1,2,3",
6366    "MSRValue": "0x00",
6367    "ELLC": "0",
6368    "Filter": "na",
6369    "ExtSel": "0",
6370    "EVENT_STATUS": "0"
6371  },
6372  {
6373    "Unit": "PCU",
6374    "EventCode": "0x63",
6375    "UMask": "0x0",
6376    "EventName": "UNC_P_CORE3_TRANSITION_CYCLES",
6377    "BriefDescription": "Core C State Transition Cycles",
6378    "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
6379    "Counter": "0,1,2,3",
6380    "MSRValue": "0x00",
6381    "ELLC": "0",
6382    "Filter": "na",
6383    "ExtSel": "0",
6384    "EVENT_STATUS": "0"
6385  },
6386  {
6387    "Unit": "PCU",
6388    "EventCode": "0x64",
6389    "UMask": "0x0",
6390    "EventName": "UNC_P_CORE4_TRANSITION_CYCLES",
6391    "BriefDescription": "Core C State Transition Cycles",
6392    "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
6393    "Counter": "0,1,2,3",
6394    "MSRValue": "0x00",
6395    "ELLC": "0",
6396    "Filter": "na",
6397    "ExtSel": "0",
6398    "EVENT_STATUS": "0"
6399  },
6400  {
6401    "Unit": "PCU",
6402    "EventCode": "0x65",
6403    "UMask": "0x0",
6404    "EventName": "UNC_P_CORE5_TRANSITION_CYCLES",
6405    "BriefDescription": "Core C State Transition Cycles",
6406    "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
6407    "Counter": "0,1,2,3",
6408    "MSRValue": "0x00",
6409    "ELLC": "0",
6410    "Filter": "na",
6411    "ExtSel": "0",
6412    "EVENT_STATUS": "0"
6413  },
6414  {
6415    "Unit": "PCU",
6416    "EventCode": "0x66",
6417    "UMask": "0x0",
6418    "EventName": "UNC_P_CORE6_TRANSITION_CYCLES",
6419    "BriefDescription": "Core C State Transition Cycles",
6420    "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
6421    "Counter": "0,1,2,3",
6422    "MSRValue": "0x00",
6423    "ELLC": "0",
6424    "Filter": "na",
6425    "ExtSel": "0",
6426    "EVENT_STATUS": "0"
6427  },
6428  {
6429    "Unit": "PCU",
6430    "EventCode": "0x67",
6431    "UMask": "0x0",
6432    "EventName": "UNC_P_CORE7_TRANSITION_CYCLES",
6433    "BriefDescription": "Core C State Transition Cycles",
6434    "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
6435    "Counter": "0,1,2,3",
6436    "MSRValue": "0x00",
6437    "ELLC": "0",
6438    "Filter": "na",
6439    "ExtSel": "0",
6440    "EVENT_STATUS": "0"
6441  },
6442  {
6443    "Unit": "PCU",
6444    "EventCode": "0x68",
6445    "UMask": "0x0",
6446    "EventName": "UNC_P_CORE8_TRANSITION_CYCLES",
6447    "BriefDescription": "Core C State Transition Cycles",
6448    "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
6449    "Counter": "0,1,2,3",
6450    "MSRValue": "0x00",
6451    "ELLC": "0",
6452    "Filter": "na",
6453    "ExtSel": "0",
6454    "EVENT_STATUS": "0"
6455  },
6456  {
6457    "Unit": "PCU",
6458    "EventCode": "0x69",
6459    "UMask": "0x0",
6460    "EventName": "UNC_P_CORE9_TRANSITION_CYCLES",
6461    "BriefDescription": "Core C State Transition Cycles",
6462    "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
6463    "Counter": "0,1,2,3",
6464    "MSRValue": "0x00",
6465    "ELLC": "0",
6466    "Filter": "na",
6467    "ExtSel": "0",
6468    "EVENT_STATUS": "0"
6469  },
6470  {
6471    "Unit": "PCU",
6472    "EventCode": "0x30",
6473    "UMask": "0x0",
6474    "EventName": "UNC_P_DEMOTIONS_CORE0",
6475    "BriefDescription": "Core C State Demotions",
6476    "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
6477    "Counter": "0,1,2,3",
6478    "MSRValue": "0x00",
6479    "ELLC": "0",
6480    "Filter": "na",
6481    "ExtSel": "0",
6482    "EVENT_STATUS": "0"
6483  },
6484  {
6485    "Unit": "PCU",
6486    "EventCode": "0x31",
6487    "UMask": "0x0",
6488    "EventName": "UNC_P_DEMOTIONS_CORE1",
6489    "BriefDescription": "Core C State Demotions",
6490    "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
6491    "Counter": "0,1,2,3",
6492    "MSRValue": "0x00",
6493    "ELLC": "0",
6494    "Filter": "na",
6495    "ExtSel": "0",
6496    "EVENT_STATUS": "0"
6497  },
6498  {
6499    "Unit": "PCU",
6500    "EventCode": "0x3A",
6501    "UMask": "0x0",
6502    "EventName": "UNC_P_DEMOTIONS_CORE10",
6503    "BriefDescription": "Core C State Demotions",
6504    "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
6505    "Counter": "0,1,2,3",
6506    "MSRValue": "0x00",
6507    "ELLC": "0",
6508    "Filter": "na",
6509    "ExtSel": "0",
6510    "EVENT_STATUS": "0"
6511  },
6512  {
6513    "Unit": "PCU",
6514    "EventCode": "0x3B",
6515    "UMask": "0x0",
6516    "EventName": "UNC_P_DEMOTIONS_CORE11",
6517    "BriefDescription": "Core C State Demotions",
6518    "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
6519    "Counter": "0,1,2,3",
6520    "MSRValue": "0x00",
6521    "ELLC": "0",
6522    "Filter": "na",
6523    "ExtSel": "0",
6524    "EVENT_STATUS": "0"
6525  },
6526  {
6527    "Unit": "PCU",
6528    "EventCode": "0x3C",
6529    "UMask": "0x0",
6530    "EventName": "UNC_P_DEMOTIONS_CORE12",
6531    "BriefDescription": "Core C State Demotions",
6532    "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
6533    "Counter": "0,1,2,3",
6534    "MSRValue": "0x00",
6535    "ELLC": "0",
6536    "Filter": "na",
6537    "ExtSel": "0",
6538    "EVENT_STATUS": "0"
6539  },
6540  {
6541    "Unit": "PCU",
6542    "EventCode": "0x3D",
6543    "UMask": "0x0",
6544    "EventName": "UNC_P_DEMOTIONS_CORE13",
6545    "BriefDescription": "Core C State Demotions",
6546    "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
6547    "Counter": "0,1,2,3",
6548    "MSRValue": "0x00",
6549    "ELLC": "0",
6550    "Filter": "na",
6551    "ExtSel": "0",
6552    "EVENT_STATUS": "0"
6553  },
6554  {
6555    "Unit": "PCU",
6556    "EventCode": "0x3E",
6557    "UMask": "0x0",
6558    "EventName": "UNC_P_DEMOTIONS_CORE14",
6559    "BriefDescription": "Core C State Demotions",
6560    "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
6561    "Counter": "0,1,2,3",
6562    "MSRValue": "0x00",
6563    "ELLC": "0",
6564    "Filter": "na",
6565    "ExtSel": "0",
6566    "EVENT_STATUS": "0"
6567  },
6568  {
6569    "Unit": "PCU",
6570    "EventCode": "0x3F",
6571    "UMask": "0x0",
6572    "EventName": "UNC_P_DEMOTIONS_CORE15",
6573    "BriefDescription": "Core C State Demotions",
6574    "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
6575    "Counter": "0,1,2,3",
6576    "MSRValue": "0x00",
6577    "ELLC": "0",
6578    "Filter": "na",
6579    "ExtSel": "0",
6580    "EVENT_STATUS": "0"
6581  },
6582  {
6583    "Unit": "PCU",
6584    "EventCode": "0x40",
6585    "UMask": "0x0",
6586    "EventName": "UNC_P_DEMOTIONS_CORE16",
6587    "BriefDescription": "Core C State Demotions",
6588    "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
6589    "Counter": "0,1,2,3",
6590    "MSRValue": "0x00",
6591    "ELLC": "0",
6592    "Filter": "na",
6593    "ExtSel": "0",
6594    "EVENT_STATUS": "0"
6595  },
6596  {
6597    "Unit": "PCU",
6598    "EventCode": "0x41",
6599    "UMask": "0x0",
6600    "EventName": "UNC_P_DEMOTIONS_CORE17",
6601    "BriefDescription": "Core C State Demotions",
6602    "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
6603    "Counter": "0,1,2,3",
6604    "MSRValue": "0x00",
6605    "ELLC": "0",
6606    "Filter": "na",
6607    "ExtSel": "0",
6608    "EVENT_STATUS": "0"
6609  },
6610  {
6611    "Unit": "PCU",
6612    "EventCode": "0x32",
6613    "UMask": "0x0",
6614    "EventName": "UNC_P_DEMOTIONS_CORE2",
6615    "BriefDescription": "Core C State Demotions",
6616    "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
6617    "Counter": "0,1,2,3",
6618    "MSRValue": "0x00",
6619    "ELLC": "0",
6620    "Filter": "na",
6621    "ExtSel": "0",
6622    "EVENT_STATUS": "0"
6623  },
6624  {
6625    "Unit": "PCU",
6626    "EventCode": "0x33",
6627    "UMask": "0x0",
6628    "EventName": "UNC_P_DEMOTIONS_CORE3",
6629    "BriefDescription": "Core C State Demotions",
6630    "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
6631    "Counter": "0,1,2,3",
6632    "MSRValue": "0x00",
6633    "ELLC": "0",
6634    "Filter": "na",
6635    "ExtSel": "0",
6636    "EVENT_STATUS": "0"
6637  },
6638  {
6639    "Unit": "PCU",
6640    "EventCode": "0x34",
6641    "UMask": "0x0",
6642    "EventName": "UNC_P_DEMOTIONS_CORE4",
6643    "BriefDescription": "Core C State Demotions",
6644    "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
6645    "Counter": "0,1,2,3",
6646    "MSRValue": "0x00",
6647    "ELLC": "0",
6648    "Filter": "na",
6649    "ExtSel": "0",
6650    "EVENT_STATUS": "0"
6651  },
6652  {
6653    "Unit": "PCU",
6654    "EventCode": "0x35",
6655    "UMask": "0x0",
6656    "EventName": "UNC_P_DEMOTIONS_CORE5",
6657    "BriefDescription": "Core C State Demotions",
6658    "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
6659    "Counter": "0,1,2,3",
6660    "MSRValue": "0x00",
6661    "ELLC": "0",
6662    "Filter": "na",
6663    "ExtSel": "0",
6664    "EVENT_STATUS": "0"
6665  },
6666  {
6667    "Unit": "PCU",
6668    "EventCode": "0x36",
6669    "UMask": "0x0",
6670    "EventName": "UNC_P_DEMOTIONS_CORE6",
6671    "BriefDescription": "Core C State Demotions",
6672    "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
6673    "Counter": "0,1,2,3",
6674    "MSRValue": "0x00",
6675    "ELLC": "0",
6676    "Filter": "na",
6677    "ExtSel": "0",
6678    "EVENT_STATUS": "0"
6679  },
6680  {
6681    "Unit": "PCU",
6682    "EventCode": "0x37",
6683    "UMask": "0x0",
6684    "EventName": "UNC_P_DEMOTIONS_CORE7",
6685    "BriefDescription": "Core C State Demotions",
6686    "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
6687    "Counter": "0,1,2,3",
6688    "MSRValue": "0x00",
6689    "ELLC": "0",
6690    "Filter": "na",
6691    "ExtSel": "0",
6692    "EVENT_STATUS": "0"
6693  },
6694  {
6695    "Unit": "PCU",
6696    "EventCode": "0x38",
6697    "UMask": "0x0",
6698    "EventName": "UNC_P_DEMOTIONS_CORE8",
6699    "BriefDescription": "Core C State Demotions",
6700    "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
6701    "Counter": "0,1,2,3",
6702    "MSRValue": "0x00",
6703    "ELLC": "0",
6704    "Filter": "na",
6705    "ExtSel": "0",
6706    "EVENT_STATUS": "0"
6707  },
6708  {
6709    "Unit": "PCU",
6710    "EventCode": "0x39",
6711    "UMask": "0x0",
6712    "EventName": "UNC_P_DEMOTIONS_CORE9",
6713    "BriefDescription": "Core C State Demotions",
6714    "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
6715    "Counter": "0,1,2,3",
6716    "MSRValue": "0x00",
6717    "ELLC": "0",
6718    "Filter": "na",
6719    "ExtSel": "0",
6720    "EVENT_STATUS": "0"
6721  },
6722  {
6723    "Unit": "PCU",
6724    "EventCode": "0xB",
6725    "UMask": "0x0",
6726    "EventName": "UNC_P_FREQ_BAND0_CYCLES",
6727    "BriefDescription": "Frequency Residency",
6728    "PublicDescription": "Counts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter.  One can use all four counters with this event, so it is possible to track up to 4 configurable bands.  One can use edge detect in conjunction with this event to track the number of times that we transitioned into a frequency greater than or equal to the configurable frequency. One can also use inversion to track cycles when we were less than the configured frequency.",
6729    "Counter": "0,1,2,3",
6730    "MSRValue": "0x00",
6731    "ELLC": "0",
6732    "Filter": "PCUFilter[7:0]",
6733    "ExtSel": "0",
6734    "EVENT_STATUS": "0"
6735  },
6736  {
6737    "Unit": "PCU",
6738    "EventCode": "0xC",
6739    "UMask": "0x0",
6740    "EventName": "UNC_P_FREQ_BAND1_CYCLES",
6741    "BriefDescription": "Frequency Residency",
6742    "PublicDescription": "Counts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter.  One can use all four counters with this event, so it is possible to track up to 4 configurable bands.  One can use edge detect in conjunction with this event to track the number of times that we transitioned into a frequency greater than or equal to the configurable frequency. One can also use inversion to track cycles when we were less than the configured frequency.",
6743    "Counter": "0,1,2,3",
6744    "MSRValue": "0x00",
6745    "ELLC": "0",
6746    "Filter": "PCUFilter[15:8]",
6747    "ExtSel": "0",
6748    "EVENT_STATUS": "0"
6749  },
6750  {
6751    "Unit": "PCU",
6752    "EventCode": "0xD",
6753    "UMask": "0x0",
6754    "EventName": "UNC_P_FREQ_BAND2_CYCLES",
6755    "BriefDescription": "Frequency Residency",
6756    "PublicDescription": "Counts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter.  One can use all four counters with this event, so it is possible to track up to 4 configurable bands.  One can use edge detect in conjunction with this event to track the number of times that we transitioned into a frequency greater than or equal to the configurable frequency. One can also use inversion to track cycles when we were less than the configured frequency.",
6757    "Counter": "0,1,2,3",
6758    "MSRValue": "0x00",
6759    "ELLC": "0",
6760    "Filter": "PCUFilter[23:16]",
6761    "ExtSel": "0",
6762    "EVENT_STATUS": "0"
6763  },
6764  {
6765    "Unit": "PCU",
6766    "EventCode": "0xE",
6767    "UMask": "0x0",
6768    "EventName": "UNC_P_FREQ_BAND3_CYCLES",
6769    "BriefDescription": "Frequency Residency",
6770    "PublicDescription": "Counts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter.  One can use all four counters with this event, so it is possible to track up to 4 configurable bands.  One can use edge detect in conjunction with this event to track the number of times that we transitioned into a frequency greater than or equal to the configurable frequency. One can also use inversion to track cycles when we were less than the configured frequency.",
6771    "Counter": "0,1,2,3",
6772    "MSRValue": "0x00",
6773    "ELLC": "0",
6774    "Filter": "PCUFilter[31:24]",
6775    "ExtSel": "0",
6776    "EVENT_STATUS": "0"
6777  },
6778  {
6779    "Unit": "PCU",
6780    "EventCode": "0x4",
6781    "UMask": "0x0",
6782    "EventName": "UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLES",
6783    "BriefDescription": "Thermal Strongest Upper Limit Cycles",
6784    "PublicDescription": "Counts the number of cycles when thermal conditions are the upper limit on frequency.  This is related to the THERMAL_THROTTLE CYCLES_ABOVE_TEMP event, which always counts cycles when we are above the thermal temperature.  This event (STRONGEST_UPPER_LIMIT) is sampled at the output of the algorithm that determines the actual frequency, while THERMAL_THROTTLE looks at the input.",
6785    "Counter": "0,1,2,3",
6786    "MSRValue": "0x00",
6787    "ELLC": "0",
6788    "Filter": "na",
6789    "ExtSel": "0",
6790    "EVENT_STATUS": "0"
6791  },
6792  {
6793    "Unit": "PCU",
6794    "EventCode": "0x6",
6795    "UMask": "0x0",
6796    "EventName": "UNC_P_FREQ_MAX_OS_CYCLES",
6797    "BriefDescription": "OS Strongest Upper Limit Cycles",
6798    "PublicDescription": "Counts the number of cycles when the OS is the upper limit on frequency.",
6799    "Counter": "0,1,2,3",
6800    "MSRValue": "0x00",
6801    "ELLC": "0",
6802    "Filter": "na",
6803    "ExtSel": "0",
6804    "EVENT_STATUS": "0"
6805  },
6806  {
6807    "Unit": "PCU",
6808    "EventCode": "0x5",
6809    "UMask": "0x0",
6810    "EventName": "UNC_P_FREQ_MAX_POWER_CYCLES",
6811    "BriefDescription": "Power Strongest Upper Limit Cycles",
6812    "PublicDescription": "Counts the number of cycles when power is the upper limit on frequency.",
6813    "Counter": "0,1,2,3",
6814    "MSRValue": "0x00",
6815    "ELLC": "0",
6816    "Filter": "na",
6817    "ExtSel": "0",
6818    "EVENT_STATUS": "0"
6819  },
6820  {
6821    "Unit": "PCU",
6822    "EventCode": "0x73",
6823    "UMask": "0x0",
6824    "EventName": "UNC_P_FREQ_MIN_IO_P_CYCLES",
6825    "BriefDescription": "IO P Limit Strongest Lower Limit Cycles",
6826    "PublicDescription": "Counts the number of cycles when IO P Limit is preventing us from dropping the frequency lower.  This algorithm monitors the needs to the IO subsystem on both local and remote sockets and will maintain a frequency high enough to maintain good IO BW.  This is necessary for when all the IA cores on a socket are idle but a user still would like to maintain high IO Bandwidth.",
6827    "Counter": "0,1,2,3",
6828    "MSRValue": "0x00",
6829    "ELLC": "0",
6830    "Filter": "na",
6831    "ExtSel": "0",
6832    "EVENT_STATUS": "0"
6833  },
6834  {
6835    "Unit": "PCU",
6836    "EventCode": "0x74",
6837    "UMask": "0x0",
6838    "EventName": "UNC_P_FREQ_TRANS_CYCLES",
6839    "BriefDescription": "Cycles spent changing Frequency",
6840    "PublicDescription": "Counts the number of cycles when the system is changing frequency.  This can not be filtered by thread ID.  One can also use it with the occupancy counter that monitors number of threads in C0 to estimate the performance impact that frequency transitions had on the system.",
6841    "Counter": "0,1,2,3",
6842    "MSRValue": "0x00",
6843    "ELLC": "0",
6844    "Filter": "na",
6845    "ExtSel": "0",
6846    "EVENT_STATUS": "0"
6847  },
6848  {
6849    "Unit": "PCU",
6850    "EventCode": "0x2F",
6851    "UMask": "0x0",
6852    "EventName": "UNC_P_MEMORY_PHASE_SHEDDING_CYCLES",
6853    "BriefDescription": "Memory Phase Shedding Cycles",
6854    "PublicDescription": "Counts the number of cycles that the PCU has triggered memory phase shedding.  This is a mode that can be run in the iMC physicals that saves power at the expense of additional latency.",
6855    "Counter": "0,1,2,3",
6856    "MSRValue": "0x00",
6857    "ELLC": "0",
6858    "Filter": "na",
6859    "ExtSel": "0",
6860    "EVENT_STATUS": "0"
6861  },
6862  {
6863    "Unit": "PCU",
6864    "EventCode": "0x2A",
6865    "UMask": "0x0",
6866    "EventName": "UNC_P_PKG_RESIDENCY_C0_CYCLES",
6867    "BriefDescription": "Package C State Residency - C0",
6868    "PublicDescription": "Counts the number of cycles when the package was in C0.  This event can be used in conjunction with edge detect to count C0 entrances (or exits using invert).  Residency events do not include transition times.",
6869    "Counter": "0,1,2,3",
6870    "MSRValue": "0x00",
6871    "ELLC": "0",
6872    "Filter": "na",
6873    "ExtSel": "0",
6874    "EVENT_STATUS": "0"
6875  },
6876  {
6877    "Unit": "PCU",
6878    "EventCode": "0x2B",
6879    "UMask": "0x0",
6880    "EventName": "UNC_P_PKG_RESIDENCY_C2E_CYCLES",
6881    "BriefDescription": "Package C State Residency - C2E",
6882    "PublicDescription": "Counts the number of cycles when the package was in C2E.  This event can be used in conjunction with edge detect to count C2E entrances (or exits using invert).  Residency events do not include transition times.",
6883    "Counter": "0,1,2,3",
6884    "MSRValue": "0x00",
6885    "ELLC": "0",
6886    "Filter": "na",
6887    "ExtSel": "0",
6888    "EVENT_STATUS": "0"
6889  },
6890  {
6891    "Unit": "PCU",
6892    "EventCode": "0x2C",
6893    "UMask": "0x0",
6894    "EventName": "UNC_P_PKG_RESIDENCY_C3_CYCLES",
6895    "BriefDescription": "Package C State Residency - C3",
6896    "PublicDescription": "Counts the number of cycles when the package was in C3.  This event can be used in conjunction with edge detect to count C3 entrances (or exits using invert).  Residency events do not include transition times.",
6897    "Counter": "0,1,2,3",
6898    "MSRValue": "0x00",
6899    "ELLC": "0",
6900    "Filter": "na",
6901    "ExtSel": "0",
6902    "EVENT_STATUS": "0"
6903  },
6904  {
6905    "Unit": "PCU",
6906    "EventCode": "0x2D",
6907    "UMask": "0x0",
6908    "EventName": "UNC_P_PKG_RESIDENCY_C6_CYCLES",
6909    "BriefDescription": "Package C State Residency - C6",
6910    "PublicDescription": "Counts the number of cycles when the package was in C6.  This event can be used in conjunction with edge detect to count C6 entrances (or exits using invert).  Residency events do not include transition times.",
6911    "Counter": "0,1,2,3",
6912    "MSRValue": "0x00",
6913    "ELLC": "0",
6914    "Filter": "na",
6915    "ExtSel": "0",
6916    "EVENT_STATUS": "0"
6917  },
6918  {
6919    "Unit": "PCU",
6920    "EventCode": "0x2E",
6921    "UMask": "0x0",
6922    "EventName": "UNC_P_PKG_RESIDENCY_C7_CYCLES",
6923    "BriefDescription": "Package C7 State Residency",
6924    "PublicDescription": "Counts the number of cycles when the package was in C7.  This event can be used in conjunction with edge detect to count C7 entrances (or exits using invert).  Residency events do not include transition times.",
6925    "Counter": "0,1,2,3",
6926    "MSRValue": "0x00",
6927    "ELLC": "0",
6928    "Filter": "na",
6929    "ExtSel": "0",
6930    "EVENT_STATUS": "0"
6931  },
6932  {
6933    "Unit": "PCU",
6934    "EventCode": "0x80",
6935    "UMask": "0x40",
6936    "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C0",
6937    "BriefDescription": "Number of cores in C-State; C0 and C1",
6938    "PublicDescription": "This is an occupancy event that tracks the number of cores that are in the chosen C-State.  It can be used by itself to get the average number of cores in that C-state with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.",
6939    "Counter": "0,1,2,3",
6940    "MSRValue": "0x00",
6941    "ELLC": "0",
6942    "Filter": "na",
6943    "ExtSel": "0",
6944    "EVENT_STATUS": "0"
6945  },
6946  {
6947    "Unit": "PCU",
6948    "EventCode": "0x80",
6949    "UMask": "0x80",
6950    "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C3",
6951    "BriefDescription": "Number of cores in C-State; C3",
6952    "PublicDescription": "This is an occupancy event that tracks the number of cores that are in the chosen C-State.  It can be used by itself to get the average number of cores in that C-state with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.",
6953    "Counter": "0,1,2,3",
6954    "MSRValue": "0x00",
6955    "ELLC": "0",
6956    "Filter": "na",
6957    "ExtSel": "0",
6958    "EVENT_STATUS": "0"
6959  },
6960  {
6961    "Unit": "PCU",
6962    "EventCode": "0x80",
6963    "UMask": "0xC0",
6964    "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C6",
6965    "BriefDescription": "Number of cores in C-State; C6 and C7",
6966    "PublicDescription": "This is an occupancy event that tracks the number of cores that are in the chosen C-State.  It can be used by itself to get the average number of cores in that C-state with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.",
6967    "Counter": "0,1,2,3",
6968    "MSRValue": "0x00",
6969    "ELLC": "0",
6970    "Filter": "na",
6971    "ExtSel": "0",
6972    "EVENT_STATUS": "0"
6973  },
6974  {
6975    "Unit": "PCU",
6976    "EventCode": "0xA",
6977    "UMask": "0x0",
6978    "EventName": "UNC_P_PROCHOT_EXTERNAL_CYCLES",
6979    "BriefDescription": "External Prochot",
6980    "PublicDescription": "Counts the number of cycles that we are in external PROCHOT mode.  This mode is triggered when a sensor off the die determines that something off-die (like DRAM) is too hot and must throttle to avoid damaging the chip.",
6981    "Counter": "0,1,2,3",
6982    "MSRValue": "0x00",
6983    "ELLC": "0",
6984    "Filter": "na",
6985    "ExtSel": "0",
6986    "EVENT_STATUS": "0"
6987  },
6988  {
6989    "Unit": "PCU",
6990    "EventCode": "0x9",
6991    "UMask": "0x0",
6992    "EventName": "UNC_P_PROCHOT_INTERNAL_CYCLES",
6993    "BriefDescription": "Internal Prochot",
6994    "PublicDescription": "Counts the number of cycles that we are in Interal PROCHOT mode.  This mode is triggered when a sensor on the die determines that we are too hot and must throttle to avoid damaging the chip.",
6995    "Counter": "0,1,2,3",
6996    "MSRValue": "0x00",
6997    "ELLC": "0",
6998    "Filter": "na",
6999    "ExtSel": "0",
7000    "EVENT_STATUS": "0"
7001  },
7002  {
7003    "Unit": "PCU",
7004    "EventCode": "0x72",
7005    "UMask": "0x0",
7006    "EventName": "UNC_P_TOTAL_TRANSITION_CYCLES",
7007    "BriefDescription": "Total Core C State Transition Cycles",
7008    "PublicDescription": "Number of cycles spent performing core C state transitions across all cores.",
7009    "Counter": "0,1,2,3",
7010    "MSRValue": "0x00",
7011    "ELLC": "0",
7012    "Filter": "na",
7013    "ExtSel": "0",
7014    "EVENT_STATUS": "0"
7015  },
7016  {
7017    "Unit": "PCU",
7018    "EventCode": "0x79",
7019    "UMask": "0x00",
7020    "EventName": "UNC_P_UFS_TRANSITIONS_NO_CHANGE",
7021    "BriefDescription": "tbd",
7022    "PublicDescription": "Ring GV with same final and initial frequency",
7023    "Counter": "0,1,2,3",
7024    "MSRValue": "0x00",
7025    "ELLC": "0",
7026    "Filter": "na",
7027    "ExtSel": "0",
7028    "EVENT_STATUS": "0"
7029  },
7030  {
7031    "Unit": "PCU",
7032    "EventCode": "0x42",
7033    "UMask": "0x0",
7034    "EventName": "UNC_P_VR_HOT_CYCLES",
7035    "BriefDescription": "VR Hot",
7036    "PublicDescription": "tbd",
7037    "Counter": "0,1,2,3",
7038    "MSRValue": "0x00",
7039    "ELLC": "0",
7040    "Filter": "na",
7041    "ExtSel": "0",
7042    "EVENT_STATUS": "0"
7043  },
7044  {
7045    "Unit": "PCU",
7046    "EventCode": "0x4E",
7047    "UMask": "0x0",
7048    "EventName": "UNC_P_PKG_RESIDENCY_C1E_CYCLES",
7049    "BriefDescription": "Package C State Residency - C1E",
7050    "PublicDescription": "Counts the number of cycles when the package was in C1E.  This event can be used in conjunction with edge detect to count C1E entrances (or exits using invert).  Residency events do not include transition times.",
7051    "Counter": "0,1,2,3",
7052    "MSRValue": "0x00",
7053    "ELLC": "0",
7054    "Filter": "na",
7055    "ExtSel": "0",
7056    "EVENT_STATUS": "0"
7057  },
7058  {
7059    "Unit": "PCU",
7060    "EventCode": "0x79",
7061    "UMask": "0x0",
7062    "EventName": "UNC_P_UFS_TRANSITIONS_RING_GV",
7063    "BriefDescription": "tbd",
7064    "PublicDescription": "Ring GV with same final and initial frequency",
7065    "Counter": "0,1,2,3",
7066    "MSRValue": "0x00",
7067    "ELLC": "0",
7068    "Filter": "na",
7069    "ExtSel": "0",
7070    "EVENT_STATUS": "0"
7071  },
7072  {
7073    "Unit": "QPI LL",
7074    "EventCode": "0x14",
7075    "UMask": "0x0",
7076    "EventName": "UNC_Q_CLOCKTICKS",
7077    "BriefDescription": "Number of qfclks",
7078    "PublicDescription": "Counts the number of clocks in the QPI LL.  This clock runs at 1/4th the GT/s speed of the QPI link.  For example, a 4GT/s link will have qfclk or 1GHz.  HSX does not support dynamic link speeds, so this frequency is fixed.",
7079    "Counter": "0,1,2,3",
7080    "MSRValue": "0x00",
7081    "ELLC": "0",
7082    "Filter": "na",
7083    "ExtSel": "0",
7084    "EVENT_STATUS": "0"
7085  },
7086  {
7087    "Unit": "QPI LL",
7088    "EventCode": "0x38",
7089    "UMask": "0x0",
7090    "EventName": "UNC_Q_CTO_COUNT",
7091    "BriefDescription": "Count of CTO Events",
7092    "PublicDescription": "Counts the number of CTO (cluster trigger outs) events that were asserted across the two slots.  If both slots trigger in a given cycle, the event will increment by 2.  You can use edge detect to count the number of cases when both events triggered.",
7093    "Counter": "0,1,2,3",
7094    "MSRValue": "0x00",
7095    "ELLC": "0",
7096    "Filter": "QPIMask0[17:0],QPIMatch0[17:0],QPIMask1[19:16],QPIMatch1[19:16]",
7097    "ExtSel": "1",
7098    "EVENT_STATUS": "0"
7099  },
7100  {
7101    "Unit": "QPI LL",
7102    "EventCode": "0x13",
7103    "UMask": "0x1",
7104    "EventName": "UNC_Q_DIRECT2CORE.SUCCESS_RBT_HIT",
7105    "BriefDescription": "Direct 2 Core Spawning; Spawn Success",
7106    "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on.  There are 4 mutually exlusive filters.  Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases.  Note that this does not count packets that are not candidates for Direct2Core.  The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn was successful.  There were sufficient credits, the RBT valid bit was set and there was an RBT tag match.  The message was marked to spawn direct2core.",
7107    "Counter": "0,1,2,3",
7108    "MSRValue": "0x00",
7109    "ELLC": "0",
7110    "Filter": "na",
7111    "ExtSel": "0",
7112    "EVENT_STATUS": "0"
7113  },
7114  {
7115    "Unit": "QPI LL",
7116    "EventCode": "0x13",
7117    "UMask": "0x2",
7118    "EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS",
7119    "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egress Credits",
7120    "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on.  There are 4 mutually exlusive filters.  Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases.  Note that this does not count packets that are not candidates for Direct2Core.  The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because there were not enough Egress credits.  Had there been enough credits, the spawn would have worked as the RBT bit was set and the RBT tag matched.",
7121    "Counter": "0,1,2,3",
7122    "MSRValue": "0x00",
7123    "ELLC": "0",
7124    "Filter": "na",
7125    "ExtSel": "0",
7126    "EVENT_STATUS": "0"
7127  },
7128  {
7129    "Unit": "QPI LL",
7130    "EventCode": "0x13",
7131    "UMask": "0x4",
7132    "EventName": "UNC_Q_DIRECT2CORE.FAILURE_RBT_HIT",
7133    "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - RBT Invalid",
7134    "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on.  There are 4 mutually exlusive filters.  Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases.  Note that this does not count packets that are not candidates for Direct2Core.  The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because the route-back table (RBT) specified that the transaction should not trigger a direct2core tranaction.  This is common for IO transactions.  There were enough Egress credits and the RBT tag matched but the valid bit was not set.",
7135    "Counter": "0,1,2,3",
7136    "MSRValue":