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README.illumos

1#
2# This file and its contents are supplied under the terms of the
3# Common Development and Distribution License ("CDDL"), version 1.0.
4# You may only use this file in accordance with the terms of version
5# 1.0 of the CDDL.
6#
7# A full copy of the text of the CDDL should have accompanied this
8# source.  A copy of the CDDL is also available via the Internet at
9# http://www.illumos.org/license/CDDL.
10#
11
12#
13# Copyright (c) 2018, Joyent, Inc.
14#
15
16Performance Monitoring Data
17
18These data files describe the performance monitoring events that
19different CPUs support. This data is provided by Intel at
20https://download.01.org/perfmon/. This data is transformed into manual
21pages and C files that are used to implement the kernel performance
22monitoring interfaces. Currently a subset of the events are supported.
23For more information, see the cpcgen tool.
24

readme.txt

1---------------------	
2This package contains performance monitoring event lists for Intel processors, as well as a mapping file	
3to help match event lists to processor Family/Model/Stepping codes. 	
4---------------------	
5	
6The event lists are available in 2 formats:	
7	Tab delimited (.tsv)
8	Json (.json)
9	
10Event lists are created per microarchitecture, and each has a version. Versions are listed in the event list	
11name as well as the header for each file. For some microarchitectures, up to three different event lists will	
12be available. These event lists correspond to the types of events that can be collected: 	
13	
14core - Contains events counted from within a logical processor core.		
15offcore - Contains matrix events counted from the core, but measuring responses that come from offcore.	
16	
17The event list filename indicates which type of list it contains, and follows this format:	
18<microarchitecture-codename>_<core/offcore>_<version>
19
20New version releases will be announced in the mail list perfmon-announce@lists.01.org 	
21	
22Different microarchitectures provide different performance monitoring capabilities, so field names and categories	
23of events may vary.	
24	
25---------------------
26Licensing Information
27---------------------
28The following files are distributed under the terms of the 3-clause BSD license:
29
30- Mapfile.csv
31- All .tsv files
32- All .json files
33
34Copyright (C) 2018 Intel Corporation
35
36Redistribution and use in source and binary forms, with or without modification,
37are permitted provided that the following conditions are met:
38
391. Redistributions of source code must retain the above copyright notice,
40   this list of conditions and the following disclaimer.
412. Redistributions in binary form must reproduce the above copyright notice,
42   this list of conditions and the following disclaimer in the documentation
43   and/or other materials provided with the distribution.
443. Neither the name of the copyright holder nor the names of its contributors
45   may be used to endorse or promote products derived from this software
46   without specific prior written permission.
47
48THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
49AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
50THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
51ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS
52BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
53OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
54OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
55OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
56WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
57OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
58EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
59
60SPDX-License-Identifier: BSD-3-Clause
61
62
63Other files in this package are ALL RIGHTS RESERVED.
64
65
66---------------------	
67Event List Field Defitions: 	
68---------------------	
69Below is a list of the fields/headers in the event files and a description of how SW tools should	
70interpret these values. A particular event list from this package may not contain all the fields described	
71below. For more detailed information of the Performance monitoring unit please refer to chapters 18 and 19	
72of Intel� 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide, Part 2.	
73	
74http://www.intel.com/content/www/us/en/processors/architectures-software-developer-manuals.html	
75	
76	
77----EventCode----	
78This field maps to the Event Select field in the IA32_PERFEVTSELx[7:0]MSRs. The set of values for this field	
79is defined architecturally. Each value corresponds to an event logic unit and should be used with a unit 	
80mask value to obtain an architectural performance event.	
81	
82----UMask----	
83This field maps to the Unit Mask filed in the IA32_PERFEVTSELx[15:8] MSRs. It further qualifies the event logic 
84unit selected in the event select field to detect a specific micro-architectural condition.
85 	
86----EventName----	
87It is a string of characters to identify the programming of an event.	
88	
89----BriefDescription----	
90This field contains a description of what is being counted by a particular event.	
91	
92----PublicDescription----	
93In some cases, this field will contain a more detailed description of what is counted by an event.	
94	
95----Counter----	
96This field lists the fixed (PERF_FIXED_CTRX) or programmable (IA32_PMCX) counters that can be used to count the event.	
97	
98----CounterHTOff----	
99This field lists the counters where this event can be sampled when Intel� Hyper-Threading Technology (Intel� HT Technology) is 	
100disabled. When Intel� HT Technology is disabled, some processor cores gain access to the programmable counters of the second 	
101thread, making a total of eight programmable counters available. The additional counters will be numbered 4,5,6,7. Fixed counter 	
102behavior remains unaffected.
103
104----PEBScounters----	
105This field is only relevant to PEBS events. It lists the counters where the event can be sampled when it is programmed as a PEBS event.
106	
107----SampleAfterValue----	
108Sample After Value (SAV) is the value that can be pre-loaded into the counter registers to set the point at which they will overflow. 	
109To make the counter overflow after N occurrences of the event, it should be loaded with (0xFF..FF � N) or �(N-1). On overflow a 	
110hardware interrupt is generated through the Local APIC and additional architectural state can be collected in the interrupt handler. 	
111This is useful in event-based sampling. This field gives a recommended default overflow value, which may be adjusted based on 	
112workload or tool preference. 	
113	
114----MSRIndex----	
115Additional MSRs may be required for programming certain events. This field gives the address of such MSRS. 	
116Potential values are: 	
1170x3F6: MSR_PEBS_LD_LAT - used to configure the Load Latency Perforamnce Monitoring Facility 	
1180x1A6/0x1A7: MSR_OFFCORE_RSP_X - used to configure the offcore response events	
119	
120----MSRValue----	
121When an MSRIndex is used (indicated by the MSRIndex column), this field will contain the value that needs to be loaded into the	
122register whose address is given in MSRIndex column. For example, in the case of the load latency events, MSRValue defines the	
123latency threshold value to write into the MSR defined in MSRIndex (0x3F6).	
124	
125----CollectPEBSRecord----
126Applies to processors that support both precise and non-precise events in Processor Event Based Sampling, such as Goldmont.	
1270: The event cannot be programmed to collect a PEBS record.  
1281: The event may be programmed to collect a PEBS record, but caution is advised.  
129For instance, PEBS collection of this event may consume limited PEBS resources whereas interrupt-based sampling may be sufficient for the usage model.  
1302: The event may programmed to collect a PEBS record, and due to the nature of the event, PEBS collection may be preferred.  For instance, 
131PEBS collection of Goldmont�s HW_INTERUPTS.RECIEVED event is recommended because the hardware interrupt being counted may lead to the masking of
132interrupts which would interfere with interrupt-based sampling.
133
134	
135	----TakenAlone----	
136This field is set for an event which can only be sampled or counted by itself, meaning that when this event is being collected,	
137the remaining programmable counters are not available to count any other events.	
138	
139----CounterMask----	
140This field maps to the Counter Mask (CMASK) field in IA32_PERFEVTSELx[31:24] MSR.
141	
142----Invert----	
143This field corresponds to the Invert Counter Mask (INV) field in IA32_PERFEVTSELx[23] MSR.
144		
145----AnyThread----	
146This field corresponds to the Any Thread (ANY) bit of IA32_PERFEVTSELx[21] MSR. 
147	
148----EdgeDetect----	
149This field corresponds to the Edge Detect (E) bit of IA32_PERFEVTSELx[18] MSR.
150 	
151----PEBS----	
152A '0' in this field means that the event cannot collect a PEBS record with a Precise IP.  A '1' in this field means that the event is a 
153precise event and can be programmed in one of two ways � as a regular event or as a PEBS event. And a '2' in this field means 
154that the event can only be programmed as a PEBS event. 	
155	
156----PRECISE_STORE----	
157A '1' in this field means the event uses the Precise Store feature and Bit 3 and bit 63 in IA32_PEBS_ENABLE MSR must be set 
158to enable IA32_PMC3 as a PEBS counter and enable the precise store facility respectively. Processors based on SandyBridge and 
159IvyBridge micro-architecture offer a precise store capability that provides a means to profile store memory references in 
160the system.	
161	
162----DATA_LA---- 	
163A '1' in this field means that when the event is configured as a PEBS event, the Data Linear Address facility is supported. 
164The Data Linear Address facility is a new feature added to Haswell as a replacement or extension of the precise store facility 
165in SNB.	
166
167----L1_HIT_INDICATION----	
168A '1' in this field means that when the event is configured as a PEBS event, the DCU hit field of the PEBS record is set to 1 
169when the store hits in the L1 cache and 0 when it misses.	
170	
171----Errata----	
172This field lists the known bugs that apply to the events. For the latest, up to date errata refer to	
173	
174Haswell:	
175http://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/4th-gen-core-family-mobile-specification-update.pdf	
176	
177IvyBridge:	
178https://www-ssl.intel.com/content/dam/www/public/us/en/documents/specification-updates/3rd-gen-core-desktop-specification-update.pdf	
179	
180SandyBridge:	
181https://www-ssl.intel.com/content/dam/www/public/us/en/documents/specification-updates/2nd-gen-core-family-mobile-specification-update.pdf	
182
183----offcore----
184This field is specific to the json format. There is only 1 file for core and offcore events in this format. This field is set to 1 for offcore events
185and 0 for core events. 
186	
187---------------------	
188For additional information:	
189---------------------	
190Intel Platform Monitoring Homepage	
191http://software.intel.com/en-us/platform-monitoring/	
192  	
193http://software.intel.com/en-us/articles/performance-monitoring-on-intel-xeon-processor-e5-family	
194 	
195http://software.intel.com/en-us/articles/monitoring-integrated-memory-controller-requests-in-the-2nd-3rd-and-4th-generation-intel
196
197http://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/4th-gen-core-family-desktop-specification-update.pdf	
198	
199---------------------	
200For questions:	
201---------------------
202email perfmon-discuss@lists.01.org	
203
204---------------------
205Notices:
206---------------------
207INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, 
208TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH 
209PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF 
210INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY 
211PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. 
212
213A "Mission Critical Application" is any application in which failure of the Intel Product could result, directly or indirectly, in 
214personal injury or death. SHOULD YOU PURCHASE OR USE INTEL'S PRODUCTS FOR ANY SUCH MISSION CRITICAL APPLICATION, YOU SHALL INDEMNIFY 
215AND HOLD INTEL AND ITS SUBSIDIARIES, SUBCONTRACTORS AND AFFILIATES, AND THE DIRECTORS, OFFICERS, AND EMPLOYEES OF EACH, HARMLESS AGAINST 
216ALL CLAIMS COSTS, DAMAGES, AND EXPENSES AND REASONABLE ATTORNEYS' FEES ARISING OUT OF, DIRECTLY OR INDIRECTLY, ANY CLAIM OF PRODUCT 
217LIABILITY, PERSONAL INJURY, OR DEATH ARISING IN ANY WAY OUT OF SUCH MISSION CRITICAL APPLICATION, WHETHER OR NOT INTEL OR ITS SUBCONTRACTOR 
218WAS NEGLIGENT IN THE DESIGN, MANUFACTURE, OR WARNING OF THE INTEL PRODUCT OR ANY OF ITS PARTS. 
219
220Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or 
221characteristics of any features or instructions marked "reserved" or "undefined". Intel reserves these for future definition and shall have 
222no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The information here is subject to 
223change without notice. Do not finalize a design with this information. 
224
225The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from 
226published specifications. Current characterized errata are available on request. 
227
228Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. 
229
230Copies of documents which have an order number and are referenced in this document, or other Intel literature, may be obtained by calling 
2311-800-548-4725, or go to: http://www.intel.com/design/literature.htm
232
233Copyright � 2014 Intel Corporation. All rights reserved.
234