/illumos-gate/usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/ |
H A D | hw_debug.h | 97 val = REG_RD(pdev, MISC_REG_CHIP_NUM); \ 98 chip_rev = REG_RD(pdev, MISC_REG_CHIP_REV); \ 99 chip_metal = REG_RD(pdev, MISC_REG_CHIP_METAL); \ 120 val = REG_RD(pdev, offset); \ 132 val = REG_RD(pdev, offset + i*(inc)); \ 144 val1 = REG_RD(pdev, offset1); \ 145 val2 = REG_RD(pdev, offset2); \ 170 val = REG_RD(pdev, offset);\ 182 val1 = REG_RD(pdev, offset + i*(inc)); \ 206 val = REG_RD(pdev, offset2 + i*4); \ [all …]
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H A D | lm_er.c | 91 val = REG_RD(pdev, MISC_REG_AEU_GENERAL_MASK); in lm_er_disable_close_the_gate() 112 val = REG_RD(pdev, IGU_REG_BLOCK_CONFIGURATION); in lm_er_set_234_gates() 224 sr_cnt = REG_RD(pdev, PXP2_REG_RD_SR_CNT); in lm_er_empty_tetris_buffer() 225 blk_cnt = REG_RD(pdev, PXP2_REG_RD_BLK_CNT); in lm_er_empty_tetris_buffer() 228 pgl_exp_rom2 = REG_RD(pdev, PXP2_REG_PGL_EXP_ROM2); in lm_er_empty_tetris_buffer() 229 pgl_b_reg_tags = REG_RD(pdev, PGLUE_B_REG_TAGS_63_32); in lm_er_empty_tetris_buffer() 269 pend_bits = REG_RD(pdev, IGU_REG_PENDING_BITS_STATUS); in lm_er_poll_igu_vq() 480 val = REG_RD(pdev, MISC_REG_AEU_ENABLE2_NIG_0); in lm_er_config_close_the_g8() 484 val = REG_RD(pdev, MISC_REG_AEU_ENABLE2_PXP_0); in lm_er_config_close_the_g8() 489 val = REG_RD(pdev, MISC_REG_AEU_ENABLE4_NIG_0); in lm_er_config_close_the_g8() [all …]
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H A D | lm_hw_access.c | 392 val = REG_RD(pdev,MISC_REG_SPIO_INT) ; in lm_setup_fan_failure_detection() 397 val = REG_RD(pdev,MISC_REG_SPIO_EVENT_EN) ; in lm_setup_fan_failure_detection() 491 reg_val = REG_RD(pdev, MISC_REG_GPIO); in lm_gpio_read() 616 gpio_reg = REG_RD(pdev, MISC_REG_GPIO); in lm_gpio_mult_write() 691 gpio_reg = REG_RD(pdev, MISC_REG_GPIO_INT); in lm_gpio_int_write() 737 reg_val = REG_RD(pdev, MISC_REG_SPIO); in lm_spio_read() 780 reg_val = REG_RD(pdev, MISC_REG_SPIO); in lm_spio_read() 820 reg_val = REG_RD(pdev, MISC_REG_SPIO); in lm_spio_write() 1193 val = REG_RD(pdev, 0x2004); in lm_is_57710A0_dbg_intr() 1645 val=REG_RD(pdev,reg_offset); in reg_wait_verify_val() [all …]
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H A D | lm_nvram.c | 72 val=REG_RD(pdev, MCP_REG_MCPR_NVM_SW_ARB); in acquire_nvram_lock() 123 val=REG_RD(pdev, MCP_REG_MCPR_NVM_SW_ARB); in release_nvram_lock() 170 val=REG_RD(pdev, MCP_REG_MCPR_NVM_COMMAND); 212 val=REG_RD(pdev, MCP_REG_MCPR_NVM_COMMAND); 237 val=REG_RD(pdev, MCP_REG_MCPR_NVM_ACCESS_ENABLE); in enable_nvram_access() 259 val=REG_RD(pdev, MCP_REG_MCPR_NVM_ACCESS_ENABLE); in disable_nvram_access() 311 val=REG_RD(pdev, MCP_REG_MCPR_NVM_COMMAND); in nvram_read_dword() 314 val=REG_RD(pdev, MCP_REG_MCPR_NVM_READ); in nvram_read_dword() 384 val=REG_RD(pdev, MCP_REG_MCPR_NVM_COMMAND); in nvram_write_dword()
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H A D | lm_hw_init_reset.c | 534 tmp = REG_RD(pdev,CFC_REG_WEAK_ENABLE_PF); in lm_cleanup_after_flr() 537 tmp = REG_RD(pdev,PBF_REG_DISABLE_PF); in lm_cleanup_after_flr() 540 tmp = REG_RD(pdev,IGU_REG_PCI_PF_MSI_EN); in lm_cleanup_after_flr() 543 tmp = REG_RD(pdev,IGU_REG_PCI_PF_MSIX_EN); in lm_cleanup_after_flr() 627 val = REG_RD(pdev,MISC_REG_RESET_REG_1) ; in rbc_reset_workaround() 2643 val = REG_RD(pdev, MISC_REG_SPIO_EVENT_EN); in init_aeu_port() 2648 val=REG_RD(pdev, offset ); in init_aeu_port() 2659 val = REG_RD(pdev, offset); in init_aeu_port() 3839 val=REG_RD(pdev,PRS_REG_NUM_OF_PACKETS); in prs_brb_mem_setup() 3902 val=REG_RD(pdev,PRS_REG_NUM_OF_PACKETS); in prs_brb_mem_setup() [all …]
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H A D | bnxe_hw_debug.c | 70 val = REG_RD(pdev, MISC_REG_CHIP_NUM); in lm_disable_timer() 77 val = REG_RD(pdev,TM_REG_EN_LINEAR0_TIMER); in lm_disable_timer() 87 val = REG_RD(pdev,TM_REG_LIN0_SCAN_ON); in lm_disable_timer() 97 val = REG_RD(pdev,TM_REG_EN_LINEAR1_TIMER); in lm_disable_timer() 128 val = REG_RD(pdev, MISC_REG_CHIP_NUM); in lm_enable_timer() 147 val = REG_RD(pdev,DORQ_REG_DQ_FILL_LVLF); in lm_get_doorbell_info() 151 val = REG_RD(pdev,DORQ_REG_DQ_FILL_LVL_MAX); in lm_get_doorbell_info() 155 val = REG_RD(pdev,DORQ_REG_DB_DIS_CNTR0); in lm_get_doorbell_info() 192 chip_num = REG_RD(pdev,MISC_REG_CHIP_NUM); in _vq_hoq() 217 rd0 = REG_RD(pdev,PXP2_REG_RQ_HOQ_RAM_DATA_RD_0); in _vq_hoq() [all …]
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H A D | lm_hw_attn.c | 596 val = REG_RD(pdev, MISC_REG_GRC_TIMEOUT_ATTN); in lm_latch_attn_everest_processing() 801 nig_status_port = REG_RD(pdev, NIG_REG_STATUS_INTERRUPT_PORT0); in lm_nig_processing() 900 mask_val=REG_RD(pdev, port_reg_name); in lm_handle_assertion_processing() 994 val = REG_RD(pdev, IGU_REG_ATTENTION_ACK_BITS); in lm_handle_assertion_processing() 1011 val = REG_RD(pdev,CFC_REG_CFC_INT_STS); in lm_cfc_attn_everest_processing() 1023 valc = REG_RD(pdev,CFC_REG_CFC_INT_STS_CLR); in lm_cfc_attn_everest_processing() 1028 u32_t val = REG_RD(pdev,PXP_REG_PXP_INT_STS_0); in lm_pxp_attn_everest_processing() 1063 val = REG_RD(pdev, offset ); in lm_spio5_attn_everest_processing() 1792 val=REG_RD(pdev,DORQ_REG_DORQ_INT_STS); in lm_dq_attn_everest_processing() 1810 valc = REG_RD(pdev,DORQ_REG_DORQ_INT_STS_CLR); in lm_dq_attn_everest_processing() [all …]
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H A D | lm_mcp.c | 145 shmem = REG_RD(pdev, MISC_REG_SHARED_MEM_ADDR); in lm_reset_mcp_prep() 171 shmem = REG_RD(pdev, MISC_REG_SHARED_MEM_ADDR); in lm_reset_mcp_comp() 191 val = REG_RD(pdev, shmem + validity_offset); in lm_reset_mcp_comp() 241 val = REG_RD(pdev, MISC_REG_DRIVER_CONTROL_15); in lm_reset_mcp() 285 val_rd = REG_RD(pdev, GRCBASE_MCP + 0x9c); in acquire_split_alr() 320 val= REG_RD(pdev, GRCBASE_MCP + 0x9c); in release_split_alr() 1106 reg = REG_RD(pdev, offset); in lm_mcp_check() 1110 if( REG_RD(pdev, offset) != reg ) in lm_mcp_check()
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H A D | lm_power.c | 376 val = REG_RD(pdev, emac.emac_mode); in set_d0_power_state() 381 val = REG_RD(pdev, rpm.rpm_config); in set_d0_power_state() 449 pf0_pcie_status_control = REG_RD(pdev, pcicfg_device_control_offset); in lm_pcie_state_save_for_d3() 463 u32_t own_pcie_status_control = REG_RD(pdev, pcicfg_device_control_offset); in lm_pcie_state_restore_for_d0() 474 pf0_pcie_status_control = REG_RD(pdev, pcicfg_device_control_offset); in lm_pcie_state_restore_for_d0()
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H A D | lm_sb.c | 104 intr_status = REG_RD(pdev, INTR_BLK_SIMD_ADDR_WOMASK(pdev)); in lm_get_interrupt_status_wo_mask() 120 intr_status = REG_RD(pdev, INTR_BLK_SIMD_ADDR_WMASK(pdev)); in lm_get_interrupt_status() 679 …REG_RD(pdev, (PORT_ID(pdev) ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : MISC_REG_AEU_ENABLE1_FUNC_0_OUT_… in init_status_blocks() 681 …REG_RD(pdev, (PORT_ID(pdev) ? MISC_REG_AEU_ENABLE2_FUNC_1_OUT_0 : MISC_REG_AEU_ENABLE2_FUNC_0_OUT_… in init_status_blocks() 984 while (!(REG_RD(pdev, igu_addr_ack) & sb_bit) && --cnt) in lm_int_igu_sb_cleanup() 989 if (!(REG_RD(pdev, igu_addr_ack) & sb_bit)) in lm_int_igu_sb_cleanup() 1005 while ((REG_RD(pdev, igu_addr_ack) & sb_bit) && --cnt) in lm_int_igu_sb_cleanup() 1010 if ((REG_RD(pdev, igu_addr_ack) & sb_bit)) in lm_int_igu_sb_cleanup() 1201 val=REG_RD(pdev, IGU_REG_PF_CONFIGURATION); in lm_enable_igu_int() 1276 val=REG_RD(pdev, reg_name); in lm_disable_hc_int() [all …]
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H A D | lm_devinfo.c | 219 val = REG_RD(pdev, BAR_ME_REGISTER); in lm_get_function_num() 632 val=REG_RD(PFDEV(pdev),MISC_REG_CHIP_NUM); in lm_get_chip_id_and_mode() 636 val=REG_RD(PFDEV(pdev),MISC_REG_CHIP_TYPE); in lm_get_chip_id_and_mode() 654 val=REG_RD(PFDEV(pdev),MISC_REG_CHIP_REV); in lm_get_chip_id_and_mode() 675 val=REG_RD(PFDEV(pdev),MISC_REG_CHIP_METAL); in lm_get_chip_id_and_mode() 677 val=REG_RD(PFDEV(pdev),MISC_REG_BOND_ID); in lm_get_chip_id_and_mode() 681 val=REG_RD(PFDEV(pdev),MISC_REG_CHIP_TEST_REG); in lm_get_chip_id_and_mode() 695 val = REG_RD(PFDEV(pdev), MISC_REG_PORT4MODE_EN); in lm_get_chip_id_and_mode() 1048 u32_t val = REG_RD(pdev,MCP_REG_MCPR_NVM_CFG4); in lm_get_nvm_info() 1789 val = REG_RD(pdev,MISC_REG_SHARED_MEM_ADDR); in lm_get_shmem_base_addr() [all …]
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H A D | lm_phy.c | 77 return REG_RD(cb, reg_addr); in elink_cb_reg_read() 255 tmp=REG_RD(pdev,emac_base+EMAC_REG_EMAC_MDIO_MODE); in lm_mwrite() 274 tmp=REG_RD(pdev,emac_base+EMAC_REG_EMAC_MDIO_COMM); in lm_mwrite() 295 tmp=REG_RD(pdev,emac_base+EMAC_REG_EMAC_MDIO_MODE); in lm_mwrite() 329 val=REG_RD(pdev,emac_base+EMAC_REG_EMAC_MDIO_MODE); in lm_mread() 347 val=REG_RD(pdev,emac_base+EMAC_REG_EMAC_MDIO_COMM); in lm_mread() 372 val=REG_RD(pdev,emac_base+EMAC_REG_EMAC_MDIO_MODE); in lm_mread()
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/illumos-gate/usr/src/uts/common/io/bnx/570x/driver/common/lmdev/ |
H A D | bnx_hw_nvram.c | 265 REG_RD(pdev, misc.misc_cfg, &val); in enable_nvram_write() 314 REG_RD(pdev, misc.misc_cfg, &val); in disable_nvram_write() 640 REG_RD(pdev, nvm.nvm_cfg4, &val); in find_atmel_size() 646 REG_RD(pdev, nvm.nvm_cfg3, &orig); in find_atmel_size() 661 REG_RD(pdev, nvm.nvm_read, &val); in find_atmel_size() 699 REG_RD(pdev, nvm.nvm_cfg4, &val); in find_stm_size() 716 REG_RD(pdev, nvm.nvm_cfg1, &val); in find_stm_size() 742 REG_RD(pdev, nvm.nvm_read, &val); in find_stm_size() 775 REG_RD(pdev, nvm.nvm_cfg1, &idx); in find_stm_size() 798 REG_RD(pdev, nvm.nvm_cfg4, &val); in find_nvram_size() [all …]
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H A D | bnx_hw_misc.c | 72 REG_RD(pdev, pci_config.pcicfg_reg_window, ret); in lm_reg_rd_ind() 142 REG_RD(pdev, context.ctx_ctx_ctrl, &val); in lm_ctx_wr() 197 REG_RD(pdev, context.ctx_ctx_ctrl, &val); in lm_ctx_rd() 209 REG_RD(pdev, context.ctx_ctx_data, &val); in lm_ctx_rd() 214 REG_RD(pdev, context.ctx_data, &val); in lm_ctx_rd() 238 REG_RD(pdev, pci_config.pcicfg_int_ack_cmd, &val); in lm_disable_int() 274 REG_RD(pdev, pci_config.pcicfg_int_ack_cmd, &val); in lm_enable_int() 280 REG_RD(pdev, hc.hc_config, &val); in lm_enable_int() 356 REG_RD(pdev, pci_config.pcicfg_reg_window, buf_ptr); in lm_reg_rd_blk_ind()
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H A D | bnx_hw_reset.c | 547 REG_RD(pdev, misc.misc_id, &val); in lm_chip_reset() 657 REG_RD(pdev, mq.mq_config, &val); in lm_chip_reset() 668 REG_RD(pdev, pci.pci_swap_diag0, &val); in lm_chip_reset() 1536 REG_RD(pdev, in init_5709_for_msix() 1592 REG_RD(pdev, in init_5709_for_msix() 1635 REG_RD(pdev, hc.hc_config, &val); in init_hc() 2045 REG_RD(pdev, tdma.tdma_config, &val); in lm_reset_setup() 2052 REG_RD(pdev, pci.pci_config_2, &val); in lm_reset_setup() 2133 REG_RD(pdev, mq.mq_config, &val); in lm_reset_setup() 2178 REG_RD(pdev, tbdr.tbdr_config, &val); in lm_reset_setup() [all …]
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H A D | bnx_hw_phy.c | 50 REG_RD(pdev, emac.emac_mdio_mode, &tmp); in lm_mwrite() 71 REG_RD(pdev, emac.emac_mdio_comm, &tmp); in lm_mwrite() 92 REG_RD(pdev, emac.emac_mdio_mode, &tmp); in lm_mwrite() 123 REG_RD(pdev, emac.emac_mdio_mode, &val); in lm_mread() 630 REG_RD(pdev, emac.emac_mode, &val); in init_utp() 1185 REG_RD(pdev, emac.emac_mode, &val); in init_5708_serdes() 1553 REG_RD(pdev, emac.emac_mode, &val); in init_5709_serdes() 1768 REG_RD(pdev, emac.emac_mode, &val); in init_5706_serdes() 2681 REG_RD(pdev, emac.emac_rx_mode, &val); in set_mac_flow_control() 2692 REG_RD(pdev, emac.emac_tx_mode, &val); in set_mac_flow_control() [all …]
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H A D | bnx_lm_main.c | 757 REG_RD(pdev, pci.pci_swap_diag0, &val); in lm_get_dev_info() 2378 REG_RD(pdev, emac.emac_rx_mode, &rx_mode); in lm_set_rx_mask() 2719 REG_RD(pdev, hc.hc_command, ®_val); in lm_get_stats() 3980 REG_RD(pdev, emac.emac_mode, &val); in set_d0_power_state() 3986 REG_RD(pdev, rpm.rpm_config, &val); in set_d0_power_state() 4014 REG_RD(pdev, emac.emac_mode, &val); in set_d3_power_state() 4066 REG_RD(pdev, rpm.rpm_config, &val); in set_d3_power_state() 4170 REG_RD(pdev, misc.misc_spio, &val); in set_d3_power_state() 4307 REG_RD(pdev, emac.emac_status, &val); in lm_get_interrupt_status() 4865 REG_RD(pdev, rlup.rlup_rss_config, &val); in lm_enable_rss() [all …]
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H A D | lm5706.h | 1338 #define REG_RD(_pdev, _name, _ret) \ macro 1403 #define REG_RD(_pdev, _name, _ret) \ macro 1489 #define REG_RD(_pdev, _name, _ret) \ macro 1552 #define REG_RD(_pdev, _name, _ret) \ macro
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/illumos-gate/usr/src/uts/common/io/bnxe/577xx/common/ |
H A D | bnxe_clc.c | 162 REG_RD(cb, shmem2_base + \ 348 u32 val = REG_RD(cb, reg); in elink_bits_en() 357 u32 val = REG_RD(cb, reg); in elink_bits_dis() 381 REG_RD(cb, params->lfa_base + in elink_check_lfa() 466 REG_RD(cb, params->lfa_base + in elink_check_lfa() 6759 latch_status = REG_RD(cb, in elink_rearm_latch_signal() 7510 val = REG_RD(cb, addr) + 1; in elink_chng_link_count() 13047 rx = REG_RD(cb, shmem_base + in elink_populate_preemphasis() 13112 phy_addr = REG_RD(cb, in elink_populate_int_phy() 13205 phy_addr = REG_RD(cb, in elink_populate_int_phy() [all …]
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/illumos-gate/usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/fw/ |
H A D | bnxe_fw_funcs.c | 43 u32_t curr_cos = REG_RD(pdev, QM_REG_QVOQIDX_0 + q_num * 4); in ecore_map_q_cos() 70 reg_bit_map = REG_RD(pdev, reg_addr); in ecore_map_q_cos() 75 reg_bit_map = REG_RD(pdev, reg_addr); in ecore_map_q_cos() 82 reg_bit_map = REG_RD(pdev, reg_addr); in ecore_map_q_cos()
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/illumos-gate/usr/src/uts/common/io/bnxe/577xx/drivers/common/ecore/ |
H A D | ecore_init.h | 203 reg_val = REG_RD(pdev, mcp_attn_ctl_regs[i].addr); in ecore_set_mcp_parity() 268 reg_val = REG_RD(pdev, ecore_blocks_parity_data[i]. in ecore_clear_blocks_parity() 280 reg_val = REG_RD(pdev, MISC_REG_AEU_AFTER_INVERT_4_MCP); in ecore_clear_blocks_parity()
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H A D | ecore_init_ops.h | 272 REG_RD(pdev, addr); in ecore_init_block() 540 val = REG_RD(pdev, write_arb_addr[i].l); in ecore_init_pxp_arb() 544 val = REG_RD(pdev, write_arb_addr[i].add); in ecore_init_pxp_arb() 548 val = REG_RD(pdev, write_arb_addr[i].ubound); in ecore_init_pxp_arb() 609 val = REG_RD(pdev, PCIE_REG_PCIER_TL_HDR_FC_ST); in ecore_init_pxp_arb()
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/illumos-gate/usr/src/uts/common/io/bnx/ |
H A D | bnx_mm.h | 37 REG_RD((_lmdevice), pci_config.pcicfg_int_ack_cmd, &dummy); \
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H A D | bnxint.c | 200 REG_RD(lmdevice, pci_config.pcicfg_misc_status, &value32); in bnx_intr_1lvl()
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/illumos-gate/usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/vf/channel_vf/ |
H A D | lm_vf.c | 2947 val=REG_RD(PFDEV(pdev), IGU_REG_VF_CONFIGURATION); in lm_pf_enable_vf_igu_int() 2991 val = REG_RD(PFDEV(pdev), IGU_REG_VF_CONFIGURATION); in lm_pf_disable_vf_igu_int() 3342 tq_occ = tq_to_free = REG_RD(PFDEV(pdev), pbf_reg_pN_tq_occupancy); in lm_pf_cleanup_vf_after_flr() 3348 tq_occ = REG_RD(PFDEV(pdev), pbf_reg_pN_tq_occupancy); in lm_pf_cleanup_vf_after_flr() 3393 credit_last = credit_start = REG_RD(PFDEV(pdev), pbf_reg_pN_credit); in lm_pf_cleanup_vf_after_flr() 3394 init_crd = REG_RD(PFDEV(pdev), pbf_reg_pN_init_crd); in lm_pf_cleanup_vf_after_flr() 3402 credit_last = REG_RD(PFDEV(pdev), pbf_reg_pN_credit); in lm_pf_cleanup_vf_after_flr() 3711 while (!(REG_RD(pdev, igu_addr_ack) & sb_bit) && --cnt) in lm_pf_int_vf_igu_sb_cleanup() 3716 if (!(REG_RD(pdev, igu_addr_ack) & sb_bit)) in lm_pf_int_vf_igu_sb_cleanup() 3732 while ((REG_RD(pdev, igu_addr_ack) & sb_bit) && --cnt) in lm_pf_int_vf_igu_sb_cleanup() [all …]
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