Lines Matching refs:we
38 # good scaling. Thus, we'll need to accommodate a number of
42 # managed via a single Unified PF and we want to accommodate scaling up
43 # to 8 CPUs, we would want:
216 # NCPUS = 16 # CPUs we want to support scalably
280 # NVI_HYPERV = 16 # VMs we want to support
296 # The sum of all the MSI-X resources above is 74 MSI-X Vectors but we'll round
307 # associated with it. Thus, the MSI-X Vector allocations we give to the
308 # UnifiedPF aren't inherited by any Virtual Functions. As a result we can
309 # provision many more Virtual Functions than we can if the UnifiedPF were
316 # For PF0-3 we assign 8 vectors each for NIC Ingress Queues of the associated
319 # For PF4, the Unified PF, we give it an MSI-X Table Size as outlined above.
321 # For PF5-6 we assign enough MSI-X Vectors to support FCoE and iSCSI
325 # Functions, we give the UnifiedPF and the PF0-3 Physical Functions
332 # readability, we use the number we actually mean ...
346 # With the above we can get 17 VFs/PF0-3 (limited by 336 MPS TCAM entries)
347 # but we'll lower that to 16 to make our total 64 and a nice power of 2 ...
352 # For those OSes which manage different ports on different PFs, we need
354 # on PF0-3. The below assumes that we're only doing NIC with NCPUS "Queue
409 # Thus we need to provide a large number of resources here. For Egress
410 # Queues we need to account for both TX Queues as well as Free List Queues
479 # and we never load PF0..3 and PF4 concurrently
505 # For Virtual functions, we only allow NIC functionality and we only allow