17c478bd9Sstevel@tonic-gate /* 27c478bd9Sstevel@tonic-gate * CDDL HEADER START 37c478bd9Sstevel@tonic-gate * 47c478bd9Sstevel@tonic-gate * The contents of this file are subject to the terms of the 5ee88d2b9Skchow * Common Development and Distribution License (the "License"). 6ee88d2b9Skchow * You may not use this file except in compliance with the License. 77c478bd9Sstevel@tonic-gate * 87c478bd9Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 97c478bd9Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 107c478bd9Sstevel@tonic-gate * See the License for the specific language governing permissions 117c478bd9Sstevel@tonic-gate * and limitations under the License. 127c478bd9Sstevel@tonic-gate * 137c478bd9Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 147c478bd9Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 157c478bd9Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 167c478bd9Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 177c478bd9Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 187c478bd9Sstevel@tonic-gate * 197c478bd9Sstevel@tonic-gate * CDDL HEADER END 207c478bd9Sstevel@tonic-gate */ 217c478bd9Sstevel@tonic-gate /* 22fb2f18f8Sesaxe * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 237c478bd9Sstevel@tonic-gate * Use is subject to license terms. 247c478bd9Sstevel@tonic-gate */ 257c478bd9Sstevel@tonic-gate 267c478bd9Sstevel@tonic-gate #ifndef _SYS_X86_ARCHEXT_H 277c478bd9Sstevel@tonic-gate #define _SYS_X86_ARCHEXT_H 287c478bd9Sstevel@tonic-gate 297c478bd9Sstevel@tonic-gate #pragma ident "%Z%%M% %I% %E% SMI" 307c478bd9Sstevel@tonic-gate 317c478bd9Sstevel@tonic-gate #if !defined(_ASM) 327c478bd9Sstevel@tonic-gate #include <sys/regset.h> 337c478bd9Sstevel@tonic-gate #include <sys/processor.h> 347c478bd9Sstevel@tonic-gate #include <vm/seg_enum.h> 357c478bd9Sstevel@tonic-gate #include <vm/page.h> 367c478bd9Sstevel@tonic-gate #endif /* _ASM */ 377c478bd9Sstevel@tonic-gate 387c478bd9Sstevel@tonic-gate #ifdef __cplusplus 397c478bd9Sstevel@tonic-gate extern "C" { 407c478bd9Sstevel@tonic-gate #endif 417c478bd9Sstevel@tonic-gate 427c478bd9Sstevel@tonic-gate /* 437c478bd9Sstevel@tonic-gate * cpuid instruction feature flags in %edx (standard function 1) 447c478bd9Sstevel@tonic-gate */ 457c478bd9Sstevel@tonic-gate 467c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_FPU 0x00000001 /* x87 fpu present */ 477c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_VME 0x00000002 /* virtual-8086 extension */ 487c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_DE 0x00000004 /* debugging extensions */ 497c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_PSE 0x00000008 /* page size extension */ 507c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_TSC 0x00000010 /* time stamp counter */ 517c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_MSR 0x00000020 /* rdmsr and wrmsr */ 527c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_PAE 0x00000040 /* physical addr extension */ 537c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_MCE 0x00000080 /* machine check exception */ 547c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_CX8 0x00000100 /* cmpxchg8b instruction */ 557c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_APIC 0x00000200 /* local APIC */ 567c478bd9Sstevel@tonic-gate /* 0x400 - reserved */ 577c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_SEP 0x00000800 /* sysenter and sysexit */ 587c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_MTRR 0x00001000 /* memory type range reg */ 597c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_PGE 0x00002000 /* page global enable */ 607c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_MCA 0x00004000 /* machine check arch */ 617c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_CMOV 0x00008000 /* conditional move insns */ 627c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_PAT 0x00010000 /* page attribute table */ 637c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */ 647c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_PSN 0x00040000 /* processor serial number */ 657c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_CLFSH 0x00080000 /* clflush instruction */ 667c478bd9Sstevel@tonic-gate /* 0x100000 - reserved */ 677c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_DS 0x00200000 /* debug store exists */ 687c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_ACPI 0x00400000 /* monitoring + clock ctrl */ 697c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_MMX 0x00800000 /* MMX instructions */ 707c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_FXSR 0x01000000 /* fxsave and fxrstor */ 717c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_SSE 0x02000000 /* streaming SIMD extensions */ 727c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_SSE2 0x04000000 /* SSE extensions */ 737c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_SS 0x08000000 /* self-snoop */ 747c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_HTT 0x10000000 /* Hyper Thread Technology */ 757c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_TM 0x20000000 /* thermal monitoring */ 76ae115bc7Smrj #define CPUID_INTC_EDX_IA64 0x40000000 /* Itanium emulating IA32 */ 777c478bd9Sstevel@tonic-gate #define CPUID_INTC_EDX_PBE 0x80000000 /* Pending Break Enable */ 787c478bd9Sstevel@tonic-gate 79ae115bc7Smrj #define FMT_CPUID_INTC_EDX \ 80ae115bc7Smrj "\20" \ 81ae115bc7Smrj "\40pbe\37ia64\36tm\35htt\34ss\33sse2\32sse\31fxsr" \ 82ae115bc7Smrj "\30mmx\27acpi\26ds\24clfsh\23psn\22pse36\21pat" \ 83ae115bc7Smrj "\20cmov\17mca\16pge\15mtrr\14sep\12apic\11cx8" \ 847c478bd9Sstevel@tonic-gate "\10mce\7pae\6msr\5tsc\4pse\3de\2vme\1fpu" 857c478bd9Sstevel@tonic-gate 867c478bd9Sstevel@tonic-gate /* 877c478bd9Sstevel@tonic-gate * cpuid instruction feature flags in %ecx (standard function 1) 887c478bd9Sstevel@tonic-gate */ 897c478bd9Sstevel@tonic-gate 907c478bd9Sstevel@tonic-gate #define CPUID_INTC_ECX_SSE3 0x00000001 /* Yet more SSE extensions */ 917c478bd9Sstevel@tonic-gate /* 0x00000002 - reserved */ 927c478bd9Sstevel@tonic-gate /* 0x00000004 - reserved */ 937c478bd9Sstevel@tonic-gate #define CPUID_INTC_ECX_MON 0x00000008 /* MONITOR/MWAIT */ 947c478bd9Sstevel@tonic-gate #define CPUID_INTC_ECX_DSCPL 0x00000010 /* CPL-qualified debug store */ 95ae115bc7Smrj #define CPUID_INTC_ECX_VMX 0x00000020 /* Hardware VM extensions */ 96ae115bc7Smrj #define CPUID_INTC_ECX_SMX 0x00000040 /* Secure mode extensions */ 977c478bd9Sstevel@tonic-gate #define CPUID_INTC_ECX_EST 0x00000080 /* enhanced SpeedStep */ 987c478bd9Sstevel@tonic-gate #define CPUID_INTC_ECX_TM2 0x00000100 /* thermal monitoring */ 99ae115bc7Smrj #define CPUID_INTC_ECX_SSSE3 0x00000200 /* Supplemental SSE3 insns */ 1007c478bd9Sstevel@tonic-gate #define CPUID_INTC_ECX_CID 0x00000400 /* L1 context ID */ 1017c478bd9Sstevel@tonic-gate /* 0x00000800 - reserved */ 1027c478bd9Sstevel@tonic-gate /* 0x00001000 - reserved */ 103ae115bc7Smrj #define CPUID_INTC_ECX_CX16 0x00002000 /* cmpxchg16 */ 104ae115bc7Smrj #define CPUID_INTC_ECX_ETPRD 0x00004000 /* extended task pri messages */ 105ae115bc7Smrj /* 0x00008000 - reserved */ 106ae115bc7Smrj /* 0x00010000 - reserved */ 107ae115bc7Smrj /* 0x00020000 - reserved */ 108ae115bc7Smrj #define CPUID_INTC_ECX_DCA 0x00040000 /* direct cache access */ 109*d0f8ff6eSkk #define CPUID_INTC_ECX_SSE4_1 0x00080000 /* SSE4.1 insns */ 110*d0f8ff6eSkk #define CPUID_INTC_ECX_SSE4_2 0x00100000 /* SSE4.2 insns */ 111f8801251Skk #define CPUID_INTC_ECX_POPCNT 0x00800000 /* POPCNT insn */ 112ae115bc7Smrj 113ae115bc7Smrj #define FMT_CPUID_INTC_ECX \ 114ae115bc7Smrj "\20" \ 115*d0f8ff6eSkk "\30popcnt\25sse4.2\24sse4.1\23dca" \ 116ae115bc7Smrj "\20\17etprd\16cx16\13cid\12ssse3\11tm2" \ 117ae115bc7Smrj "\10est\7smx\6vmx\5dscpl\4mon\1sse3" 1187c478bd9Sstevel@tonic-gate 1197c478bd9Sstevel@tonic-gate /* 1207c478bd9Sstevel@tonic-gate * cpuid instruction feature flags in %edx (extended function 0x80000001) 1217c478bd9Sstevel@tonic-gate */ 1227c478bd9Sstevel@tonic-gate 1237c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_FPU 0x00000001 /* x87 fpu present */ 1247c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_VME 0x00000002 /* virtual-8086 extension */ 1257c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_DE 0x00000004 /* debugging extensions */ 1267c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_PSE 0x00000008 /* page size extensions */ 1277c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_TSC 0x00000010 /* time stamp counter */ 1287c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_MSR 0x00000020 /* rdmsr and wrmsr */ 1297c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_PAE 0x00000040 /* physical addr extension */ 1307c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_MCE 0x00000080 /* machine check exception */ 1317c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_CX8 0x00000100 /* cmpxchg8b instruction */ 1327c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_APIC 0x00000200 /* local APIC */ 1337c478bd9Sstevel@tonic-gate /* 0x00000400 - sysc on K6m6 */ 1347c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_SYSC 0x00000800 /* AMD: syscall and sysret */ 1357c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_MTRR 0x00001000 /* memory type and range reg */ 1367c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_PGE 0x00002000 /* page global enable */ 1377c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_MCA 0x00004000 /* machine check arch */ 1387c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_CMOV 0x00008000 /* conditional move insns */ 139ae115bc7Smrj #define CPUID_AMD_EDX_PAT 0x00010000 /* K7: page attribute table */ 140ae115bc7Smrj #define CPUID_AMD_EDX_FCMOV 0x00010000 /* FCMOVcc etc. */ 1417c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */ 1427c478bd9Sstevel@tonic-gate /* 0x00040000 - reserved */ 1437c478bd9Sstevel@tonic-gate /* 0x00080000 - reserved */ 1447c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_NX 0x00100000 /* AMD: no-execute page prot */ 1457c478bd9Sstevel@tonic-gate /* 0x00200000 - reserved */ 1467c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_MMXamd 0x00400000 /* AMD: MMX extensions */ 1477c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_MMX 0x00800000 /* MMX instructions */ 1487c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_FXSR 0x01000000 /* fxsave and fxrstor */ 149ae115bc7Smrj #define CPUID_AMD_EDX_FFXSR 0x02000000 /* fast fxsave/fxrstor */ 1507c478bd9Sstevel@tonic-gate /* 0x04000000 - reserved */ 151ae115bc7Smrj #define CPUID_AMD_EDX_TSCP 0x08000000 /* rdtscp instruction */ 1527c478bd9Sstevel@tonic-gate /* 0x10000000 - reserved */ 1537c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_LM 0x20000000 /* AMD: long mode */ 1547c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_3DNowx 0x40000000 /* AMD: extensions to 3DNow! */ 1557c478bd9Sstevel@tonic-gate #define CPUID_AMD_EDX_3DNow 0x80000000 /* AMD: 3DNow! instructions */ 1567c478bd9Sstevel@tonic-gate 1577c478bd9Sstevel@tonic-gate #define FMT_CPUID_AMD_EDX \ 1587c478bd9Sstevel@tonic-gate "\20" \ 159ae115bc7Smrj "\40a3d\37a3d+\36lm\34tscp\32ffxsr\31fxsr" \ 1607c478bd9Sstevel@tonic-gate "\30mmx\27mmxext\25nx\22pse\21pat" \ 1617c478bd9Sstevel@tonic-gate "\20cmov\17mca\16pge\15mtrr\14syscall\12apic\11cx8" \ 1627c478bd9Sstevel@tonic-gate "\10mce\7pae\6msr\5tsc\4pse\3de\2vme\1fpu" 1637c478bd9Sstevel@tonic-gate 164ae115bc7Smrj #define CPUID_AMD_ECX_AHF64 0x00000001 /* LAHF and SAHF in long mode */ 165ae115bc7Smrj #define CPUID_AMD_ECX_CMP_LGCY 0x00000002 /* AMD: multicore chip */ 166ae115bc7Smrj #define CPUID_AMD_ECX_SVM 0x00000004 /* AMD: secure VM */ 167ae115bc7Smrj #define CPUID_AMD_ECX_EAS 0x00000008 /* extended apic space */ 168ae115bc7Smrj #define CPUID_AMD_ECX_CR8D 0x00000010 /* AMD: 32-bit mov %cr8 */ 169f8801251Skk #define CPUID_AMD_ECX_LZCNT 0x00000020 /* AMD: LZCNT insn */ 170f8801251Skk #define CPUID_AMD_ECX_SSE4A 0x00000040 /* AMD: SSE4A insns */ 1717c478bd9Sstevel@tonic-gate 1727c478bd9Sstevel@tonic-gate #define FMT_CPUID_AMD_ECX \ 1737c478bd9Sstevel@tonic-gate "\20" \ 174f8801251Skk "\7sse4a\6lzcnt\5cr8d\3svm\2lcmplgcy\1ahf64" 175ae115bc7Smrj 176ae115bc7Smrj /* 177ae115bc7Smrj * Intel now seems to have claimed part of the "extended" function 178ae115bc7Smrj * space that we previously for non-Intel implementors to use. 179ae115bc7Smrj * More excitingly still, they've claimed bit 20 to mean LAHF/SAHF 180ae115bc7Smrj * is available in long mode i.e. what AMD indicate using bit 0. 181ae115bc7Smrj * On the other hand, everything else is labelled as reserved. 182ae115bc7Smrj */ 183ae115bc7Smrj #define CPUID_INTC_ECX_AHF64 0x00100000 /* LAHF and SAHF in long mode */ 184ae115bc7Smrj 1857c478bd9Sstevel@tonic-gate 1867c478bd9Sstevel@tonic-gate #define P5_MCHADDR 0x0 1877c478bd9Sstevel@tonic-gate #define P5_CESR 0x11 1887c478bd9Sstevel@tonic-gate #define P5_CTR0 0x12 1897c478bd9Sstevel@tonic-gate #define P5_CTR1 0x13 1907c478bd9Sstevel@tonic-gate 1917c478bd9Sstevel@tonic-gate #define K5_MCHADDR 0x0 1927c478bd9Sstevel@tonic-gate #define K5_MCHTYPE 0x01 1937c478bd9Sstevel@tonic-gate #define K5_TSC 0x10 1947c478bd9Sstevel@tonic-gate #define K5_TR12 0x12 1957c478bd9Sstevel@tonic-gate 1961d03c31eSjohnlev #define REG_PAT 0x277 1971d03c31eSjohnlev 1987c478bd9Sstevel@tonic-gate #define REG_MC0_CTL 0x400 1997c478bd9Sstevel@tonic-gate #define REG_MC5_MISC 0x417 2007c478bd9Sstevel@tonic-gate #define REG_PERFCTR0 0xc1 2017c478bd9Sstevel@tonic-gate #define REG_PERFCTR1 0xc2 2027c478bd9Sstevel@tonic-gate 2037c478bd9Sstevel@tonic-gate #define REG_PERFEVNT0 0x186 2047c478bd9Sstevel@tonic-gate #define REG_PERFEVNT1 0x187 2057c478bd9Sstevel@tonic-gate 2067c478bd9Sstevel@tonic-gate #define REG_TSC 0x10 /* timestamp counter */ 2077c478bd9Sstevel@tonic-gate #define REG_APIC_BASE_MSR 0x1b 2087c478bd9Sstevel@tonic-gate 2097c478bd9Sstevel@tonic-gate #define MSR_DEBUGCTL 0x1d9 2107c478bd9Sstevel@tonic-gate 2117c478bd9Sstevel@tonic-gate #define DEBUGCTL_LBR 0x01 2127c478bd9Sstevel@tonic-gate #define DEBUGCTL_BTF 0x02 2137c478bd9Sstevel@tonic-gate 2147c478bd9Sstevel@tonic-gate /* Intel P6, AMD */ 2157c478bd9Sstevel@tonic-gate #define MSR_LBR_FROM 0x1db 2167c478bd9Sstevel@tonic-gate #define MSR_LBR_TO 0x1dc 2177c478bd9Sstevel@tonic-gate #define MSR_LEX_FROM 0x1dd 2187c478bd9Sstevel@tonic-gate #define MSR_LEX_TO 0x1de 2197c478bd9Sstevel@tonic-gate 2207c478bd9Sstevel@tonic-gate /* Intel P4 (pre-Prescott, non P4 M) */ 2217c478bd9Sstevel@tonic-gate #define MSR_P4_LBSTK_TOS 0x1da 2227c478bd9Sstevel@tonic-gate #define MSR_P4_LBSTK_0 0x1db 2237c478bd9Sstevel@tonic-gate #define MSR_P4_LBSTK_1 0x1dc 2247c478bd9Sstevel@tonic-gate #define MSR_P4_LBSTK_2 0x1dd 2257c478bd9Sstevel@tonic-gate #define MSR_P4_LBSTK_3 0x1de 2267c478bd9Sstevel@tonic-gate 2277c478bd9Sstevel@tonic-gate /* Intel Pentium M */ 2287c478bd9Sstevel@tonic-gate #define MSR_P6M_LBSTK_TOS 0x1c9 2297c478bd9Sstevel@tonic-gate #define MSR_P6M_LBSTK_0 0x040 2307c478bd9Sstevel@tonic-gate #define MSR_P6M_LBSTK_1 0x041 2317c478bd9Sstevel@tonic-gate #define MSR_P6M_LBSTK_2 0x042 2327c478bd9Sstevel@tonic-gate #define MSR_P6M_LBSTK_3 0x043 2337c478bd9Sstevel@tonic-gate #define MSR_P6M_LBSTK_4 0x044 2347c478bd9Sstevel@tonic-gate #define MSR_P6M_LBSTK_5 0x045 2357c478bd9Sstevel@tonic-gate #define MSR_P6M_LBSTK_6 0x046 2367c478bd9Sstevel@tonic-gate #define MSR_P6M_LBSTK_7 0x047 2377c478bd9Sstevel@tonic-gate 2387c478bd9Sstevel@tonic-gate /* Intel P4 (Prescott) */ 2397c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TOS 0x1da 2407c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_0 0x680 2417c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_1 0x681 2427c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_2 0x682 2437c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_3 0x683 2447c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_4 0x684 2457c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_5 0x685 2467c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_6 0x686 2477c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_7 0x687 2487c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_8 0x688 2497c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_9 0x689 2507c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_10 0x68a 2517c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_11 0x68b 2527c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_12 0x68c 2537c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_13 0x68d 2547c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_14 0x68e 2557c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_FROM_15 0x68f 2567c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_0 0x6c0 2577c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_1 0x6c1 2587c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_2 0x6c2 2597c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_3 0x6c3 2607c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_4 0x6c4 2617c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_5 0x6c5 2627c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_6 0x6c6 2637c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_7 0x6c7 2647c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_8 0x6c8 2657c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_9 0x6c9 2667c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_10 0x6ca 2677c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_11 0x6cb 2687c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_12 0x6cc 2697c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_13 0x6cd 2707c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_14 0x6ce 2717c478bd9Sstevel@tonic-gate #define MSR_PRP4_LBSTK_TO_15 0x6cf 2727c478bd9Sstevel@tonic-gate 2737c478bd9Sstevel@tonic-gate #define MCI_CTL_VALUE 0xffffffff 2747c478bd9Sstevel@tonic-gate 2757c478bd9Sstevel@tonic-gate #define MTRR_TYPE_UC 0 2767c478bd9Sstevel@tonic-gate #define MTRR_TYPE_WC 1 2777c478bd9Sstevel@tonic-gate #define MTRR_TYPE_WT 4 2787c478bd9Sstevel@tonic-gate #define MTRR_TYPE_WP 5 2797c478bd9Sstevel@tonic-gate #define MTRR_TYPE_WB 6 2801d03c31eSjohnlev #define MTRR_TYPE_UC_ 7 2817c478bd9Sstevel@tonic-gate 2827c478bd9Sstevel@tonic-gate /* 2831d03c31eSjohnlev * For Solaris we set up the page attritubute table in the following way: 2841d03c31eSjohnlev * PAT0 Write-Back 2857c478bd9Sstevel@tonic-gate * PAT1 Write-Through 2861d03c31eSjohnlev * PAT2 Unchacheable- 2877c478bd9Sstevel@tonic-gate * PAT3 Uncacheable 2881d03c31eSjohnlev * PAT4 Write-Back 2891d03c31eSjohnlev * PAT5 Write-Through 2907c478bd9Sstevel@tonic-gate * PAT6 Write-Combine 2917c478bd9Sstevel@tonic-gate * PAT7 Uncacheable 2921d03c31eSjohnlev * The only difference from h/w default is entry 6. 2937c478bd9Sstevel@tonic-gate */ 2941d03c31eSjohnlev #define PAT_DEFAULT_ATTRIBUTE \ 2951d03c31eSjohnlev ((uint64_t)MTRR_TYPE_WB | \ 2961d03c31eSjohnlev ((uint64_t)MTRR_TYPE_WT << 8) | \ 2971d03c31eSjohnlev ((uint64_t)MTRR_TYPE_UC_ << 16) | \ 2981d03c31eSjohnlev ((uint64_t)MTRR_TYPE_UC << 24) | \ 2991d03c31eSjohnlev ((uint64_t)MTRR_TYPE_WB << 32) | \ 3001d03c31eSjohnlev ((uint64_t)MTRR_TYPE_WT << 40) | \ 3011d03c31eSjohnlev ((uint64_t)MTRR_TYPE_WC << 48) | \ 3021d03c31eSjohnlev ((uint64_t)MTRR_TYPE_UC << 56)) 3037c478bd9Sstevel@tonic-gate 3047c478bd9Sstevel@tonic-gate #define X86_LARGEPAGE 0x00000001 3057c478bd9Sstevel@tonic-gate #define X86_TSC 0x00000002 3067c478bd9Sstevel@tonic-gate #define X86_MSR 0x00000004 3077c478bd9Sstevel@tonic-gate #define X86_MTRR 0x00000008 3087c478bd9Sstevel@tonic-gate #define X86_PGE 0x00000010 309ae115bc7Smrj #define X86_DE 0x00000020 3107c478bd9Sstevel@tonic-gate #define X86_CMOV 0x00000040 3117c478bd9Sstevel@tonic-gate #define X86_MMX 0x00000080 3127c478bd9Sstevel@tonic-gate #define X86_MCA 0x00000100 3137c478bd9Sstevel@tonic-gate #define X86_PAE 0x00000200 3147c478bd9Sstevel@tonic-gate #define X86_CX8 0x00000400 3157c478bd9Sstevel@tonic-gate #define X86_PAT 0x00000800 3167c478bd9Sstevel@tonic-gate #define X86_SEP 0x00001000 3177c478bd9Sstevel@tonic-gate #define X86_SSE 0x00002000 3187c478bd9Sstevel@tonic-gate #define X86_SSE2 0x00004000 3197c478bd9Sstevel@tonic-gate #define X86_HTT 0x00008000 3207c478bd9Sstevel@tonic-gate #define X86_ASYSC 0x00010000 3217c478bd9Sstevel@tonic-gate #define X86_NX 0x00020000 3227c478bd9Sstevel@tonic-gate #define X86_SSE3 0x00040000 3237c478bd9Sstevel@tonic-gate #define X86_CX16 0x00080000 3247c478bd9Sstevel@tonic-gate #define X86_CMP 0x00100000 325ae115bc7Smrj #define X86_TSCP 0x00200000 326f98fbcecSbholler #define X86_MWAIT 0x00400000 327f8801251Skk #define X86_SSE4A 0x00800000 3287c478bd9Sstevel@tonic-gate #define X86_CPUID 0x01000000 329*d0f8ff6eSkk #define X86_SSSE3 0x02000000 330*d0f8ff6eSkk #define X86_SSE4_1 0x04000000 331*d0f8ff6eSkk #define X86_SSE4_2 0x08000000 3327c478bd9Sstevel@tonic-gate 3337c478bd9Sstevel@tonic-gate #define FMT_X86_FEATURE \ 3347c478bd9Sstevel@tonic-gate "\20" \ 335*d0f8ff6eSkk "\34sse4_2\33sse4_1\32ssse3\31cpuid" \ 336f8801251Skk "\30sse4a\27mwait\26tscp\25cmp\24cx16\23sse3\22nx\21asysc"\ 3377c478bd9Sstevel@tonic-gate "\20htt\17sse2\16sse\15sep\14pat\13cx8\12pae\11mca" \ 338ae115bc7Smrj "\10mmx\7cmov\6de\5pge\4mtrr\3msr\2tsc\1lgpg" 3397c478bd9Sstevel@tonic-gate 3407c478bd9Sstevel@tonic-gate /* 3417c478bd9Sstevel@tonic-gate * x86_type is a legacy concept; this is supplanted 3427c478bd9Sstevel@tonic-gate * for most purposes by x86_feature; modern CPUs 3437c478bd9Sstevel@tonic-gate * should be X86_TYPE_OTHER 3447c478bd9Sstevel@tonic-gate */ 3457c478bd9Sstevel@tonic-gate #define X86_TYPE_OTHER 0 3467c478bd9Sstevel@tonic-gate #define X86_TYPE_486 1 3477c478bd9Sstevel@tonic-gate #define X86_TYPE_P5 2 3487c478bd9Sstevel@tonic-gate #define X86_TYPE_P6 3 3497c478bd9Sstevel@tonic-gate #define X86_TYPE_CYRIX_486 4 3507c478bd9Sstevel@tonic-gate #define X86_TYPE_CYRIX_6x86L 5 3517c478bd9Sstevel@tonic-gate #define X86_TYPE_CYRIX_6x86 6 3527c478bd9Sstevel@tonic-gate #define X86_TYPE_CYRIX_GXm 7 3537c478bd9Sstevel@tonic-gate #define X86_TYPE_CYRIX_6x86MX 8 3547c478bd9Sstevel@tonic-gate #define X86_TYPE_CYRIX_MediaGX 9 3557c478bd9Sstevel@tonic-gate #define X86_TYPE_CYRIX_MII 10 3567c478bd9Sstevel@tonic-gate #define X86_TYPE_VIA_CYRIX_III 11 3577c478bd9Sstevel@tonic-gate #define X86_TYPE_P4 12 3587c478bd9Sstevel@tonic-gate 3597c478bd9Sstevel@tonic-gate /* 3607c478bd9Sstevel@tonic-gate * x86_vendor allows us to select between 3617c478bd9Sstevel@tonic-gate * implementation features and helps guide 3627c478bd9Sstevel@tonic-gate * the interpretation of the cpuid instruction. 3637c478bd9Sstevel@tonic-gate */ 3647c478bd9Sstevel@tonic-gate #define X86_VENDOR_Intel 0 /* GenuineIntel */ 3657c478bd9Sstevel@tonic-gate #define X86_VENDOR_IntelClone 1 /* (an Intel clone) */ 3667c478bd9Sstevel@tonic-gate #define X86_VENDOR_AMD 2 /* AuthenticAMD */ 3677c478bd9Sstevel@tonic-gate #define X86_VENDOR_Cyrix 3 /* CyrixInstead */ 3687c478bd9Sstevel@tonic-gate #define X86_VENDOR_UMC 4 /* UMC UMC UMC */ 3697c478bd9Sstevel@tonic-gate #define X86_VENDOR_NexGen 5 /* NexGenDriven */ 3707c478bd9Sstevel@tonic-gate #define X86_VENDOR_Centaur 6 /* CentaurHauls */ 3717c478bd9Sstevel@tonic-gate #define X86_VENDOR_Rise 7 /* RiseRiseRise */ 3727c478bd9Sstevel@tonic-gate #define X86_VENDOR_SiS 8 /* SiS SiS SiS */ 3737c478bd9Sstevel@tonic-gate #define X86_VENDOR_TM 9 /* GenuineTMx86 */ 3747c478bd9Sstevel@tonic-gate #define X86_VENDOR_NSC 10 /* Geode by NSC */ 3757c478bd9Sstevel@tonic-gate 3767aec1d6eScindi #define X86_VENDOR_STRLEN 13 /* vendor string max len + \0 */ 3777aec1d6eScindi 3788a40a695Sgavinm /* 3798a40a695Sgavinm * Some vendor/family/model/stepping ranges are commonly grouped under 3808a40a695Sgavinm * a single identifying banner by the vendor. The following encode 3818a40a695Sgavinm * that "revision" in a uint32_t with the 8 most significant bits 3828a40a695Sgavinm * identifying the vendor with X86_VENDOR_*, the next 8 identifying the 3838a40a695Sgavinm * family, and the remaining 16 typically forming a bitmask of revisions 3848a40a695Sgavinm * within that family with more significant bits indicating "later" revisions. 3858a40a695Sgavinm */ 3868a40a695Sgavinm 3878a40a695Sgavinm #define _X86_CHIPREV_VENDOR_MASK 0xff000000u 3888a40a695Sgavinm #define _X86_CHIPREV_VENDOR_SHIFT 24 3898a40a695Sgavinm #define _X86_CHIPREV_FAMILY_MASK 0x00ff0000u 3908a40a695Sgavinm #define _X86_CHIPREV_FAMILY_SHIFT 16 3918a40a695Sgavinm #define _X86_CHIPREV_REV_MASK 0x0000ffffu 3928a40a695Sgavinm 3938a40a695Sgavinm #define _X86_CHIPREV_VENDOR(x) \ 3948a40a695Sgavinm (((x) & _X86_CHIPREV_VENDOR_MASK) >> _X86_CHIPREV_VENDOR_SHIFT) 3958a40a695Sgavinm #define _X86_CHIPREV_FAMILY(x) \ 3968a40a695Sgavinm (((x) & _X86_CHIPREV_FAMILY_MASK) >> _X86_CHIPREV_FAMILY_SHIFT) 3978a40a695Sgavinm #define _X86_CHIPREV_REV(x) \ 3988a40a695Sgavinm ((x) & _X86_CHIPREV_REV_MASK) 3998a40a695Sgavinm 4008a40a695Sgavinm /* True if x matches in vendor and family and if x matches the given rev mask */ 4018a40a695Sgavinm #define X86_CHIPREV_MATCH(x, mask) \ 4028a40a695Sgavinm (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(mask) && \ 4038a40a695Sgavinm _X86_CHIPREV_FAMILY(x) == _X86_CHIPREV_FAMILY(mask) && \ 4048a40a695Sgavinm ((_X86_CHIPREV_REV(x) & _X86_CHIPREV_REV(mask)) != 0)) 4058a40a695Sgavinm 4068a40a695Sgavinm /* True if x matches in vendor and family and rev is at least minx */ 4078a40a695Sgavinm #define X86_CHIPREV_ATLEAST(x, minx) \ 4088a40a695Sgavinm (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(minx) && \ 4098a40a695Sgavinm _X86_CHIPREV_FAMILY(x) == _X86_CHIPREV_FAMILY(minx) && \ 4108a40a695Sgavinm _X86_CHIPREV_REV(x) >= _X86_CHIPREV_REV(minx)) 4118a40a695Sgavinm 4128a40a695Sgavinm #define _X86_CHIPREV_MKREV(vendor, family, rev) \ 4138a40a695Sgavinm ((uint32_t)(vendor) << _X86_CHIPREV_VENDOR_SHIFT | \ 4148a40a695Sgavinm (family) << _X86_CHIPREV_FAMILY_SHIFT | (rev)) 4158a40a695Sgavinm 4168a40a695Sgavinm /* Revision default */ 4178a40a695Sgavinm #define X86_CHIPREV_UNKNOWN 0x0 4188a40a695Sgavinm 4198a40a695Sgavinm /* 42020c794b3Sgavinm * Definitions for AMD Family 0xf. Minor revisions C0 and CG are 42120c794b3Sgavinm * sufficiently different that we will distinguish them; in all other 4228a40a695Sgavinm * case we will identify the major revision. 4238a40a695Sgavinm */ 4248a40a695Sgavinm #define X86_CHIPREV_AMD_F_REV_B _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0001) 4258a40a695Sgavinm #define X86_CHIPREV_AMD_F_REV_C0 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0002) 4268a40a695Sgavinm #define X86_CHIPREV_AMD_F_REV_CG _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0004) 4278a40a695Sgavinm #define X86_CHIPREV_AMD_F_REV_D _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0008) 4288a40a695Sgavinm #define X86_CHIPREV_AMD_F_REV_E _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0010) 4298a40a695Sgavinm #define X86_CHIPREV_AMD_F_REV_F _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0020) 4308a40a695Sgavinm #define X86_CHIPREV_AMD_F_REV_G _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0040) 43120c794b3Sgavinm 43220c794b3Sgavinm /* 43320c794b3Sgavinm * Definitions for AMD Family 0x10. Rev A was Engineering Samples only. 43420c794b3Sgavinm */ 43520c794b3Sgavinm #define X86_CHIPREV_AMD_10_REV_A \ 43631725658Sksadhukh _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0001) 43720c794b3Sgavinm #define X86_CHIPREV_AMD_10_REV_B \ 43820c794b3Sgavinm _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0002) 4398a40a695Sgavinm 4408a40a695Sgavinm /* 4418a40a695Sgavinm * Various socket/package types, extended as the need to distinguish 4428a40a695Sgavinm * a new type arises. The top 8 byte identfies the vendor and the 4438a40a695Sgavinm * remaining 24 bits describe 24 socket types. 4448a40a695Sgavinm */ 4458a40a695Sgavinm 4468a40a695Sgavinm #define _X86_SOCKET_VENDOR_SHIFT 24 4478a40a695Sgavinm #define _X86_SOCKET_VENDOR(x) ((x) >> _X86_SOCKET_VENDOR_SHIFT) 4488a40a695Sgavinm #define _X86_SOCKET_TYPE_MASK 0x00ffffff 4498a40a695Sgavinm #define _X86_SOCKET_TYPE(x) ((x) & _X86_SOCKET_TYPE_MASK) 4508a40a695Sgavinm 4518a40a695Sgavinm #define _X86_SOCKET_MKVAL(vendor, bitval) \ 4528a40a695Sgavinm ((uint32_t)(vendor) << _X86_SOCKET_VENDOR_SHIFT | (bitval)) 4538a40a695Sgavinm 4548a40a695Sgavinm #define X86_SOCKET_MATCH(s, mask) \ 4558a40a695Sgavinm (_X86_SOCKET_VENDOR(s) == _X86_SOCKET_VENDOR(mask) && \ 4568a40a695Sgavinm (_X86_SOCKET_TYPE(s) & _X86_SOCKET_TYPE(mask)) != 0) 4578a40a695Sgavinm 4588a40a695Sgavinm #define X86_SOCKET_UNKNOWN 0x0 4598a40a695Sgavinm /* 4608a40a695Sgavinm * AMD socket types 4618a40a695Sgavinm */ 4628a40a695Sgavinm #define X86_SOCKET_754 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000001) 4638a40a695Sgavinm #define X86_SOCKET_939 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000002) 4648a40a695Sgavinm #define X86_SOCKET_940 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000004) 4658a40a695Sgavinm #define X86_SOCKET_S1g1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000008) 4668a40a695Sgavinm #define X86_SOCKET_AM2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000010) 4678a40a695Sgavinm #define X86_SOCKET_F1207 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000020) 4688a40a695Sgavinm 4697c478bd9Sstevel@tonic-gate #if !defined(_ASM) 4707c478bd9Sstevel@tonic-gate 4717c478bd9Sstevel@tonic-gate #if defined(_KERNEL) || defined(_KMEMUSER) 4727c478bd9Sstevel@tonic-gate 4737c478bd9Sstevel@tonic-gate extern uint_t x86_feature; 4747c478bd9Sstevel@tonic-gate extern uint_t x86_type; 4757c478bd9Sstevel@tonic-gate extern uint_t x86_vendor; 4767c478bd9Sstevel@tonic-gate 4777c478bd9Sstevel@tonic-gate extern uint_t pentiumpro_bug4046376; 4787c478bd9Sstevel@tonic-gate extern uint_t pentiumpro_bug4064495; 4797c478bd9Sstevel@tonic-gate 4807c478bd9Sstevel@tonic-gate extern uint_t enable486; 4817c478bd9Sstevel@tonic-gate 4827c478bd9Sstevel@tonic-gate extern const char CyrixInstead[]; 4837c478bd9Sstevel@tonic-gate 4847c478bd9Sstevel@tonic-gate #endif 4857c478bd9Sstevel@tonic-gate 4867c478bd9Sstevel@tonic-gate #if defined(_KERNEL) 4877c478bd9Sstevel@tonic-gate 4888949bcd6Sandrei /* 4898949bcd6Sandrei * This structure is used to pass arguments and get return values back 4908949bcd6Sandrei * from the CPUID instruction in __cpuid_insn() routine. 4918949bcd6Sandrei */ 4928949bcd6Sandrei struct cpuid_regs { 4938949bcd6Sandrei uint32_t cp_eax; 4948949bcd6Sandrei uint32_t cp_ebx; 4958949bcd6Sandrei uint32_t cp_ecx; 4968949bcd6Sandrei uint32_t cp_edx; 4978949bcd6Sandrei }; 4987c478bd9Sstevel@tonic-gate 4990ac7d7d8Skucharsk extern uint64_t rdmsr(uint_t); 5000ac7d7d8Skucharsk extern void wrmsr(uint_t, const uint64_t); 501ee88d2b9Skchow extern uint64_t xrdmsr(uint_t); 502ee88d2b9Skchow extern void xwrmsr(uint_t, const uint64_t); 503ae115bc7Smrj extern int checked_rdmsr(uint_t, uint64_t *); 504ae115bc7Smrj extern int checked_wrmsr(uint_t, uint64_t); 505ae115bc7Smrj 5067c478bd9Sstevel@tonic-gate extern void invalidate_cache(void); 5077c478bd9Sstevel@tonic-gate extern ulong_t getcr4(void); 5087c478bd9Sstevel@tonic-gate extern void setcr4(ulong_t); 509ae115bc7Smrj 5107c478bd9Sstevel@tonic-gate extern void mtrr_sync(void); 5117c478bd9Sstevel@tonic-gate 5127c478bd9Sstevel@tonic-gate extern void cpu_fast_syscall_enable(void *); 5137c478bd9Sstevel@tonic-gate extern void cpu_fast_syscall_disable(void *); 5147c478bd9Sstevel@tonic-gate 5157c478bd9Sstevel@tonic-gate struct cpu; 5167c478bd9Sstevel@tonic-gate 5177c478bd9Sstevel@tonic-gate extern int cpuid_checkpass(struct cpu *, int); 5188949bcd6Sandrei extern uint32_t cpuid_insn(struct cpu *, struct cpuid_regs *); 5198949bcd6Sandrei extern uint32_t __cpuid_insn(struct cpuid_regs *); 5207c478bd9Sstevel@tonic-gate extern int cpuid_getbrandstr(struct cpu *, char *, size_t); 5217c478bd9Sstevel@tonic-gate extern int cpuid_getidstr(struct cpu *, char *, size_t); 5227c478bd9Sstevel@tonic-gate extern const char *cpuid_getvendorstr(struct cpu *); 5237c478bd9Sstevel@tonic-gate extern uint_t cpuid_getvendor(struct cpu *); 5247c478bd9Sstevel@tonic-gate extern uint_t cpuid_getfamily(struct cpu *); 5257c478bd9Sstevel@tonic-gate extern uint_t cpuid_getmodel(struct cpu *); 5267c478bd9Sstevel@tonic-gate extern uint_t cpuid_getstep(struct cpu *); 5272449e17fSsherrym extern uint_t cpuid_getsig(struct cpu *); 5287c478bd9Sstevel@tonic-gate extern uint_t cpuid_get_ncpu_per_chip(struct cpu *); 5298949bcd6Sandrei extern uint_t cpuid_get_ncore_per_chip(struct cpu *); 530d129bde2Sesaxe extern uint_t cpuid_get_ncpu_sharing_last_cache(struct cpu *); 531d129bde2Sesaxe extern id_t cpuid_get_last_lvl_cacheid(struct cpu *); 532fb2f18f8Sesaxe extern int cpuid_get_chipid(struct cpu *); 533fb2f18f8Sesaxe extern id_t cpuid_get_coreid(struct cpu *); 534fb2f18f8Sesaxe extern int cpuid_get_clogid(struct cpu *); 5358949bcd6Sandrei extern int cpuid_is_cmt(struct cpu *); 5367c478bd9Sstevel@tonic-gate extern int cpuid_syscall32_insn(struct cpu *); 5377c478bd9Sstevel@tonic-gate extern int getl2cacheinfo(struct cpu *, int *, int *, int *); 5388a40a695Sgavinm 5398a40a695Sgavinm extern uint32_t cpuid_getchiprev(struct cpu *); 5408a40a695Sgavinm extern const char *cpuid_getchiprevstr(struct cpu *); 5418a40a695Sgavinm extern uint32_t cpuid_getsockettype(struct cpu *); 5427c478bd9Sstevel@tonic-gate 5437c478bd9Sstevel@tonic-gate extern int cpuid_opteron_erratum(struct cpu *, uint_t); 5447c478bd9Sstevel@tonic-gate 5457c478bd9Sstevel@tonic-gate struct cpuid_info; 5467c478bd9Sstevel@tonic-gate 5477c478bd9Sstevel@tonic-gate extern void setx86isalist(void); 548ae115bc7Smrj extern void cpuid_alloc_space(struct cpu *); 549ae115bc7Smrj extern void cpuid_free_space(struct cpu *); 5507c478bd9Sstevel@tonic-gate extern uint_t cpuid_pass1(struct cpu *); 5517c478bd9Sstevel@tonic-gate extern void cpuid_pass2(struct cpu *); 5527c478bd9Sstevel@tonic-gate extern void cpuid_pass3(struct cpu *); 5537c478bd9Sstevel@tonic-gate extern uint_t cpuid_pass4(struct cpu *); 5547c478bd9Sstevel@tonic-gate extern void add_cpunode2devtree(processorid_t, struct cpuid_info *); 5557c478bd9Sstevel@tonic-gate 5567c478bd9Sstevel@tonic-gate extern void cpuid_get_addrsize(struct cpu *, uint_t *, uint_t *); 5577c478bd9Sstevel@tonic-gate extern uint_t cpuid_get_dtlb_nent(struct cpu *, size_t); 558843e1988Sjohnlev 559843e1988Sjohnlev #if !defined(__xpv) 5605b8a6efeSbholler extern uint32_t *cpuid_mwait_alloc(struct cpu *); 5615b8a6efeSbholler extern void cpuid_mwait_free(struct cpu *); 562843e1988Sjohnlev #endif 5637c478bd9Sstevel@tonic-gate 5642449e17fSsherrym struct cpu_ucode_info; 5652449e17fSsherrym 566843e1988Sjohnlev #if !defined(__xpv) 5672449e17fSsherrym extern void ucode_alloc_space(struct cpu *); 5682449e17fSsherrym extern void ucode_free_space(struct cpu *); 5692449e17fSsherrym extern void ucode_check(struct cpu *); 5702449e17fSsherrym extern void ucode_free(); 571843e1988Sjohnlev #endif 5722449e17fSsherrym 5737c478bd9Sstevel@tonic-gate extern uint_t workaround_errata(struct cpu *); 5747c478bd9Sstevel@tonic-gate 5757c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_93) 5767c478bd9Sstevel@tonic-gate extern int opteron_erratum_93; 5777c478bd9Sstevel@tonic-gate #endif 5787c478bd9Sstevel@tonic-gate 5797c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_91) 5807c478bd9Sstevel@tonic-gate extern int opteron_erratum_91; 5817c478bd9Sstevel@tonic-gate #endif 5827c478bd9Sstevel@tonic-gate 5837c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_100) 5847c478bd9Sstevel@tonic-gate extern int opteron_erratum_100; 5857c478bd9Sstevel@tonic-gate #endif 5867c478bd9Sstevel@tonic-gate 5877c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_121) 5887c478bd9Sstevel@tonic-gate extern int opteron_erratum_121; 5897c478bd9Sstevel@tonic-gate #endif 5907c478bd9Sstevel@tonic-gate 591ee88d2b9Skchow #if defined(OPTERON_WORKAROUND_6323525) 592ee88d2b9Skchow extern int opteron_workaround_6323525; 593ee88d2b9Skchow extern void patch_workaround_6323525(void); 594ee88d2b9Skchow #endif 595ee88d2b9Skchow 5967c478bd9Sstevel@tonic-gate #endif /* _KERNEL */ 5977c478bd9Sstevel@tonic-gate 5987c478bd9Sstevel@tonic-gate #endif 5997c478bd9Sstevel@tonic-gate 6007c478bd9Sstevel@tonic-gate #ifdef __cplusplus 6017c478bd9Sstevel@tonic-gate } 6027c478bd9Sstevel@tonic-gate #endif 6037c478bd9Sstevel@tonic-gate 6047c478bd9Sstevel@tonic-gate #endif /* _SYS_X86_ARCHEXT_H */ 605