1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21/* 22 * Copyright (c) 1995, 2010, Oracle and/or its affiliates. All rights reserved. 23 * Copyright (c) 2011 by Delphix. All rights reserved. 24 */ 25/* 26 * Copyright (c) 2010, Intel Corporation. 27 * All rights reserved. 28 */ 29/* 30 * Copyright 2020 Joyent, Inc. 31 * Copyright 2012 Jens Elkner <jel+illumos@cs.uni-magdeburg.de> 32 * Copyright 2012 Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> 33 * Copyright 2014 Josef 'Jeff' Sipek <jeffpc@josefsipek.net> 34 * Copyright 2018 Nexenta Systems, Inc. 35 */ 36 37#ifndef _SYS_X86_ARCHEXT_H 38#define _SYS_X86_ARCHEXT_H 39 40#if !defined(_ASM) 41#include <sys/regset.h> 42#include <sys/processor.h> 43#include <vm/seg_enum.h> 44#include <vm/page.h> 45#endif /* _ASM */ 46 47#ifdef __cplusplus 48extern "C" { 49#endif 50 51/* 52 * cpuid instruction feature flags in %edx (standard function 1) 53 */ 54 55#define CPUID_INTC_EDX_FPU 0x00000001 /* x87 fpu present */ 56#define CPUID_INTC_EDX_VME 0x00000002 /* virtual-8086 extension */ 57#define CPUID_INTC_EDX_DE 0x00000004 /* debugging extensions */ 58#define CPUID_INTC_EDX_PSE 0x00000008 /* page size extension */ 59#define CPUID_INTC_EDX_TSC 0x00000010 /* time stamp counter */ 60#define CPUID_INTC_EDX_MSR 0x00000020 /* rdmsr and wrmsr */ 61#define CPUID_INTC_EDX_PAE 0x00000040 /* physical addr extension */ 62#define CPUID_INTC_EDX_MCE 0x00000080 /* machine check exception */ 63#define CPUID_INTC_EDX_CX8 0x00000100 /* cmpxchg8b instruction */ 64#define CPUID_INTC_EDX_APIC 0x00000200 /* local APIC */ 65 /* 0x400 - reserved */ 66#define CPUID_INTC_EDX_SEP 0x00000800 /* sysenter and sysexit */ 67#define CPUID_INTC_EDX_MTRR 0x00001000 /* memory type range reg */ 68#define CPUID_INTC_EDX_PGE 0x00002000 /* page global enable */ 69#define CPUID_INTC_EDX_MCA 0x00004000 /* machine check arch */ 70#define CPUID_INTC_EDX_CMOV 0x00008000 /* conditional move insns */ 71#define CPUID_INTC_EDX_PAT 0x00010000 /* page attribute table */ 72#define CPUID_INTC_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */ 73#define CPUID_INTC_EDX_PSN 0x00040000 /* processor serial number */ 74#define CPUID_INTC_EDX_CLFSH 0x00080000 /* clflush instruction */ 75 /* 0x100000 - reserved */ 76#define CPUID_INTC_EDX_DS 0x00200000 /* debug store exists */ 77#define CPUID_INTC_EDX_ACPI 0x00400000 /* monitoring + clock ctrl */ 78#define CPUID_INTC_EDX_MMX 0x00800000 /* MMX instructions */ 79#define CPUID_INTC_EDX_FXSR 0x01000000 /* fxsave and fxrstor */ 80#define CPUID_INTC_EDX_SSE 0x02000000 /* streaming SIMD extensions */ 81#define CPUID_INTC_EDX_SSE2 0x04000000 /* SSE extensions */ 82#define CPUID_INTC_EDX_SS 0x08000000 /* self-snoop */ 83#define CPUID_INTC_EDX_HTT 0x10000000 /* Hyper Thread Technology */ 84#define CPUID_INTC_EDX_TM 0x20000000 /* thermal monitoring */ 85#define CPUID_INTC_EDX_IA64 0x40000000 /* Itanium emulating IA32 */ 86#define CPUID_INTC_EDX_PBE 0x80000000 /* Pending Break Enable */ 87 88/* 89 * cpuid instruction feature flags in %ecx (standard function 1) 90 */ 91 92#define CPUID_INTC_ECX_SSE3 0x00000001 /* Yet more SSE extensions */ 93#define CPUID_INTC_ECX_PCLMULQDQ 0x00000002 /* PCLMULQDQ insn */ 94#define CPUID_INTC_ECX_DTES64 0x00000004 /* 64-bit DS area */ 95#define CPUID_INTC_ECX_MON 0x00000008 /* MONITOR/MWAIT */ 96#define CPUID_INTC_ECX_DSCPL 0x00000010 /* CPL-qualified debug store */ 97#define CPUID_INTC_ECX_VMX 0x00000020 /* Hardware VM extensions */ 98#define CPUID_INTC_ECX_SMX 0x00000040 /* Secure mode extensions */ 99#define CPUID_INTC_ECX_EST 0x00000080 /* enhanced SpeedStep */ 100#define CPUID_INTC_ECX_TM2 0x00000100 /* thermal monitoring */ 101#define CPUID_INTC_ECX_SSSE3 0x00000200 /* Supplemental SSE3 insns */ 102#define CPUID_INTC_ECX_CID 0x00000400 /* L1 context ID */ 103 /* 0x00000800 - reserved */ 104#define CPUID_INTC_ECX_FMA 0x00001000 /* Fused Multiply Add */ 105#define CPUID_INTC_ECX_CX16 0x00002000 /* cmpxchg16 */ 106#define CPUID_INTC_ECX_ETPRD 0x00004000 /* extended task pri messages */ 107#define CPUID_INTC_ECX_PDCM 0x00008000 /* Perf/Debug Capability MSR */ 108 /* 0x00010000 - reserved */ 109#define CPUID_INTC_ECX_PCID 0x00020000 /* process-context ids */ 110#define CPUID_INTC_ECX_DCA 0x00040000 /* direct cache access */ 111#define CPUID_INTC_ECX_SSE4_1 0x00080000 /* SSE4.1 insns */ 112#define CPUID_INTC_ECX_SSE4_2 0x00100000 /* SSE4.2 insns */ 113#define CPUID_INTC_ECX_X2APIC 0x00200000 /* x2APIC */ 114#define CPUID_INTC_ECX_MOVBE 0x00400000 /* MOVBE insn */ 115#define CPUID_INTC_ECX_POPCNT 0x00800000 /* POPCNT insn */ 116#define CPUID_INTC_ECX_TSCDL 0x01000000 /* Deadline TSC */ 117#define CPUID_INTC_ECX_AES 0x02000000 /* AES insns */ 118#define CPUID_INTC_ECX_XSAVE 0x04000000 /* XSAVE/XRESTOR insns */ 119#define CPUID_INTC_ECX_OSXSAVE 0x08000000 /* OS supports XSAVE insns */ 120#define CPUID_INTC_ECX_AVX 0x10000000 /* AVX supported */ 121#define CPUID_INTC_ECX_F16C 0x20000000 /* F16C supported */ 122#define CPUID_INTC_ECX_RDRAND 0x40000000 /* RDRAND supported */ 123#define CPUID_INTC_ECX_HV 0x80000000 /* Hypervisor */ 124 125/* 126 * cpuid instruction feature flags in %edx (extended function 0x80000001) 127 */ 128 129#define CPUID_AMD_EDX_FPU 0x00000001 /* x87 fpu present */ 130#define CPUID_AMD_EDX_VME 0x00000002 /* virtual-8086 extension */ 131#define CPUID_AMD_EDX_DE 0x00000004 /* debugging extensions */ 132#define CPUID_AMD_EDX_PSE 0x00000008 /* page size extensions */ 133#define CPUID_AMD_EDX_TSC 0x00000010 /* time stamp counter */ 134#define CPUID_AMD_EDX_MSR 0x00000020 /* rdmsr and wrmsr */ 135#define CPUID_AMD_EDX_PAE 0x00000040 /* physical addr extension */ 136#define CPUID_AMD_EDX_MCE 0x00000080 /* machine check exception */ 137#define CPUID_AMD_EDX_CX8 0x00000100 /* cmpxchg8b instruction */ 138#define CPUID_AMD_EDX_APIC 0x00000200 /* local APIC */ 139 /* 0x00000400 - sysc on K6m6 */ 140#define CPUID_AMD_EDX_SYSC 0x00000800 /* AMD: syscall and sysret */ 141#define CPUID_AMD_EDX_MTRR 0x00001000 /* memory type and range reg */ 142#define CPUID_AMD_EDX_PGE 0x00002000 /* page global enable */ 143#define CPUID_AMD_EDX_MCA 0x00004000 /* machine check arch */ 144#define CPUID_AMD_EDX_CMOV 0x00008000 /* conditional move insns */ 145#define CPUID_AMD_EDX_PAT 0x00010000 /* K7: page attribute table */ 146#define CPUID_AMD_EDX_FCMOV 0x00010000 /* FCMOVcc etc. */ 147#define CPUID_AMD_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */ 148 /* 0x00040000 - reserved */ 149 /* 0x00080000 - reserved */ 150#define CPUID_AMD_EDX_NX 0x00100000 /* AMD: no-execute page prot */ 151 /* 0x00200000 - reserved */ 152#define CPUID_AMD_EDX_MMXamd 0x00400000 /* AMD: MMX extensions */ 153#define CPUID_AMD_EDX_MMX 0x00800000 /* MMX instructions */ 154#define CPUID_AMD_EDX_FXSR 0x01000000 /* fxsave and fxrstor */ 155#define CPUID_AMD_EDX_FFXSR 0x02000000 /* fast fxsave/fxrstor */ 156#define CPUID_AMD_EDX_1GPG 0x04000000 /* 1GB page */ 157#define CPUID_AMD_EDX_TSCP 0x08000000 /* rdtscp instruction */ 158 /* 0x10000000 - reserved */ 159#define CPUID_AMD_EDX_LM 0x20000000 /* AMD: long mode */ 160#define CPUID_AMD_EDX_3DNowx 0x40000000 /* AMD: extensions to 3DNow! */ 161#define CPUID_AMD_EDX_3DNow 0x80000000 /* AMD: 3DNow! instructions */ 162 163/* 164 * AMD extended function 0x80000001 %ecx 165 */ 166 167#define CPUID_AMD_ECX_AHF64 0x00000001 /* LAHF and SAHF in long mode */ 168#define CPUID_AMD_ECX_CMP_LGCY 0x00000002 /* AMD: multicore chip */ 169#define CPUID_AMD_ECX_SVM 0x00000004 /* AMD: secure VM */ 170#define CPUID_AMD_ECX_EAS 0x00000008 /* extended apic space */ 171#define CPUID_AMD_ECX_CR8D 0x00000010 /* AMD: 32-bit mov %cr8 */ 172#define CPUID_AMD_ECX_LZCNT 0x00000020 /* AMD: LZCNT insn */ 173#define CPUID_AMD_ECX_SSE4A 0x00000040 /* AMD: SSE4A insns */ 174#define CPUID_AMD_ECX_MAS 0x00000080 /* AMD: MisAlignSse mnode */ 175#define CPUID_AMD_ECX_3DNP 0x00000100 /* AMD: 3DNowPrefectch */ 176#define CPUID_AMD_ECX_OSVW 0x00000200 /* AMD: OSVW */ 177#define CPUID_AMD_ECX_IBS 0x00000400 /* AMD: IBS */ 178#define CPUID_AMD_ECX_XOP 0x00000800 /* AMD: Extended Operation */ 179#define CPUID_AMD_ECX_SKINIT 0x00001000 /* AMD: SKINIT */ 180#define CPUID_AMD_ECX_WDT 0x00002000 /* AMD: WDT */ 181 /* 0x00004000 - reserved */ 182#define CPUID_AMD_ECX_LWP 0x00008000 /* AMD: Lightweight profiling */ 183#define CPUID_AMD_ECX_FMA4 0x00010000 /* AMD: 4-operand FMA support */ 184 /* 0x00020000 - reserved */ 185 /* 0x00040000 - reserved */ 186#define CPUID_AMD_ECX_NIDMSR 0x00080000 /* AMD: Node ID MSR */ 187 /* 0x00100000 - reserved */ 188#define CPUID_AMD_ECX_TBM 0x00200000 /* AMD: trailing bit manips. */ 189#define CPUID_AMD_ECX_TOPOEXT 0x00400000 /* AMD: Topology Extensions */ 190#define CPUID_AMD_ECX_PCEC 0x00800000 /* AMD: Core ext perf counter */ 191#define CUPID_AMD_ECX_PCENB 0x01000000 /* AMD: NB ext perf counter */ 192 /* 0x02000000 - reserved */ 193#define CPUID_AMD_ECX_DBKP 0x40000000 /* AMD: Data breakpoint */ 194#define CPUID_AMD_ECX_PERFTSC 0x08000000 /* AMD: TSC Perf Counter */ 195#define CPUID_AMD_ECX_PERFL3 0x10000000 /* AMD: L3 Perf Counter */ 196#define CPUID_AMD_ECX_MONITORX 0x20000000 /* AMD: clzero */ 197 /* 0x40000000 - reserved */ 198 /* 0x80000000 - reserved */ 199 200/* 201 * AMD uses %ebx for some of their features (extended function 0x80000008). 202 */ 203#define CPUID_AMD_EBX_CLZERO 0x000000001 /* AMD: CLZERO instr */ 204#define CPUID_AMD_EBX_IRCMSR 0x000000002 /* AMD: Ret. instrs MSR */ 205#define CPUID_AMD_EBX_ERR_PTR_ZERO 0x000000004 /* AMD: FP Err. Ptr. Zero */ 206#define CPUID_AMD_EBX_IBPB 0x000001000 /* AMD: IBPB */ 207#define CPUID_AMD_EBX_IBRS 0x000004000 /* AMD: IBRS */ 208#define CPUID_AMD_EBX_STIBP 0x000008000 /* AMD: STIBP */ 209#define CPUID_AMD_EBX_IBRS_ALL 0x000010000 /* AMD: Enhanced IBRS */ 210#define CPUID_AMD_EBX_STIBP_ALL 0x000020000 /* AMD: STIBP ALL */ 211#define CPUID_AMD_EBX_PREFER_IBRS 0x000040000 /* AMD: Don't retpoline */ 212#define CPUID_AMD_EBX_SSBD 0x001000000 /* AMD: SSBD */ 213#define CPUID_AMD_EBX_VIRT_SSBD 0x002000000 /* AMD: VIRT SSBD */ 214#define CPUID_AMD_EBX_SSB_NO 0x004000000 /* AMD: SSB Fixed */ 215 216/* 217 * Intel now seems to have claimed part of the "extended" function 218 * space that we previously for non-Intel implementors to use. 219 * More excitingly still, they've claimed bit 20 to mean LAHF/SAHF 220 * is available in long mode i.e. what AMD indicate using bit 0. 221 * On the other hand, everything else is labelled as reserved. 222 */ 223#define CPUID_INTC_ECX_AHF64 0x00100000 /* LAHF and SAHF in long mode */ 224 225/* 226 * Intel uses cpuid leaf 6 to cover various thermal and power control 227 * operations. 228 */ 229#define CPUID_INTC_EAX_DTS 0x00000001 /* Digital Thermal Sensor */ 230#define CPUID_INTC_EAX_TURBO 0x00000002 /* Turboboost */ 231#define CPUID_INTC_EAX_ARAT 0x00000004 /* APIC-Timer-Always-Running */ 232/* bit 3 is reserved */ 233#define CPUID_INTC_EAX_PLN 0x00000010 /* Power limit notification */ 234#define CPUID_INTC_EAX_ECMD 0x00000020 /* Clock mod. duty cycle */ 235#define CPUID_INTC_EAX_PTM 0x00000040 /* Package thermal management */ 236#define CPUID_INTC_EAX_HWP 0x00000080 /* HWP base registers */ 237#define CPUID_INTC_EAX_HWP_NOT 0x00000100 /* HWP Notification */ 238#define CPUID_INTC_EAX_HWP_ACT 0x00000200 /* HWP Activity Window */ 239#define CPUID_INTC_EAX_HWP_EPR 0x00000400 /* HWP Energy Perf. Pref. */ 240#define CPUID_INTC_EAX_HWP_PLR 0x00000800 /* HWP Package Level Request */ 241/* bit 12 is reserved */ 242#define CPUID_INTC_EAX_HDC 0x00002000 /* HDC */ 243#define CPUID_INTC_EAX_TURBO3 0x00004000 /* Turbo Boost Max Tech 3.0 */ 244#define CPUID_INTC_EAX_HWP_CAP 0x00008000 /* HWP Capabilities */ 245#define CPUID_INTC_EAX_HWP_PECI 0x00010000 /* HWP PECI override */ 246#define CPUID_INTC_EAX_HWP_FLEX 0x00020000 /* Flexible HWP */ 247#define CPUID_INTC_EAX_HWP_FAST 0x00040000 /* Fast IA32_HWP_REQUEST */ 248/* bit 19 is reserved */ 249#define CPUID_INTC_EAX_HWP_IDLE 0x00100000 /* Ignore Idle Logical HWP */ 250 251#define CPUID_INTC_EBX_DTS_NTRESH(x) ((x) & 0xf) 252 253#define CPUID_INTC_ECX_MAPERF 0x00000001 /* IA32_MPERF / IA32_APERF */ 254/* bits 1-2 are reserved */ 255#define CPUID_INTC_ECX_PERFBIAS 0x00000008 /* IA32_ENERGY_PERF_BIAS */ 256 257/* 258 * Intel also uses cpuid leaf 7 to have additional instructions and features. 259 * Like some other leaves, but unlike the current ones we care about, it 260 * requires us to specify both a leaf in %eax and a sub-leaf in %ecx. To deal 261 * with the potential use of additional sub-leaves in the future, we now 262 * specifically label the EBX features with their leaf and sub-leaf. 263 */ 264#define CPUID_INTC_EBX_7_0_FSGSBASE 0x00000001 /* FSGSBASE */ 265#define CPUID_INTC_EBX_7_0_TSC_ADJ 0x00000002 /* TSC adjust MSR */ 266#define CPUID_INTC_EBX_7_0_SGX 0x00000004 /* SGX */ 267#define CPUID_INTC_EBX_7_0_BMI1 0x00000008 /* BMI1 instrs */ 268#define CPUID_INTC_EBX_7_0_HLE 0x00000010 /* HLE */ 269#define CPUID_INTC_EBX_7_0_AVX2 0x00000020 /* AVX2 supported */ 270/* Bit 6 is reserved */ 271#define CPUID_INTC_EBX_7_0_SMEP 0x00000080 /* SMEP in CR4 */ 272#define CPUID_INTC_EBX_7_0_BMI2 0x00000100 /* BMI2 instrs */ 273#define CPUID_INTC_EBX_7_0_ENH_REP_MOV 0x00000200 /* Enhanced REP MOVSB */ 274#define CPUID_INTC_EBX_7_0_INVPCID 0x00000400 /* invpcid instr */ 275#define CPUID_INTC_EBX_7_0_RTM 0x00000800 /* RTM instrs */ 276#define CPUID_INTC_EBX_7_0_PQM 0x00001000 /* QoS Monitoring */ 277#define CPUID_INTC_EBX_7_0_DEP_CSDS 0x00002000 /* Deprecates CS/DS */ 278#define CPUID_INTC_EBX_7_0_MPX 0x00004000 /* Mem. Prot. Ext. */ 279#define CPUID_INTC_EBX_7_0_PQE 0x00080000 /* QoS Enforcement */ 280#define CPUID_INTC_EBX_7_0_AVX512F 0x00010000 /* AVX512 foundation */ 281#define CPUID_INTC_EBX_7_0_AVX512DQ 0x00020000 /* AVX512DQ */ 282#define CPUID_INTC_EBX_7_0_RDSEED 0x00040000 /* RDSEED instr */ 283#define CPUID_INTC_EBX_7_0_ADX 0x00080000 /* ADX instrs */ 284#define CPUID_INTC_EBX_7_0_SMAP 0x00100000 /* SMAP in CR 4 */ 285#define CPUID_INTC_EBX_7_0_AVX512IFMA 0x00200000 /* AVX512IFMA */ 286/* Bit 22 is reserved */ 287#define CPUID_INTC_EBX_7_0_CLFLUSHOPT 0x00800000 /* CLFLUSOPT */ 288#define CPUID_INTC_EBX_7_0_CLWB 0x01000000 /* CLWB */ 289#define CPUID_INTC_EBX_7_0_PTRACE 0x02000000 /* Processor Trace */ 290#define CPUID_INTC_EBX_7_0_AVX512PF 0x04000000 /* AVX512PF */ 291#define CPUID_INTC_EBX_7_0_AVX512ER 0x08000000 /* AVX512ER */ 292#define CPUID_INTC_EBX_7_0_AVX512CD 0x10000000 /* AVX512CD */ 293#define CPUID_INTC_EBX_7_0_SHA 0x20000000 /* SHA extensions */ 294#define CPUID_INTC_EBX_7_0_AVX512BW 0x40000000 /* AVX512BW */ 295#define CPUID_INTC_EBX_7_0_AVX512VL 0x80000000 /* AVX512VL */ 296 297#define CPUID_INTC_EBX_7_0_ALL_AVX512 \ 298 (CPUID_INTC_EBX_7_0_AVX512F | CPUID_INTC_EBX_7_0_AVX512DQ | \ 299 CPUID_INTC_EBX_7_0_AVX512IFMA | CPUID_INTC_EBX_7_0_AVX512PF | \ 300 CPUID_INTC_EBX_7_0_AVX512ER | CPUID_INTC_EBX_7_0_AVX512CD | \ 301 CPUID_INTC_EBX_7_0_AVX512BW | CPUID_INTC_EBX_7_0_AVX512VL) 302 303#define CPUID_INTC_ECX_7_0_PREFETCHWT1 0x00000001 /* PREFETCHWT1 */ 304#define CPUID_INTC_ECX_7_0_AVX512VBMI 0x00000002 /* AVX512VBMI */ 305#define CPUID_INTC_ECX_7_0_UMIP 0x00000004 /* UMIP */ 306#define CPUID_INTC_ECX_7_0_PKU 0x00000008 /* umode prot. keys */ 307#define CPUID_INTC_ECX_7_0_OSPKE 0x00000010 /* OSPKE */ 308#define CPUID_INTC_ECX_7_0_WAITPKG 0x00000020 /* WAITPKG */ 309#define CPUID_INTC_ECX_7_0_AVX512VBMI2 0x00000040 /* AVX512 VBMI2 */ 310/* bit 7 is reserved */ 311#define CPUID_INTC_ECX_7_0_GFNI 0x00000100 /* GFNI */ 312#define CPUID_INTC_ECX_7_0_VAES 0x00000200 /* VAES */ 313#define CPUID_INTC_ECX_7_0_VPCLMULQDQ 0x00000400 /* VPCLMULQDQ */ 314#define CPUID_INTC_ECX_7_0_AVX512VNNI 0x00000800 /* AVX512 VNNI */ 315#define CPUID_INTC_ECX_7_0_AVX512BITALG 0x00001000 /* AVX512 BITALG */ 316/* bit 13 is reserved */ 317#define CPUID_INTC_ECX_7_0_AVX512VPOPCDQ 0x00004000 /* AVX512 VPOPCNTDQ */ 318/* bits 15-16 are reserved */ 319/* bits 17-21 are the value of MAWAU */ 320#define CPUID_INTC_ECX_7_0_RDPID 0x00400000 /* RPID, IA32_TSC_AUX */ 321/* bits 23-24 are reserved */ 322#define CPUID_INTC_ECX_7_0_CLDEMOTE 0x02000000 /* Cache line demote */ 323/* bit 26 is resrved */ 324#define CPUID_INTC_ECX_7_0_MOVDIRI 0x08000000 /* MOVDIRI insn */ 325#define CPUID_INTC_ECX_7_0_MOVDIR64B 0x10000000 /* MOVDIR64B insn */ 326/* bit 29 is reserved */ 327#define CPUID_INTC_ECX_7_0_SGXLC 0x40000000 /* SGX Launch config */ 328/* bit 31 is reserved */ 329 330/* 331 * While CPUID_INTC_ECX_7_0_GFNI, CPUID_INTC_ECX_7_0_VAES, and 332 * CPUID_INTC_ECX_7_0_VPCLMULQDQ all have AVX512 components, they are still 333 * valid when AVX512 is not. However, the following flags all are only valid 334 * when AVX512 is present. 335 */ 336#define CPUID_INTC_ECX_7_0_ALL_AVX512 \ 337 (CPUID_INTC_ECX_7_0_AVX512VBMI | CPUID_INTC_ECX_7_0_AVX512VNNI | \ 338 CPUID_INTC_ECX_7_0_AVX512BITALG | CPUID_INTC_ECX_7_0_AVX512VPOPCDQ) 339 340/* bits 0-1 are reserved */ 341#define CPUID_INTC_EDX_7_0_AVX5124NNIW 0x00000004 /* AVX512 4NNIW */ 342#define CPUID_INTC_EDX_7_0_AVX5124FMAPS 0x00000008 /* AVX512 4FMAPS */ 343#define CPUID_INTC_EDX_7_0_FSREPMOV 0x00000010 /* fast short rep mov */ 344/* bits 5-9 are reserved */ 345#define CPUID_INTC_EDX_7_0_MD_CLEAR 0x00000400 /* MB VERW */ 346/* bits 11-17 are reserved */ 347#define CPUID_INTC_EDX_7_0_PCONFIG 0x00040000 /* PCONFIG */ 348/* bits 19-26 are reserved */ 349#define CPUID_INTC_EDX_7_0_SPEC_CTRL 0x04000000 /* Spec, IBPB, IBRS */ 350#define CPUID_INTC_EDX_7_0_STIBP 0x08000000 /* STIBP */ 351#define CPUID_INTC_EDX_7_0_FLUSH_CMD 0x10000000 /* IA32_FLUSH_CMD */ 352#define CPUID_INTC_EDX_7_0_ARCH_CAPS 0x20000000 /* IA32_ARCH_CAPS */ 353#define CPUID_INTC_EDX_7_0_SSBD 0x80000000 /* SSBD */ 354 355#define CPUID_INTC_EDX_7_0_ALL_AVX512 \ 356 (CPUID_INTC_EDX_7_0_AVX5124NNIW | CPUID_INTC_EDX_7_0_AVX5124FMAPS) 357 358/* 359 * Intel also uses cpuid leaf 0xd to report additional instructions and features 360 * when the sub-leaf in %ecx == 1. We label these using the same convention as 361 * with leaf 7. 362 */ 363#define CPUID_INTC_EAX_D_1_XSAVEOPT 0x00000001 /* xsaveopt inst. */ 364#define CPUID_INTC_EAX_D_1_XSAVEC 0x00000002 /* xsavec inst. */ 365#define CPUID_INTC_EAX_D_1_XSAVES 0x00000008 /* xsaves inst. */ 366 367#define REG_PAT 0x277 368#define REG_TSC 0x10 /* timestamp counter */ 369#define REG_APIC_BASE_MSR 0x1b 370#define REG_X2APIC_BASE_MSR 0x800 /* The MSR address offset of x2APIC */ 371 372#if !defined(__xpv) 373/* 374 * AMD C1E 375 */ 376#define MSR_AMD_INT_PENDING_CMP_HALT 0xC0010055 377#define AMD_ACTONCMPHALT_SHIFT 27 378#define AMD_ACTONCMPHALT_MASK 3 379#endif 380 381#define MSR_DEBUGCTL 0x1d9 382 383#define DEBUGCTL_LBR 0x01 384#define DEBUGCTL_BTF 0x02 385 386/* Intel P6, AMD */ 387#define MSR_LBR_FROM 0x1db 388#define MSR_LBR_TO 0x1dc 389#define MSR_LEX_FROM 0x1dd 390#define MSR_LEX_TO 0x1de 391 392/* Intel P4 (pre-Prescott, non P4 M) */ 393#define MSR_P4_LBSTK_TOS 0x1da 394#define MSR_P4_LBSTK_0 0x1db 395#define MSR_P4_LBSTK_1 0x1dc 396#define MSR_P4_LBSTK_2 0x1dd 397#define MSR_P4_LBSTK_3 0x1de 398 399/* Intel Pentium M */ 400#define MSR_P6M_LBSTK_TOS 0x1c9 401#define MSR_P6M_LBSTK_0 0x040 402#define MSR_P6M_LBSTK_1 0x041 403#define MSR_P6M_LBSTK_2 0x042 404#define MSR_P6M_LBSTK_3 0x043 405#define MSR_P6M_LBSTK_4 0x044 406#define MSR_P6M_LBSTK_5 0x045 407#define MSR_P6M_LBSTK_6 0x046 408#define MSR_P6M_LBSTK_7 0x047 409 410/* Intel P4 (Prescott) */ 411#define MSR_PRP4_LBSTK_TOS 0x1da 412#define MSR_PRP4_LBSTK_FROM_0 0x680 413#define MSR_PRP4_LBSTK_FROM_1 0x681 414#define MSR_PRP4_LBSTK_FROM_2 0x682 415#define MSR_PRP4_LBSTK_FROM_3 0x683 416#define MSR_PRP4_LBSTK_FROM_4 0x684 417#define MSR_PRP4_LBSTK_FROM_5 0x685 418#define MSR_PRP4_LBSTK_FROM_6 0x686 419#define MSR_PRP4_LBSTK_FROM_7 0x687 420#define MSR_PRP4_LBSTK_FROM_8 0x688 421#define MSR_PRP4_LBSTK_FROM_9 0x689 422#define MSR_PRP4_LBSTK_FROM_10 0x68a 423#define MSR_PRP4_LBSTK_FROM_11 0x68b 424#define MSR_PRP4_LBSTK_FROM_12 0x68c 425#define MSR_PRP4_LBSTK_FROM_13 0x68d 426#define MSR_PRP4_LBSTK_FROM_14 0x68e 427#define MSR_PRP4_LBSTK_FROM_15 0x68f 428#define MSR_PRP4_LBSTK_TO_0 0x6c0 429#define MSR_PRP4_LBSTK_TO_1 0x6c1 430#define MSR_PRP4_LBSTK_TO_2 0x6c2 431#define MSR_PRP4_LBSTK_TO_3 0x6c3 432#define MSR_PRP4_LBSTK_TO_4 0x6c4 433#define MSR_PRP4_LBSTK_TO_5 0x6c5 434#define MSR_PRP4_LBSTK_TO_6 0x6c6 435#define MSR_PRP4_LBSTK_TO_7 0x6c7 436#define MSR_PRP4_LBSTK_TO_8 0x6c8 437#define MSR_PRP4_LBSTK_TO_9 0x6c9 438#define MSR_PRP4_LBSTK_TO_10 0x6ca 439#define MSR_PRP4_LBSTK_TO_11 0x6cb 440#define MSR_PRP4_LBSTK_TO_12 0x6cc 441#define MSR_PRP4_LBSTK_TO_13 0x6cd 442#define MSR_PRP4_LBSTK_TO_14 0x6ce 443#define MSR_PRP4_LBSTK_TO_15 0x6cf 444 445/* 446 * General Xeon based MSRs 447 */ 448#define MSR_PPIN_CTL 0x04e 449#define MSR_PPIN 0x04f 450#define MSR_PLATFORM_INFO 0x0ce 451 452#define MSR_PLATFORM_INFO_PPIN (1 << 23) 453#define MSR_PPIN_CTL_MASK 0x03 454#define MSR_PPIN_CTL_LOCKED 0x01 455#define MSR_PPIN_CTL_ENABLED 0x02 456 457/* 458 * Intel IA32_ARCH_CAPABILITIES MSR. 459 */ 460#define MSR_IA32_ARCH_CAPABILITIES 0x10a 461#define IA32_ARCH_CAP_RDCL_NO 0x0001 462#define IA32_ARCH_CAP_IBRS_ALL 0x0002 463#define IA32_ARCH_CAP_RSBA 0x0004 464#define IA32_ARCH_CAP_SKIP_L1DFL_VMENTRY 0x0008 465#define IA32_ARCH_CAP_SSB_NO 0x0010 466#define IA32_ARCH_CAP_MDS_NO 0x0020 467#define IA32_ARCH_CAP_IF_PSCHANGE_MC_NO 0x0040 468#define IA32_ARCH_CAP_TSX_CTRL 0x0080 469#define IA32_ARCH_CAP_TAA_NO 0x0100 470 471/* 472 * Intel Speculation related MSRs 473 */ 474#define MSR_IA32_SPEC_CTRL 0x48 475#define IA32_SPEC_CTRL_IBRS 0x01 476#define IA32_SPEC_CTRL_STIBP 0x02 477#define IA32_SPEC_CTRL_SSBD 0x04 478 479#define MSR_IA32_PRED_CMD 0x49 480#define IA32_PRED_CMD_IBPB 0x01 481 482#define MSR_IA32_FLUSH_CMD 0x10b 483#define IA32_FLUSH_CMD_L1D 0x01 484 485/* 486 * Intel TSX Control MSRs 487 */ 488#define MSR_IA32_TSX_CTRL 0x122 489#define IA32_TSX_CTRL_RTM_DISABLE 0x01 490#define IA32_TSX_CTRL_CPUID_CLEAR 0x02 491 492/* 493 * Intel Thermal MSRs 494 */ 495#define MSR_IA32_THERM_INTERRUPT 0x19b 496#define IA32_THERM_INTERRUPT_HIGH_IE 0x00000001 497#define IA32_THERM_INTERRUPT_LOW_IE 0x00000002 498#define IA32_THERM_INTERRUPT_PROCHOT_IE 0x00000004 499#define IA32_THERM_INTERRUPT_FORCEPR_IE 0x00000008 500#define IA32_THERM_INTERRUPT_CRIT_IE 0x00000010 501#define IA32_THERM_INTERRUPT_TR1_VAL(x) (((x) >> 8) & 0x7f) 502#define IA32_THERM_INTTERUPT_TR1_IE 0x00008000 503#define IA32_THERM_INTTERUPT_TR2_VAL(x) (((x) >> 16) & 0x7f) 504#define IA32_THERM_INTERRUPT_TR2_IE 0x00800000 505#define IA32_THERM_INTERRUPT_PL_NE 0x01000000 506 507#define MSR_IA32_THERM_STATUS 0x19c 508#define IA32_THERM_STATUS_STATUS 0x00000001 509#define IA32_THERM_STATUS_STATUS_LOG 0x00000002 510#define IA32_THERM_STATUS_PROCHOT 0x00000004 511#define IA32_THERM_STATUS_PROCHOT_LOG 0x00000008 512#define IA32_THERM_STATUS_CRIT_STATUS 0x00000010 513#define IA32_THERM_STATUS_CRIT_LOG 0x00000020 514#define IA32_THERM_STATUS_TR1_STATUS 0x00000040 515#define IA32_THERM_STATUS_TR1_LOG 0x00000080 516#define IA32_THERM_STATUS_TR2_STATUS 0x00000100 517#define IA32_THERM_STATUS_TR2_LOG 0x00000200 518#define IA32_THERM_STATUS_POWER_LIMIT_STATUS 0x00000400 519#define IA32_THERM_STATUS_POWER_LIMIT_LOG 0x00000800 520#define IA32_THERM_STATUS_CURRENT_STATUS 0x00001000 521#define IA32_THERM_STATUS_CURRENT_LOG 0x00002000 522#define IA32_THERM_STATUS_CROSS_DOMAIN_STATUS 0x00004000 523#define IA32_THERM_STATUS_CROSS_DOMAIN_LOG 0x00008000 524#define IA32_THERM_STATUS_READING(x) (((x) >> 16) & 0x7f) 525#define IA32_THERM_STATUS_RESOLUTION(x) (((x) >> 27) & 0x0f) 526#define IA32_THERM_STATUS_READ_VALID 0x80000000 527 528#define MSR_TEMPERATURE_TARGET 0x1a2 529#define MSR_TEMPERATURE_TARGET_TARGET(x) (((x) >> 16) & 0xff) 530/* 531 * Not all models support the offset. Refer to the Intel SDM Volume 4 for a list 532 * of which models have support for which bits. 533 */ 534#define MSR_TEMPERATURE_TARGET_OFFSET(x) (((x) >> 24) & 0x0f) 535 536#define MSR_IA32_PACKAGE_THERM_STATUS 0x1b1 537#define IA32_PKG_THERM_STATUS_STATUS 0x00000001 538#define IA32_PKG_THERM_STATUS_STATUS_LOG 0x00000002 539#define IA32_PKG_THERM_STATUS_PROCHOT 0x00000004 540#define IA32_PKG_THERM_STATUS_PROCHOT_LOG 0x00000008 541#define IA32_PKG_THERM_STATUS_CRIT_STATUS 0x00000010 542#define IA32_PKG_THERM_STATUS_CRIT_LOG 0x00000020 543#define IA32_PKG_THERM_STATUS_TR1_STATUS 0x00000040 544#define IA32_PKG_THERM_STATUS_TR1_LOG 0x00000080 545#define IA32_PKG_THERM_STATUS_TR2_STATUS 0x00000100 546#define IA32_PKG_THERM_STATUS_TR2_LOG 0x00000200 547#define IA32_PKG_THERM_STATUS_READING(x) (((x) >> 16) & 0x7f) 548 549#define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x1b2 550#define IA32_PKG_THERM_INTERRUPT_HIGH_IE 0x00000001 551#define IA32_PKG_THERM_INTERRUPT_LOW_IE 0x00000002 552#define IA32_PKG_THERM_INTERRUPT_PROCHOT_IE 0x00000004 553#define IA32_PKG_THERM_INTERRUPT_OVERHEAT_IE 0x00000010 554#define IA32_PKG_THERM_INTERRUPT_TR1_VAL(x) (((x) >> 8) & 0x7f) 555#define IA32_PKG_THERM_INTTERUPT_TR1_IE 0x00008000 556#define IA32_PKG_THERM_INTTERUPT_TR2_VAL(x) (((x) >> 16) & 0x7f) 557#define IA32_PKG_THERM_INTERRUPT_TR2_IE 0x00800000 558#define IA32_PKG_THERM_INTERRUPT_PL_NE 0x01000000 559 560/* 561 * This MSR exists on families, 10h, 12h+ for AMD. This controls instruction 562 * decoding. Most notably, for the AMD variant of retpolines, we must improve 563 * the serializability of lfence for the lfence based method to work. 564 */ 565#define MSR_AMD_DECODE_CONFIG 0xc0011029 566#define AMD_DECODE_CONFIG_LFENCE_DISPATCH 0x02 567 568#define MCI_CTL_VALUE 0xffffffff 569 570#define MTRR_TYPE_UC 0 571#define MTRR_TYPE_WC 1 572#define MTRR_TYPE_WT 4 573#define MTRR_TYPE_WP 5 574#define MTRR_TYPE_WB 6 575#define MTRR_TYPE_UC_ 7 576 577/* 578 * For Solaris we set up the page attritubute table in the following way: 579 * PAT0 Write-Back 580 * PAT1 Write-Through 581 * PAT2 Unchacheable- 582 * PAT3 Uncacheable 583 * PAT4 Write-Back 584 * PAT5 Write-Through 585 * PAT6 Write-Combine 586 * PAT7 Uncacheable 587 * The only difference from h/w default is entry 6. 588 */ 589#define PAT_DEFAULT_ATTRIBUTE \ 590 ((uint64_t)MTRR_TYPE_WB | \ 591 ((uint64_t)MTRR_TYPE_WT << 8) | \ 592 ((uint64_t)MTRR_TYPE_UC_ << 16) | \ 593 ((uint64_t)MTRR_TYPE_UC << 24) | \ 594 ((uint64_t)MTRR_TYPE_WB << 32) | \ 595 ((uint64_t)MTRR_TYPE_WT << 40) | \ 596 ((uint64_t)MTRR_TYPE_WC << 48) | \ 597 ((uint64_t)MTRR_TYPE_UC << 56)) 598 599#define X86FSET_LARGEPAGE 0 600#define X86FSET_TSC 1 601#define X86FSET_MSR 2 602#define X86FSET_MTRR 3 603#define X86FSET_PGE 4 604#define X86FSET_DE 5 605#define X86FSET_CMOV 6 606#define X86FSET_MMX 7 607#define X86FSET_MCA 8 608#define X86FSET_PAE 9 609#define X86FSET_CX8 10 610#define X86FSET_PAT 11 611#define X86FSET_SEP 12 612#define X86FSET_SSE 13 613#define X86FSET_SSE2 14 614#define X86FSET_HTT 15 615#define X86FSET_ASYSC 16 616#define X86FSET_NX 17 617#define X86FSET_SSE3 18 618#define X86FSET_CX16 19 619#define X86FSET_CMP 20 620#define X86FSET_TSCP 21 621#define X86FSET_MWAIT 22 622#define X86FSET_SSE4A 23 623#define X86FSET_CPUID 24 624#define X86FSET_SSSE3 25 625#define X86FSET_SSE4_1 26 626#define X86FSET_SSE4_2 27 627#define X86FSET_1GPG 28 628#define X86FSET_CLFSH 29 629#define X86FSET_64 30 630#define X86FSET_AES 31 631#define X86FSET_PCLMULQDQ 32 632#define X86FSET_XSAVE 33 633#define X86FSET_AVX 34 634#define X86FSET_VMX 35 635#define X86FSET_SVM 36 636#define X86FSET_TOPOEXT 37 637#define X86FSET_F16C 38 638#define X86FSET_RDRAND 39 639#define X86FSET_X2APIC 40 640#define X86FSET_AVX2 41 641#define X86FSET_BMI1 42 642#define X86FSET_BMI2 43 643#define X86FSET_FMA 44 644#define X86FSET_SMEP 45 645#define X86FSET_SMAP 46 646#define X86FSET_ADX 47 647#define X86FSET_RDSEED 48 648#define X86FSET_MPX 49 649#define X86FSET_AVX512F 50 650#define X86FSET_AVX512DQ 51 651#define X86FSET_AVX512PF 52 652#define X86FSET_AVX512ER 53 653#define X86FSET_AVX512CD 54 654#define X86FSET_AVX512BW 55 655#define X86FSET_AVX512VL 56 656#define X86FSET_AVX512FMA 57 657#define X86FSET_AVX512VBMI 58 658#define X86FSET_AVX512VPOPCDQ 59 659#define X86FSET_AVX512NNIW 60 660#define X86FSET_AVX512FMAPS 61 661#define X86FSET_XSAVEOPT 62 662#define X86FSET_XSAVEC 63 663#define X86FSET_XSAVES 64 664#define X86FSET_SHA 65 665#define X86FSET_UMIP 66 666#define X86FSET_PKU 67 667#define X86FSET_OSPKE 68 668#define X86FSET_PCID 69 669#define X86FSET_INVPCID 70 670#define X86FSET_IBRS 71 671#define X86FSET_IBPB 72 672#define X86FSET_STIBP 73 673#define X86FSET_SSBD 74 674#define X86FSET_SSBD_VIRT 75 675#define X86FSET_RDCL_NO 76 676#define X86FSET_IBRS_ALL 77 677#define X86FSET_RSBA 78 678#define X86FSET_SSB_NO 79 679#define X86FSET_STIBP_ALL 80 680#define X86FSET_FLUSH_CMD 81 681#define X86FSET_L1D_VM_NO 82 682#define X86FSET_FSGSBASE 83 683#define X86FSET_CLFLUSHOPT 84 684#define X86FSET_CLWB 85 685#define X86FSET_MONITORX 86 686#define X86FSET_CLZERO 87 687#define X86FSET_XOP 88 688#define X86FSET_FMA4 89 689#define X86FSET_TBM 90 690#define X86FSET_AVX512VNNI 91 691#define X86FSET_AMD_PCEC 92 692#define X86FSET_MD_CLEAR 93 693#define X86FSET_MDS_NO 94 694#define X86FSET_CORE_THERMAL 95 695#define X86FSET_PKG_THERMAL 96 696#define X86FSET_TSX_CTRL 97 697#define X86FSET_TAA_NO 98 698 699/* 700 * Intel Deep C-State invariant TSC in leaf 0x80000007. 701 */ 702#define CPUID_TSC_CSTATE_INVARIANCE (0x100) 703 704/* 705 * Intel TSC deadline timer 706 */ 707#define CPUID_DEADLINE_TSC (1 << 24) 708 709/* 710 * x86_type is a legacy concept; this is supplanted 711 * for most purposes by x86_featureset; modern CPUs 712 * should be X86_TYPE_OTHER 713 */ 714#define X86_TYPE_OTHER 0 715#define X86_TYPE_486 1 716#define X86_TYPE_P5 2 717#define X86_TYPE_P6 3 718#define X86_TYPE_CYRIX_486 4 719#define X86_TYPE_CYRIX_6x86L 5 720#define X86_TYPE_CYRIX_6x86 6 721#define X86_TYPE_CYRIX_GXm 7 722#define X86_TYPE_CYRIX_6x86MX 8 723#define X86_TYPE_CYRIX_MediaGX 9 724#define X86_TYPE_CYRIX_MII 10 725#define X86_TYPE_VIA_CYRIX_III 11 726#define X86_TYPE_P4 12 727 728/* 729 * x86_vendor allows us to select between 730 * implementation features and helps guide 731 * the interpretation of the cpuid instruction. 732 */ 733#define X86_VENDOR_Intel 0 734#define X86_VENDORSTR_Intel "GenuineIntel" 735 736#define X86_VENDOR_IntelClone 1 737 738#define X86_VENDOR_AMD 2 739#define X86_VENDORSTR_AMD "AuthenticAMD" 740 741#define X86_VENDOR_Cyrix 3 742#define X86_VENDORSTR_CYRIX "CyrixInstead" 743 744#define X86_VENDOR_UMC 4 745#define X86_VENDORSTR_UMC "UMC UMC UMC " 746 747#define X86_VENDOR_NexGen 5 748#define X86_VENDORSTR_NexGen "NexGenDriven" 749 750#define X86_VENDOR_Centaur 6 751#define X86_VENDORSTR_Centaur "CentaurHauls" 752 753#define X86_VENDOR_Rise 7 754#define X86_VENDORSTR_Rise "RiseRiseRise" 755 756#define X86_VENDOR_SiS 8 757#define X86_VENDORSTR_SiS "SiS SiS SiS " 758 759#define X86_VENDOR_TM 9 760#define X86_VENDORSTR_TM "GenuineTMx86" 761 762#define X86_VENDOR_NSC 10 763#define X86_VENDORSTR_NSC "Geode by NSC" 764 765/* 766 * Vendor string max len + \0 767 */ 768#define X86_VENDOR_STRLEN 13 769 770/* 771 * Some vendor/family/model/stepping ranges are commonly grouped under 772 * a single identifying banner by the vendor. The following encode 773 * that "revision" in a uint32_t with the 8 most significant bits 774 * identifying the vendor with X86_VENDOR_*, the next 8 identifying the 775 * family, and the remaining 16 typically forming a bitmask of revisions 776 * within that family with more significant bits indicating "later" revisions. 777 */ 778 779#define _X86_CHIPREV_VENDOR_MASK 0xff000000u 780#define _X86_CHIPREV_VENDOR_SHIFT 24 781#define _X86_CHIPREV_FAMILY_MASK 0x00ff0000u 782#define _X86_CHIPREV_FAMILY_SHIFT 16 783#define _X86_CHIPREV_REV_MASK 0x0000ffffu 784 785#define _X86_CHIPREV_VENDOR(x) \ 786 (((x) & _X86_CHIPREV_VENDOR_MASK) >> _X86_CHIPREV_VENDOR_SHIFT) 787#define _X86_CHIPREV_FAMILY(x) \ 788 (((x) & _X86_CHIPREV_FAMILY_MASK) >> _X86_CHIPREV_FAMILY_SHIFT) 789#define _X86_CHIPREV_REV(x) \ 790 ((x) & _X86_CHIPREV_REV_MASK) 791 792/* True if x matches in vendor and family and if x matches the given rev mask */ 793#define X86_CHIPREV_MATCH(x, mask) \ 794 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(mask) && \ 795 _X86_CHIPREV_FAMILY(x) == _X86_CHIPREV_FAMILY(mask) && \ 796 ((_X86_CHIPREV_REV(x) & _X86_CHIPREV_REV(mask)) != 0)) 797 798/* True if x matches in vendor and family, and rev is at least minx */ 799#define X86_CHIPREV_ATLEAST(x, minx) \ 800 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(minx) && \ 801 _X86_CHIPREV_FAMILY(x) == _X86_CHIPREV_FAMILY(minx) && \ 802 _X86_CHIPREV_REV(x) >= _X86_CHIPREV_REV(minx)) 803 804#define _X86_CHIPREV_MKREV(vendor, family, rev) \ 805 ((uint32_t)(vendor) << _X86_CHIPREV_VENDOR_SHIFT | \ 806 (family) << _X86_CHIPREV_FAMILY_SHIFT | (rev)) 807 808/* True if x matches in vendor, and family is at least minx */ 809#define X86_CHIPFAM_ATLEAST(x, minx) \ 810 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(minx) && \ 811 _X86_CHIPREV_FAMILY(x) >= _X86_CHIPREV_FAMILY(minx)) 812 813/* Revision default */ 814#define X86_CHIPREV_UNKNOWN 0x0 815 816/* 817 * Definitions for AMD Family 0xf. Minor revisions C0 and CG are 818 * sufficiently different that we will distinguish them; in all other 819 * case we will identify the major revision. 820 */ 821#define X86_CHIPREV_AMD_F_REV_B _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0001) 822#define X86_CHIPREV_AMD_F_REV_C0 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0002) 823#define X86_CHIPREV_AMD_F_REV_CG _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0004) 824#define X86_CHIPREV_AMD_F_REV_D _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0008) 825#define X86_CHIPREV_AMD_F_REV_E _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0010) 826#define X86_CHIPREV_AMD_F_REV_F _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0020) 827#define X86_CHIPREV_AMD_F_REV_G _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0040) 828 829/* 830 * Definitions for AMD Family 0x10. Rev A was Engineering Samples only. 831 */ 832#define X86_CHIPREV_AMD_10_REV_A \ 833 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0001) 834#define X86_CHIPREV_AMD_10_REV_B \ 835 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0002) 836#define X86_CHIPREV_AMD_10_REV_C2 \ 837 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0004) 838#define X86_CHIPREV_AMD_10_REV_C3 \ 839 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0008) 840#define X86_CHIPREV_AMD_10_REV_D0 \ 841 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0010) 842#define X86_CHIPREV_AMD_10_REV_D1 \ 843 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0020) 844#define X86_CHIPREV_AMD_10_REV_E \ 845 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0040) 846 847/* 848 * Definitions for AMD Family 0x11. 849 */ 850#define X86_CHIPREV_AMD_11_REV_B \ 851 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x11, 0x0002) 852 853/* 854 * Definitions for AMD Family 0x12. 855 */ 856#define X86_CHIPREV_AMD_12_REV_B \ 857 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x12, 0x0002) 858 859/* 860 * Definitions for AMD Family 0x14. 861 */ 862#define X86_CHIPREV_AMD_14_REV_B \ 863 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x14, 0x0002) 864#define X86_CHIPREV_AMD_14_REV_C \ 865 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x14, 0x0004) 866 867/* 868 * Definitions for AMD Family 0x15 869 */ 870#define X86_CHIPREV_AMD_15OR_REV_B2 \ 871 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x15, 0x0001) 872 873#define X86_CHIPREV_AMD_15TN_REV_A1 \ 874 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x15, 0x0002) 875 876#define X86_CHIPREV_AMD_150R_REV_C0 \ 877 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x15, 0x0003) 878 879#define X86_CHIPREV_AMD_15KV_REV_A1 \ 880 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x15, 0x0004) 881 882#define X86_CHIPREV_AMD_15F60 \ 883 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x15, 0x0005) 884 885#define X86_CHIPREV_AMD_15ST_REV_A0 \ 886 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x15, 0x0006) 887 888/* 889 * Definitions for AMD Family 0x16 890 */ 891#define X86_CHIPREV_AMD_16_KB_A1 \ 892 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x16, 0x0001) 893 894#define X86_CHIPREV_AMD_16_ML_A1 \ 895 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x16, 0x0002) 896 897/* 898 * Definitions for AMD Family 0x17 899 */ 900 901#define X86_CHIPREV_AMD_17_ZP_B1 \ 902 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x17, 0x0001) 903 904#define X86_CHIPREV_AMD_17_ZP_B2 \ 905 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x17, 0x0002) 906 907#define X86_CHIPREV_AMD_17_PiR_B2 \ 908 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x17, 0x0003) 909 910/* 911 * Various socket/package types, extended as the need to distinguish 912 * a new type arises. The top 8 byte identfies the vendor and the 913 * remaining 24 bits describe 24 socket types. 914 */ 915 916#define _X86_SOCKET_VENDOR_SHIFT 24 917#define _X86_SOCKET_VENDOR(x) ((x) >> _X86_SOCKET_VENDOR_SHIFT) 918#define _X86_SOCKET_TYPE_MASK 0x00ffffff 919#define _X86_SOCKET_TYPE(x) ((x) & _X86_SOCKET_TYPE_MASK) 920 921#define _X86_SOCKET_MKVAL(vendor, bitval) \ 922 ((uint32_t)(vendor) << _X86_SOCKET_VENDOR_SHIFT | (bitval)) 923 924#define X86_SOCKET_MATCH(s, mask) \ 925 (_X86_SOCKET_VENDOR(s) == _X86_SOCKET_VENDOR(mask) && \ 926 (_X86_SOCKET_TYPE(s) & _X86_SOCKET_TYPE(mask)) != 0) 927 928#define X86_SOCKET_UNKNOWN 0x0 929 /* 930 * AMD socket types 931 */ 932#define X86_SOCKET_754 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x01) 933#define X86_SOCKET_939 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x02) 934#define X86_SOCKET_940 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x03) 935#define X86_SOCKET_S1g1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x04) 936#define X86_SOCKET_AM2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x05) 937#define X86_SOCKET_F1207 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x06) 938#define X86_SOCKET_S1g2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x07) 939#define X86_SOCKET_S1g3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x08) 940#define X86_SOCKET_AM _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x09) 941#define X86_SOCKET_AM2R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x0a) 942#define X86_SOCKET_AM3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x0b) 943#define X86_SOCKET_G34 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x0c) 944#define X86_SOCKET_ASB2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x0d) 945#define X86_SOCKET_C32 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x0e) 946#define X86_SOCKET_S1g4 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x0f) 947#define X86_SOCKET_FT1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x10) 948#define X86_SOCKET_FM1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x11) 949#define X86_SOCKET_FS1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x12) 950#define X86_SOCKET_AM3R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x13) 951#define X86_SOCKET_FP2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x14) 952#define X86_SOCKET_FS1R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x15) 953#define X86_SOCKET_FM2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x16) 954#define X86_SOCKET_FP3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x17) 955#define X86_SOCKET_FM2R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x18) 956#define X86_SOCKET_FP4 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x19) 957#define X86_SOCKET_AM4 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x1a) 958#define X86_SOCKET_FT3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x1b) 959#define X86_SOCKET_FT4 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x1c) 960#define X86_SOCKET_FS1B _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x1d) 961#define X86_SOCKET_FT3B _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x1e) 962#define X86_SOCKET_SP3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x1f) 963#define X86_SOCKET_SP3R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x20) 964#define X86_NUM_SOCKETS_AMD 0x21 965 966 967/* 968 * Definitions for Intel processor models. These are all for Family 6 969 * processors. This list and the Atom set below it are not exhuastive. 970 */ 971#define INTC_MODEL_YONAH 0x0e 972#define INTC_MODEL_MEROM 0x0f 973#define INTC_MODEL_MEROM_L 0x16 974#define INTC_MODEL_PENRYN 0x17 975#define INTC_MODEL_DUNNINGTON 0x1d 976 977#define INTC_MODEL_NEHALEM 0x1e 978#define INTC_MODEL_NEHALEM2 0x1f 979#define INTC_MODEL_NEHALEM_EP 0x1a 980#define INTC_MODEL_NEHALEM_EX 0x2e 981 982#define INTC_MODEL_WESTMERE 0x25 983#define INTC_MODEL_WESTMERE_EP 0x2c 984#define INTC_MODEL_WESTMERE_EX 0x2f 985 986#define INTC_MODEL_SANDYBRIDGE 0x2a 987#define INTC_MODEL_SANDYBRIDGE_XEON 0x2d 988#define INTC_MODEL_IVYBRIDGE 0x3a 989#define INTC_MODEL_IVYBRIDGE_XEON 0x3e 990 991#define INTC_MODEL_HASWELL 0x3c 992#define INTC_MODEL_HASWELL_ULT 0x45 993#define INTC_MODEL_HASWELL_GT3E 0x46 994#define INTC_MODEL_HASWELL_XEON 0x3f 995 996#define INTC_MODEL_BROADWELL 0x3d 997#define INTC_MODEL_BROADELL_2 0x47 998#define INTC_MODEL_BROADWELL_XEON 0x4f 999#define INTC_MODEL_BROADWELL_XEON_D 0x56 1000 1001#define INTC_MODEL_SKYLAKE_MOBILE 0x4e 1002#define INTC_MODEL_SKYLAKE_XEON 0x55 1003#define INTC_MODEL_SKYLAKE_DESKTOP 0x5e 1004 1005#define INTC_MODEL_KABYLAKE_MOBILE 0x8e 1006#define INTC_MODEL_KABYLAKE_DESKTOP 0x9e 1007 1008/* 1009 * Atom Processors 1010 */ 1011#define INTC_MODEL_SILVERTHORNE 0x1c 1012#define INTC_MODEL_LINCROFT 0x26 1013#define INTC_MODEL_PENWELL 0x27 1014#define INTC_MODEL_CLOVERVIEW 0x35 1015#define INTC_MODEL_CEDARVIEW 0x36 1016#define INTC_MODEL_BAY_TRAIL 0x37 1017#define INTC_MODEL_AVATON 0x4d 1018#define INTC_MODEL_AIRMONT 0x4c 1019#define INTC_MODEL_GOLDMONT 0x5c 1020#define INTC_MODEL_DENVERTON 0x5f 1021#define INTC_MODEL_GEMINI_LAKE 0x7a 1022 1023/* 1024 * xgetbv/xsetbv support 1025 * See section 13.3 in vol. 1 of the Intel devlopers manual. 1026 */ 1027 1028#define XFEATURE_ENABLED_MASK 0x0 1029/* 1030 * XFEATURE_ENABLED_MASK values (eax) 1031 * See setup_xfem(). 1032 */ 1033#define XFEATURE_LEGACY_FP 0x1 1034#define XFEATURE_SSE 0x2 1035#define XFEATURE_AVX 0x4 1036#define XFEATURE_MPX 0x18 /* 2 bits, both 0 or 1 */ 1037#define XFEATURE_AVX512 0xe0 /* 3 bits, all 0 or 1 */ 1038 /* bit 8 unused */ 1039#define XFEATURE_PKRU 0x200 1040#define XFEATURE_FP_ALL \ 1041 (XFEATURE_LEGACY_FP | XFEATURE_SSE | XFEATURE_AVX | XFEATURE_MPX | \ 1042 XFEATURE_AVX512 | XFEATURE_PKRU) 1043 1044/* 1045 * Define the set of xfeature flags that should be considered valid in the xsave 1046 * state vector when we initialize an lwp. This is distinct from the full set so 1047 * that all of the processor's normal logic and tracking of the xsave state is 1048 * usable. This should correspond to the state that's been initialized by the 1049 * ABI to hold meaningful values. Adding additional bits here can have serious 1050 * performance implications and cause performance degradations when using the 1051 * FPU vector (xmm) registers. 1052 */ 1053#define XFEATURE_FP_INITIAL (XFEATURE_LEGACY_FP | XFEATURE_SSE) 1054 1055#if !defined(_ASM) 1056 1057#if defined(_KERNEL) || defined(_KMEMUSER) 1058 1059#define NUM_X86_FEATURES 99 1060extern uchar_t x86_featureset[]; 1061 1062extern void free_x86_featureset(void *featureset); 1063extern boolean_t is_x86_feature(void *featureset, uint_t feature); 1064extern void add_x86_feature(void *featureset, uint_t feature); 1065extern void remove_x86_feature(void *featureset, uint_t feature); 1066extern boolean_t compare_x86_featureset(void *setA, void *setB); 1067extern void print_x86_featureset(void *featureset); 1068 1069 1070extern uint_t x86_type; 1071extern uint_t x86_vendor; 1072extern uint_t x86_clflush_size; 1073 1074extern uint_t pentiumpro_bug4046376; 1075 1076extern const char CyrixInstead[]; 1077 1078/* 1079 * These functions are all used to perform various side-channel mitigations. 1080 * Please see uts/i86pc/os/cpuid.c for more information. 1081 */ 1082extern void (*spec_uarch_flush)(void); 1083extern void x86_rsb_stuff(void); 1084extern void x86_md_clear(void); 1085 1086#endif 1087 1088#if defined(_KERNEL) 1089 1090/* 1091 * This structure is used to pass arguments and get return values back 1092 * from the CPUID instruction in __cpuid_insn() routine. 1093 */ 1094struct cpuid_regs { 1095 uint32_t cp_eax; 1096 uint32_t cp_ebx; 1097 uint32_t cp_ecx; 1098 uint32_t cp_edx; 1099}; 1100 1101extern int x86_use_pcid; 1102extern int x86_use_invpcid; 1103 1104/* 1105 * Utility functions to get/set extended control registers (XCR) 1106 * Initial use is to get/set the contents of the XFEATURE_ENABLED_MASK. 1107 */ 1108extern uint64_t get_xcr(uint_t); 1109extern void set_xcr(uint_t, uint64_t); 1110 1111extern uint64_t rdmsr(uint_t); 1112extern void wrmsr(uint_t, const uint64_t); 1113extern uint64_t xrdmsr(uint_t); 1114extern void xwrmsr(uint_t, const uint64_t); 1115extern int checked_rdmsr(uint_t, uint64_t *); 1116extern int checked_wrmsr(uint_t, uint64_t); 1117 1118extern void invalidate_cache(void); 1119extern ulong_t getcr4(void); 1120extern void setcr4(ulong_t); 1121 1122extern void mtrr_sync(void); 1123 1124extern void cpu_fast_syscall_enable(void); 1125extern void cpu_fast_syscall_disable(void); 1126 1127struct cpu; 1128 1129extern int cpuid_checkpass(struct cpu *, int); 1130extern uint32_t cpuid_insn(struct cpu *, struct cpuid_regs *); 1131extern uint32_t __cpuid_insn(struct cpuid_regs *); 1132extern int cpuid_getbrandstr(struct cpu *, char *, size_t); 1133extern int cpuid_getidstr(struct cpu *, char *, size_t); 1134extern const char *cpuid_getvendorstr(struct cpu *); 1135extern uint_t cpuid_getvendor(struct cpu *); 1136extern uint_t cpuid_getfamily(struct cpu *); 1137extern uint_t cpuid_getmodel(struct cpu *); 1138extern uint_t cpuid_getstep(struct cpu *); 1139extern uint_t cpuid_getsig(struct cpu *); 1140extern uint_t cpuid_get_ncpu_per_chip(struct cpu *); 1141extern uint_t cpuid_get_ncore_per_chip(struct cpu *); 1142extern uint_t cpuid_get_ncpu_sharing_last_cache(struct cpu *); 1143extern id_t cpuid_get_last_lvl_cacheid(struct cpu *); 1144extern int cpuid_get_chipid(struct cpu *); 1145extern id_t cpuid_get_coreid(struct cpu *); 1146extern int cpuid_get_pkgcoreid(struct cpu *); 1147extern int cpuid_get_clogid(struct cpu *); 1148extern int cpuid_get_cacheid(struct cpu *); 1149extern uint32_t cpuid_get_apicid(struct cpu *); 1150extern uint_t cpuid_get_procnodeid(struct cpu *cpu); 1151extern uint_t cpuid_get_procnodes_per_pkg(struct cpu *cpu); 1152extern uint_t cpuid_get_compunitid(struct cpu *cpu); 1153extern uint_t cpuid_get_cores_per_compunit(struct cpu *cpu); 1154extern size_t cpuid_get_xsave_size(); 1155extern boolean_t cpuid_need_fp_excp_handling(); 1156extern int cpuid_is_cmt(struct cpu *); 1157extern int cpuid_syscall32_insn(struct cpu *); 1158extern int getl2cacheinfo(struct cpu *, int *, int *, int *); 1159 1160extern uint32_t cpuid_getchiprev(struct cpu *); 1161extern const char *cpuid_getchiprevstr(struct cpu *); 1162extern uint32_t cpuid_getsockettype(struct cpu *); 1163extern const char *cpuid_getsocketstr(struct cpu *); 1164 1165extern int cpuid_have_cr8access(struct cpu *); 1166 1167extern int cpuid_opteron_erratum(struct cpu *, uint_t); 1168 1169struct cpuid_info; 1170 1171extern void setx86isalist(void); 1172extern void cpuid_alloc_space(struct cpu *); 1173extern void cpuid_free_space(struct cpu *); 1174extern void cpuid_pass1(struct cpu *, uchar_t *); 1175extern void cpuid_pass2(struct cpu *); 1176extern void cpuid_pass3(struct cpu *); 1177extern void cpuid_pass4(struct cpu *, uint_t *); 1178extern void cpuid_set_cpu_properties(void *, processorid_t, 1179 struct cpuid_info *); 1180extern void cpuid_pass_ucode(struct cpu *, uchar_t *); 1181extern void cpuid_post_ucodeadm(void); 1182 1183extern void cpuid_get_addrsize(struct cpu *, uint_t *, uint_t *); 1184extern uint_t cpuid_get_dtlb_nent(struct cpu *, size_t); 1185 1186#if !defined(__xpv) 1187extern uint32_t *cpuid_mwait_alloc(struct cpu *); 1188extern void cpuid_mwait_free(struct cpu *); 1189extern int cpuid_deep_cstates_supported(void); 1190extern int cpuid_arat_supported(void); 1191extern int cpuid_iepb_supported(struct cpu *); 1192extern int cpuid_deadline_tsc_supported(void); 1193extern void vmware_port(int, uint32_t *); 1194#endif 1195 1196struct cpu_ucode_info; 1197 1198extern void ucode_alloc_space(struct cpu *); 1199extern void ucode_free_space(struct cpu *); 1200extern void ucode_check(struct cpu *); 1201extern void ucode_cleanup(); 1202 1203#if !defined(__xpv) 1204extern char _tsc_mfence_start; 1205extern char _tsc_mfence_end; 1206extern char _tscp_start; 1207extern char _tscp_end; 1208extern char _no_rdtsc_start; 1209extern char _no_rdtsc_end; 1210extern char _tsc_lfence_start; 1211extern char _tsc_lfence_end; 1212#endif 1213 1214#if !defined(__xpv) 1215extern char bcopy_patch_start; 1216extern char bcopy_patch_end; 1217extern char bcopy_ck_size; 1218#endif 1219 1220extern void post_startup_cpu_fixups(void); 1221 1222extern uint_t workaround_errata(struct cpu *); 1223 1224#if defined(OPTERON_ERRATUM_93) 1225extern int opteron_erratum_93; 1226#endif 1227 1228#if defined(OPTERON_ERRATUM_91) 1229extern int opteron_erratum_91; 1230#endif 1231 1232#if defined(OPTERON_ERRATUM_100) 1233extern int opteron_erratum_100; 1234#endif 1235 1236#if defined(OPTERON_ERRATUM_121) 1237extern int opteron_erratum_121; 1238#endif 1239 1240#if defined(OPTERON_WORKAROUND_6323525) 1241extern int opteron_workaround_6323525; 1242extern void patch_workaround_6323525(void); 1243#endif 1244 1245#if !defined(__xpv) 1246extern void determine_platform(void); 1247#endif 1248extern int get_hwenv(void); 1249extern int is_controldom(void); 1250 1251extern void enable_pcid(void); 1252 1253extern void xsave_setup_msr(struct cpu *); 1254 1255#if !defined(__xpv) 1256extern void reset_gdtr_limit(void); 1257#endif 1258 1259/* 1260 * Hypervisor signatures 1261 */ 1262#define HVSIG_XEN_HVM "XenVMMXenVMM" 1263#define HVSIG_VMWARE "VMwareVMware" 1264#define HVSIG_KVM "KVMKVMKVM" 1265#define HVSIG_MICROSOFT "Microsoft Hv" 1266#define HVSIG_BHYVE "bhyve bhyve " 1267 1268/* 1269 * Defined hardware environments 1270 */ 1271#define HW_NATIVE (1 << 0) /* Running on bare metal */ 1272#define HW_XEN_PV (1 << 1) /* Running on Xen PVM */ 1273 1274#define HW_XEN_HVM (1 << 2) /* Running on Xen HVM */ 1275#define HW_VMWARE (1 << 3) /* Running on VMware hypervisor */ 1276#define HW_KVM (1 << 4) /* Running on KVM hypervisor */ 1277#define HW_MICROSOFT (1 << 5) /* Running on Microsoft hypervisor */ 1278#define HW_BHYVE (1 << 6) /* Running on bhyve hypervisor */ 1279 1280#define HW_VIRTUAL (HW_XEN_HVM | HW_VMWARE | HW_KVM | HW_MICROSOFT | \ 1281 HW_BHYVE) 1282 1283#endif /* _KERNEL */ 1284 1285#endif /* !_ASM */ 1286 1287/* 1288 * VMware hypervisor related defines 1289 */ 1290#define VMWARE_HVMAGIC 0x564d5868 1291#define VMWARE_HVPORT 0x5658 1292#define VMWARE_HVCMD_GETVERSION 0x0a 1293#define VMWARE_HVCMD_GETTSCFREQ 0x2d 1294 1295#ifdef __cplusplus 1296} 1297#endif 1298 1299#endif /* _SYS_X86_ARCHEXT_H */ 1300