1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21/* 22 * Copyright (c) 1995, 2010, Oracle and/or its affiliates. All rights reserved. 23 * Copyright (c) 2011 by Delphix. All rights reserved. 24 */ 25/* 26 * Copyright (c) 2010, Intel Corporation. 27 * All rights reserved. 28 */ 29/* 30 * Copyright 2020 Joyent, Inc. 31 * Copyright 2012 Jens Elkner <jel+illumos@cs.uni-magdeburg.de> 32 * Copyright 2012 Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> 33 * Copyright 2014 Josef 'Jeff' Sipek <jeffpc@josefsipek.net> 34 * Copyright 2018 Nexenta Systems, Inc. 35 */ 36 37#ifndef _SYS_X86_ARCHEXT_H 38#define _SYS_X86_ARCHEXT_H 39 40#if !defined(_ASM) 41#include <sys/regset.h> 42#include <sys/processor.h> 43#include <vm/seg_enum.h> 44#include <vm/page.h> 45#endif /* _ASM */ 46 47#ifdef __cplusplus 48extern "C" { 49#endif 50 51/* 52 * cpuid instruction feature flags in %edx (standard function 1) 53 */ 54 55#define CPUID_INTC_EDX_FPU 0x00000001 /* x87 fpu present */ 56#define CPUID_INTC_EDX_VME 0x00000002 /* virtual-8086 extension */ 57#define CPUID_INTC_EDX_DE 0x00000004 /* debugging extensions */ 58#define CPUID_INTC_EDX_PSE 0x00000008 /* page size extension */ 59#define CPUID_INTC_EDX_TSC 0x00000010 /* time stamp counter */ 60#define CPUID_INTC_EDX_MSR 0x00000020 /* rdmsr and wrmsr */ 61#define CPUID_INTC_EDX_PAE 0x00000040 /* physical addr extension */ 62#define CPUID_INTC_EDX_MCE 0x00000080 /* machine check exception */ 63#define CPUID_INTC_EDX_CX8 0x00000100 /* cmpxchg8b instruction */ 64#define CPUID_INTC_EDX_APIC 0x00000200 /* local APIC */ 65 /* 0x400 - reserved */ 66#define CPUID_INTC_EDX_SEP 0x00000800 /* sysenter and sysexit */ 67#define CPUID_INTC_EDX_MTRR 0x00001000 /* memory type range reg */ 68#define CPUID_INTC_EDX_PGE 0x00002000 /* page global enable */ 69#define CPUID_INTC_EDX_MCA 0x00004000 /* machine check arch */ 70#define CPUID_INTC_EDX_CMOV 0x00008000 /* conditional move insns */ 71#define CPUID_INTC_EDX_PAT 0x00010000 /* page attribute table */ 72#define CPUID_INTC_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */ 73#define CPUID_INTC_EDX_PSN 0x00040000 /* processor serial number */ 74#define CPUID_INTC_EDX_CLFSH 0x00080000 /* clflush instruction */ 75 /* 0x100000 - reserved */ 76#define CPUID_INTC_EDX_DS 0x00200000 /* debug store exists */ 77#define CPUID_INTC_EDX_ACPI 0x00400000 /* monitoring + clock ctrl */ 78#define CPUID_INTC_EDX_MMX 0x00800000 /* MMX instructions */ 79#define CPUID_INTC_EDX_FXSR 0x01000000 /* fxsave and fxrstor */ 80#define CPUID_INTC_EDX_SSE 0x02000000 /* streaming SIMD extensions */ 81#define CPUID_INTC_EDX_SSE2 0x04000000 /* SSE extensions */ 82#define CPUID_INTC_EDX_SS 0x08000000 /* self-snoop */ 83#define CPUID_INTC_EDX_HTT 0x10000000 /* Hyper Thread Technology */ 84#define CPUID_INTC_EDX_TM 0x20000000 /* thermal monitoring */ 85#define CPUID_INTC_EDX_IA64 0x40000000 /* Itanium emulating IA32 */ 86#define CPUID_INTC_EDX_PBE 0x80000000 /* Pending Break Enable */ 87 88/* 89 * cpuid instruction feature flags in %ecx (standard function 1) 90 */ 91 92#define CPUID_INTC_ECX_SSE3 0x00000001 /* Yet more SSE extensions */ 93#define CPUID_INTC_ECX_PCLMULQDQ 0x00000002 /* PCLMULQDQ insn */ 94#define CPUID_INTC_ECX_DTES64 0x00000004 /* 64-bit DS area */ 95#define CPUID_INTC_ECX_MON 0x00000008 /* MONITOR/MWAIT */ 96#define CPUID_INTC_ECX_DSCPL 0x00000010 /* CPL-qualified debug store */ 97#define CPUID_INTC_ECX_VMX 0x00000020 /* Hardware VM extensions */ 98#define CPUID_INTC_ECX_SMX 0x00000040 /* Secure mode extensions */ 99#define CPUID_INTC_ECX_EST 0x00000080 /* enhanced SpeedStep */ 100#define CPUID_INTC_ECX_TM2 0x00000100 /* thermal monitoring */ 101#define CPUID_INTC_ECX_SSSE3 0x00000200 /* Supplemental SSE3 insns */ 102#define CPUID_INTC_ECX_CID 0x00000400 /* L1 context ID */ 103 /* 0x00000800 - reserved */ 104#define CPUID_INTC_ECX_FMA 0x00001000 /* Fused Multiply Add */ 105#define CPUID_INTC_ECX_CX16 0x00002000 /* cmpxchg16 */ 106#define CPUID_INTC_ECX_ETPRD 0x00004000 /* extended task pri messages */ 107#define CPUID_INTC_ECX_PDCM 0x00008000 /* Perf/Debug Capability MSR */ 108 /* 0x00010000 - reserved */ 109#define CPUID_INTC_ECX_PCID 0x00020000 /* process-context ids */ 110#define CPUID_INTC_ECX_DCA 0x00040000 /* direct cache access */ 111#define CPUID_INTC_ECX_SSE4_1 0x00080000 /* SSE4.1 insns */ 112#define CPUID_INTC_ECX_SSE4_2 0x00100000 /* SSE4.2 insns */ 113#define CPUID_INTC_ECX_X2APIC 0x00200000 /* x2APIC */ 114#define CPUID_INTC_ECX_MOVBE 0x00400000 /* MOVBE insn */ 115#define CPUID_INTC_ECX_POPCNT 0x00800000 /* POPCNT insn */ 116#define CPUID_INTC_ECX_TSCDL 0x01000000 /* Deadline TSC */ 117#define CPUID_INTC_ECX_AES 0x02000000 /* AES insns */ 118#define CPUID_INTC_ECX_XSAVE 0x04000000 /* XSAVE/XRESTOR insns */ 119#define CPUID_INTC_ECX_OSXSAVE 0x08000000 /* OS supports XSAVE insns */ 120#define CPUID_INTC_ECX_AVX 0x10000000 /* AVX supported */ 121#define CPUID_INTC_ECX_F16C 0x20000000 /* F16C supported */ 122#define CPUID_INTC_ECX_RDRAND 0x40000000 /* RDRAND supported */ 123#define CPUID_INTC_ECX_HV 0x80000000 /* Hypervisor */ 124 125/* 126 * cpuid instruction feature flags in %edx (extended function 0x80000001) 127 */ 128 129#define CPUID_AMD_EDX_FPU 0x00000001 /* x87 fpu present */ 130#define CPUID_AMD_EDX_VME 0x00000002 /* virtual-8086 extension */ 131#define CPUID_AMD_EDX_DE 0x00000004 /* debugging extensions */ 132#define CPUID_AMD_EDX_PSE 0x00000008 /* page size extensions */ 133#define CPUID_AMD_EDX_TSC 0x00000010 /* time stamp counter */ 134#define CPUID_AMD_EDX_MSR 0x00000020 /* rdmsr and wrmsr */ 135#define CPUID_AMD_EDX_PAE 0x00000040 /* physical addr extension */ 136#define CPUID_AMD_EDX_MCE 0x00000080 /* machine check exception */ 137#define CPUID_AMD_EDX_CX8 0x00000100 /* cmpxchg8b instruction */ 138#define CPUID_AMD_EDX_APIC 0x00000200 /* local APIC */ 139 /* 0x00000400 - sysc on K6m6 */ 140#define CPUID_AMD_EDX_SYSC 0x00000800 /* AMD: syscall and sysret */ 141#define CPUID_AMD_EDX_MTRR 0x00001000 /* memory type and range reg */ 142#define CPUID_AMD_EDX_PGE 0x00002000 /* page global enable */ 143#define CPUID_AMD_EDX_MCA 0x00004000 /* machine check arch */ 144#define CPUID_AMD_EDX_CMOV 0x00008000 /* conditional move insns */ 145#define CPUID_AMD_EDX_PAT 0x00010000 /* K7: page attribute table */ 146#define CPUID_AMD_EDX_FCMOV 0x00010000 /* FCMOVcc etc. */ 147#define CPUID_AMD_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */ 148 /* 0x00040000 - reserved */ 149 /* 0x00080000 - reserved */ 150#define CPUID_AMD_EDX_NX 0x00100000 /* AMD: no-execute page prot */ 151 /* 0x00200000 - reserved */ 152#define CPUID_AMD_EDX_MMXamd 0x00400000 /* AMD: MMX extensions */ 153#define CPUID_AMD_EDX_MMX 0x00800000 /* MMX instructions */ 154#define CPUID_AMD_EDX_FXSR 0x01000000 /* fxsave and fxrstor */ 155#define CPUID_AMD_EDX_FFXSR 0x02000000 /* fast fxsave/fxrstor */ 156#define CPUID_AMD_EDX_1GPG 0x04000000 /* 1GB page */ 157#define CPUID_AMD_EDX_TSCP 0x08000000 /* rdtscp instruction */ 158 /* 0x10000000 - reserved */ 159#define CPUID_AMD_EDX_LM 0x20000000 /* AMD: long mode */ 160#define CPUID_AMD_EDX_3DNowx 0x40000000 /* AMD: extensions to 3DNow! */ 161#define CPUID_AMD_EDX_3DNow 0x80000000 /* AMD: 3DNow! instructions */ 162 163/* 164 * AMD extended function 0x80000001 %ecx 165 */ 166 167#define CPUID_AMD_ECX_AHF64 0x00000001 /* LAHF and SAHF in long mode */ 168#define CPUID_AMD_ECX_CMP_LGCY 0x00000002 /* AMD: multicore chip */ 169#define CPUID_AMD_ECX_SVM 0x00000004 /* AMD: secure VM */ 170#define CPUID_AMD_ECX_EAS 0x00000008 /* extended apic space */ 171#define CPUID_AMD_ECX_CR8D 0x00000010 /* AMD: 32-bit mov %cr8 */ 172#define CPUID_AMD_ECX_LZCNT 0x00000020 /* AMD: LZCNT insn */ 173#define CPUID_AMD_ECX_SSE4A 0x00000040 /* AMD: SSE4A insns */ 174#define CPUID_AMD_ECX_MAS 0x00000080 /* AMD: MisAlignSse mnode */ 175#define CPUID_AMD_ECX_3DNP 0x00000100 /* AMD: 3DNowPrefectch */ 176#define CPUID_AMD_ECX_OSVW 0x00000200 /* AMD: OSVW */ 177#define CPUID_AMD_ECX_IBS 0x00000400 /* AMD: IBS */ 178#define CPUID_AMD_ECX_XOP 0x00000800 /* AMD: Extended Operation */ 179#define CPUID_AMD_ECX_SKINIT 0x00001000 /* AMD: SKINIT */ 180#define CPUID_AMD_ECX_WDT 0x00002000 /* AMD: WDT */ 181 /* 0x00004000 - reserved */ 182#define CPUID_AMD_ECX_LWP 0x00008000 /* AMD: Lightweight profiling */ 183#define CPUID_AMD_ECX_FMA4 0x00010000 /* AMD: 4-operand FMA support */ 184 /* 0x00020000 - reserved */ 185 /* 0x00040000 - reserved */ 186#define CPUID_AMD_ECX_NIDMSR 0x00080000 /* AMD: Node ID MSR */ 187 /* 0x00100000 - reserved */ 188#define CPUID_AMD_ECX_TBM 0x00200000 /* AMD: trailing bit manips. */ 189#define CPUID_AMD_ECX_TOPOEXT 0x00400000 /* AMD: Topology Extensions */ 190#define CPUID_AMD_ECX_PCEC 0x00800000 /* AMD: Core ext perf counter */ 191#define CUPID_AMD_ECX_PCENB 0x01000000 /* AMD: NB ext perf counter */ 192 /* 0x02000000 - reserved */ 193#define CPUID_AMD_ECX_DBKP 0x40000000 /* AMD: Data breakpoint */ 194#define CPUID_AMD_ECX_PERFTSC 0x08000000 /* AMD: TSC Perf Counter */ 195#define CPUID_AMD_ECX_PERFL3 0x10000000 /* AMD: L3 Perf Counter */ 196#define CPUID_AMD_ECX_MONITORX 0x20000000 /* AMD: clzero */ 197 /* 0x40000000 - reserved */ 198 /* 0x80000000 - reserved */ 199 200/* 201 * AMD uses %ebx for some of their features (extended function 0x80000008). 202 */ 203#define CPUID_AMD_EBX_CLZERO 0x000000001 /* AMD: CLZERO instr */ 204#define CPUID_AMD_EBX_IRCMSR 0x000000002 /* AMD: Ret. instrs MSR */ 205#define CPUID_AMD_EBX_ERR_PTR_ZERO 0x000000004 /* AMD: FP Err. Ptr. Zero */ 206#define CPUID_AMD_EBX_IBPB 0x000001000 /* AMD: IBPB */ 207#define CPUID_AMD_EBX_IBRS 0x000004000 /* AMD: IBRS */ 208#define CPUID_AMD_EBX_STIBP 0x000008000 /* AMD: STIBP */ 209#define CPUID_AMD_EBX_IBRS_ALL 0x000010000 /* AMD: Enhanced IBRS */ 210#define CPUID_AMD_EBX_STIBP_ALL 0x000020000 /* AMD: STIBP ALL */ 211#define CPUID_AMD_EBX_PREFER_IBRS 0x000040000 /* AMD: Don't retpoline */ 212#define CPUID_AMD_EBX_PPIN 0x000800000 /* AMD: PPIN Support */ 213#define CPUID_AMD_EBX_SSBD 0x001000000 /* AMD: SSBD */ 214#define CPUID_AMD_EBX_VIRT_SSBD 0x002000000 /* AMD: VIRT SSBD */ 215#define CPUID_AMD_EBX_SSB_NO 0x004000000 /* AMD: SSB Fixed */ 216 217/* 218 * AMD SVM features (extended function 0x8000000A). 219 */ 220#define CPUID_AMD_EDX_NESTED_PAGING 0x000000001 /* AMD: SVM NP */ 221#define CPUID_AMD_EDX_LBR_VIRT 0x000000002 /* AMD: LBR virt. */ 222#define CPUID_AMD_EDX_SVML 0x000000004 /* AMD: SVM lock */ 223#define CPUID_AMD_EDX_NRIPS 0x000000008 /* AMD: NRIP save */ 224#define CPUID_AMD_EDX_TSC_RATE_MSR 0x000000010 /* AMD: MSR TSC ctrl */ 225#define CPUID_AMD_EDX_VMCB_CLEAN 0x000000020 /* AMD: VMCB clean bits */ 226#define CPUID_AMD_EDX_FLUSH_ASID 0x000000040 /* AMD: flush by ASID */ 227#define CPUID_AMD_EDX_DECODE_ASSISTS 0x000000080 /* AMD: decode assists */ 228 229/* 230 * Intel now seems to have claimed part of the "extended" function 231 * space that we previously for non-Intel implementors to use. 232 * More excitingly still, they've claimed bit 20 to mean LAHF/SAHF 233 * is available in long mode i.e. what AMD indicate using bit 0. 234 * On the other hand, everything else is labelled as reserved. 235 */ 236#define CPUID_INTC_ECX_AHF64 0x00100000 /* LAHF and SAHF in long mode */ 237 238/* 239 * Intel uses cpuid leaf 6 to cover various thermal and power control 240 * operations. 241 */ 242#define CPUID_INTC_EAX_DTS 0x00000001 /* Digital Thermal Sensor */ 243#define CPUID_INTC_EAX_TURBO 0x00000002 /* Turboboost */ 244#define CPUID_INTC_EAX_ARAT 0x00000004 /* APIC-Timer-Always-Running */ 245/* bit 3 is reserved */ 246#define CPUID_INTC_EAX_PLN 0x00000010 /* Power limit notification */ 247#define CPUID_INTC_EAX_ECMD 0x00000020 /* Clock mod. duty cycle */ 248#define CPUID_INTC_EAX_PTM 0x00000040 /* Package thermal management */ 249#define CPUID_INTC_EAX_HWP 0x00000080 /* HWP base registers */ 250#define CPUID_INTC_EAX_HWP_NOT 0x00000100 /* HWP Notification */ 251#define CPUID_INTC_EAX_HWP_ACT 0x00000200 /* HWP Activity Window */ 252#define CPUID_INTC_EAX_HWP_EPR 0x00000400 /* HWP Energy Perf. Pref. */ 253#define CPUID_INTC_EAX_HWP_PLR 0x00000800 /* HWP Package Level Request */ 254/* bit 12 is reserved */ 255#define CPUID_INTC_EAX_HDC 0x00002000 /* HDC */ 256#define CPUID_INTC_EAX_TURBO3 0x00004000 /* Turbo Boost Max Tech 3.0 */ 257#define CPUID_INTC_EAX_HWP_CAP 0x00008000 /* HWP Capabilities */ 258#define CPUID_INTC_EAX_HWP_PECI 0x00010000 /* HWP PECI override */ 259#define CPUID_INTC_EAX_HWP_FLEX 0x00020000 /* Flexible HWP */ 260#define CPUID_INTC_EAX_HWP_FAST 0x00040000 /* Fast IA32_HWP_REQUEST */ 261/* bit 19 is reserved */ 262#define CPUID_INTC_EAX_HWP_IDLE 0x00100000 /* Ignore Idle Logical HWP */ 263 264#define CPUID_INTC_EBX_DTS_NTRESH(x) ((x) & 0xf) 265 266#define CPUID_INTC_ECX_MAPERF 0x00000001 /* IA32_MPERF / IA32_APERF */ 267/* bits 1-2 are reserved */ 268#define CPUID_INTC_ECX_PERFBIAS 0x00000008 /* IA32_ENERGY_PERF_BIAS */ 269 270/* 271 * Intel also uses cpuid leaf 7 to have additional instructions and features. 272 * Like some other leaves, but unlike the current ones we care about, it 273 * requires us to specify both a leaf in %eax and a sub-leaf in %ecx. To deal 274 * with the potential use of additional sub-leaves in the future, we now 275 * specifically label the EBX features with their leaf and sub-leaf. 276 */ 277#define CPUID_INTC_EBX_7_0_FSGSBASE 0x00000001 /* FSGSBASE */ 278#define CPUID_INTC_EBX_7_0_TSC_ADJ 0x00000002 /* TSC adjust MSR */ 279#define CPUID_INTC_EBX_7_0_SGX 0x00000004 /* SGX */ 280#define CPUID_INTC_EBX_7_0_BMI1 0x00000008 /* BMI1 instrs */ 281#define CPUID_INTC_EBX_7_0_HLE 0x00000010 /* HLE */ 282#define CPUID_INTC_EBX_7_0_AVX2 0x00000020 /* AVX2 supported */ 283/* Bit 6 is reserved */ 284#define CPUID_INTC_EBX_7_0_SMEP 0x00000080 /* SMEP in CR4 */ 285#define CPUID_INTC_EBX_7_0_BMI2 0x00000100 /* BMI2 instrs */ 286#define CPUID_INTC_EBX_7_0_ENH_REP_MOV 0x00000200 /* Enhanced REP MOVSB */ 287#define CPUID_INTC_EBX_7_0_INVPCID 0x00000400 /* invpcid instr */ 288#define CPUID_INTC_EBX_7_0_RTM 0x00000800 /* RTM instrs */ 289#define CPUID_INTC_EBX_7_0_PQM 0x00001000 /* QoS Monitoring */ 290#define CPUID_INTC_EBX_7_0_DEP_CSDS 0x00002000 /* Deprecates CS/DS */ 291#define CPUID_INTC_EBX_7_0_MPX 0x00004000 /* Mem. Prot. Ext. */ 292#define CPUID_INTC_EBX_7_0_PQE 0x00080000 /* QoS Enforcement */ 293#define CPUID_INTC_EBX_7_0_AVX512F 0x00010000 /* AVX512 foundation */ 294#define CPUID_INTC_EBX_7_0_AVX512DQ 0x00020000 /* AVX512DQ */ 295#define CPUID_INTC_EBX_7_0_RDSEED 0x00040000 /* RDSEED instr */ 296#define CPUID_INTC_EBX_7_0_ADX 0x00080000 /* ADX instrs */ 297#define CPUID_INTC_EBX_7_0_SMAP 0x00100000 /* SMAP in CR 4 */ 298#define CPUID_INTC_EBX_7_0_AVX512IFMA 0x00200000 /* AVX512IFMA */ 299/* Bit 22 is reserved */ 300#define CPUID_INTC_EBX_7_0_CLFLUSHOPT 0x00800000 /* CLFLUSOPT */ 301#define CPUID_INTC_EBX_7_0_CLWB 0x01000000 /* CLWB */ 302#define CPUID_INTC_EBX_7_0_PTRACE 0x02000000 /* Processor Trace */ 303#define CPUID_INTC_EBX_7_0_AVX512PF 0x04000000 /* AVX512PF */ 304#define CPUID_INTC_EBX_7_0_AVX512ER 0x08000000 /* AVX512ER */ 305#define CPUID_INTC_EBX_7_0_AVX512CD 0x10000000 /* AVX512CD */ 306#define CPUID_INTC_EBX_7_0_SHA 0x20000000 /* SHA extensions */ 307#define CPUID_INTC_EBX_7_0_AVX512BW 0x40000000 /* AVX512BW */ 308#define CPUID_INTC_EBX_7_0_AVX512VL 0x80000000 /* AVX512VL */ 309 310#define CPUID_INTC_EBX_7_0_ALL_AVX512 \ 311 (CPUID_INTC_EBX_7_0_AVX512F | CPUID_INTC_EBX_7_0_AVX512DQ | \ 312 CPUID_INTC_EBX_7_0_AVX512IFMA | CPUID_INTC_EBX_7_0_AVX512PF | \ 313 CPUID_INTC_EBX_7_0_AVX512ER | CPUID_INTC_EBX_7_0_AVX512CD | \ 314 CPUID_INTC_EBX_7_0_AVX512BW | CPUID_INTC_EBX_7_0_AVX512VL) 315 316#define CPUID_INTC_ECX_7_0_PREFETCHWT1 0x00000001 /* PREFETCHWT1 */ 317#define CPUID_INTC_ECX_7_0_AVX512VBMI 0x00000002 /* AVX512VBMI */ 318#define CPUID_INTC_ECX_7_0_UMIP 0x00000004 /* UMIP */ 319#define CPUID_INTC_ECX_7_0_PKU 0x00000008 /* umode prot. keys */ 320#define CPUID_INTC_ECX_7_0_OSPKE 0x00000010 /* OSPKE */ 321#define CPUID_INTC_ECX_7_0_WAITPKG 0x00000020 /* WAITPKG */ 322#define CPUID_INTC_ECX_7_0_AVX512VBMI2 0x00000040 /* AVX512 VBMI2 */ 323/* bit 7 is reserved */ 324#define CPUID_INTC_ECX_7_0_GFNI 0x00000100 /* GFNI */ 325#define CPUID_INTC_ECX_7_0_VAES 0x00000200 /* VAES */ 326#define CPUID_INTC_ECX_7_0_VPCLMULQDQ 0x00000400 /* VPCLMULQDQ */ 327#define CPUID_INTC_ECX_7_0_AVX512VNNI 0x00000800 /* AVX512 VNNI */ 328#define CPUID_INTC_ECX_7_0_AVX512BITALG 0x00001000 /* AVX512 BITALG */ 329/* bit 13 is reserved */ 330#define CPUID_INTC_ECX_7_0_AVX512VPOPCDQ 0x00004000 /* AVX512 VPOPCNTDQ */ 331/* bits 15-16 are reserved */ 332/* bits 17-21 are the value of MAWAU */ 333#define CPUID_INTC_ECX_7_0_RDPID 0x00400000 /* RPID, IA32_TSC_AUX */ 334/* bits 23-24 are reserved */ 335#define CPUID_INTC_ECX_7_0_CLDEMOTE 0x02000000 /* Cache line demote */ 336/* bit 26 is resrved */ 337#define CPUID_INTC_ECX_7_0_MOVDIRI 0x08000000 /* MOVDIRI insn */ 338#define CPUID_INTC_ECX_7_0_MOVDIR64B 0x10000000 /* MOVDIR64B insn */ 339/* bit 29 is reserved */ 340#define CPUID_INTC_ECX_7_0_SGXLC 0x40000000 /* SGX Launch config */ 341/* bit 31 is reserved */ 342 343/* 344 * While CPUID_INTC_ECX_7_0_GFNI, CPUID_INTC_ECX_7_0_VAES, and 345 * CPUID_INTC_ECX_7_0_VPCLMULQDQ all have AVX512 components, they are still 346 * valid when AVX512 is not. However, the following flags all are only valid 347 * when AVX512 is present. 348 */ 349#define CPUID_INTC_ECX_7_0_ALL_AVX512 \ 350 (CPUID_INTC_ECX_7_0_AVX512VBMI | CPUID_INTC_ECX_7_0_AVX512VNNI | \ 351 CPUID_INTC_ECX_7_0_AVX512BITALG | CPUID_INTC_ECX_7_0_AVX512VPOPCDQ) 352 353/* bits 0-1 are reserved */ 354#define CPUID_INTC_EDX_7_0_AVX5124NNIW 0x00000004 /* AVX512 4NNIW */ 355#define CPUID_INTC_EDX_7_0_AVX5124FMAPS 0x00000008 /* AVX512 4FMAPS */ 356#define CPUID_INTC_EDX_7_0_FSREPMOV 0x00000010 /* fast short rep mov */ 357/* bits 5-9 are reserved */ 358#define CPUID_INTC_EDX_7_0_MD_CLEAR 0x00000400 /* MB VERW */ 359/* bits 11-17 are reserved */ 360#define CPUID_INTC_EDX_7_0_PCONFIG 0x00040000 /* PCONFIG */ 361/* bits 19-26 are reserved */ 362#define CPUID_INTC_EDX_7_0_SPEC_CTRL 0x04000000 /* Spec, IBPB, IBRS */ 363#define CPUID_INTC_EDX_7_0_STIBP 0x08000000 /* STIBP */ 364#define CPUID_INTC_EDX_7_0_FLUSH_CMD 0x10000000 /* IA32_FLUSH_CMD */ 365#define CPUID_INTC_EDX_7_0_ARCH_CAPS 0x20000000 /* IA32_ARCH_CAPS */ 366#define CPUID_INTC_EDX_7_0_SSBD 0x80000000 /* SSBD */ 367 368#define CPUID_INTC_EDX_7_0_ALL_AVX512 \ 369 (CPUID_INTC_EDX_7_0_AVX5124NNIW | CPUID_INTC_EDX_7_0_AVX5124FMAPS) 370 371/* 372 * Intel also uses cpuid leaf 0xd to report additional instructions and features 373 * when the sub-leaf in %ecx == 1. We label these using the same convention as 374 * with leaf 7. 375 */ 376#define CPUID_INTC_EAX_D_1_XSAVEOPT 0x00000001 /* xsaveopt inst. */ 377#define CPUID_INTC_EAX_D_1_XSAVEC 0x00000002 /* xsavec inst. */ 378#define CPUID_INTC_EAX_D_1_XSAVES 0x00000008 /* xsaves inst. */ 379 380#define REG_PAT 0x277 381#define REG_TSC 0x10 /* timestamp counter */ 382#define REG_APIC_BASE_MSR 0x1b 383#define REG_X2APIC_BASE_MSR 0x800 /* The MSR address offset of x2APIC */ 384 385#if !defined(__xpv) 386/* 387 * AMD C1E 388 */ 389#define MSR_AMD_INT_PENDING_CMP_HALT 0xC0010055 390#define AMD_ACTONCMPHALT_SHIFT 27 391#define AMD_ACTONCMPHALT_MASK 3 392#endif 393 394#define MSR_DEBUGCTL 0x1d9 395 396#define DEBUGCTL_LBR 0x01 397#define DEBUGCTL_BTF 0x02 398 399/* Intel P6, AMD */ 400#define MSR_LBR_FROM 0x1db 401#define MSR_LBR_TO 0x1dc 402#define MSR_LEX_FROM 0x1dd 403#define MSR_LEX_TO 0x1de 404 405/* Intel P4 (pre-Prescott, non P4 M) */ 406#define MSR_P4_LBSTK_TOS 0x1da 407#define MSR_P4_LBSTK_0 0x1db 408#define MSR_P4_LBSTK_1 0x1dc 409#define MSR_P4_LBSTK_2 0x1dd 410#define MSR_P4_LBSTK_3 0x1de 411 412/* Intel Pentium M */ 413#define MSR_P6M_LBSTK_TOS 0x1c9 414#define MSR_P6M_LBSTK_0 0x040 415#define MSR_P6M_LBSTK_1 0x041 416#define MSR_P6M_LBSTK_2 0x042 417#define MSR_P6M_LBSTK_3 0x043 418#define MSR_P6M_LBSTK_4 0x044 419#define MSR_P6M_LBSTK_5 0x045 420#define MSR_P6M_LBSTK_6 0x046 421#define MSR_P6M_LBSTK_7 0x047 422 423/* Intel P4 (Prescott) */ 424#define MSR_PRP4_LBSTK_TOS 0x1da 425#define MSR_PRP4_LBSTK_FROM_0 0x680 426#define MSR_PRP4_LBSTK_FROM_1 0x681 427#define MSR_PRP4_LBSTK_FROM_2 0x682 428#define MSR_PRP4_LBSTK_FROM_3 0x683 429#define MSR_PRP4_LBSTK_FROM_4 0x684 430#define MSR_PRP4_LBSTK_FROM_5 0x685 431#define MSR_PRP4_LBSTK_FROM_6 0x686 432#define MSR_PRP4_LBSTK_FROM_7 0x687 433#define MSR_PRP4_LBSTK_FROM_8 0x688 434#define MSR_PRP4_LBSTK_FROM_9 0x689 435#define MSR_PRP4_LBSTK_FROM_10 0x68a 436#define MSR_PRP4_LBSTK_FROM_11 0x68b 437#define MSR_PRP4_LBSTK_FROM_12 0x68c 438#define MSR_PRP4_LBSTK_FROM_13 0x68d 439#define MSR_PRP4_LBSTK_FROM_14 0x68e 440#define MSR_PRP4_LBSTK_FROM_15 0x68f 441#define MSR_PRP4_LBSTK_TO_0 0x6c0 442#define MSR_PRP4_LBSTK_TO_1 0x6c1 443#define MSR_PRP4_LBSTK_TO_2 0x6c2 444#define MSR_PRP4_LBSTK_TO_3 0x6c3 445#define MSR_PRP4_LBSTK_TO_4 0x6c4 446#define MSR_PRP4_LBSTK_TO_5 0x6c5 447#define MSR_PRP4_LBSTK_TO_6 0x6c6 448#define MSR_PRP4_LBSTK_TO_7 0x6c7 449#define MSR_PRP4_LBSTK_TO_8 0x6c8 450#define MSR_PRP4_LBSTK_TO_9 0x6c9 451#define MSR_PRP4_LBSTK_TO_10 0x6ca 452#define MSR_PRP4_LBSTK_TO_11 0x6cb 453#define MSR_PRP4_LBSTK_TO_12 0x6cc 454#define MSR_PRP4_LBSTK_TO_13 0x6cd 455#define MSR_PRP4_LBSTK_TO_14 0x6ce 456#define MSR_PRP4_LBSTK_TO_15 0x6cf 457 458/* 459 * PPIN definitions for Intel and AMD. Unfortunately, Intel and AMD use 460 * different MSRS for this and different MSRS to control whether or not it 461 * should be readable. 462 */ 463#define MSR_PPIN_CTL_INTC 0x04e 464#define MSR_PPIN_INTC 0x04f 465#define MSR_PLATFORM_INFO 0x0ce 466#define MSR_PLATFORM_INFO_PPIN (1 << 23) 467 468#define MSR_PPIN_CTL_AMD 0xC00102F0 469#define MSR_PPIN_AMD 0xC00102F1 470 471/* 472 * These values are currently the same between Intel and AMD. 473 */ 474#define MSR_PPIN_CTL_MASK 0x03 475#define MSR_PPIN_CTL_LOCKED 0x01 476#define MSR_PPIN_CTL_ENABLED 0x02 477 478/* 479 * Intel IA32_ARCH_CAPABILITIES MSR. 480 */ 481#define MSR_IA32_ARCH_CAPABILITIES 0x10a 482#define IA32_ARCH_CAP_RDCL_NO 0x0001 483#define IA32_ARCH_CAP_IBRS_ALL 0x0002 484#define IA32_ARCH_CAP_RSBA 0x0004 485#define IA32_ARCH_CAP_SKIP_L1DFL_VMENTRY 0x0008 486#define IA32_ARCH_CAP_SSB_NO 0x0010 487#define IA32_ARCH_CAP_MDS_NO 0x0020 488#define IA32_ARCH_CAP_IF_PSCHANGE_MC_NO 0x0040 489#define IA32_ARCH_CAP_TSX_CTRL 0x0080 490#define IA32_ARCH_CAP_TAA_NO 0x0100 491 492/* 493 * Intel Speculation related MSRs 494 */ 495#define MSR_IA32_SPEC_CTRL 0x48 496#define IA32_SPEC_CTRL_IBRS 0x01 497#define IA32_SPEC_CTRL_STIBP 0x02 498#define IA32_SPEC_CTRL_SSBD 0x04 499 500#define MSR_IA32_PRED_CMD 0x49 501#define IA32_PRED_CMD_IBPB 0x01 502 503#define MSR_IA32_FLUSH_CMD 0x10b 504#define IA32_FLUSH_CMD_L1D 0x01 505 506/* 507 * Intel VMX related MSRs 508 */ 509#define MSR_IA32_FEAT_CTRL 0x03a 510#define IA32_FEAT_CTRL_LOCK 0x1 511#define IA32_FEAT_CTRL_SMX_EN 0x2 512#define IA32_FEAT_CTRL_VMX_EN 0x4 513 514#define MSR_IA32_VMX_BASIC 0x480 515#define IA32_VMX_BASIC_INS_OUTS (1UL << 54) 516#define IA32_VMX_BASIC_TRUE_CTRLS (1UL << 55) 517 518#define MSR_IA32_VMX_PROCBASED_CTLS 0x482 519#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x48e 520#define IA32_VMX_PROCBASED_2ND_CTLS (1UL << 31) 521 522#define MSR_IA32_VMX_PROCBASED2_CTLS 0x48b 523#define IA32_VMX_PROCBASED2_EPT (1UL << 1) 524#define IA32_VMX_PROCBASED2_VPID (1UL << 5) 525 526#define MSR_IA32_VMX_EPT_VPID_CAP 0x48c 527#define IA32_VMX_EPT_VPID_INVEPT (1UL << 20) 528#define IA32_VMX_EPT_VPID_INVEPT_SINGLE (1UL << 25) 529#define IA32_VMX_EPT_VPID_INVEPT_ALL (1UL << 26) 530 531/* 532 * Intel TSX Control MSRs 533 */ 534#define MSR_IA32_TSX_CTRL 0x122 535#define IA32_TSX_CTRL_RTM_DISABLE 0x01 536#define IA32_TSX_CTRL_CPUID_CLEAR 0x02 537 538/* 539 * Intel Thermal MSRs 540 */ 541#define MSR_IA32_THERM_INTERRUPT 0x19b 542#define IA32_THERM_INTERRUPT_HIGH_IE 0x00000001 543#define IA32_THERM_INTERRUPT_LOW_IE 0x00000002 544#define IA32_THERM_INTERRUPT_PROCHOT_IE 0x00000004 545#define IA32_THERM_INTERRUPT_FORCEPR_IE 0x00000008 546#define IA32_THERM_INTERRUPT_CRIT_IE 0x00000010 547#define IA32_THERM_INTERRUPT_TR1_VAL(x) (((x) >> 8) & 0x7f) 548#define IA32_THERM_INTTERUPT_TR1_IE 0x00008000 549#define IA32_THERM_INTTERUPT_TR2_VAL(x) (((x) >> 16) & 0x7f) 550#define IA32_THERM_INTERRUPT_TR2_IE 0x00800000 551#define IA32_THERM_INTERRUPT_PL_NE 0x01000000 552 553#define MSR_IA32_THERM_STATUS 0x19c 554#define IA32_THERM_STATUS_STATUS 0x00000001 555#define IA32_THERM_STATUS_STATUS_LOG 0x00000002 556#define IA32_THERM_STATUS_PROCHOT 0x00000004 557#define IA32_THERM_STATUS_PROCHOT_LOG 0x00000008 558#define IA32_THERM_STATUS_CRIT_STATUS 0x00000010 559#define IA32_THERM_STATUS_CRIT_LOG 0x00000020 560#define IA32_THERM_STATUS_TR1_STATUS 0x00000040 561#define IA32_THERM_STATUS_TR1_LOG 0x00000080 562#define IA32_THERM_STATUS_TR2_STATUS 0x00000100 563#define IA32_THERM_STATUS_TR2_LOG 0x00000200 564#define IA32_THERM_STATUS_POWER_LIMIT_STATUS 0x00000400 565#define IA32_THERM_STATUS_POWER_LIMIT_LOG 0x00000800 566#define IA32_THERM_STATUS_CURRENT_STATUS 0x00001000 567#define IA32_THERM_STATUS_CURRENT_LOG 0x00002000 568#define IA32_THERM_STATUS_CROSS_DOMAIN_STATUS 0x00004000 569#define IA32_THERM_STATUS_CROSS_DOMAIN_LOG 0x00008000 570#define IA32_THERM_STATUS_READING(x) (((x) >> 16) & 0x7f) 571#define IA32_THERM_STATUS_RESOLUTION(x) (((x) >> 27) & 0x0f) 572#define IA32_THERM_STATUS_READ_VALID 0x80000000 573 574#define MSR_TEMPERATURE_TARGET 0x1a2 575#define MSR_TEMPERATURE_TARGET_TARGET(x) (((x) >> 16) & 0xff) 576/* 577 * Not all models support the offset. Refer to the Intel SDM Volume 4 for a list 578 * of which models have support for which bits. 579 */ 580#define MSR_TEMPERATURE_TARGET_OFFSET(x) (((x) >> 24) & 0x0f) 581 582#define MSR_IA32_PACKAGE_THERM_STATUS 0x1b1 583#define IA32_PKG_THERM_STATUS_STATUS 0x00000001 584#define IA32_PKG_THERM_STATUS_STATUS_LOG 0x00000002 585#define IA32_PKG_THERM_STATUS_PROCHOT 0x00000004 586#define IA32_PKG_THERM_STATUS_PROCHOT_LOG 0x00000008 587#define IA32_PKG_THERM_STATUS_CRIT_STATUS 0x00000010 588#define IA32_PKG_THERM_STATUS_CRIT_LOG 0x00000020 589#define IA32_PKG_THERM_STATUS_TR1_STATUS 0x00000040 590#define IA32_PKG_THERM_STATUS_TR1_LOG 0x00000080 591#define IA32_PKG_THERM_STATUS_TR2_STATUS 0x00000100 592#define IA32_PKG_THERM_STATUS_TR2_LOG 0x00000200 593#define IA32_PKG_THERM_STATUS_READING(x) (((x) >> 16) & 0x7f) 594 595#define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x1b2 596#define IA32_PKG_THERM_INTERRUPT_HIGH_IE 0x00000001 597#define IA32_PKG_THERM_INTERRUPT_LOW_IE 0x00000002 598#define IA32_PKG_THERM_INTERRUPT_PROCHOT_IE 0x00000004 599#define IA32_PKG_THERM_INTERRUPT_OVERHEAT_IE 0x00000010 600#define IA32_PKG_THERM_INTERRUPT_TR1_VAL(x) (((x) >> 8) & 0x7f) 601#define IA32_PKG_THERM_INTTERUPT_TR1_IE 0x00008000 602#define IA32_PKG_THERM_INTTERUPT_TR2_VAL(x) (((x) >> 16) & 0x7f) 603#define IA32_PKG_THERM_INTERRUPT_TR2_IE 0x00800000 604#define IA32_PKG_THERM_INTERRUPT_PL_NE 0x01000000 605 606 607#define MCI_CTL_VALUE 0xffffffff 608 609#define MTRR_TYPE_UC 0 610#define MTRR_TYPE_WC 1 611#define MTRR_TYPE_WT 4 612#define MTRR_TYPE_WP 5 613#define MTRR_TYPE_WB 6 614#define MTRR_TYPE_UC_ 7 615 616/* 617 * For Solaris we set up the page attritubute table in the following way: 618 * PAT0 Write-Back 619 * PAT1 Write-Through 620 * PAT2 Unchacheable- 621 * PAT3 Uncacheable 622 * PAT4 Write-Back 623 * PAT5 Write-Through 624 * PAT6 Write-Combine 625 * PAT7 Uncacheable 626 * The only difference from h/w default is entry 6. 627 */ 628#define PAT_DEFAULT_ATTRIBUTE \ 629 ((uint64_t)MTRR_TYPE_WB | \ 630 ((uint64_t)MTRR_TYPE_WT << 8) | \ 631 ((uint64_t)MTRR_TYPE_UC_ << 16) | \ 632 ((uint64_t)MTRR_TYPE_UC << 24) | \ 633 ((uint64_t)MTRR_TYPE_WB << 32) | \ 634 ((uint64_t)MTRR_TYPE_WT << 40) | \ 635 ((uint64_t)MTRR_TYPE_WC << 48) | \ 636 ((uint64_t)MTRR_TYPE_UC << 56)) 637 638#define X86FSET_LARGEPAGE 0 639#define X86FSET_TSC 1 640#define X86FSET_MSR 2 641#define X86FSET_MTRR 3 642#define X86FSET_PGE 4 643#define X86FSET_DE 5 644#define X86FSET_CMOV 6 645#define X86FSET_MMX 7 646#define X86FSET_MCA 8 647#define X86FSET_PAE 9 648#define X86FSET_CX8 10 649#define X86FSET_PAT 11 650#define X86FSET_SEP 12 651#define X86FSET_SSE 13 652#define X86FSET_SSE2 14 653#define X86FSET_HTT 15 654#define X86FSET_ASYSC 16 655#define X86FSET_NX 17 656#define X86FSET_SSE3 18 657#define X86FSET_CX16 19 658#define X86FSET_CMP 20 659#define X86FSET_TSCP 21 660#define X86FSET_MWAIT 22 661#define X86FSET_SSE4A 23 662#define X86FSET_CPUID 24 663#define X86FSET_SSSE3 25 664#define X86FSET_SSE4_1 26 665#define X86FSET_SSE4_2 27 666#define X86FSET_1GPG 28 667#define X86FSET_CLFSH 29 668#define X86FSET_64 30 669#define X86FSET_AES 31 670#define X86FSET_PCLMULQDQ 32 671#define X86FSET_XSAVE 33 672#define X86FSET_AVX 34 673#define X86FSET_VMX 35 674#define X86FSET_SVM 36 675#define X86FSET_TOPOEXT 37 676#define X86FSET_F16C 38 677#define X86FSET_RDRAND 39 678#define X86FSET_X2APIC 40 679#define X86FSET_AVX2 41 680#define X86FSET_BMI1 42 681#define X86FSET_BMI2 43 682#define X86FSET_FMA 44 683#define X86FSET_SMEP 45 684#define X86FSET_SMAP 46 685#define X86FSET_ADX 47 686#define X86FSET_RDSEED 48 687#define X86FSET_MPX 49 688#define X86FSET_AVX512F 50 689#define X86FSET_AVX512DQ 51 690#define X86FSET_AVX512PF 52 691#define X86FSET_AVX512ER 53 692#define X86FSET_AVX512CD 54 693#define X86FSET_AVX512BW 55 694#define X86FSET_AVX512VL 56 695#define X86FSET_AVX512FMA 57 696#define X86FSET_AVX512VBMI 58 697#define X86FSET_AVX512VPOPCDQ 59 698#define X86FSET_AVX512NNIW 60 699#define X86FSET_AVX512FMAPS 61 700#define X86FSET_XSAVEOPT 62 701#define X86FSET_XSAVEC 63 702#define X86FSET_XSAVES 64 703#define X86FSET_SHA 65 704#define X86FSET_UMIP 66 705#define X86FSET_PKU 67 706#define X86FSET_OSPKE 68 707#define X86FSET_PCID 69 708#define X86FSET_INVPCID 70 709#define X86FSET_IBRS 71 710#define X86FSET_IBPB 72 711#define X86FSET_STIBP 73 712#define X86FSET_SSBD 74 713#define X86FSET_SSBD_VIRT 75 714#define X86FSET_RDCL_NO 76 715#define X86FSET_IBRS_ALL 77 716#define X86FSET_RSBA 78 717#define X86FSET_SSB_NO 79 718#define X86FSET_STIBP_ALL 80 719#define X86FSET_FLUSH_CMD 81 720#define X86FSET_L1D_VM_NO 82 721#define X86FSET_FSGSBASE 83 722#define X86FSET_CLFLUSHOPT 84 723#define X86FSET_CLWB 85 724#define X86FSET_MONITORX 86 725#define X86FSET_CLZERO 87 726#define X86FSET_XOP 88 727#define X86FSET_FMA4 89 728#define X86FSET_TBM 90 729#define X86FSET_AVX512VNNI 91 730#define X86FSET_AMD_PCEC 92 731#define X86FSET_MD_CLEAR 93 732#define X86FSET_MDS_NO 94 733#define X86FSET_CORE_THERMAL 95 734#define X86FSET_PKG_THERMAL 96 735#define X86FSET_TSX_CTRL 97 736#define X86FSET_TAA_NO 98 737#define X86FSET_PPIN 99 738 739/* 740 * Intel Deep C-State invariant TSC in leaf 0x80000007. 741 */ 742#define CPUID_TSC_CSTATE_INVARIANCE (0x100) 743 744/* 745 * Intel TSC deadline timer 746 */ 747#define CPUID_DEADLINE_TSC (1 << 24) 748 749/* 750 * x86_type is a legacy concept; this is supplanted 751 * for most purposes by x86_featureset; modern CPUs 752 * should be X86_TYPE_OTHER 753 */ 754#define X86_TYPE_OTHER 0 755#define X86_TYPE_486 1 756#define X86_TYPE_P5 2 757#define X86_TYPE_P6 3 758#define X86_TYPE_CYRIX_486 4 759#define X86_TYPE_CYRIX_6x86L 5 760#define X86_TYPE_CYRIX_6x86 6 761#define X86_TYPE_CYRIX_GXm 7 762#define X86_TYPE_CYRIX_6x86MX 8 763#define X86_TYPE_CYRIX_MediaGX 9 764#define X86_TYPE_CYRIX_MII 10 765#define X86_TYPE_VIA_CYRIX_III 11 766#define X86_TYPE_P4 12 767 768/* 769 * x86_vendor allows us to select between 770 * implementation features and helps guide 771 * the interpretation of the cpuid instruction. 772 */ 773#define X86_VENDOR_Intel 0 774#define X86_VENDORSTR_Intel "GenuineIntel" 775 776#define X86_VENDOR_IntelClone 1 777 778#define X86_VENDOR_AMD 2 779#define X86_VENDORSTR_AMD "AuthenticAMD" 780 781#define X86_VENDOR_Cyrix 3 782#define X86_VENDORSTR_CYRIX "CyrixInstead" 783 784#define X86_VENDOR_UMC 4 785#define X86_VENDORSTR_UMC "UMC UMC UMC " 786 787#define X86_VENDOR_NexGen 5 788#define X86_VENDORSTR_NexGen "NexGenDriven" 789 790#define X86_VENDOR_Centaur 6 791#define X86_VENDORSTR_Centaur "CentaurHauls" 792 793#define X86_VENDOR_Rise 7 794#define X86_VENDORSTR_Rise "RiseRiseRise" 795 796#define X86_VENDOR_SiS 8 797#define X86_VENDORSTR_SiS "SiS SiS SiS " 798 799#define X86_VENDOR_TM 9 800#define X86_VENDORSTR_TM "GenuineTMx86" 801 802#define X86_VENDOR_NSC 10 803#define X86_VENDORSTR_NSC "Geode by NSC" 804 805/* 806 * Vendor string max len + \0 807 */ 808#define X86_VENDOR_STRLEN 13 809 810/* 811 * Some vendor/family/model/stepping ranges are commonly grouped under 812 * a single identifying banner by the vendor. The following encode 813 * that "revision" in a uint32_t with the 8 most significant bits 814 * identifying the vendor with X86_VENDOR_*, the next 8 identifying the 815 * family, and the remaining 16 typically forming a bitmask of revisions 816 * within that family with more significant bits indicating "later" revisions. 817 */ 818 819#define _X86_CHIPREV_VENDOR_MASK 0xff000000u 820#define _X86_CHIPREV_VENDOR_SHIFT 24 821#define _X86_CHIPREV_FAMILY_MASK 0x00ff0000u 822#define _X86_CHIPREV_FAMILY_SHIFT 16 823#define _X86_CHIPREV_REV_MASK 0x0000ffffu 824 825#define _X86_CHIPREV_VENDOR(x) \ 826 (((x) & _X86_CHIPREV_VENDOR_MASK) >> _X86_CHIPREV_VENDOR_SHIFT) 827#define _X86_CHIPREV_FAMILY(x) \ 828 (((x) & _X86_CHIPREV_FAMILY_MASK) >> _X86_CHIPREV_FAMILY_SHIFT) 829#define _X86_CHIPREV_REV(x) \ 830 ((x) & _X86_CHIPREV_REV_MASK) 831 832/* True if x matches in vendor and family and if x matches the given rev mask */ 833#define X86_CHIPREV_MATCH(x, mask) \ 834 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(mask) && \ 835 _X86_CHIPREV_FAMILY(x) == _X86_CHIPREV_FAMILY(mask) && \ 836 ((_X86_CHIPREV_REV(x) & _X86_CHIPREV_REV(mask)) != 0)) 837 838/* True if x matches in vendor and family, and rev is at least minx */ 839#define X86_CHIPREV_ATLEAST(x, minx) \ 840 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(minx) && \ 841 _X86_CHIPREV_FAMILY(x) == _X86_CHIPREV_FAMILY(minx) && \ 842 _X86_CHIPREV_REV(x) >= _X86_CHIPREV_REV(minx)) 843 844#define _X86_CHIPREV_MKREV(vendor, family, rev) \ 845 ((uint32_t)(vendor) << _X86_CHIPREV_VENDOR_SHIFT | \ 846 (family) << _X86_CHIPREV_FAMILY_SHIFT | (rev)) 847 848/* True if x matches in vendor, and family is at least minx */ 849#define X86_CHIPFAM_ATLEAST(x, minx) \ 850 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(minx) && \ 851 _X86_CHIPREV_FAMILY(x) >= _X86_CHIPREV_FAMILY(minx)) 852 853/* Revision default */ 854#define X86_CHIPREV_UNKNOWN 0x0 855 856/* 857 * Definitions for AMD Family 0xf. Minor revisions C0 and CG are 858 * sufficiently different that we will distinguish them; in all other 859 * case we will identify the major revision. 860 */ 861#define X86_CHIPREV_AMD_F_REV_B _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0001) 862#define X86_CHIPREV_AMD_F_REV_C0 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0002) 863#define X86_CHIPREV_AMD_F_REV_CG _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0004) 864#define X86_CHIPREV_AMD_F_REV_D _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0008) 865#define X86_CHIPREV_AMD_F_REV_E _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0010) 866#define X86_CHIPREV_AMD_F_REV_F _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0020) 867#define X86_CHIPREV_AMD_F_REV_G _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0040) 868 869/* 870 * Definitions for AMD Family 0x10. Rev A was Engineering Samples only. 871 */ 872#define X86_CHIPREV_AMD_10_REV_A \ 873 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0001) 874#define X86_CHIPREV_AMD_10_REV_B \ 875 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0002) 876#define X86_CHIPREV_AMD_10_REV_C2 \ 877 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0004) 878#define X86_CHIPREV_AMD_10_REV_C3 \ 879 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0008) 880#define X86_CHIPREV_AMD_10_REV_D0 \ 881 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0010) 882#define X86_CHIPREV_AMD_10_REV_D1 \ 883 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0020) 884#define X86_CHIPREV_AMD_10_REV_E \ 885 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0040) 886 887/* 888 * Definitions for AMD Family 0x11. 889 */ 890#define X86_CHIPREV_AMD_11_REV_B \ 891 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x11, 0x0002) 892 893/* 894 * Definitions for AMD Family 0x12. 895 */ 896#define X86_CHIPREV_AMD_12_REV_B \ 897 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x12, 0x0002) 898 899/* 900 * Definitions for AMD Family 0x14. 901 */ 902#define X86_CHIPREV_AMD_14_REV_B \ 903 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x14, 0x0002) 904#define X86_CHIPREV_AMD_14_REV_C \ 905 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x14, 0x0004) 906 907/* 908 * Definitions for AMD Family 0x15 909 */ 910#define X86_CHIPREV_AMD_15OR_REV_B2 \ 911 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x15, 0x0001) 912 913#define X86_CHIPREV_AMD_15TN_REV_A1 \ 914 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x15, 0x0002) 915 916#define X86_CHIPREV_AMD_150R_REV_C0 \ 917 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x15, 0x0003) 918 919#define X86_CHIPREV_AMD_15KV_REV_A1 \ 920 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x15, 0x0004) 921 922#define X86_CHIPREV_AMD_15F60 \ 923 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x15, 0x0005) 924 925#define X86_CHIPREV_AMD_15ST_REV_A0 \ 926 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x15, 0x0006) 927 928/* 929 * Definitions for AMD Family 0x16 930 */ 931#define X86_CHIPREV_AMD_16_KB_A1 \ 932 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x16, 0x0001) 933 934#define X86_CHIPREV_AMD_16_ML_A1 \ 935 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x16, 0x0002) 936 937/* 938 * Definitions for AMD Family 0x17 939 */ 940 941#define X86_CHIPREV_AMD_17_ZP_B1 \ 942 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x17, 0x0001) 943 944#define X86_CHIPREV_AMD_17_ZP_B2 \ 945 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x17, 0x0002) 946 947#define X86_CHIPREV_AMD_17_PiR_B2 \ 948 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x17, 0x0003) 949 950#define X86_CHIPREV_AMD_17_RV_B0 \ 951 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x17, 0x0004) 952 953#define X86_CHIPREV_AMD_17_RV_B1 \ 954 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x17, 0x0005) 955 956#define X86_CHIPREV_AMD_17_PCO_B1 \ 957 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x17, 0x0006) 958 959#define X86_CHIPREV_AMD_17_SSP_A0 \ 960 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x17, 0x0007) 961 962#define X86_CHIPREV_AMD_17_SSP_B0 \ 963 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x17, 0x0008) 964 965/* 966 * Various socket/package types, extended as the need to distinguish 967 * a new type arises. The top 8 byte identfies the vendor and the 968 * remaining 24 bits describe 24 socket types. 969 */ 970 971#define _X86_SOCKET_VENDOR_SHIFT 24 972#define _X86_SOCKET_VENDOR(x) ((x) >> _X86_SOCKET_VENDOR_SHIFT) 973#define _X86_SOCKET_TYPE_MASK 0x00ffffff 974#define _X86_SOCKET_TYPE(x) ((x) & _X86_SOCKET_TYPE_MASK) 975 976#define _X86_SOCKET_MKVAL(vendor, bitval) \ 977 ((uint32_t)(vendor) << _X86_SOCKET_VENDOR_SHIFT | (bitval)) 978 979#define X86_SOCKET_MATCH(s, mask) \ 980 (_X86_SOCKET_VENDOR(s) == _X86_SOCKET_VENDOR(mask) && \ 981 (_X86_SOCKET_TYPE(s) & _X86_SOCKET_TYPE(mask)) != 0) 982 983#define X86_SOCKET_UNKNOWN 0x0 984 /* 985 * AMD socket types 986 */ 987#define X86_SOCKET_754 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x01) 988#define X86_SOCKET_939 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x02) 989#define X86_SOCKET_940 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x03) 990#define X86_SOCKET_S1g1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x04) 991#define X86_SOCKET_AM2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x05) 992#define X86_SOCKET_F1207 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x06) 993#define X86_SOCKET_S1g2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x07) 994#define X86_SOCKET_S1g3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x08) 995#define X86_SOCKET_AM _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x09) 996#define X86_SOCKET_AM2R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x0a) 997#define X86_SOCKET_AM3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x0b) 998#define X86_SOCKET_G34 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x0c) 999#define X86_SOCKET_ASB2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x0d) 1000#define X86_SOCKET_C32 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x0e) 1001#define X86_SOCKET_S1g4 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x0f) 1002#define X86_SOCKET_FT1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x10) 1003#define X86_SOCKET_FM1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x11) 1004#define X86_SOCKET_FS1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x12) 1005#define X86_SOCKET_AM3R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x13) 1006#define X86_SOCKET_FP2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x14) 1007#define X86_SOCKET_FS1R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x15) 1008#define X86_SOCKET_FM2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x16) 1009#define X86_SOCKET_FP3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x17) 1010#define X86_SOCKET_FM2R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x18) 1011#define X86_SOCKET_FP4 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x19) 1012#define X86_SOCKET_AM4 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x1a) 1013#define X86_SOCKET_FT3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x1b) 1014#define X86_SOCKET_FT4 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x1c) 1015#define X86_SOCKET_FS1B _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x1d) 1016#define X86_SOCKET_FT3B _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x1e) 1017#define X86_SOCKET_SP3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x1f) 1018#define X86_SOCKET_SP3R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x20) 1019#define X86_SOCKET_FP5 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x21) 1020#define X86_NUM_SOCKETS_AMD 0x22 1021 1022 1023/* 1024 * Definitions for Intel processor models. These are all for Family 6 1025 * processors. This list and the Atom set below it are not exhuastive. 1026 */ 1027#define INTC_MODEL_YONAH 0x0e 1028#define INTC_MODEL_MEROM 0x0f 1029#define INTC_MODEL_MEROM_L 0x16 1030#define INTC_MODEL_PENRYN 0x17 1031#define INTC_MODEL_DUNNINGTON 0x1d 1032 1033#define INTC_MODEL_NEHALEM 0x1e 1034#define INTC_MODEL_NEHALEM2 0x1f 1035#define INTC_MODEL_NEHALEM_EP 0x1a 1036#define INTC_MODEL_NEHALEM_EX 0x2e 1037 1038#define INTC_MODEL_WESTMERE 0x25 1039#define INTC_MODEL_WESTMERE_EP 0x2c 1040#define INTC_MODEL_WESTMERE_EX 0x2f 1041 1042#define INTC_MODEL_SANDYBRIDGE 0x2a 1043#define INTC_MODEL_SANDYBRIDGE_XEON 0x2d 1044#define INTC_MODEL_IVYBRIDGE 0x3a 1045#define INTC_MODEL_IVYBRIDGE_XEON 0x3e 1046 1047#define INTC_MODEL_HASWELL 0x3c 1048#define INTC_MODEL_HASWELL_ULT 0x45 1049#define INTC_MODEL_HASWELL_GT3E 0x46 1050#define INTC_MODEL_HASWELL_XEON 0x3f 1051 1052#define INTC_MODEL_BROADWELL 0x3d 1053#define INTC_MODEL_BROADELL_2 0x47 1054#define INTC_MODEL_BROADWELL_XEON 0x4f 1055#define INTC_MODEL_BROADWELL_XEON_D 0x56 1056 1057#define INTC_MODEL_SKYLAKE_MOBILE 0x4e 1058#define INTC_MODEL_SKYLAKE_XEON 0x55 1059#define INTC_MODEL_SKYLAKE_DESKTOP 0x5e 1060 1061#define INTC_MODEL_KABYLAKE_MOBILE 0x8e 1062#define INTC_MODEL_KABYLAKE_DESKTOP 0x9e 1063 1064/* 1065 * Atom Processors 1066 */ 1067#define INTC_MODEL_SILVERTHORNE 0x1c 1068#define INTC_MODEL_LINCROFT 0x26 1069#define INTC_MODEL_PENWELL 0x27 1070#define INTC_MODEL_CLOVERVIEW 0x35 1071#define INTC_MODEL_CEDARVIEW 0x36 1072#define INTC_MODEL_BAY_TRAIL 0x37 1073#define INTC_MODEL_AVATON 0x4d 1074#define INTC_MODEL_AIRMONT 0x4c 1075#define INTC_MODEL_GOLDMONT 0x5c 1076#define INTC_MODEL_DENVERTON 0x5f 1077#define INTC_MODEL_GEMINI_LAKE 0x7a 1078 1079/* 1080 * xgetbv/xsetbv support 1081 * See section 13.3 in vol. 1 of the Intel devlopers manual. 1082 */ 1083 1084#define XFEATURE_ENABLED_MASK 0x0 1085/* 1086 * XFEATURE_ENABLED_MASK values (eax) 1087 * See setup_xfem(). 1088 */ 1089#define XFEATURE_LEGACY_FP 0x1 1090#define XFEATURE_SSE 0x2 1091#define XFEATURE_AVX 0x4 1092#define XFEATURE_MPX 0x18 /* 2 bits, both 0 or 1 */ 1093#define XFEATURE_AVX512 0xe0 /* 3 bits, all 0 or 1 */ 1094 /* bit 8 unused */ 1095#define XFEATURE_PKRU 0x200 1096#define XFEATURE_FP_ALL \ 1097 (XFEATURE_LEGACY_FP | XFEATURE_SSE | XFEATURE_AVX | XFEATURE_MPX | \ 1098 XFEATURE_AVX512 | XFEATURE_PKRU) 1099 1100/* 1101 * Define the set of xfeature flags that should be considered valid in the xsave 1102 * state vector when we initialize an lwp. This is distinct from the full set so 1103 * that all of the processor's normal logic and tracking of the xsave state is 1104 * usable. This should correspond to the state that's been initialized by the 1105 * ABI to hold meaningful values. Adding additional bits here can have serious 1106 * performance implications and cause performance degradations when using the 1107 * FPU vector (xmm) registers. 1108 */ 1109#define XFEATURE_FP_INITIAL (XFEATURE_LEGACY_FP | XFEATURE_SSE) 1110 1111#if !defined(_ASM) 1112 1113#if defined(_KERNEL) || defined(_KMEMUSER) 1114 1115#define NUM_X86_FEATURES 100 1116extern uchar_t x86_featureset[]; 1117 1118extern void free_x86_featureset(void *featureset); 1119extern boolean_t is_x86_feature(void *featureset, uint_t feature); 1120extern void add_x86_feature(void *featureset, uint_t feature); 1121extern void remove_x86_feature(void *featureset, uint_t feature); 1122extern boolean_t compare_x86_featureset(void *setA, void *setB); 1123extern void print_x86_featureset(void *featureset); 1124 1125 1126extern uint_t x86_type; 1127extern uint_t x86_vendor; 1128extern uint_t x86_clflush_size; 1129 1130extern uint_t pentiumpro_bug4046376; 1131 1132extern const char CyrixInstead[]; 1133 1134/* 1135 * These functions are all used to perform various side-channel mitigations. 1136 * Please see uts/i86pc/os/cpuid.c for more information. 1137 */ 1138extern void (*spec_uarch_flush)(void); 1139extern void x86_rsb_stuff(void); 1140extern void x86_md_clear(void); 1141 1142#endif 1143 1144#if defined(_KERNEL) 1145 1146/* 1147 * This structure is used to pass arguments and get return values back 1148 * from the CPUID instruction in __cpuid_insn() routine. 1149 */ 1150struct cpuid_regs { 1151 uint32_t cp_eax; 1152 uint32_t cp_ebx; 1153 uint32_t cp_ecx; 1154 uint32_t cp_edx; 1155}; 1156 1157extern int x86_use_pcid; 1158extern int x86_use_invpcid; 1159 1160/* 1161 * Utility functions to get/set extended control registers (XCR) 1162 * Initial use is to get/set the contents of the XFEATURE_ENABLED_MASK. 1163 */ 1164extern uint64_t get_xcr(uint_t); 1165extern void set_xcr(uint_t, uint64_t); 1166 1167extern uint64_t rdmsr(uint_t); 1168extern void wrmsr(uint_t, const uint64_t); 1169extern uint64_t xrdmsr(uint_t); 1170extern void xwrmsr(uint_t, const uint64_t); 1171extern int checked_rdmsr(uint_t, uint64_t *); 1172extern int checked_wrmsr(uint_t, uint64_t); 1173 1174extern void invalidate_cache(void); 1175extern ulong_t getcr4(void); 1176extern void setcr4(ulong_t); 1177 1178extern void mtrr_sync(void); 1179 1180extern void cpu_fast_syscall_enable(void); 1181extern void cpu_fast_syscall_disable(void); 1182 1183struct cpu; 1184 1185extern int cpuid_checkpass(struct cpu *, int); 1186extern uint32_t cpuid_insn(struct cpu *, struct cpuid_regs *); 1187extern uint32_t __cpuid_insn(struct cpuid_regs *); 1188extern int cpuid_getbrandstr(struct cpu *, char *, size_t); 1189extern int cpuid_getidstr(struct cpu *, char *, size_t); 1190extern const char *cpuid_getvendorstr(struct cpu *); 1191extern uint_t cpuid_getvendor(struct cpu *); 1192extern uint_t cpuid_getfamily(struct cpu *); 1193extern uint_t cpuid_getmodel(struct cpu *); 1194extern uint_t cpuid_getstep(struct cpu *); 1195extern uint_t cpuid_getsig(struct cpu *); 1196extern uint_t cpuid_get_ncpu_per_chip(struct cpu *); 1197extern uint_t cpuid_get_ncore_per_chip(struct cpu *); 1198extern uint_t cpuid_get_ncpu_sharing_last_cache(struct cpu *); 1199extern id_t cpuid_get_last_lvl_cacheid(struct cpu *); 1200extern int cpuid_get_chipid(struct cpu *); 1201extern id_t cpuid_get_coreid(struct cpu *); 1202extern int cpuid_get_pkgcoreid(struct cpu *); 1203extern int cpuid_get_clogid(struct cpu *); 1204extern int cpuid_get_cacheid(struct cpu *); 1205extern uint32_t cpuid_get_apicid(struct cpu *); 1206extern uint_t cpuid_get_procnodeid(struct cpu *cpu); 1207extern uint_t cpuid_get_procnodes_per_pkg(struct cpu *cpu); 1208extern uint_t cpuid_get_compunitid(struct cpu *cpu); 1209extern uint_t cpuid_get_cores_per_compunit(struct cpu *cpu); 1210extern size_t cpuid_get_xsave_size(); 1211extern boolean_t cpuid_need_fp_excp_handling(); 1212extern int cpuid_is_cmt(struct cpu *); 1213extern int cpuid_syscall32_insn(struct cpu *); 1214extern int getl2cacheinfo(struct cpu *, int *, int *, int *); 1215 1216extern uint32_t cpuid_getchiprev(struct cpu *); 1217extern const char *cpuid_getchiprevstr(struct cpu *); 1218extern uint32_t cpuid_getsockettype(struct cpu *); 1219extern const char *cpuid_getsocketstr(struct cpu *); 1220 1221extern int cpuid_have_cr8access(struct cpu *); 1222 1223extern int cpuid_opteron_erratum(struct cpu *, uint_t); 1224 1225struct cpuid_info; 1226 1227extern void setx86isalist(void); 1228extern void cpuid_alloc_space(struct cpu *); 1229extern void cpuid_free_space(struct cpu *); 1230extern void cpuid_pass1(struct cpu *, uchar_t *); 1231extern void cpuid_pass2(struct cpu *); 1232extern void cpuid_pass3(struct cpu *); 1233extern void cpuid_pass4(struct cpu *, uint_t *); 1234extern void cpuid_set_cpu_properties(void *, processorid_t, 1235 struct cpuid_info *); 1236extern void cpuid_pass_ucode(struct cpu *, uchar_t *); 1237extern void cpuid_post_ucodeadm(void); 1238 1239extern void cpuid_get_addrsize(struct cpu *, uint_t *, uint_t *); 1240extern uint_t cpuid_get_dtlb_nent(struct cpu *, size_t); 1241 1242#if !defined(__xpv) 1243extern uint32_t *cpuid_mwait_alloc(struct cpu *); 1244extern void cpuid_mwait_free(struct cpu *); 1245extern int cpuid_deep_cstates_supported(void); 1246extern int cpuid_arat_supported(void); 1247extern int cpuid_iepb_supported(struct cpu *); 1248extern int cpuid_deadline_tsc_supported(void); 1249extern void vmware_port(int, uint32_t *); 1250#endif 1251 1252struct cpu_ucode_info; 1253 1254extern void ucode_alloc_space(struct cpu *); 1255extern void ucode_free_space(struct cpu *); 1256extern void ucode_check(struct cpu *); 1257extern void ucode_cleanup(); 1258 1259#if !defined(__xpv) 1260extern char _tsc_mfence_start; 1261extern char _tsc_mfence_end; 1262extern char _tscp_start; 1263extern char _tscp_end; 1264extern char _no_rdtsc_start; 1265extern char _no_rdtsc_end; 1266extern char _tsc_lfence_start; 1267extern char _tsc_lfence_end; 1268#endif 1269 1270#if !defined(__xpv) 1271extern char bcopy_patch_start; 1272extern char bcopy_patch_end; 1273extern char bcopy_ck_size; 1274#endif 1275 1276extern void post_startup_cpu_fixups(void); 1277 1278extern uint_t workaround_errata(struct cpu *); 1279 1280#if defined(OPTERON_ERRATUM_93) 1281extern int opteron_erratum_93; 1282#endif 1283 1284#if defined(OPTERON_ERRATUM_91) 1285extern int opteron_erratum_91; 1286#endif 1287 1288#if defined(OPTERON_ERRATUM_100) 1289extern int opteron_erratum_100; 1290#endif 1291 1292#if defined(OPTERON_ERRATUM_121) 1293extern int opteron_erratum_121; 1294#endif 1295 1296#if defined(OPTERON_WORKAROUND_6323525) 1297extern int opteron_workaround_6323525; 1298extern void patch_workaround_6323525(void); 1299#endif 1300 1301#if !defined(__xpv) 1302extern void determine_platform(void); 1303#endif 1304extern int get_hwenv(void); 1305extern int is_controldom(void); 1306 1307extern void enable_pcid(void); 1308 1309extern void xsave_setup_msr(struct cpu *); 1310 1311#if !defined(__xpv) 1312extern void reset_gdtr_limit(void); 1313#endif 1314 1315/* 1316 * Hypervisor signatures 1317 */ 1318#define HVSIG_XEN_HVM "XenVMMXenVMM" 1319#define HVSIG_VMWARE "VMwareVMware" 1320#define HVSIG_KVM "KVMKVMKVM" 1321#define HVSIG_MICROSOFT "Microsoft Hv" 1322#define HVSIG_BHYVE "bhyve bhyve " 1323 1324/* 1325 * Defined hardware environments 1326 */ 1327#define HW_NATIVE (1 << 0) /* Running on bare metal */ 1328#define HW_XEN_PV (1 << 1) /* Running on Xen PVM */ 1329 1330#define HW_XEN_HVM (1 << 2) /* Running on Xen HVM */ 1331#define HW_VMWARE (1 << 3) /* Running on VMware hypervisor */ 1332#define HW_KVM (1 << 4) /* Running on KVM hypervisor */ 1333#define HW_MICROSOFT (1 << 5) /* Running on Microsoft hypervisor */ 1334#define HW_BHYVE (1 << 6) /* Running on bhyve hypervisor */ 1335 1336#define HW_VIRTUAL (HW_XEN_HVM | HW_VMWARE | HW_KVM | HW_MICROSOFT | \ 1337 HW_BHYVE) 1338 1339#endif /* _KERNEL */ 1340 1341#endif /* !_ASM */ 1342 1343/* 1344 * VMware hypervisor related defines 1345 */ 1346#define VMWARE_HVMAGIC 0x564d5868 1347#define VMWARE_HVPORT 0x5658 1348#define VMWARE_HVCMD_GETVERSION 0x0a 1349#define VMWARE_HVCMD_GETTSCFREQ 0x2d 1350 1351#ifdef __cplusplus 1352} 1353#endif 1354 1355#endif /* _SYS_X86_ARCHEXT_H */ 1356