1/*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22/*
23 * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
24 * Use is subject to license terms.
25 */
26
27#pragma ident	"%Z%%M%	%I%	%E% SMI"
28
29#include <sys/fasttrap_isa.h>
30#include <sys/fasttrap_impl.h>
31#include <sys/dtrace.h>
32#include <sys/dtrace_impl.h>
33#include <sys/cmn_err.h>
34#include <sys/regset.h>
35#include <sys/privregs.h>
36#include <sys/segments.h>
37#include <sys/x86_archext.h>
38#include <sys/sysmacros.h>
39#include <sys/trap.h>
40#include <sys/archsystm.h>
41
42/*
43 * Lossless User-Land Tracing on x86
44 * ---------------------------------
45 *
46 * The execution of most instructions is not dependent on the address; for
47 * these instructions it is sufficient to copy them into the user process's
48 * address space and execute them. To effectively single-step an instruction
49 * in user-land, we copy out the following sequence of instructions to scratch
50 * space in the user thread's ulwp_t structure.
51 *
52 * We then set the program counter (%eip or %rip) to point to this scratch
53 * space. Once execution resumes, the original instruction is executed and
54 * then control flow is redirected to what was originally the subsequent
55 * instruction. If the kernel attemps to deliver a signal while single-
56 * stepping, the signal is deferred and the program counter is moved into the
57 * second sequence of instructions. The second sequence ends in a trap into
58 * the kernel where the deferred signal is then properly handled and delivered.
59 *
60 * For instructions whose execute is position dependent, we perform simple
61 * emulation. These instructions are limited to control transfer
62 * instructions in 32-bit mode, but in 64-bit mode there's the added wrinkle
63 * of %rip-relative addressing that means that almost any instruction can be
64 * position dependent. For all the details on how we emulate generic
65 * instructions included %rip-relative instructions, see the code in
66 * fasttrap_pid_probe() below where we handle instructions of type
67 * FASTTRAP_T_COMMON (under the header: Generic Instruction Tracing).
68 */
69
70#define	FASTTRAP_MODRM_MOD(modrm)	(((modrm) >> 6) & 0x3)
71#define	FASTTRAP_MODRM_REG(modrm)	(((modrm) >> 3) & 0x7)
72#define	FASTTRAP_MODRM_RM(modrm)	((modrm) & 0x7)
73#define	FASTTRAP_MODRM(mod, reg, rm)	(((mod) << 6) | ((reg) << 3) | (rm))
74
75#define	FASTTRAP_SIB_SCALE(sib)		(((sib) >> 6) & 0x3)
76#define	FASTTRAP_SIB_INDEX(sib)		(((sib) >> 3) & 0x7)
77#define	FASTTRAP_SIB_BASE(sib)		((sib) & 0x7)
78
79#define	FASTTRAP_REX_W(rex)		(((rex) >> 3) & 1)
80#define	FASTTRAP_REX_R(rex)		(((rex) >> 2) & 1)
81#define	FASTTRAP_REX_X(rex)		(((rex) >> 1) & 1)
82#define	FASTTRAP_REX_B(rex)		((rex) & 1)
83#define	FASTTRAP_REX(w, r, x, b)	\
84	(0x40 | ((w) << 3) | ((r) << 2) | ((x) << 1) | (b))
85
86/*
87 * Single-byte op-codes.
88 */
89#define	FASTTRAP_PUSHL_EBP	0x55
90
91#define	FASTTRAP_JO		0x70
92#define	FASTTRAP_JNO		0x71
93#define	FASTTRAP_JB		0x72
94#define	FASTTRAP_JAE		0x73
95#define	FASTTRAP_JE		0x74
96#define	FASTTRAP_JNE		0x75
97#define	FASTTRAP_JBE		0x76
98#define	FASTTRAP_JA		0x77
99#define	FASTTRAP_JS		0x78
100#define	FASTTRAP_JNS		0x79
101#define	FASTTRAP_JP		0x7a
102#define	FASTTRAP_JNP		0x7b
103#define	FASTTRAP_JL		0x7c
104#define	FASTTRAP_JGE		0x7d
105#define	FASTTRAP_JLE		0x7e
106#define	FASTTRAP_JG		0x7f
107
108#define	FASTTRAP_NOP		0x90
109
110#define	FASTTRAP_MOV_EAX	0xb8
111#define	FASTTRAP_MOV_ECX	0xb9
112
113#define	FASTTRAP_RET16		0xc2
114#define	FASTTRAP_RET		0xc3
115
116#define	FASTTRAP_LOOPNZ		0xe0
117#define	FASTTRAP_LOOPZ		0xe1
118#define	FASTTRAP_LOOP		0xe2
119#define	FASTTRAP_JCXZ		0xe3
120
121#define	FASTTRAP_CALL		0xe8
122#define	FASTTRAP_JMP32		0xe9
123#define	FASTTRAP_JMP8		0xeb
124
125#define	FASTTRAP_INT3		0xcc
126#define	FASTTRAP_INT		0xcd
127
128#define	FASTTRAP_2_BYTE_OP	0x0f
129#define	FASTTRAP_GROUP5_OP	0xff
130
131/*
132 * Two-byte op-codes (second byte only).
133 */
134#define	FASTTRAP_0F_JO		0x80
135#define	FASTTRAP_0F_JNO		0x81
136#define	FASTTRAP_0F_JB		0x82
137#define	FASTTRAP_0F_JAE		0x83
138#define	FASTTRAP_0F_JE		0x84
139#define	FASTTRAP_0F_JNE		0x85
140#define	FASTTRAP_0F_JBE		0x86
141#define	FASTTRAP_0F_JA		0x87
142#define	FASTTRAP_0F_JS		0x88
143#define	FASTTRAP_0F_JNS		0x89
144#define	FASTTRAP_0F_JP		0x8a
145#define	FASTTRAP_0F_JNP		0x8b
146#define	FASTTRAP_0F_JL		0x8c
147#define	FASTTRAP_0F_JGE		0x8d
148#define	FASTTRAP_0F_JLE		0x8e
149#define	FASTTRAP_0F_JG		0x8f
150
151#define	FASTTRAP_EFLAGS_OF	0x800
152#define	FASTTRAP_EFLAGS_DF	0x400
153#define	FASTTRAP_EFLAGS_SF	0x080
154#define	FASTTRAP_EFLAGS_ZF	0x040
155#define	FASTTRAP_EFLAGS_AF	0x010
156#define	FASTTRAP_EFLAGS_PF	0x004
157#define	FASTTRAP_EFLAGS_CF	0x001
158
159/*
160 * Instruction prefixes.
161 */
162#define	FASTTRAP_PREFIX_OPERAND	0x66
163#define	FASTTRAP_PREFIX_ADDRESS	0x67
164#define	FASTTRAP_PREFIX_CS	0x2E
165#define	FASTTRAP_PREFIX_DS	0x3E
166#define	FASTTRAP_PREFIX_ES	0x26
167#define	FASTTRAP_PREFIX_FS	0x64
168#define	FASTTRAP_PREFIX_GS	0x65
169#define	FASTTRAP_PREFIX_SS	0x36
170#define	FASTTRAP_PREFIX_LOCK	0xF0
171#define	FASTTRAP_PREFIX_REP	0xF3
172#define	FASTTRAP_PREFIX_REPNE	0xF2
173
174#define	FASTTRAP_NOREG	0xff
175
176/*
177 * Map between instruction register encodings and the kernel constants which
178 * correspond to indicies into struct regs.
179 */
180#ifdef __amd64
181static const uint8_t regmap[16] = {
182	REG_RAX, REG_RCX, REG_RDX, REG_RBX, REG_RSP, REG_RBP, REG_RSI, REG_RDI,
183	REG_R8, REG_R9, REG_R10, REG_R11, REG_R12, REG_R13, REG_R14, REG_R15,
184};
185#else
186static const uint8_t regmap[8] = {
187	EAX, ECX, EDX, EBX, UESP, EBP, ESI, EDI
188};
189#endif
190
191static ulong_t fasttrap_getreg(struct regs *, uint_t);
192
193static uint64_t
194fasttrap_anarg(struct regs *rp, int function_entry, int argno)
195{
196	uint64_t value;
197	int shift = function_entry ? 1 : 0;
198
199#ifdef __amd64
200	if (curproc->p_model == DATAMODEL_LP64) {
201		uintptr_t *stack;
202
203		/*
204		 * In 64-bit mode, the first six arguments are stored in
205		 * registers.
206		 */
207		if (argno < 6)
208			return ((&rp->r_rdi)[argno]);
209
210		stack = (uintptr_t *)rp->r_sp;
211		DTRACE_CPUFLAG_SET(CPU_DTRACE_NOFAULT);
212		value = dtrace_fulword(&stack[argno - 6 + shift]);
213		DTRACE_CPUFLAG_CLEAR(CPU_DTRACE_NOFAULT | CPU_DTRACE_BADADDR);
214	} else {
215#endif
216		uint32_t *stack = (uint32_t *)rp->r_sp;
217		DTRACE_CPUFLAG_SET(CPU_DTRACE_NOFAULT);
218		value = dtrace_fuword32(&stack[argno + shift]);
219		DTRACE_CPUFLAG_CLEAR(CPU_DTRACE_NOFAULT | CPU_DTRACE_BADADDR);
220#ifdef __amd64
221	}
222#endif
223
224	return (value);
225}
226
227/*ARGSUSED*/
228int
229fasttrap_tracepoint_init(proc_t *p, fasttrap_tracepoint_t *tp, uintptr_t pc,
230    fasttrap_probe_type_t type)
231{
232	uint8_t instr[FASTTRAP_MAX_INSTR_SIZE + 10];
233	size_t len = FASTTRAP_MAX_INSTR_SIZE;
234	size_t first = MIN(len, PAGESIZE - (pc & PAGEOFFSET));
235	uint_t start = 0;
236	int rmindex, size;
237	uint8_t seg, rex = 0;
238
239	/*
240	 * Read the instruction at the given address out of the process's
241	 * address space. We don't have to worry about a debugger
242	 * changing this instruction before we overwrite it with our trap
243	 * instruction since P_PR_LOCK is set. Since instructions can span
244	 * pages, we potentially read the instruction in two parts. If the
245	 * second part fails, we just zero out that part of the instruction.
246	 */
247	if (uread(p, &instr[0], first, pc) != 0)
248		return (-1);
249	if (len > first &&
250	    uread(p, &instr[first], len - first, pc + first) != 0) {
251		bzero(&instr[first], len - first);
252		len = first;
253	}
254
255	/*
256	 * If the disassembly fails, then we have a malformed instruction.
257	 */
258	if ((size = dtrace_instr_size_isa(instr, p->p_model, &rmindex)) <= 0)
259		return (-1);
260
261	/*
262	 * Make sure the disassembler isn't completely broken.
263	 */
264	ASSERT(-1 <= rmindex && rmindex < size);
265
266	/*
267	 * If the computed size is greater than the number of bytes read,
268	 * then it was a malformed instruction possibly because it fell on a
269	 * page boundary and the subsequent page was missing or because of
270	 * some malicious user.
271	 */
272	if (size > len)
273		return (-1);
274
275	tp->ftt_size = (uint8_t)size;
276	tp->ftt_segment = FASTTRAP_SEG_NONE;
277
278	/*
279	 * Find the start of the instruction's opcode by processing any
280	 * legacy prefixes.
281	 */
282	for (;;) {
283		seg = 0;
284		switch (instr[start]) {
285		case FASTTRAP_PREFIX_SS:
286			seg++;
287			/*FALLTHRU*/
288		case FASTTRAP_PREFIX_GS:
289			seg++;
290			/*FALLTHRU*/
291		case FASTTRAP_PREFIX_FS:
292			seg++;
293			/*FALLTHRU*/
294		case FASTTRAP_PREFIX_ES:
295			seg++;
296			/*FALLTHRU*/
297		case FASTTRAP_PREFIX_DS:
298			seg++;
299			/*FALLTHRU*/
300		case FASTTRAP_PREFIX_CS:
301			seg++;
302			/*FALLTHRU*/
303		case FASTTRAP_PREFIX_OPERAND:
304		case FASTTRAP_PREFIX_ADDRESS:
305		case FASTTRAP_PREFIX_LOCK:
306		case FASTTRAP_PREFIX_REP:
307		case FASTTRAP_PREFIX_REPNE:
308			if (seg != 0) {
309				/*
310				 * It's illegal for an instruction to specify
311				 * two segment prefixes -- give up on this
312				 * illegal instruction.
313				 */
314				if (tp->ftt_segment != FASTTRAP_SEG_NONE)
315					return (-1);
316
317				tp->ftt_segment = seg;
318			}
319			start++;
320			continue;
321		}
322		break;
323	}
324
325#ifdef __amd64
326	/*
327	 * Identify the REX prefix on 64-bit processes.
328	 */
329	if (p->p_model == DATAMODEL_LP64 && (instr[start] & 0xf0) == 0x40)
330		rex = instr[start++];
331#endif
332
333	/*
334	 * Now that we're pretty sure that the instruction is okay, copy the
335	 * valid part to the tracepoint.
336	 */
337	bcopy(instr, tp->ftt_instr, FASTTRAP_MAX_INSTR_SIZE);
338
339	tp->ftt_type = FASTTRAP_T_COMMON;
340	if (instr[start] == FASTTRAP_2_BYTE_OP) {
341		switch (instr[start + 1]) {
342		case FASTTRAP_0F_JO:
343		case FASTTRAP_0F_JNO:
344		case FASTTRAP_0F_JB:
345		case FASTTRAP_0F_JAE:
346		case FASTTRAP_0F_JE:
347		case FASTTRAP_0F_JNE:
348		case FASTTRAP_0F_JBE:
349		case FASTTRAP_0F_JA:
350		case FASTTRAP_0F_JS:
351		case FASTTRAP_0F_JNS:
352		case FASTTRAP_0F_JP:
353		case FASTTRAP_0F_JNP:
354		case FASTTRAP_0F_JL:
355		case FASTTRAP_0F_JGE:
356		case FASTTRAP_0F_JLE:
357		case FASTTRAP_0F_JG:
358			tp->ftt_type = FASTTRAP_T_JCC;
359			tp->ftt_code = (instr[start + 1] & 0x0f) | FASTTRAP_JO;
360			tp->ftt_dest = pc + tp->ftt_size +
361			    /* LINTED - alignment */
362			    *(int32_t *)&instr[start + 2];
363			break;
364		}
365	} else if (instr[start] == FASTTRAP_GROUP5_OP) {
366		uint_t mod = FASTTRAP_MODRM_MOD(instr[start + 1]);
367		uint_t reg = FASTTRAP_MODRM_REG(instr[start + 1]);
368		uint_t rm = FASTTRAP_MODRM_RM(instr[start + 1]);
369
370		if (reg == 2 || reg == 4) {
371			uint_t i, sz;
372
373			if (reg == 2)
374				tp->ftt_type = FASTTRAP_T_CALL;
375			else
376				tp->ftt_type = FASTTRAP_T_JMP;
377
378			if (mod == 3)
379				tp->ftt_code = 2;
380			else
381				tp->ftt_code = 1;
382
383			ASSERT(p->p_model == DATAMODEL_LP64 || rex == 0);
384
385			/*
386			 * See AMD x86-64 Architecture Programmer's Manual
387			 * Volume 3, Section 1.2.7, Table 1-12, and
388			 * Appendix A.3.1, Table A-15.
389			 */
390			if (mod != 3 && rm == 4) {
391				uint8_t sib = instr[start + 2];
392				uint_t index = FASTTRAP_SIB_INDEX(sib);
393				uint_t base = FASTTRAP_SIB_BASE(sib);
394
395				tp->ftt_scale = FASTTRAP_SIB_SCALE(sib);
396
397				tp->ftt_index = (index == 4) ?
398				    FASTTRAP_NOREG :
399				    regmap[index | (FASTTRAP_REX_X(rex) << 3)];
400				tp->ftt_base = (mod == 0 && base == 5) ?
401				    FASTTRAP_NOREG :
402				    regmap[base | (FASTTRAP_REX_B(rex) << 3)];
403
404				i = 3;
405				sz = mod == 1 ? 1 : 4;
406			} else {
407				/*
408				 * In 64-bit mode, mod == 0 and r/m == 5
409				 * denotes %rip-relative addressing; in 32-bit
410				 * mode, the base register isn't used. In both
411				 * modes, there is a 32-bit operand.
412				 */
413				if (mod == 0 && rm == 5) {
414#ifdef __amd64
415					if (p->p_model == DATAMODEL_LP64)
416						tp->ftt_base = REG_RIP;
417					else
418#endif
419						tp->ftt_base = FASTTRAP_NOREG;
420					sz = 4;
421				} else  {
422					uint8_t base = rm |
423					    (FASTTRAP_REX_B(rex) << 3);
424
425					tp->ftt_base = regmap[base];
426					sz = mod == 1 ? 1 : mod == 2 ? 4 : 0;
427				}
428				tp->ftt_index = FASTTRAP_NOREG;
429				i = 2;
430			}
431
432			if (sz == 1) {
433				tp->ftt_dest = *(int8_t *)&instr[start + i];
434			} else if (sz == 4) {
435				/* LINTED - alignment */
436				tp->ftt_dest = *(int32_t *)&instr[start + i];
437			} else {
438				tp->ftt_dest = 0;
439			}
440		}
441	} else {
442		switch (instr[start]) {
443		case FASTTRAP_RET:
444			tp->ftt_type = FASTTRAP_T_RET;
445			break;
446
447		case FASTTRAP_RET16:
448			tp->ftt_type = FASTTRAP_T_RET16;
449			/* LINTED - alignment */
450			tp->ftt_dest = *(uint16_t *)&instr[start + 1];
451			break;
452
453		case FASTTRAP_JO:
454		case FASTTRAP_JNO:
455		case FASTTRAP_JB:
456		case FASTTRAP_JAE:
457		case FASTTRAP_JE:
458		case FASTTRAP_JNE:
459		case FASTTRAP_JBE:
460		case FASTTRAP_JA:
461		case FASTTRAP_JS:
462		case FASTTRAP_JNS:
463		case FASTTRAP_JP:
464		case FASTTRAP_JNP:
465		case FASTTRAP_JL:
466		case FASTTRAP_JGE:
467		case FASTTRAP_JLE:
468		case FASTTRAP_JG:
469			tp->ftt_type = FASTTRAP_T_JCC;
470			tp->ftt_code = instr[start];
471			tp->ftt_dest = pc + tp->ftt_size +
472			    (int8_t)instr[start + 1];
473			break;
474
475		case FASTTRAP_LOOPNZ:
476		case FASTTRAP_LOOPZ:
477		case FASTTRAP_LOOP:
478			tp->ftt_type = FASTTRAP_T_LOOP;
479			tp->ftt_code = instr[start];
480			tp->ftt_dest = pc + tp->ftt_size +
481			    (int8_t)instr[start + 1];
482			break;
483
484		case FASTTRAP_JCXZ:
485			tp->ftt_type = FASTTRAP_T_JCXZ;
486			tp->ftt_dest = pc + tp->ftt_size +
487			    (int8_t)instr[start + 1];
488			break;
489
490		case FASTTRAP_CALL:
491			tp->ftt_type = FASTTRAP_T_CALL;
492			tp->ftt_dest = pc + tp->ftt_size +
493			    /* LINTED - alignment */
494			    *(int32_t *)&instr[start + 1];
495			tp->ftt_code = 0;
496			break;
497
498		case FASTTRAP_JMP32:
499			tp->ftt_type = FASTTRAP_T_JMP;
500			tp->ftt_dest = pc + tp->ftt_size +
501			    /* LINTED - alignment */
502			    *(int32_t *)&instr[start + 1];
503			break;
504		case FASTTRAP_JMP8:
505			tp->ftt_type = FASTTRAP_T_JMP;
506			tp->ftt_dest = pc + tp->ftt_size +
507			    (int8_t)instr[start + 1];
508			break;
509
510		case FASTTRAP_PUSHL_EBP:
511			if (start == 0)
512				tp->ftt_type = FASTTRAP_T_PUSHL_EBP;
513			break;
514
515		case FASTTRAP_NOP:
516#ifdef __amd64
517			ASSERT(p->p_model == DATAMODEL_LP64 || rex == 0);
518
519			/*
520			 * On amd64 we have to be careful not to confuse a nop
521			 * (actually xchgl %eax, %eax) with an instruction using
522			 * the same opcode, but that does something different
523			 * (e.g. xchgl %r8d, %eax or xcghq %r8, %rax).
524			 */
525			if (FASTTRAP_REX_B(rex) == 0)
526#endif
527				tp->ftt_type = FASTTRAP_T_NOP;
528			break;
529
530		case FASTTRAP_INT3:
531			/*
532			 * The pid provider shares the int3 trap with debugger
533			 * breakpoints so we can't instrument them.
534			 */
535			ASSERT(instr[start] == FASTTRAP_INSTR);
536			return (-1);
537
538		case FASTTRAP_INT:
539			/*
540			 * Interrupts seem like they could be traced with
541			 * no negative implications, but it's possible that
542			 * a thread could be redirected by the trap handling
543			 * code which would eventually return to the
544			 * instruction after the interrupt. If the interrupt
545			 * were in our scratch space, the subsequent
546			 * instruction might be overwritten before we return.
547			 * Accordingly we refuse to instrument any interrupt.
548			 */
549			return (-1);
550		}
551	}
552
553#ifdef __amd64
554	if (p->p_model == DATAMODEL_LP64 && tp->ftt_type == FASTTRAP_T_COMMON) {
555		/*
556		 * If the process is 64-bit and the instruction type is still
557		 * FASTTRAP_T_COMMON -- meaning we're going to copy it out an
558		 * execute it -- we need to watch for %rip-relative
559		 * addressing mode. See the portion of fasttrap_pid_probe()
560		 * below where we handle tracepoints with type
561		 * FASTTRAP_T_COMMON for how we emulate instructions that
562		 * employ %rip-relative addressing.
563		 */
564		if (rmindex != -1) {
565			uint_t mod = FASTTRAP_MODRM_MOD(instr[rmindex]);
566			uint_t reg = FASTTRAP_MODRM_REG(instr[rmindex]);
567			uint_t rm = FASTTRAP_MODRM_RM(instr[rmindex]);
568
569			ASSERT(rmindex > start);
570
571			if (mod == 0 && rm == 5) {
572				/*
573				 * We need to be sure to avoid other
574				 * registers used by this instruction. While
575				 * the reg field may determine the op code
576				 * rather than denoting a register, assuming
577				 * that it denotes a register is always safe.
578				 * We leave the REX field intact and use
579				 * whatever value's there for simplicity.
580				 */
581				if (reg != 0) {
582					tp->ftt_ripmode = FASTTRAP_RIP_1 |
583					    (FASTTRAP_RIP_X *
584					    FASTTRAP_REX_B(rex));
585					rm = 0;
586				} else {
587					tp->ftt_ripmode = FASTTRAP_RIP_2 |
588					    (FASTTRAP_RIP_X *
589					    FASTTRAP_REX_B(rex));
590					rm = 1;
591				}
592
593				tp->ftt_modrm = tp->ftt_instr[rmindex];
594				tp->ftt_instr[rmindex] =
595				    FASTTRAP_MODRM(2, reg, rm);
596			}
597		}
598	}
599#endif
600
601	return (0);
602}
603
604int
605fasttrap_tracepoint_install(proc_t *p, fasttrap_tracepoint_t *tp)
606{
607	fasttrap_instr_t instr = FASTTRAP_INSTR;
608
609	if (uwrite(p, &instr, 1, tp->ftt_pc) != 0)
610		return (-1);
611
612	return (0);
613}
614
615int
616fasttrap_tracepoint_remove(proc_t *p, fasttrap_tracepoint_t *tp)
617{
618	uint8_t instr;
619
620	/*
621	 * Distinguish between read or write failures and a changed
622	 * instruction.
623	 */
624	if (uread(p, &instr, 1, tp->ftt_pc) != 0)
625		return (0);
626	if (instr != FASTTRAP_INSTR)
627		return (0);
628	if (uwrite(p, &tp->ftt_instr[0], 1, tp->ftt_pc) != 0)
629		return (-1);
630
631	return (0);
632}
633
634#ifdef __amd64
635static uintptr_t
636fasttrap_fulword_noerr(const void *uaddr)
637{
638	uintptr_t ret;
639
640	if (fasttrap_fulword(uaddr, &ret) == 0)
641		return (ret);
642
643	return (0);
644}
645#endif
646
647static uint32_t
648fasttrap_fuword32_noerr(const void *uaddr)
649{
650	uint32_t ret;
651
652	if (fasttrap_fuword32(uaddr, &ret) == 0)
653		return (ret);
654
655	return (0);
656}
657
658static void
659fasttrap_return_common(struct regs *rp, uintptr_t pc, pid_t pid,
660    uintptr_t new_pc)
661{
662	fasttrap_tracepoint_t *tp;
663	fasttrap_bucket_t *bucket;
664	fasttrap_id_t *id;
665	kmutex_t *pid_mtx;
666
667	pid_mtx = &cpu_core[CPU->cpu_id].cpuc_pid_lock;
668	mutex_enter(pid_mtx);
669	bucket = &fasttrap_tpoints.fth_table[FASTTRAP_TPOINTS_INDEX(pid, pc)];
670
671	for (tp = bucket->ftb_data; tp != NULL; tp = tp->ftt_next) {
672		if (pid == tp->ftt_pid && pc == tp->ftt_pc &&
673		    tp->ftt_proc->ftpc_acount != 0)
674			break;
675	}
676
677	/*
678	 * Don't sweat it if we can't find the tracepoint again; unlike
679	 * when we're in fasttrap_pid_probe(), finding the tracepoint here
680	 * is not essential to the correct execution of the process.
681	 */
682	if (tp == NULL) {
683		mutex_exit(pid_mtx);
684		return;
685	}
686
687	for (id = tp->ftt_retids; id != NULL; id = id->fti_next) {
688		/*
689		 * If there's a branch that could act as a return site, we
690		 * need to trace it, and check here if the program counter is
691		 * external to the function.
692		 */
693		if (tp->ftt_type != FASTTRAP_T_RET &&
694		    tp->ftt_type != FASTTRAP_T_RET16 &&
695		    new_pc - id->fti_probe->ftp_faddr <
696		    id->fti_probe->ftp_fsize)
697			continue;
698
699		dtrace_probe(id->fti_probe->ftp_id,
700		    pc - id->fti_probe->ftp_faddr,
701		    rp->r_r0, rp->r_r1, 0, 0);
702	}
703
704	mutex_exit(pid_mtx);
705}
706
707static void
708fasttrap_sigsegv(proc_t *p, kthread_t *t, uintptr_t addr)
709{
710	sigqueue_t *sqp = kmem_zalloc(sizeof (sigqueue_t), KM_SLEEP);
711
712	sqp->sq_info.si_signo = SIGSEGV;
713	sqp->sq_info.si_code = SEGV_MAPERR;
714	sqp->sq_info.si_addr = (caddr_t)addr;
715
716	mutex_enter(&p->p_lock);
717	sigaddqa(p, t, sqp);
718	mutex_exit(&p->p_lock);
719
720	if (t != NULL)
721		aston(t);
722}
723
724#ifdef __amd64
725static void
726fasttrap_usdt_args64(fasttrap_probe_t *probe, struct regs *rp, int argc,
727    uintptr_t *argv)
728{
729	int i, x, cap = MIN(argc, probe->ftp_nargs);
730	uintptr_t *stack = (uintptr_t *)rp->r_sp;
731
732	for (i = 0; i < cap; i++) {
733		x = probe->ftp_argmap[i];
734
735		if (x < 6)
736			argv[i] = (&rp->r_rdi)[x];
737		else
738			argv[i] = fasttrap_fulword_noerr(&stack[x]);
739	}
740
741	for (; i < argc; i++) {
742		argv[i] = 0;
743	}
744}
745#endif
746
747static void
748fasttrap_usdt_args32(fasttrap_probe_t *probe, struct regs *rp, int argc,
749    uint32_t *argv)
750{
751	int i, x, cap = MIN(argc, probe->ftp_nargs);
752	uint32_t *stack = (uint32_t *)rp->r_sp;
753
754	for (i = 0; i < cap; i++) {
755		x = probe->ftp_argmap[i];
756
757		argv[i] = fasttrap_fuword32_noerr(&stack[x]);
758	}
759
760	for (; i < argc; i++) {
761		argv[i] = 0;
762	}
763}
764
765static int
766fasttrap_do_seg(fasttrap_tracepoint_t *tp, struct regs *rp, uintptr_t *addr)
767{
768	proc_t *p = curproc;
769	user_desc_t *desc;
770	uint16_t sel, ndx, type;
771	uintptr_t limit;
772
773	switch (tp->ftt_segment) {
774	case FASTTRAP_SEG_CS:
775		sel = rp->r_cs;
776		break;
777	case FASTTRAP_SEG_DS:
778		sel = rp->r_ds;
779		break;
780	case FASTTRAP_SEG_ES:
781		sel = rp->r_es;
782		break;
783	case FASTTRAP_SEG_FS:
784		sel = rp->r_fs;
785		break;
786	case FASTTRAP_SEG_GS:
787		sel = rp->r_gs;
788		break;
789	case FASTTRAP_SEG_SS:
790		sel = rp->r_ss;
791		break;
792	}
793
794	/*
795	 * Make sure the given segment register specifies a user priority
796	 * selector rather than a kernel selector.
797	 */
798	if (!SELISUPL(sel))
799		return (-1);
800
801	ndx = SELTOIDX(sel);
802
803	/*
804	 * Check the bounds and grab the descriptor out of the specified
805	 * descriptor table.
806	 */
807	if (SELISLDT(sel)) {
808		if (ndx > p->p_ldtlimit)
809			return (-1);
810
811		desc = p->p_ldt + ndx;
812
813	} else {
814		if (ndx >= NGDT)
815			return (-1);
816
817		desc = cpu_get_gdt() + ndx;
818	}
819
820	/*
821	 * The descriptor must have user privilege level and it must be
822	 * present in memory.
823	 */
824	if (desc->usd_dpl != SEL_UPL || desc->usd_p != 1)
825		return (-1);
826
827	type = desc->usd_type;
828
829	/*
830	 * If the S bit in the type field is not set, this descriptor can
831	 * only be used in system context.
832	 */
833	if ((type & 0x10) != 0x10)
834		return (-1);
835
836	limit = USEGD_GETLIMIT(desc) * (desc->usd_gran ? PAGESIZE : 1);
837
838	if (tp->ftt_segment == FASTTRAP_SEG_CS) {
839		/*
840		 * The code/data bit and readable bit must both be set.
841		 */
842		if ((type & 0xa) != 0xa)
843			return (-1);
844
845		if (*addr > limit)
846			return (-1);
847	} else {
848		/*
849		 * The code/data bit must be clear.
850		 */
851		if ((type & 0x8) != 0)
852			return (-1);
853
854		/*
855		 * If the expand-down bit is clear, we just check the limit as
856		 * it would naturally be applied. Otherwise, we need to check
857		 * that the address is the range [limit + 1 .. 0xffff] or
858		 * [limit + 1 ... 0xffffffff] depending on if the default
859		 * operand size bit is set.
860		 */
861		if ((type & 0x4) == 0) {
862			if (*addr > limit)
863				return (-1);
864		} else if (desc->usd_def32) {
865			if (*addr < limit + 1 || 0xffff < *addr)
866				return (-1);
867		} else {
868			if (*addr < limit + 1 || 0xffffffff < *addr)
869				return (-1);
870		}
871	}
872
873	*addr += USEGD_GETBASE(desc);
874
875	return (0);
876}
877
878int
879fasttrap_pid_probe(struct regs *rp)
880{
881	proc_t *p = curproc;
882	uintptr_t pc = rp->r_pc - 1, new_pc = 0;
883	fasttrap_bucket_t *bucket;
884	kmutex_t *pid_mtx;
885	fasttrap_tracepoint_t *tp, tp_local;
886	pid_t pid;
887	dtrace_icookie_t cookie;
888	uint_t is_enabled = 0;
889
890	/*
891	 * It's possible that a user (in a veritable orgy of bad planning)
892	 * could redirect this thread's flow of control before it reached the
893	 * return probe fasttrap. In this case we need to kill the process
894	 * since it's in a unrecoverable state.
895	 */
896	if (curthread->t_dtrace_step) {
897		ASSERT(curthread->t_dtrace_on);
898		fasttrap_sigtrap(p, curthread, pc);
899		return (0);
900	}
901
902	/*
903	 * Clear all user tracing flags.
904	 */
905	curthread->t_dtrace_ft = 0;
906	curthread->t_dtrace_pc = 0;
907	curthread->t_dtrace_npc = 0;
908	curthread->t_dtrace_scrpc = 0;
909	curthread->t_dtrace_astpc = 0;
910#ifdef __amd64
911	curthread->t_dtrace_regv = 0;
912#endif
913
914	/*
915	 * Treat a child created by a call to vfork(2) as if it were its
916	 * parent. We know that there's only one thread of control in such a
917	 * process: this one.
918	 */
919	while (p->p_flag & SVFORK) {
920		p = p->p_parent;
921	}
922
923	pid = p->p_pid;
924	pid_mtx = &cpu_core[CPU->cpu_id].cpuc_pid_lock;
925	mutex_enter(pid_mtx);
926	bucket = &fasttrap_tpoints.fth_table[FASTTRAP_TPOINTS_INDEX(pid, pc)];
927
928	/*
929	 * Lookup the tracepoint that the process just hit.
930	 */
931	for (tp = bucket->ftb_data; tp != NULL; tp = tp->ftt_next) {
932		if (pid == tp->ftt_pid && pc == tp->ftt_pc &&
933		    tp->ftt_proc->ftpc_acount != 0)
934			break;
935	}
936
937	/*
938	 * If we couldn't find a matching tracepoint, either a tracepoint has
939	 * been inserted without using the pid<pid> ioctl interface (see
940	 * fasttrap_ioctl), or somehow we have mislaid this tracepoint.
941	 */
942	if (tp == NULL) {
943		mutex_exit(pid_mtx);
944		return (-1);
945	}
946
947	/*
948	 * Set the program counter to the address of the traced instruction
949	 * so that it looks right in ustack() output.
950	 */
951	rp->r_pc = pc;
952
953	if (tp->ftt_ids != NULL) {
954		fasttrap_id_t *id;
955
956#ifdef __amd64
957		if (p->p_model == DATAMODEL_LP64) {
958			for (id = tp->ftt_ids; id != NULL; id = id->fti_next) {
959				fasttrap_probe_t *probe = id->fti_probe;
960
961				if (id->fti_ptype == DTFTP_ENTRY) {
962					/*
963					 * We note that this was an entry
964					 * probe to help ustack() find the
965					 * first caller.
966					 */
967					cookie = dtrace_interrupt_disable();
968					DTRACE_CPUFLAG_SET(CPU_DTRACE_ENTRY);
969					dtrace_probe(probe->ftp_id, rp->r_rdi,
970					    rp->r_rsi, rp->r_rdx, rp->r_rcx,
971					    rp->r_r8);
972					DTRACE_CPUFLAG_CLEAR(CPU_DTRACE_ENTRY);
973					dtrace_interrupt_enable(cookie);
974				} else if (id->fti_ptype == DTFTP_IS_ENABLED) {
975					/*
976					 * Note that in this case, we don't
977					 * call dtrace_probe() since it's only
978					 * an artificial probe meant to change
979					 * the flow of control so that it
980					 * encounters the true probe.
981					 */
982					is_enabled = 1;
983				} else if (probe->ftp_argmap == NULL) {
984					dtrace_probe(probe->ftp_id, rp->r_rdi,
985					    rp->r_rsi, rp->r_rdx, rp->r_rcx,
986					    rp->r_r8);
987				} else {
988					uintptr_t t[5];
989
990					fasttrap_usdt_args64(probe, rp,
991					    sizeof (t) / sizeof (t[0]), t);
992
993					dtrace_probe(probe->ftp_id, t[0], t[1],
994					    t[2], t[3], t[4]);
995				}
996			}
997		} else {
998#endif
999			uintptr_t s0, s1, s2, s3, s4, s5;
1000			uint32_t *stack = (uint32_t *)rp->r_sp;
1001
1002			/*
1003			 * In 32-bit mode, all arguments are passed on the
1004			 * stack. If this is a function entry probe, we need
1005			 * to skip the first entry on the stack as it
1006			 * represents the return address rather than a
1007			 * parameter to the function.
1008			 */
1009			s0 = fasttrap_fuword32_noerr(&stack[0]);
1010			s1 = fasttrap_fuword32_noerr(&stack[1]);
1011			s2 = fasttrap_fuword32_noerr(&stack[2]);
1012			s3 = fasttrap_fuword32_noerr(&stack[3]);
1013			s4 = fasttrap_fuword32_noerr(&stack[4]);
1014			s5 = fasttrap_fuword32_noerr(&stack[5]);
1015
1016			for (id = tp->ftt_ids; id != NULL; id = id->fti_next) {
1017				fasttrap_probe_t *probe = id->fti_probe;
1018
1019				if (id->fti_ptype == DTFTP_ENTRY) {
1020					/*
1021					 * We note that this was an entry
1022					 * probe to help ustack() find the
1023					 * first caller.
1024					 */
1025					cookie = dtrace_interrupt_disable();
1026					DTRACE_CPUFLAG_SET(CPU_DTRACE_ENTRY);
1027					dtrace_probe(probe->ftp_id, s1, s2,
1028					    s3, s4, s5);
1029					DTRACE_CPUFLAG_CLEAR(CPU_DTRACE_ENTRY);
1030					dtrace_interrupt_enable(cookie);
1031				} else if (id->fti_ptype == DTFTP_IS_ENABLED) {
1032					/*
1033					 * Note that in this case, we don't
1034					 * call dtrace_probe() since it's only
1035					 * an artificial probe meant to change
1036					 * the flow of control so that it
1037					 * encounters the true probe.
1038					 */
1039					is_enabled = 1;
1040				} else if (probe->ftp_argmap == NULL) {
1041					dtrace_probe(probe->ftp_id, s0, s1,
1042					    s2, s3, s4);
1043				} else {
1044					uint32_t t[5];
1045
1046					fasttrap_usdt_args32(probe, rp,
1047					    sizeof (t) / sizeof (t[0]), t);
1048
1049					dtrace_probe(probe->ftp_id, t[0], t[1],
1050					    t[2], t[3], t[4]);
1051				}
1052			}
1053#ifdef __amd64
1054		}
1055#endif
1056	}
1057
1058	/*
1059	 * We're about to do a bunch of work so we cache a local copy of
1060	 * the tracepoint to emulate the instruction, and then find the
1061	 * tracepoint again later if we need to light up any return probes.
1062	 */
1063	tp_local = *tp;
1064	mutex_exit(pid_mtx);
1065	tp = &tp_local;
1066
1067	/*
1068	 * Set the program counter to appear as though the traced instruction
1069	 * had completely executed. This ensures that fasttrap_getreg() will
1070	 * report the expected value for REG_RIP.
1071	 */
1072	rp->r_pc = pc + tp->ftt_size;
1073
1074	/*
1075	 * If there's an is-enabled probe connected to this tracepoint it
1076	 * means that there was a 'xorl %eax, %eax' or 'xorq %rax, %rax'
1077	 * instruction that was placed there by DTrace when the binary was
1078	 * linked. As this probe is, in fact, enabled, we need to stuff 1
1079	 * into %eax or %rax. Accordingly, we can bypass all the instruction
1080	 * emulation logic since we know the inevitable result. It's possible
1081	 * that a user could construct a scenario where the 'is-enabled'
1082	 * probe was on some other instruction, but that would be a rather
1083	 * exotic way to shoot oneself in the foot.
1084	 */
1085	if (is_enabled) {
1086		rp->r_r0 = 1;
1087		new_pc = rp->r_pc;
1088		goto done;
1089	}
1090
1091	/*
1092	 * We emulate certain types of instructions to ensure correctness
1093	 * (in the case of position dependent instructions) or optimize
1094	 * common cases. The rest we have the thread execute back in user-
1095	 * land.
1096	 */
1097	switch (tp->ftt_type) {
1098	case FASTTRAP_T_RET:
1099	case FASTTRAP_T_RET16:
1100	{
1101		uintptr_t dst;
1102		uintptr_t addr;
1103		int ret;
1104
1105		/*
1106		 * We have to emulate _every_ facet of the behavior of a ret
1107		 * instruction including what happens if the load from %esp
1108		 * fails; in that case, we send a SIGSEGV.
1109		 */
1110#ifdef __amd64
1111		if (p->p_model == DATAMODEL_NATIVE) {
1112#endif
1113			ret = fasttrap_fulword((void *)rp->r_sp, &dst);
1114			addr = rp->r_sp + sizeof (uintptr_t);
1115#ifdef __amd64
1116		} else {
1117			uint32_t dst32;
1118			ret = fasttrap_fuword32((void *)rp->r_sp, &dst32);
1119			dst = dst32;
1120			addr = rp->r_sp + sizeof (uint32_t);
1121		}
1122#endif
1123
1124		if (ret == -1) {
1125			fasttrap_sigsegv(p, curthread, rp->r_sp);
1126			new_pc = pc;
1127			break;
1128		}
1129
1130		if (tp->ftt_type == FASTTRAP_T_RET16)
1131			addr += tp->ftt_dest;
1132
1133		rp->r_sp = addr;
1134		new_pc = dst;
1135		break;
1136	}
1137
1138	case FASTTRAP_T_JCC:
1139	{
1140		uint_t taken;
1141
1142		switch (tp->ftt_code) {
1143		case FASTTRAP_JO:
1144			taken = (rp->r_ps & FASTTRAP_EFLAGS_OF) != 0;
1145			break;
1146		case FASTTRAP_JNO:
1147			taken = (rp->r_ps & FASTTRAP_EFLAGS_OF) == 0;
1148			break;
1149		case FASTTRAP_JB:
1150			taken = (rp->r_ps & FASTTRAP_EFLAGS_CF) != 0;
1151			break;
1152		case FASTTRAP_JAE:
1153			taken = (rp->r_ps & FASTTRAP_EFLAGS_CF) == 0;
1154			break;
1155		case FASTTRAP_JE:
1156			taken = (rp->r_ps & FASTTRAP_EFLAGS_ZF) != 0;
1157			break;
1158		case FASTTRAP_JNE:
1159			taken = (rp->r_ps & FASTTRAP_EFLAGS_ZF) == 0;
1160			break;
1161		case FASTTRAP_JBE:
1162			taken = (rp->r_ps & FASTTRAP_EFLAGS_CF) != 0 ||
1163			    (rp->r_ps & FASTTRAP_EFLAGS_ZF) != 0;
1164			break;
1165		case FASTTRAP_JA:
1166			taken = (rp->r_ps & FASTTRAP_EFLAGS_CF) == 0 &&
1167			    (rp->r_ps & FASTTRAP_EFLAGS_ZF) == 0;
1168			break;
1169		case FASTTRAP_JS:
1170			taken = (rp->r_ps & FASTTRAP_EFLAGS_SF) != 0;
1171			break;
1172		case FASTTRAP_JNS:
1173			taken = (rp->r_ps & FASTTRAP_EFLAGS_SF) == 0;
1174			break;
1175		case FASTTRAP_JP:
1176			taken = (rp->r_ps & FASTTRAP_EFLAGS_PF) != 0;
1177			break;
1178		case FASTTRAP_JNP:
1179			taken = (rp->r_ps & FASTTRAP_EFLAGS_PF) == 0;
1180			break;
1181		case FASTTRAP_JL:
1182			taken = ((rp->r_ps & FASTTRAP_EFLAGS_SF) == 0) !=
1183			    ((rp->r_ps & FASTTRAP_EFLAGS_OF) == 0);
1184			break;
1185		case FASTTRAP_JGE:
1186			taken = ((rp->r_ps & FASTTRAP_EFLAGS_SF) == 0) ==
1187			    ((rp->r_ps & FASTTRAP_EFLAGS_OF) == 0);
1188			break;
1189		case FASTTRAP_JLE:
1190			taken = (rp->r_ps & FASTTRAP_EFLAGS_ZF) != 0 ||
1191			    ((rp->r_ps & FASTTRAP_EFLAGS_SF) == 0) !=
1192			    ((rp->r_ps & FASTTRAP_EFLAGS_OF) == 0);
1193			break;
1194		case FASTTRAP_JG:
1195			taken = (rp->r_ps & FASTTRAP_EFLAGS_ZF) == 0 &&
1196			    ((rp->r_ps & FASTTRAP_EFLAGS_SF) == 0) ==
1197			    ((rp->r_ps & FASTTRAP_EFLAGS_OF) == 0);
1198			break;
1199
1200		}
1201
1202		if (taken)
1203			new_pc = tp->ftt_dest;
1204		else
1205			new_pc = pc + tp->ftt_size;
1206		break;
1207	}
1208
1209	case FASTTRAP_T_LOOP:
1210	{
1211		uint_t taken;
1212#ifdef __amd64
1213		greg_t cx = rp->r_rcx--;
1214#else
1215		greg_t cx = rp->r_ecx--;
1216#endif
1217
1218		switch (tp->ftt_code) {
1219		case FASTTRAP_LOOPNZ:
1220			taken = (rp->r_ps & FASTTRAP_EFLAGS_ZF) == 0 &&
1221			    cx != 0;
1222			break;
1223		case FASTTRAP_LOOPZ:
1224			taken = (rp->r_ps & FASTTRAP_EFLAGS_ZF) != 0 &&
1225			    cx != 0;
1226			break;
1227		case FASTTRAP_LOOP:
1228			taken = (cx != 0);
1229			break;
1230		}
1231
1232		if (taken)
1233			new_pc = tp->ftt_dest;
1234		else
1235			new_pc = pc + tp->ftt_size;
1236		break;
1237	}
1238
1239	case FASTTRAP_T_JCXZ:
1240	{
1241#ifdef __amd64
1242		greg_t cx = rp->r_rcx;
1243#else
1244		greg_t cx = rp->r_ecx;
1245#endif
1246
1247		if (cx == 0)
1248			new_pc = tp->ftt_dest;
1249		else
1250			new_pc = pc + tp->ftt_size;
1251		break;
1252	}
1253
1254	case FASTTRAP_T_PUSHL_EBP:
1255	{
1256		int ret;
1257		uintptr_t addr;
1258#ifdef __amd64
1259		if (p->p_model == DATAMODEL_NATIVE) {
1260#endif
1261			addr = rp->r_sp - sizeof (uintptr_t);
1262			ret = fasttrap_sulword((void *)addr, rp->r_fp);
1263#ifdef __amd64
1264		} else {
1265			addr = rp->r_sp - sizeof (uint32_t);
1266			ret = fasttrap_suword32((void *)addr,
1267			    (uint32_t)rp->r_fp);
1268		}
1269#endif
1270
1271		if (ret == -1) {
1272			fasttrap_sigsegv(p, curthread, addr);
1273			new_pc = pc;
1274			break;
1275		}
1276
1277		rp->r_sp = addr;
1278		new_pc = pc + tp->ftt_size;
1279		break;
1280	}
1281
1282	case FASTTRAP_T_NOP:
1283		new_pc = pc + tp->ftt_size;
1284		break;
1285
1286	case FASTTRAP_T_JMP:
1287	case FASTTRAP_T_CALL:
1288		if (tp->ftt_code == 0) {
1289			new_pc = tp->ftt_dest;
1290		} else {
1291			uintptr_t value, addr = tp->ftt_dest;
1292
1293			if (tp->ftt_base != FASTTRAP_NOREG)
1294				addr += fasttrap_getreg(rp, tp->ftt_base);
1295			if (tp->ftt_index != FASTTRAP_NOREG)
1296				addr += fasttrap_getreg(rp, tp->ftt_index) <<
1297				    tp->ftt_scale;
1298
1299			if (tp->ftt_code == 1) {
1300				/*
1301				 * If there's a segment prefix for this
1302				 * instruction, we'll need to check permissions
1303				 * and bounds on the given selector, and adjust
1304				 * the address accordingly.
1305				 */
1306				if (tp->ftt_segment != FASTTRAP_SEG_NONE &&
1307				    fasttrap_do_seg(tp, rp, &addr) != 0) {
1308					fasttrap_sigsegv(p, curthread, addr);
1309					new_pc = pc;
1310					break;
1311				}
1312
1313#ifdef __amd64
1314				if (p->p_model == DATAMODEL_NATIVE) {
1315#endif
1316					if (fasttrap_fulword((void *)addr,
1317					    &value) == -1) {
1318						fasttrap_sigsegv(p, curthread,
1319						    addr);
1320						new_pc = pc;
1321						break;
1322					}
1323					new_pc = value;
1324#ifdef __amd64
1325				} else {
1326					uint32_t value32;
1327					addr = (uintptr_t)(uint32_t)addr;
1328					if (fasttrap_fuword32((void *)addr,
1329					    &value32) == -1) {
1330						fasttrap_sigsegv(p, curthread,
1331						    addr);
1332						new_pc = pc;
1333						break;
1334					}
1335					new_pc = value32;
1336				}
1337#endif
1338			} else {
1339				new_pc = addr;
1340			}
1341		}
1342
1343		/*
1344		 * If this is a call instruction, we need to push the return
1345		 * address onto the stack. If this fails, we send the process
1346		 * a SIGSEGV and reset the pc to emulate what would happen if
1347		 * this instruction weren't traced.
1348		 */
1349		if (tp->ftt_type == FASTTRAP_T_CALL) {
1350			int ret;
1351			uintptr_t addr;
1352#ifdef __amd64
1353			if (p->p_model == DATAMODEL_NATIVE) {
1354				addr = rp->r_sp - sizeof (uintptr_t);
1355				ret = fasttrap_sulword((void *)addr,
1356				    pc + tp->ftt_size);
1357			} else {
1358#endif
1359				addr = rp->r_sp - sizeof (uint32_t);
1360				ret = fasttrap_suword32((void *)addr,
1361				    (uint32_t)(pc + tp->ftt_size));
1362#ifdef __amd64
1363			}
1364#endif
1365
1366			if (ret == -1) {
1367				fasttrap_sigsegv(p, curthread, addr);
1368				new_pc = pc;
1369				break;
1370			}
1371
1372			rp->r_sp = addr;
1373		}
1374
1375		break;
1376
1377	case FASTTRAP_T_COMMON:
1378	{
1379		uintptr_t addr;
1380#if defined(__amd64)
1381		uint8_t scratch[2 * FASTTRAP_MAX_INSTR_SIZE + 22];
1382#else
1383		uint8_t scratch[2 * FASTTRAP_MAX_INSTR_SIZE + 7];
1384#endif
1385		uint_t i = 0;
1386		klwp_t *lwp = ttolwp(curthread);
1387
1388		/*
1389		 * Compute the address of the ulwp_t and step over the
1390		 * ul_self pointer. The method used to store the user-land
1391		 * thread pointer is very different on 32- and 64-bit
1392		 * kernels.
1393		 */
1394#if defined(__amd64)
1395		if (p->p_model == DATAMODEL_LP64) {
1396			addr = lwp->lwp_pcb.pcb_fsbase;
1397			addr += sizeof (void *);
1398		} else {
1399			addr = lwp->lwp_pcb.pcb_gsbase;
1400			addr += sizeof (caddr32_t);
1401		}
1402#else
1403		addr = USEGD_GETBASE(&lwp->lwp_pcb.pcb_gsdesc);
1404		addr += sizeof (void *);
1405#endif
1406
1407		/*
1408		 * Generic Instruction Tracing
1409		 * ---------------------------
1410		 *
1411		 * This is the layout of the scratch space in the user-land
1412		 * thread structure for our generated instructions.
1413		 *
1414		 *	32-bit mode			bytes
1415		 *	------------------------	-----
1416		 * a:	<original instruction>		<= 15
1417		 *	jmp	<pc + tp->ftt_size>	    5
1418		 * b:	<original instrction>		<= 15
1419		 *	int	T_DTRACE_RET		    2
1420		 *					-----
1421		 *					<= 37
1422		 *
1423		 *	64-bit mode			bytes
1424		 *	------------------------	-----
1425		 * a:	<original instruction>		<= 15
1426		 *	jmp	0(%rip)			    6
1427		 *	<pc + tp->ftt_size>		    8
1428		 * b:	<original instruction>		<= 15
1429		 * 	int	T_DTRACE_RET		    2
1430		 * 					-----
1431		 * 					<= 46
1432		 *
1433		 * The %pc is set to a, and curthread->t_dtrace_astpc is set
1434		 * to b. If we encounter a signal on the way out of the
1435		 * kernel, trap() will set %pc to curthread->t_dtrace_astpc
1436		 * so that we execute the original instruction and re-enter
1437		 * the kernel rather than redirecting to the next instruction.
1438		 *
1439		 * If there are return probes (so we know that we're going to
1440		 * need to reenter the kernel after executing the original
1441		 * instruction), the scratch space will just contain the
1442		 * original instruction followed by an interrupt -- the same
1443		 * data as at b.
1444		 *
1445		 * %rip-relative Addressing
1446		 * ------------------------
1447		 *
1448		 * There's a further complication in 64-bit mode due to %rip-
1449		 * relative addressing. While this is clearly a beneficial
1450		 * architectural decision for position independent code, it's
1451		 * hard not to see it as a personal attack against the pid
1452		 * provider since before there was a relatively small set of
1453		 * instructions to emulate; with %rip-relative addressing,
1454		 * almost every instruction can potentially depend on the
1455		 * address at which it's executed. Rather than emulating
1456		 * the broad spectrum of instructions that can now be
1457		 * position dependent, we emulate jumps and others as in
1458		 * 32-bit mode, and take a different tack for instructions
1459		 * using %rip-relative addressing.
1460		 *
1461		 * For every instruction that uses the ModRM byte, the
1462		 * in-kernel disassembler reports its location. We use the
1463		 * ModRM byte to identify that an instruction uses
1464		 * %rip-relative addressing and to see what other registers
1465		 * the instruction uses. To emulate those instructions,
1466		 * we modify the instruction to be %rax-relative rather than
1467		 * %rip-relative (or %rcx-relative if the instruction uses
1468		 * %rax; or %r8- or %r9-relative if the REX.B is present so
1469		 * we don't have to rewrite the REX prefix). We then load
1470		 * the value that %rip would have been into the scratch
1471		 * register and generate an instruction to reset the scratch
1472		 * register back to its original value. The instruction
1473		 * sequence looks like this:
1474		 *
1475		 *	64-mode %rip-relative		bytes
1476		 *	------------------------	-----
1477		 * a:	<modified instruction>		<= 15
1478		 *	movq	$<value>, %<scratch>	    6
1479		 *	jmp	0(%rip)			    6
1480		 *	<pc + tp->ftt_size>		    8
1481		 * b:	<modified instruction>  	<= 15
1482		 * 	int	T_DTRACE_RET		    2
1483		 * 					-----
1484		 *					   52
1485		 *
1486		 * We set curthread->t_dtrace_regv so that upon receiving
1487		 * a signal we can reset the value of the scratch register.
1488		 */
1489
1490		ASSERT(tp->ftt_size < FASTTRAP_MAX_INSTR_SIZE);
1491
1492		curthread->t_dtrace_scrpc = addr;
1493		bcopy(tp->ftt_instr, &scratch[i], tp->ftt_size);
1494		i += tp->ftt_size;
1495
1496#ifdef __amd64
1497		if (tp->ftt_ripmode != 0) {
1498			greg_t *reg;
1499
1500			ASSERT(p->p_model == DATAMODEL_LP64);
1501			ASSERT(tp->ftt_ripmode &
1502			    (FASTTRAP_RIP_1 | FASTTRAP_RIP_2));
1503
1504			/*
1505			 * If this was a %rip-relative instruction, we change
1506			 * it to be either a %rax- or %rcx-relative
1507			 * instruction (depending on whether those registers
1508			 * are used as another operand; or %r8- or %r9-
1509			 * relative depending on the value of REX.B). We then
1510			 * set that register and generate a movq instruction
1511			 * to reset the value.
1512			 */
1513			if (tp->ftt_ripmode & FASTTRAP_RIP_X)
1514				scratch[i++] = FASTTRAP_REX(1, 0, 0, 1);
1515			else
1516				scratch[i++] = FASTTRAP_REX(1, 0, 0, 0);
1517
1518			if (tp->ftt_ripmode & FASTTRAP_RIP_1)
1519				scratch[i++] = FASTTRAP_MOV_EAX;
1520			else
1521				scratch[i++] = FASTTRAP_MOV_ECX;
1522
1523			switch (tp->ftt_ripmode) {
1524			case FASTTRAP_RIP_1:
1525				reg = &rp->r_rax;
1526				curthread->t_dtrace_reg = REG_RAX;
1527				break;
1528			case FASTTRAP_RIP_2:
1529				reg = &rp->r_rcx;
1530				curthread->t_dtrace_reg = REG_RCX;
1531				break;
1532			case FASTTRAP_RIP_1 | FASTTRAP_RIP_X:
1533				reg = &rp->r_r8;
1534				curthread->t_dtrace_reg = REG_R8;
1535				break;
1536			case FASTTRAP_RIP_2 | FASTTRAP_RIP_X:
1537				reg = &rp->r_r9;
1538				curthread->t_dtrace_reg = REG_R9;
1539				break;
1540			}
1541
1542			/* LINTED - alignment */
1543			*(uint64_t *)&scratch[i] = *reg;
1544			curthread->t_dtrace_regv = *reg;
1545			*reg = pc + tp->ftt_size;
1546			i += sizeof (uint64_t);
1547		}
1548#endif
1549
1550		/*
1551		 * Generate the branch instruction to what would have
1552		 * normally been the subsequent instruction. In 32-bit mode,
1553		 * this is just a relative branch; in 64-bit mode this is a
1554		 * %rip-relative branch that loads the 64-bit pc value
1555		 * immediately after the jmp instruction.
1556		 */
1557#ifdef __amd64
1558		if (p->p_model == DATAMODEL_LP64) {
1559			scratch[i++] = FASTTRAP_GROUP5_OP;
1560			scratch[i++] = FASTTRAP_MODRM(0, 4, 5);
1561			/* LINTED - alignment */
1562			*(uint32_t *)&scratch[i] = 0;
1563			i += sizeof (uint32_t);
1564			/* LINTED - alignment */
1565			*(uint64_t *)&scratch[i] = pc + tp->ftt_size;
1566			i += sizeof (uint64_t);
1567		} else {
1568#endif
1569			/*
1570			 * Set up the jmp to the next instruction; note that
1571			 * the size of the traced instruction cancels out.
1572			 */
1573			scratch[i++] = FASTTRAP_JMP32;
1574			/* LINTED - alignment */
1575			*(uint32_t *)&scratch[i] = pc - addr - 5;
1576			i += sizeof (uint32_t);
1577#ifdef __amd64
1578		}
1579#endif
1580
1581		curthread->t_dtrace_astpc = addr + i;
1582		bcopy(tp->ftt_instr, &scratch[i], tp->ftt_size);
1583		i += tp->ftt_size;
1584		scratch[i++] = FASTTRAP_INT;
1585		scratch[i++] = T_DTRACE_RET;
1586
1587		ASSERT(i <= sizeof (scratch));
1588
1589		if (fasttrap_copyout(scratch, (char *)addr, i)) {
1590			fasttrap_sigtrap(p, curthread, pc);
1591			new_pc = pc;
1592			break;
1593		}
1594
1595		if (tp->ftt_retids != NULL) {
1596			curthread->t_dtrace_step = 1;
1597			curthread->t_dtrace_ret = 1;
1598			new_pc = curthread->t_dtrace_astpc;
1599		} else {
1600			new_pc = curthread->t_dtrace_scrpc;
1601		}
1602
1603		curthread->t_dtrace_pc = pc;
1604		curthread->t_dtrace_npc = pc + tp->ftt_size;
1605		curthread->t_dtrace_on = 1;
1606		break;
1607	}
1608
1609	default:
1610		panic("fasttrap: mishandled an instruction");
1611	}
1612
1613done:
1614	/*
1615	 * If there were no return probes when we first found the tracepoint,
1616	 * we should feel no obligation to honor any return probes that were
1617	 * subsequently enabled -- they'll just have to wait until the next
1618	 * time around.
1619	 */
1620	if (tp->ftt_retids != NULL) {
1621		/*
1622		 * We need to wait until the results of the instruction are
1623		 * apparent before invoking any return probes. If this
1624		 * instruction was emulated we can just call
1625		 * fasttrap_return_common(); if it needs to be executed, we
1626		 * need to wait until the user thread returns to the kernel.
1627		 */
1628		if (tp->ftt_type != FASTTRAP_T_COMMON) {
1629			/*
1630			 * Set the program counter to the address of the traced
1631			 * instruction so that it looks right in ustack()
1632			 * output. We had previously set it to the end of the
1633			 * instruction to simplify %rip-relative addressing.
1634			 */
1635			rp->r_pc = pc;
1636
1637			fasttrap_return_common(rp, pc, pid, new_pc);
1638		} else {
1639			ASSERT(curthread->t_dtrace_ret != 0);
1640			ASSERT(curthread->t_dtrace_pc == pc);
1641			ASSERT(curthread->t_dtrace_scrpc != 0);
1642			ASSERT(new_pc == curthread->t_dtrace_astpc);
1643		}
1644	}
1645
1646	rp->r_pc = new_pc;
1647
1648	return (0);
1649}
1650
1651int
1652fasttrap_return_probe(struct regs *rp)
1653{
1654	proc_t *p = curproc;
1655	uintptr_t pc = curthread->t_dtrace_pc;
1656	uintptr_t npc = curthread->t_dtrace_npc;
1657
1658	curthread->t_dtrace_pc = 0;
1659	curthread->t_dtrace_npc = 0;
1660	curthread->t_dtrace_scrpc = 0;
1661	curthread->t_dtrace_astpc = 0;
1662
1663	/*
1664	 * Treat a child created by a call to vfork(2) as if it were its
1665	 * parent. We know that there's only one thread of control in such a
1666	 * process: this one.
1667	 */
1668	while (p->p_flag & SVFORK) {
1669		p = p->p_parent;
1670	}
1671
1672	/*
1673	 * We set rp->r_pc to the address of the traced instruction so
1674	 * that it appears to dtrace_probe() that we're on the original
1675	 * instruction, and so that the user can't easily detect our
1676	 * complex web of lies. dtrace_return_probe() (our caller)
1677	 * will correctly set %pc after we return.
1678	 */
1679	rp->r_pc = pc;
1680
1681	fasttrap_return_common(rp, pc, p->p_pid, npc);
1682
1683	return (0);
1684}
1685
1686/*ARGSUSED*/
1687uint64_t
1688fasttrap_pid_getarg(void *arg, dtrace_id_t id, void *parg, int argno,
1689    int aframes)
1690{
1691	return (fasttrap_anarg(ttolwp(curthread)->lwp_regs, 1, argno));
1692}
1693
1694/*ARGSUSED*/
1695uint64_t
1696fasttrap_usdt_getarg(void *arg, dtrace_id_t id, void *parg, int argno,
1697    int aframes)
1698{
1699	return (fasttrap_anarg(ttolwp(curthread)->lwp_regs, 0, argno));
1700}
1701
1702static ulong_t
1703fasttrap_getreg(struct regs *rp, uint_t reg)
1704{
1705#ifdef __amd64
1706	switch (reg) {
1707	case REG_R15:		return (rp->r_r15);
1708	case REG_R14:		return (rp->r_r14);
1709	case REG_R13:		return (rp->r_r13);
1710	case REG_R12:		return (rp->r_r12);
1711	case REG_R11:		return (rp->r_r11);
1712	case REG_R10:		return (rp->r_r10);
1713	case REG_R9:		return (rp->r_r9);
1714	case REG_R8:		return (rp->r_r8);
1715	case REG_RDI:		return (rp->r_rdi);
1716	case REG_RSI:		return (rp->r_rsi);
1717	case REG_RBP:		return (rp->r_rbp);
1718	case REG_RBX:		return (rp->r_rbx);
1719	case REG_RDX:		return (rp->r_rdx);
1720	case REG_RCX:		return (rp->r_rcx);
1721	case REG_RAX:		return (rp->r_rax);
1722	case REG_TRAPNO:	return (rp->r_trapno);
1723	case REG_ERR:		return (rp->r_err);
1724	case REG_RIP:		return (rp->r_rip);
1725	case REG_CS:		return (rp->r_cs);
1726	case REG_RFL:		return (rp->r_rfl);
1727	case REG_RSP:		return (rp->r_rsp);
1728	case REG_SS:		return (rp->r_ss);
1729	case REG_FS:		return (rp->r_fs);
1730	case REG_GS:		return (rp->r_gs);
1731	case REG_DS:		return (rp->r_ds);
1732	case REG_ES:		return (rp->r_es);
1733	case REG_FSBASE:	return (rdmsr(MSR_AMD_FSBASE));
1734	case REG_GSBASE:	return (rdmsr(MSR_AMD_GSBASE));
1735	}
1736
1737	panic("dtrace: illegal register constant");
1738	/*NOTREACHED*/
1739#else
1740	if (reg >= _NGREG)
1741		panic("dtrace: illegal register constant");
1742
1743	return (((greg_t *)&rp->r_gs)[reg]);
1744#endif
1745}
1746