17c478bd9Sstevel@tonic-gate /* 27c478bd9Sstevel@tonic-gate * CDDL HEADER START 37c478bd9Sstevel@tonic-gate * 47c478bd9Sstevel@tonic-gate * The contents of this file are subject to the terms of the 541791439Sandrei * Common Development and Distribution License (the "License"). 641791439Sandrei * You may not use this file except in compliance with the License. 77c478bd9Sstevel@tonic-gate * 87c478bd9Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 97c478bd9Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 107c478bd9Sstevel@tonic-gate * See the License for the specific language governing permissions 117c478bd9Sstevel@tonic-gate * and limitations under the License. 127c478bd9Sstevel@tonic-gate * 137c478bd9Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 147c478bd9Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 157c478bd9Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 167c478bd9Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 177c478bd9Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 187c478bd9Sstevel@tonic-gate * 197c478bd9Sstevel@tonic-gate * CDDL HEADER END 207c478bd9Sstevel@tonic-gate */ 217c478bd9Sstevel@tonic-gate /* 220d928757SGary Mills * Copyright (c) 2012 Gary Mills 230d928757SGary Mills * 247417cfdeSKuriakose Kuruvilla * Copyright (c) 1993, 2010, Oracle and/or its affiliates. All rights reserved. 25cfe84b82SMatt Amdur * Copyright (c) 2011 by Delphix. All rights reserved. 26*74ecdb51SJohn Levon * Copyright 2018 Joyent, Inc. 277c478bd9Sstevel@tonic-gate */ 28a3114836SGerry Liu /* 29a3114836SGerry Liu * Copyright (c) 2010, Intel Corporation. 30a3114836SGerry Liu * All rights reserved. 31a3114836SGerry Liu */ 327c478bd9Sstevel@tonic-gate 337c478bd9Sstevel@tonic-gate #include <sys/types.h> 34ae115bc7Smrj #include <sys/sysmacros.h> 357c478bd9Sstevel@tonic-gate #include <sys/disp.h> 367c478bd9Sstevel@tonic-gate #include <sys/promif.h> 377c478bd9Sstevel@tonic-gate #include <sys/clock.h> 387c478bd9Sstevel@tonic-gate #include <sys/cpuvar.h> 397c478bd9Sstevel@tonic-gate #include <sys/stack.h> 407c478bd9Sstevel@tonic-gate #include <vm/as.h> 417c478bd9Sstevel@tonic-gate #include <vm/hat.h> 427c478bd9Sstevel@tonic-gate #include <sys/reboot.h> 437c478bd9Sstevel@tonic-gate #include <sys/avintr.h> 447c478bd9Sstevel@tonic-gate #include <sys/vtrace.h> 457c478bd9Sstevel@tonic-gate #include <sys/proc.h> 467c478bd9Sstevel@tonic-gate #include <sys/thread.h> 477c478bd9Sstevel@tonic-gate #include <sys/cpupart.h> 487c478bd9Sstevel@tonic-gate #include <sys/pset.h> 497c478bd9Sstevel@tonic-gate #include <sys/copyops.h> 50fb2f18f8Sesaxe #include <sys/pg.h> 517c478bd9Sstevel@tonic-gate #include <sys/disp.h> 527c478bd9Sstevel@tonic-gate #include <sys/debug.h> 537c478bd9Sstevel@tonic-gate #include <sys/sunddi.h> 547c478bd9Sstevel@tonic-gate #include <sys/x86_archext.h> 557c478bd9Sstevel@tonic-gate #include <sys/privregs.h> 567c478bd9Sstevel@tonic-gate #include <sys/machsystm.h> 577c478bd9Sstevel@tonic-gate #include <sys/ontrap.h> 587c478bd9Sstevel@tonic-gate #include <sys/bootconf.h> 599db7147eSSherry Moore #include <sys/boot_console.h> 60ae115bc7Smrj #include <sys/kdi_machimpl.h> 617c478bd9Sstevel@tonic-gate #include <sys/archsystm.h> 627c478bd9Sstevel@tonic-gate #include <sys/promif.h> 63c88420b3Sdmick #include <sys/pci_cfgspace.h> 640181461bSKeith M Wesolowski #include <sys/bootvfs.h> 652428aad8SPatrick Mooney #include <sys/tsc.h> 66843e1988Sjohnlev #ifdef __xpv 67843e1988Sjohnlev #include <sys/hypervisor.h> 68349b53ddSStuart Maybee #else 69349b53ddSStuart Maybee #include <sys/xpv_support.h> 70843e1988Sjohnlev #endif 717c478bd9Sstevel@tonic-gate 727c478bd9Sstevel@tonic-gate /* 737c478bd9Sstevel@tonic-gate * some globals for patching the result of cpuid 747c478bd9Sstevel@tonic-gate * to solve problems w/ creative cpu vendors 757c478bd9Sstevel@tonic-gate */ 767c478bd9Sstevel@tonic-gate 777c478bd9Sstevel@tonic-gate extern uint32_t cpuid_feature_ecx_include; 787c478bd9Sstevel@tonic-gate extern uint32_t cpuid_feature_ecx_exclude; 797c478bd9Sstevel@tonic-gate extern uint32_t cpuid_feature_edx_include; 807c478bd9Sstevel@tonic-gate extern uint32_t cpuid_feature_edx_exclude; 817c478bd9Sstevel@tonic-gate 829db7147eSSherry Moore /* 839db7147eSSherry Moore * Set console mode 849db7147eSSherry Moore */ 859db7147eSSherry Moore static void 869db7147eSSherry Moore set_console_mode(uint8_t val) 879db7147eSSherry Moore { 889db7147eSSherry Moore struct bop_regs rp = {0}; 899db7147eSSherry Moore 909db7147eSSherry Moore rp.eax.byte.ah = 0x0; 919db7147eSSherry Moore rp.eax.byte.al = val; 929db7147eSSherry Moore rp.ebx.word.bx = 0x0; 939db7147eSSherry Moore 949db7147eSSherry Moore BOP_DOINT(bootops, 0x10, &rp); 959db7147eSSherry Moore } 969db7147eSSherry Moore 977c478bd9Sstevel@tonic-gate 987c478bd9Sstevel@tonic-gate /* 997c478bd9Sstevel@tonic-gate * Setup routine called right before main(). Interposing this function 1007c478bd9Sstevel@tonic-gate * before main() allows us to call it in a machine-independent fashion. 1017c478bd9Sstevel@tonic-gate */ 1027c478bd9Sstevel@tonic-gate void 1037c478bd9Sstevel@tonic-gate mlsetup(struct regs *rp) 1047c478bd9Sstevel@tonic-gate { 1052baa66a0SJonathan Chew u_longlong_t prop_value; 1067c478bd9Sstevel@tonic-gate extern struct classfuncs sys_classfuncs; 1077c478bd9Sstevel@tonic-gate extern disp_t cpu0_disp; 1087c478bd9Sstevel@tonic-gate extern char t0stack[]; 1099db7147eSSherry Moore extern int post_fastreboot; 110a3114836SGerry Liu extern uint64_t plat_dr_options; 1117c478bd9Sstevel@tonic-gate 1127c478bd9Sstevel@tonic-gate ASSERT_STACK_ALIGNED(); 1137c478bd9Sstevel@tonic-gate 1147c478bd9Sstevel@tonic-gate /* 1157c478bd9Sstevel@tonic-gate * initialize cpu_self 1167c478bd9Sstevel@tonic-gate */ 1177c478bd9Sstevel@tonic-gate cpu[0]->cpu_self = cpu[0]; 1187c478bd9Sstevel@tonic-gate 119843e1988Sjohnlev #if defined(__xpv) 120843e1988Sjohnlev /* 121843e1988Sjohnlev * Point at the hypervisor's virtual cpu structure 122843e1988Sjohnlev */ 123843e1988Sjohnlev cpu[0]->cpu_m.mcpu_vcpu_info = &HYPERVISOR_shared_info->vcpu_info[0]; 124843e1988Sjohnlev #endif 125843e1988Sjohnlev 1267c478bd9Sstevel@tonic-gate /* 1277c478bd9Sstevel@tonic-gate * check if we've got special bits to clear or set 1287c478bd9Sstevel@tonic-gate * when checking cpu features 1297c478bd9Sstevel@tonic-gate */ 1307c478bd9Sstevel@tonic-gate 1312baa66a0SJonathan Chew if (bootprop_getval("cpuid_feature_ecx_include", &prop_value) != 0) 1322baa66a0SJonathan Chew cpuid_feature_ecx_include = 0; 1332baa66a0SJonathan Chew else 1342baa66a0SJonathan Chew cpuid_feature_ecx_include = (uint32_t)prop_value; 1352baa66a0SJonathan Chew 1362baa66a0SJonathan Chew if (bootprop_getval("cpuid_feature_ecx_exclude", &prop_value) != 0) 1372baa66a0SJonathan Chew cpuid_feature_ecx_exclude = 0; 1382baa66a0SJonathan Chew else 1392baa66a0SJonathan Chew cpuid_feature_ecx_exclude = (uint32_t)prop_value; 1402baa66a0SJonathan Chew 1412baa66a0SJonathan Chew if (bootprop_getval("cpuid_feature_edx_include", &prop_value) != 0) 1422baa66a0SJonathan Chew cpuid_feature_edx_include = 0; 1432baa66a0SJonathan Chew else 1442baa66a0SJonathan Chew cpuid_feature_edx_include = (uint32_t)prop_value; 1452baa66a0SJonathan Chew 1462baa66a0SJonathan Chew if (bootprop_getval("cpuid_feature_edx_exclude", &prop_value) != 0) 1472baa66a0SJonathan Chew cpuid_feature_edx_exclude = 0; 1482baa66a0SJonathan Chew else 1492baa66a0SJonathan Chew cpuid_feature_edx_exclude = (uint32_t)prop_value; 1507c478bd9Sstevel@tonic-gate 151*74ecdb51SJohn Levon #if !defined(__xpv) 152*74ecdb51SJohn Levon /* 153*74ecdb51SJohn Levon * Check to see if KPTI has been explicitly enabled or disabled. 154*74ecdb51SJohn Levon * We have to check this before init_desctbls(). 155*74ecdb51SJohn Levon */ 156*74ecdb51SJohn Levon if (bootprop_getval("kpti", &prop_value) == 0) { 157*74ecdb51SJohn Levon kpti_enable = (uint64_t)(prop_value == 1); 158*74ecdb51SJohn Levon prom_printf("unix: forcing kpti to %s due to boot argument\n", 159*74ecdb51SJohn Levon (kpti_enable == 1) ? "ON" : "OFF"); 160*74ecdb51SJohn Levon } else { 161*74ecdb51SJohn Levon kpti_enable = 1; 162*74ecdb51SJohn Levon } 163*74ecdb51SJohn Levon 164*74ecdb51SJohn Levon if (bootprop_getval("pcid", &prop_value) == 0 && prop_value == 0) { 165*74ecdb51SJohn Levon prom_printf("unix: forcing pcid to OFF due to boot argument\n"); 166*74ecdb51SJohn Levon x86_use_pcid = 0; 167*74ecdb51SJohn Levon } else if (kpti_enable != 1) { 168*74ecdb51SJohn Levon x86_use_pcid = 0; 169*74ecdb51SJohn Levon } 170*74ecdb51SJohn Levon #endif 171*74ecdb51SJohn Levon 17245e032f7SDan Mick /* 17345e032f7SDan Mick * Initialize idt0, gdt0, ldt0_default, ktss0 and dftss. 17445e032f7SDan Mick */ 17545e032f7SDan Mick init_desctbls(); 17645e032f7SDan Mick 17745e032f7SDan Mick /* 17845e032f7SDan Mick * lgrp_init() and possibly cpuid_pass1() need PCI config 17945e032f7SDan Mick * space access 18045e032f7SDan Mick */ 18145e032f7SDan Mick #if defined(__xpv) 18245e032f7SDan Mick if (DOMAIN_IS_INITDOMAIN(xen_info)) 18345e032f7SDan Mick pci_cfgspace_init(); 18445e032f7SDan Mick #else 18545e032f7SDan Mick pci_cfgspace_init(); 186cfe84b82SMatt Amdur /* 187cfe84b82SMatt Amdur * Initialize the platform type from CPU 0 to ensure that 188cfe84b82SMatt Amdur * determine_platform() is only ever called once. 189cfe84b82SMatt Amdur */ 190cfe84b82SMatt Amdur determine_platform(); 19145e032f7SDan Mick #endif 19245e032f7SDan Mick 1937c478bd9Sstevel@tonic-gate /* 1947c478bd9Sstevel@tonic-gate * The first lightweight pass (pass0) through the cpuid data 1957c478bd9Sstevel@tonic-gate * was done in locore before mlsetup was called. Do the next 1967c478bd9Sstevel@tonic-gate * pass in C code. 1977c478bd9Sstevel@tonic-gate * 1987417cfdeSKuriakose Kuruvilla * The x86_featureset is initialized here based on the capabilities 1997c478bd9Sstevel@tonic-gate * of the boot CPU. Note that if we choose to support CPUs that have 2007c478bd9Sstevel@tonic-gate * different feature sets (at which point we would almost certainly 2017c478bd9Sstevel@tonic-gate * want to set the feature bits to correspond to the feature 2027c478bd9Sstevel@tonic-gate * minimum) this value may be altered. 2037c478bd9Sstevel@tonic-gate */ 204dfea898aSKuriakose Kuruvilla cpuid_pass1(cpu[0], x86_featureset); 2057c478bd9Sstevel@tonic-gate 206247dbb3dSsudheer #if !defined(__xpv) 20779ec9da8SYuri Pankov if ((get_hwenv() & HW_XEN_HVM) != 0) 208349b53ddSStuart Maybee xen_hvm_init(); 209349b53ddSStuart Maybee 2104948216cSKeith M Wesolowski /* 2114948216cSKeith M Wesolowski * Before we do anything with the TSCs, we need to work around 2124948216cSKeith M Wesolowski * Intel erratum BT81. On some CPUs, warm reset does not 2134948216cSKeith M Wesolowski * clear the TSC. If we are on such a CPU, we will clear TSC ourselves 2144948216cSKeith M Wesolowski * here. Other CPUs will clear it when we boot them later, and the 2154948216cSKeith M Wesolowski * resulting skew will be handled by tsc_sync_master()/_slave(); 2164948216cSKeith M Wesolowski * note that such skew already exists and has to be handled anyway. 2174948216cSKeith M Wesolowski * 2184948216cSKeith M Wesolowski * We do this only on metal. This same problem can occur with a 2194948216cSKeith M Wesolowski * hypervisor that does not happen to virtualise a TSC that starts from 2204948216cSKeith M Wesolowski * zero, regardless of CPU type; however, we do not expect hypervisors 2214948216cSKeith M Wesolowski * that do not virtualise TSC that way to handle writes to TSC 2224948216cSKeith M Wesolowski * correctly, either. 2234948216cSKeith M Wesolowski */ 2244948216cSKeith M Wesolowski if (get_hwenv() == HW_NATIVE && 2254948216cSKeith M Wesolowski cpuid_getvendor(CPU) == X86_VENDOR_Intel && 2264948216cSKeith M Wesolowski cpuid_getfamily(CPU) == 6 && 2274948216cSKeith M Wesolowski (cpuid_getmodel(CPU) == 0x2d || cpuid_getmodel(CPU) == 0x3e) && 2284948216cSKeith M Wesolowski is_x86_feature(x86_featureset, X86FSET_TSC)) { 2294948216cSKeith M Wesolowski (void) wrmsr(REG_TSC, 0UL); 2304948216cSKeith M Wesolowski } 2314948216cSKeith M Wesolowski 232247dbb3dSsudheer /* 233247dbb3dSsudheer * Patch the tsc_read routine with appropriate set of instructions, 234247dbb3dSsudheer * depending on the processor family and architecure, to read the 235247dbb3dSsudheer * time-stamp counter while ensuring no out-of-order execution. 236247dbb3dSsudheer * Patch it while the kernel text is still writable. 237247dbb3dSsudheer * 238247dbb3dSsudheer * Note: tsc_read is not patched for intel processors whose family 239247dbb3dSsudheer * is >6 and for amd whose family >f (in case they don't support rdtscp 240247dbb3dSsudheer * instruction, unlikely). By default tsc_read will use cpuid for 241247dbb3dSsudheer * serialization in such cases. The following code needs to be 242247dbb3dSsudheer * revisited if intel processors of family >= f retains the 243247dbb3dSsudheer * instruction serialization nature of mfence instruction. 2442b0bcb26Ssudheer * Note: tsc_read is not patched for x86 processors which do 2452b0bcb26Ssudheer * not support "mfence". By default tsc_read will use cpuid for 2462b0bcb26Ssudheer * serialization in such cases. 247551bc2a6Smrj * 248551bc2a6Smrj * The Xen hypervisor does not correctly report whether rdtscp is 249551bc2a6Smrj * supported or not, so we must assume that it is not. 250247dbb3dSsudheer */ 25179ec9da8SYuri Pankov if ((get_hwenv() & HW_XEN_HVM) == 0 && 2527417cfdeSKuriakose Kuruvilla is_x86_feature(x86_featureset, X86FSET_TSCP)) 2532428aad8SPatrick Mooney patch_tsc_read(TSC_TSCP); 254247dbb3dSsudheer else if (cpuid_getvendor(CPU) == X86_VENDOR_AMD && 2557417cfdeSKuriakose Kuruvilla cpuid_getfamily(CPU) <= 0xf && 2567417cfdeSKuriakose Kuruvilla is_x86_feature(x86_featureset, X86FSET_SSE2)) 2572428aad8SPatrick Mooney patch_tsc_read(TSC_RDTSC_MFENCE); 258247dbb3dSsudheer else if (cpuid_getvendor(CPU) == X86_VENDOR_Intel && 2597417cfdeSKuriakose Kuruvilla cpuid_getfamily(CPU) <= 6 && 2607417cfdeSKuriakose Kuruvilla is_x86_feature(x86_featureset, X86FSET_SSE2)) 2612428aad8SPatrick Mooney patch_tsc_read(TSC_RDTSC_LFENCE); 262247dbb3dSsudheer 263247dbb3dSsudheer #endif /* !__xpv */ 2647c478bd9Sstevel@tonic-gate 265843e1988Sjohnlev #if defined(__i386) && !defined(__xpv) 2667c478bd9Sstevel@tonic-gate /* 2677c478bd9Sstevel@tonic-gate * Some i386 processors do not implement the rdtsc instruction, 268247dbb3dSsudheer * or at least they do not implement it correctly. Patch them to 269247dbb3dSsudheer * return 0. 2707c478bd9Sstevel@tonic-gate */ 2717417cfdeSKuriakose Kuruvilla if (!is_x86_feature(x86_featureset, X86FSET_TSC)) 2722428aad8SPatrick Mooney patch_tsc_read(TSC_NONE); 273843e1988Sjohnlev #endif /* __i386 && !__xpv */ 274843e1988Sjohnlev 27522cc0e45SBill Holler #if defined(__amd64) && !defined(__xpv) 27622cc0e45SBill Holler patch_memops(cpuid_getvendor(CPU)); 27722cc0e45SBill Holler #endif /* __amd64 && !__xpv */ 27822cc0e45SBill Holler 279843e1988Sjohnlev #if !defined(__xpv) 280843e1988Sjohnlev /* XXPV what, if anything, should be dorked with here under xen? */ 281ae115bc7Smrj 282ae115bc7Smrj /* 283ae115bc7Smrj * While we're thinking about the TSC, let's set up %cr4 so that 284ae115bc7Smrj * userland can issue rdtsc, and initialize the TSC_AUX value 285ae115bc7Smrj * (the cpuid) for the rdtscp instruction on appropriately 286ae115bc7Smrj * capable hardware. 287ae115bc7Smrj */ 2887417cfdeSKuriakose Kuruvilla if (is_x86_feature(x86_featureset, X86FSET_TSC)) 289ae115bc7Smrj setcr4(getcr4() & ~CR4_TSD); 290ae115bc7Smrj 2917417cfdeSKuriakose Kuruvilla if (is_x86_feature(x86_featureset, X86FSET_TSCP)) 292ae115bc7Smrj (void) wrmsr(MSR_AMD_TSCAUX, 0); 293ae115bc7Smrj 294799823bbSRobert Mustacchi /* 2953ce2fcdcSRobert Mustacchi * Let's get the other %cr4 stuff while we're here. Note, we defer 2963ce2fcdcSRobert Mustacchi * enabling CR4_SMAP until startup_end(); however, that's importantly 2973ce2fcdcSRobert Mustacchi * before we start other CPUs. That ensures that it will be synced out 2983ce2fcdcSRobert Mustacchi * to other CPUs. 299799823bbSRobert Mustacchi */ 3007417cfdeSKuriakose Kuruvilla if (is_x86_feature(x86_featureset, X86FSET_DE)) 301ae115bc7Smrj setcr4(getcr4() | CR4_DE); 302799823bbSRobert Mustacchi 303799823bbSRobert Mustacchi if (is_x86_feature(x86_featureset, X86FSET_SMEP)) 304799823bbSRobert Mustacchi setcr4(getcr4() | CR4_SMEP); 305843e1988Sjohnlev #endif /* __xpv */ 3067c478bd9Sstevel@tonic-gate 3077c478bd9Sstevel@tonic-gate /* 3087c478bd9Sstevel@tonic-gate * initialize t0 3097c478bd9Sstevel@tonic-gate */ 3107c478bd9Sstevel@tonic-gate t0.t_stk = (caddr_t)rp - MINFRAME; 3117c478bd9Sstevel@tonic-gate t0.t_stkbase = t0stack; 3127c478bd9Sstevel@tonic-gate t0.t_pri = maxclsyspri - 3; 3137c478bd9Sstevel@tonic-gate t0.t_schedflag = TS_LOAD | TS_DONT_SWAP; 3147c478bd9Sstevel@tonic-gate t0.t_procp = &p0; 3157c478bd9Sstevel@tonic-gate t0.t_plockp = &p0lock.pl_lock; 3167c478bd9Sstevel@tonic-gate t0.t_lwp = &lwp0; 3177c478bd9Sstevel@tonic-gate t0.t_forw = &t0; 3187c478bd9Sstevel@tonic-gate t0.t_back = &t0; 3197c478bd9Sstevel@tonic-gate t0.t_next = &t0; 3207c478bd9Sstevel@tonic-gate t0.t_prev = &t0; 3217c478bd9Sstevel@tonic-gate t0.t_cpu = cpu[0]; 3227c478bd9Sstevel@tonic-gate t0.t_disp_queue = &cpu0_disp; 3237c478bd9Sstevel@tonic-gate t0.t_bind_cpu = PBIND_NONE; 3247c478bd9Sstevel@tonic-gate t0.t_bind_pset = PS_NONE; 3250b70c467Sakolb t0.t_bindflag = (uchar_t)default_binding_mode; 3267c478bd9Sstevel@tonic-gate t0.t_cpupart = &cp_default; 3277c478bd9Sstevel@tonic-gate t0.t_clfuncs = &sys_classfuncs.thread; 3287c478bd9Sstevel@tonic-gate t0.t_copyops = NULL; 3297c478bd9Sstevel@tonic-gate THREAD_ONPROC(&t0, CPU); 3307c478bd9Sstevel@tonic-gate 3317c478bd9Sstevel@tonic-gate lwp0.lwp_thread = &t0; 332ae115bc7Smrj lwp0.lwp_regs = (void *)rp; 3337c478bd9Sstevel@tonic-gate lwp0.lwp_procp = &p0; 3347c478bd9Sstevel@tonic-gate t0.t_tid = p0.p_lwpcnt = p0.p_lwprcnt = p0.p_lwpid = 1; 3357c478bd9Sstevel@tonic-gate 3367c478bd9Sstevel@tonic-gate p0.p_exec = NULL; 3377c478bd9Sstevel@tonic-gate p0.p_stat = SRUN; 3387c478bd9Sstevel@tonic-gate p0.p_flag = SSYS; 3397c478bd9Sstevel@tonic-gate p0.p_tlist = &t0; 3407c478bd9Sstevel@tonic-gate p0.p_stksize = 2*PAGESIZE; 3417c478bd9Sstevel@tonic-gate p0.p_stkpageszc = 0; 3427c478bd9Sstevel@tonic-gate p0.p_as = &kas; 3437c478bd9Sstevel@tonic-gate p0.p_lockp = &p0lock; 3447c478bd9Sstevel@tonic-gate p0.p_brkpageszc = 0; 3452cb27123Saguzovsk p0.p_t1_lgrpid = LGRP_NONE; 3462cb27123Saguzovsk p0.p_tr_lgrpid = LGRP_NONE; 347d2a70789SRichard Lowe psecflags_default(&p0.p_secflags); 348d2a70789SRichard Lowe 3497c478bd9Sstevel@tonic-gate sigorset(&p0.p_ignore, &ignoredefault); 3507c478bd9Sstevel@tonic-gate 3517c478bd9Sstevel@tonic-gate CPU->cpu_thread = &t0; 3527c478bd9Sstevel@tonic-gate bzero(&cpu0_disp, sizeof (disp_t)); 3537c478bd9Sstevel@tonic-gate CPU->cpu_disp = &cpu0_disp; 3547c478bd9Sstevel@tonic-gate CPU->cpu_disp->disp_cpu = CPU; 3557c478bd9Sstevel@tonic-gate CPU->cpu_dispthread = &t0; 3567c478bd9Sstevel@tonic-gate CPU->cpu_idle_thread = &t0; 3577c478bd9Sstevel@tonic-gate CPU->cpu_flags = CPU_READY | CPU_RUNNING | CPU_EXISTS | CPU_ENABLE; 3587c478bd9Sstevel@tonic-gate CPU->cpu_dispatch_pri = t0.t_pri; 3597c478bd9Sstevel@tonic-gate 3607c478bd9Sstevel@tonic-gate CPU->cpu_id = 0; 3617c478bd9Sstevel@tonic-gate 3627c478bd9Sstevel@tonic-gate CPU->cpu_pri = 12; /* initial PIL for the boot CPU */ 3637c478bd9Sstevel@tonic-gate 3647c478bd9Sstevel@tonic-gate /* 3650baeff3dSrab * The kernel doesn't use LDTs unless a process explicitly requests one. 3667c478bd9Sstevel@tonic-gate */ 367843e1988Sjohnlev p0.p_ldt_desc = null_sdesc; 3687c478bd9Sstevel@tonic-gate 3697c478bd9Sstevel@tonic-gate /* 370ae115bc7Smrj * Initialize thread/cpu microstate accounting 3717c478bd9Sstevel@tonic-gate */ 3727c478bd9Sstevel@tonic-gate init_mstate(&t0, LMS_SYSTEM); 3737c478bd9Sstevel@tonic-gate init_cpu_mstate(CPU, CMS_SYSTEM); 3747c478bd9Sstevel@tonic-gate 3757c478bd9Sstevel@tonic-gate /* 3767c478bd9Sstevel@tonic-gate * Initialize lists of available and active CPUs. 3777c478bd9Sstevel@tonic-gate */ 3787c478bd9Sstevel@tonic-gate cpu_list_init(CPU); 3790e751525SEric Saxe 3800e751525SEric Saxe pg_cpu_bootstrap(CPU); 3817c478bd9Sstevel@tonic-gate 382ae115bc7Smrj /* 383ae115bc7Smrj * Now that we have taken over the GDT, IDT and have initialized 384ae115bc7Smrj * active CPU list it's time to inform kmdb if present. 385ae115bc7Smrj */ 386ae115bc7Smrj if (boothowto & RB_DEBUG) 387ae115bc7Smrj kdi_idt_sync(); 388ae115bc7Smrj 389c66b891eSToomas Soome if (BOP_GETPROPLEN(bootops, "efi-systab") < 0) { 390c66b891eSToomas Soome /* 391c66b891eSToomas Soome * In BIOS system, explicitly set console to text mode (0x3) 392c66b891eSToomas Soome * if this is a boot post Fast Reboot, and the console is set 393c66b891eSToomas Soome * to CONS_SCREEN_TEXT. 394c66b891eSToomas Soome */ 395c66b891eSToomas Soome if (post_fastreboot && 396c66b891eSToomas Soome boot_console_type(NULL) == CONS_SCREEN_TEXT) { 397c66b891eSToomas Soome set_console_mode(0x3); 398c66b891eSToomas Soome } 399c66b891eSToomas Soome } 4009db7147eSSherry Moore 401ae115bc7Smrj /* 402ae115bc7Smrj * If requested (boot -d) drop into kmdb. 403ae115bc7Smrj * 404ae115bc7Smrj * This must be done after cpu_list_init() on the 64-bit kernel 405ae115bc7Smrj * since taking a trap requires that we re-compute gsbase based 406ae115bc7Smrj * on the cpu list. 407ae115bc7Smrj */ 408ae115bc7Smrj if (boothowto & RB_DEBUGENTER) 409ae115bc7Smrj kmdb_enter(); 410ae115bc7Smrj 411affbd3ccSkchow cpu_vm_data_init(CPU); 412affbd3ccSkchow 4137c478bd9Sstevel@tonic-gate rp->r_fp = 0; /* terminate kernel stack traces! */ 4147c478bd9Sstevel@tonic-gate 4157c478bd9Sstevel@tonic-gate prom_init("kernel", (void *)NULL); 4167c478bd9Sstevel@tonic-gate 417a3114836SGerry Liu /* User-set option overrides firmware value. */ 418a3114836SGerry Liu if (bootprop_getval(PLAT_DR_OPTIONS_NAME, &prop_value) == 0) { 419a3114836SGerry Liu plat_dr_options = (uint64_t)prop_value; 420a3114836SGerry Liu } 421a3114836SGerry Liu #if defined(__xpv) 422a3114836SGerry Liu /* No support of DR operations on xpv */ 423a3114836SGerry Liu plat_dr_options = 0; 424a3114836SGerry Liu #else /* __xpv */ 425a3114836SGerry Liu /* Flag PLAT_DR_FEATURE_ENABLED should only be set by DR driver. */ 426a3114836SGerry Liu plat_dr_options &= ~PLAT_DR_FEATURE_ENABLED; 427a3114836SGerry Liu #ifndef __amd64 428a3114836SGerry Liu /* Only enable CPU/memory DR on 64 bits kernel. */ 429a3114836SGerry Liu plat_dr_options &= ~PLAT_DR_FEATURE_MEMORY; 430a3114836SGerry Liu plat_dr_options &= ~PLAT_DR_FEATURE_CPU; 431a3114836SGerry Liu #endif /* __amd64 */ 432a3114836SGerry Liu #endif /* __xpv */ 433a3114836SGerry Liu 434a3114836SGerry Liu /* 435a3114836SGerry Liu * Get value of "plat_dr_physmax" boot option. 436a3114836SGerry Liu * It overrides values calculated from MSCT or SRAT table. 437a3114836SGerry Liu */ 438a3114836SGerry Liu if (bootprop_getval(PLAT_DR_PHYSMAX_NAME, &prop_value) == 0) { 439a3114836SGerry Liu plat_dr_physmax = ((uint64_t)prop_value) >> PAGESHIFT; 440a3114836SGerry Liu } 441a3114836SGerry Liu 442a3114836SGerry Liu /* Get value of boot_ncpus. */ 443a3114836SGerry Liu if (bootprop_getval(BOOT_NCPUS_NAME, &prop_value) != 0) { 444ae115bc7Smrj boot_ncpus = NCPU; 445a3114836SGerry Liu } else { 4462baa66a0SJonathan Chew boot_ncpus = (int)prop_value; 4472baa66a0SJonathan Chew if (boot_ncpus <= 0 || boot_ncpus > NCPU) 4482baa66a0SJonathan Chew boot_ncpus = NCPU; 4492baa66a0SJonathan Chew } 45041791439Sandrei 451a3114836SGerry Liu /* 452a3114836SGerry Liu * Set max_ncpus and boot_max_ncpus to boot_ncpus if platform doesn't 453a3114836SGerry Liu * support CPU DR operations. 454a3114836SGerry Liu */ 455a3114836SGerry Liu if (plat_dr_support_cpu() == 0) { 456a3114836SGerry Liu max_ncpus = boot_max_ncpus = boot_ncpus; 457a3114836SGerry Liu } else { 458a3114836SGerry Liu if (bootprop_getval(PLAT_MAX_NCPUS_NAME, &prop_value) != 0) { 459a3114836SGerry Liu max_ncpus = NCPU; 460a3114836SGerry Liu } else { 461a3114836SGerry Liu max_ncpus = (int)prop_value; 462a3114836SGerry Liu if (max_ncpus <= 0 || max_ncpus > NCPU) { 463a3114836SGerry Liu max_ncpus = NCPU; 464a3114836SGerry Liu } 465a3114836SGerry Liu if (boot_ncpus > max_ncpus) { 466a3114836SGerry Liu boot_ncpus = max_ncpus; 467a3114836SGerry Liu } 468a3114836SGerry Liu } 469a3114836SGerry Liu 470a3114836SGerry Liu if (bootprop_getval(BOOT_MAX_NCPUS_NAME, &prop_value) != 0) { 471a3114836SGerry Liu boot_max_ncpus = boot_ncpus; 472a3114836SGerry Liu } else { 473a3114836SGerry Liu boot_max_ncpus = (int)prop_value; 474a3114836SGerry Liu if (boot_max_ncpus <= 0 || boot_max_ncpus > NCPU) { 475a3114836SGerry Liu boot_max_ncpus = boot_ncpus; 476a3114836SGerry Liu } else if (boot_max_ncpus > max_ncpus) { 477a3114836SGerry Liu boot_max_ncpus = max_ncpus; 478a3114836SGerry Liu } 479a3114836SGerry Liu } 480a3114836SGerry Liu } 48141791439Sandrei 4822e2c009bSjjc /* 4832e2c009bSjjc * Initialize the lgrp framework 4842e2c009bSjjc */ 485d5d7cf4eSJonathan Chew lgrp_init(LGRP_INIT_STAGE1); 4862e2c009bSjjc 4877c478bd9Sstevel@tonic-gate if (boothowto & RB_HALT) { 4887c478bd9Sstevel@tonic-gate prom_printf("unix: kernel halted by -h flag\n"); 4897c478bd9Sstevel@tonic-gate prom_enter_mon(); 4907c478bd9Sstevel@tonic-gate } 4917c478bd9Sstevel@tonic-gate 4927c478bd9Sstevel@tonic-gate ASSERT_STACK_ALIGNED(); 4937c478bd9Sstevel@tonic-gate 4942449e17fSsherrym /* 4952449e17fSsherrym * Fill out cpu_ucode_info. Update microcode if necessary. 4962449e17fSsherrym */ 4972449e17fSsherrym ucode_check(CPU); 4982449e17fSsherrym 4997c478bd9Sstevel@tonic-gate if (workaround_errata(CPU) != 0) 5007c478bd9Sstevel@tonic-gate panic("critical workaround(s) missing for boot cpu"); 5017c478bd9Sstevel@tonic-gate } 502986fd29aSsetje 503986fd29aSsetje 504986fd29aSsetje void 505986fd29aSsetje mach_modpath(char *path, const char *filename) 506986fd29aSsetje { 507986fd29aSsetje /* 508986fd29aSsetje * Construct the directory path from the filename. 509986fd29aSsetje */ 510986fd29aSsetje 511986fd29aSsetje int len; 512986fd29aSsetje char *p; 513986fd29aSsetje const char isastr[] = "/amd64"; 514986fd29aSsetje size_t isalen = strlen(isastr); 515986fd29aSsetje 5160181461bSKeith M Wesolowski len = strlen(SYSTEM_BOOT_PATH "/kernel"); 5170181461bSKeith M Wesolowski (void) strcpy(path, SYSTEM_BOOT_PATH "/kernel "); 5180181461bSKeith M Wesolowski path += len + 1; 5190181461bSKeith M Wesolowski 520986fd29aSsetje if ((p = strrchr(filename, '/')) == NULL) 521986fd29aSsetje return; 522986fd29aSsetje 523986fd29aSsetje while (p > filename && *(p - 1) == '/') 524986fd29aSsetje p--; /* remove trailing '/' characters */ 525986fd29aSsetje if (p == filename) 526986fd29aSsetje p++; /* so "/" -is- the modpath in this case */ 527986fd29aSsetje 528986fd29aSsetje /* 529986fd29aSsetje * Remove optional isa-dependent directory name - the module 530986fd29aSsetje * subsystem will put this back again (!) 531986fd29aSsetje */ 532986fd29aSsetje len = p - filename; 533986fd29aSsetje if (len > isalen && 534986fd29aSsetje strncmp(&filename[len - isalen], isastr, isalen) == 0) 535986fd29aSsetje p -= isalen; 536986fd29aSsetje 537986fd29aSsetje /* 538986fd29aSsetje * "/platform/mumblefrotz" + " " + MOD_DEFPATH 539986fd29aSsetje */ 540986fd29aSsetje len += (p - filename) + 1 + strlen(MOD_DEFPATH) + 1; 541986fd29aSsetje (void) strncpy(path, filename, p - filename); 542986fd29aSsetje } 543