1/*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21/*
22 * Copyright (c) 2012 Gary Mills
23 *
24 * Copyright (c) 1993, 2010, Oracle and/or its affiliates. All rights reserved.
25 * Copyright (c) 2011 by Delphix. All rights reserved.
26 * Copyright 2019 Joyent, Inc.
27 */
28/*
29 * Copyright (c) 2010, Intel Corporation.
30 * All rights reserved.
31 */
32
33#include <sys/types.h>
34#include <sys/sysmacros.h>
35#include <sys/disp.h>
36#include <sys/promif.h>
37#include <sys/clock.h>
38#include <sys/cpuvar.h>
39#include <sys/stack.h>
40#include <vm/as.h>
41#include <vm/hat.h>
42#include <sys/reboot.h>
43#include <sys/avintr.h>
44#include <sys/vtrace.h>
45#include <sys/proc.h>
46#include <sys/thread.h>
47#include <sys/cpupart.h>
48#include <sys/pset.h>
49#include <sys/copyops.h>
50#include <sys/pg.h>
51#include <sys/disp.h>
52#include <sys/debug.h>
53#include <sys/sunddi.h>
54#include <sys/x86_archext.h>
55#include <sys/privregs.h>
56#include <sys/machsystm.h>
57#include <sys/ontrap.h>
58#include <sys/bootconf.h>
59#include <sys/boot_console.h>
60#include <sys/kdi_machimpl.h>
61#include <sys/archsystm.h>
62#include <sys/promif.h>
63#include <sys/pci_cfgspace.h>
64#include <sys/apic.h>
65#include <sys/apic_common.h>
66#include <sys/bootvfs.h>
67#include <sys/tsc.h>
68#include <sys/smt.h>
69#ifdef __xpv
70#include <sys/hypervisor.h>
71#else
72#include <sys/xpv_support.h>
73#endif
74
75/*
76 * some globals for patching the result of cpuid
77 * to solve problems w/ creative cpu vendors
78 */
79
80extern uint32_t cpuid_feature_ecx_include;
81extern uint32_t cpuid_feature_ecx_exclude;
82extern uint32_t cpuid_feature_edx_include;
83extern uint32_t cpuid_feature_edx_exclude;
84
85nmi_action_t nmi_action = NMI_ACTION_UNSET;
86
87/*
88 * Set console mode
89 */
90static void
91set_console_mode(uint8_t val)
92{
93	struct bop_regs rp = {0};
94
95	rp.eax.byte.ah = 0x0;
96	rp.eax.byte.al = val;
97	rp.ebx.word.bx = 0x0;
98
99	BOP_DOINT(bootops, 0x10, &rp);
100}
101
102
103/*
104 * Setup routine called right before main(). Interposing this function
105 * before main() allows us to call it in a machine-independent fashion.
106 */
107void
108mlsetup(struct regs *rp)
109{
110	u_longlong_t prop_value;
111	char prop_str[BP_MAX_STRLEN];
112	extern struct classfuncs sys_classfuncs;
113	extern disp_t cpu0_disp;
114	extern char t0stack[];
115	extern int post_fastreboot;
116	extern uint64_t plat_dr_options;
117
118	ASSERT_STACK_ALIGNED();
119
120	/*
121	 * initialize cpu_self
122	 */
123	cpu[0]->cpu_self = cpu[0];
124
125#if defined(__xpv)
126	/*
127	 * Point at the hypervisor's virtual cpu structure
128	 */
129	cpu[0]->cpu_m.mcpu_vcpu_info = &HYPERVISOR_shared_info->vcpu_info[0];
130#endif
131
132	/*
133	 * check if we've got special bits to clear or set
134	 * when checking cpu features
135	 */
136
137	if (bootprop_getval("cpuid_feature_ecx_include", &prop_value) != 0)
138		cpuid_feature_ecx_include = 0;
139	else
140		cpuid_feature_ecx_include = (uint32_t)prop_value;
141
142	if (bootprop_getval("cpuid_feature_ecx_exclude", &prop_value) != 0)
143		cpuid_feature_ecx_exclude = 0;
144	else
145		cpuid_feature_ecx_exclude = (uint32_t)prop_value;
146
147	if (bootprop_getval("cpuid_feature_edx_include", &prop_value) != 0)
148		cpuid_feature_edx_include = 0;
149	else
150		cpuid_feature_edx_include = (uint32_t)prop_value;
151
152	if (bootprop_getval("cpuid_feature_edx_exclude", &prop_value) != 0)
153		cpuid_feature_edx_exclude = 0;
154	else
155		cpuid_feature_edx_exclude = (uint32_t)prop_value;
156
157#if !defined(__xpv)
158	if (bootprop_getstr("nmi", prop_str, sizeof (prop_str)) == 0) {
159		if (strcmp(prop_str, "ignore") == 0) {
160			nmi_action = NMI_ACTION_IGNORE;
161		} else if (strcmp(prop_str, "panic") == 0) {
162			nmi_action = NMI_ACTION_PANIC;
163		} else if (strcmp(prop_str, "kmdb") == 0) {
164			nmi_action = NMI_ACTION_KMDB;
165		} else {
166			prom_printf("unix: ignoring unknown nmi=%s\n",
167			    prop_str);
168		}
169	}
170
171	/*
172	 * Check to see if KPTI has been explicitly enabled or disabled.
173	 * We have to check this before init_desctbls().
174	 */
175	if (bootprop_getval("kpti", &prop_value) == 0) {
176		kpti_enable = (uint64_t)(prop_value == 1);
177		prom_printf("unix: forcing kpti to %s due to boot argument\n",
178		    (kpti_enable == 1) ? "ON" : "OFF");
179	} else {
180		kpti_enable = 1;
181	}
182
183	if (bootprop_getval("pcid", &prop_value) == 0 && prop_value == 0) {
184		prom_printf("unix: forcing pcid to OFF due to boot argument\n");
185		x86_use_pcid = 0;
186	} else if (kpti_enable != 1) {
187		x86_use_pcid = 0;
188	}
189
190	/*
191	 * While we don't need to check this until later, we might as well do it
192	 * here.
193	 */
194	if (bootprop_getstr("smt_enabled", prop_str, sizeof (prop_str)) == 0) {
195		if (strcasecmp(prop_str, "false") == 0 ||
196		    strcmp(prop_str, "0") == 0)
197			smt_boot_disable = 1;
198	}
199
200#endif
201
202	/*
203	 * Initialize idt0, gdt0, ldt0_default, ktss0 and dftss.
204	 */
205	init_desctbls();
206
207	/*
208	 * lgrp_init() and possibly cpuid_pass1() need PCI config
209	 * space access
210	 */
211#if defined(__xpv)
212	if (DOMAIN_IS_INITDOMAIN(xen_info))
213		pci_cfgspace_init();
214#else
215	pci_cfgspace_init();
216	/*
217	 * Initialize the platform type from CPU 0 to ensure that
218	 * determine_platform() is only ever called once.
219	 */
220	determine_platform();
221#endif
222
223	/*
224	 * The first lightweight pass (pass0) through the cpuid data
225	 * was done in locore before mlsetup was called.  Do the next
226	 * pass in C code.
227	 *
228	 * The x86_featureset is initialized here based on the capabilities
229	 * of the boot CPU.  Note that if we choose to support CPUs that have
230	 * different feature sets (at which point we would almost certainly
231	 * want to set the feature bits to correspond to the feature
232	 * minimum) this value may be altered.
233	 */
234	cpuid_pass1(cpu[0], x86_featureset);
235
236#if !defined(__xpv)
237	if ((get_hwenv() & HW_XEN_HVM) != 0)
238		xen_hvm_init();
239
240	/*
241	 * Before we do anything with the TSCs, we need to work around
242	 * Intel erratum BT81.  On some CPUs, warm reset does not
243	 * clear the TSC.  If we are on such a CPU, we will clear TSC ourselves
244	 * here.  Other CPUs will clear it when we boot them later, and the
245	 * resulting skew will be handled by tsc_sync_master()/_slave();
246	 * note that such skew already exists and has to be handled anyway.
247	 *
248	 * We do this only on metal.  This same problem can occur with a
249	 * hypervisor that does not happen to virtualise a TSC that starts from
250	 * zero, regardless of CPU type; however, we do not expect hypervisors
251	 * that do not virtualise TSC that way to handle writes to TSC
252	 * correctly, either.
253	 */
254	if (get_hwenv() == HW_NATIVE &&
255	    cpuid_getvendor(CPU) == X86_VENDOR_Intel &&
256	    cpuid_getfamily(CPU) == 6 &&
257	    (cpuid_getmodel(CPU) == 0x2d || cpuid_getmodel(CPU) == 0x3e) &&
258	    is_x86_feature(x86_featureset, X86FSET_TSC)) {
259		(void) wrmsr(REG_TSC, 0UL);
260	}
261
262	/*
263	 * Patch the tsc_read routine with appropriate set of instructions,
264	 * depending on the processor family and architecure, to read the
265	 * time-stamp counter while ensuring no out-of-order execution.
266	 * Patch it while the kernel text is still writable.
267	 *
268	 * Note: tsc_read is not patched for intel processors whose family
269	 * is >6 and for amd whose family >f (in case they don't support rdtscp
270	 * instruction, unlikely). By default tsc_read will use cpuid for
271	 * serialization in such cases. The following code needs to be
272	 * revisited if intel processors of family >= f retains the
273	 * instruction serialization nature of mfence instruction.
274	 * Note: tsc_read is not patched for x86 processors which do
275	 * not support "mfence". By default tsc_read will use cpuid for
276	 * serialization in such cases.
277	 *
278	 * The Xen hypervisor does not correctly report whether rdtscp is
279	 * supported or not, so we must assume that it is not.
280	 */
281	if ((get_hwenv() & HW_XEN_HVM) == 0 &&
282	    is_x86_feature(x86_featureset, X86FSET_TSCP))
283		patch_tsc_read(TSC_TSCP);
284	else if (cpuid_getvendor(CPU) == X86_VENDOR_AMD &&
285	    cpuid_getfamily(CPU) <= 0xf &&
286	    is_x86_feature(x86_featureset, X86FSET_SSE2))
287		patch_tsc_read(TSC_RDTSC_MFENCE);
288	else if (cpuid_getvendor(CPU) == X86_VENDOR_Intel &&
289	    cpuid_getfamily(CPU) <= 6 &&
290	    is_x86_feature(x86_featureset, X86FSET_SSE2))
291		patch_tsc_read(TSC_RDTSC_LFENCE);
292
293#endif	/* !__xpv */
294
295#if defined(__i386) && !defined(__xpv)
296	/*
297	 * Some i386 processors do not implement the rdtsc instruction,
298	 * or at least they do not implement it correctly. Patch them to
299	 * return 0.
300	 */
301	if (!is_x86_feature(x86_featureset, X86FSET_TSC))
302		patch_tsc_read(TSC_NONE);
303#endif	/* __i386 && !__xpv */
304
305#if defined(__amd64) && !defined(__xpv)
306	patch_memops(cpuid_getvendor(CPU));
307#endif	/* __amd64 && !__xpv */
308
309#if !defined(__xpv)
310	/* XXPV	what, if anything, should be dorked with here under xen? */
311
312	/*
313	 * While we're thinking about the TSC, let's set up %cr4 so that
314	 * userland can issue rdtsc, and initialize the TSC_AUX value
315	 * (the cpuid) for the rdtscp instruction on appropriately
316	 * capable hardware.
317	 */
318	if (is_x86_feature(x86_featureset, X86FSET_TSC))
319		setcr4(getcr4() & ~CR4_TSD);
320
321	if (is_x86_feature(x86_featureset, X86FSET_TSCP))
322		(void) wrmsr(MSR_AMD_TSCAUX, 0);
323
324	/*
325	 * Let's get the other %cr4 stuff while we're here. Note, we defer
326	 * enabling CR4_SMAP until startup_end(); however, that's importantly
327	 * before we start other CPUs. That ensures that it will be synced out
328	 * to other CPUs.
329	 */
330	if (is_x86_feature(x86_featureset, X86FSET_DE))
331		setcr4(getcr4() | CR4_DE);
332
333	if (is_x86_feature(x86_featureset, X86FSET_SMEP))
334		setcr4(getcr4() | CR4_SMEP);
335#endif /* __xpv */
336
337	/*
338	 * initialize t0
339	 */
340	t0.t_stk = (caddr_t)rp - MINFRAME;
341	t0.t_stkbase = t0stack;
342	t0.t_pri = maxclsyspri - 3;
343	t0.t_schedflag = TS_LOAD | TS_DONT_SWAP;
344	t0.t_procp = &p0;
345	t0.t_plockp = &p0lock.pl_lock;
346	t0.t_lwp = &lwp0;
347	t0.t_forw = &t0;
348	t0.t_back = &t0;
349	t0.t_next = &t0;
350	t0.t_prev = &t0;
351	t0.t_cpu = cpu[0];
352	t0.t_disp_queue = &cpu0_disp;
353	t0.t_bind_cpu = PBIND_NONE;
354	t0.t_bind_pset = PS_NONE;
355	t0.t_bindflag = (uchar_t)default_binding_mode;
356	t0.t_cpupart = &cp_default;
357	t0.t_clfuncs = &sys_classfuncs.thread;
358	t0.t_copyops = NULL;
359	THREAD_ONPROC(&t0, CPU);
360
361	lwp0.lwp_thread = &t0;
362	lwp0.lwp_regs = (void *)rp;
363	lwp0.lwp_procp = &p0;
364	t0.t_tid = p0.p_lwpcnt = p0.p_lwprcnt = p0.p_lwpid = 1;
365
366	p0.p_exec = NULL;
367	p0.p_stat = SRUN;
368	p0.p_flag = SSYS;
369	p0.p_tlist = &t0;
370	p0.p_stksize = 2*PAGESIZE;
371	p0.p_stkpageszc = 0;
372	p0.p_as = &kas;
373	p0.p_lockp = &p0lock;
374	p0.p_brkpageszc = 0;
375	p0.p_t1_lgrpid = LGRP_NONE;
376	p0.p_tr_lgrpid = LGRP_NONE;
377	psecflags_default(&p0.p_secflags);
378
379	sigorset(&p0.p_ignore, &ignoredefault);
380
381	CPU->cpu_thread = &t0;
382	bzero(&cpu0_disp, sizeof (disp_t));
383	CPU->cpu_disp = &cpu0_disp;
384	CPU->cpu_disp->disp_cpu = CPU;
385	CPU->cpu_dispthread = &t0;
386	CPU->cpu_idle_thread = &t0;
387	CPU->cpu_flags = CPU_READY | CPU_RUNNING | CPU_EXISTS | CPU_ENABLE;
388	CPU->cpu_dispatch_pri = t0.t_pri;
389
390	CPU->cpu_id = 0;
391
392	CPU->cpu_pri = 12;		/* initial PIL for the boot CPU */
393
394	/*
395	 * Initialize thread/cpu microstate accounting
396	 */
397	init_mstate(&t0, LMS_SYSTEM);
398	init_cpu_mstate(CPU, CMS_SYSTEM);
399
400	/*
401	 * Initialize lists of available and active CPUs.
402	 */
403	cpu_list_init(CPU);
404
405	pg_cpu_bootstrap(CPU);
406
407	/*
408	 * Now that we have taken over the GDT, IDT and have initialized
409	 * active CPU list it's time to inform kmdb if present.
410	 */
411	if (boothowto & RB_DEBUG)
412		kdi_idt_sync();
413
414	if (BOP_GETPROPLEN(bootops, "efi-systab") < 0) {
415		/*
416		 * In BIOS system, explicitly set console to text mode (0x3)
417		 * if this is a boot post Fast Reboot, and the console is set
418		 * to CONS_SCREEN_TEXT.
419		 */
420		if (post_fastreboot &&
421		    boot_console_type(NULL) == CONS_SCREEN_TEXT) {
422			set_console_mode(0x3);
423		}
424	}
425
426	/*
427	 * If requested (boot -d) drop into kmdb.
428	 *
429	 * This must be done after cpu_list_init() on the 64-bit kernel
430	 * since taking a trap requires that we re-compute gsbase based
431	 * on the cpu list.
432	 */
433	if (boothowto & RB_DEBUGENTER)
434		kmdb_enter();
435
436	cpu_vm_data_init(CPU);
437
438	rp->r_fp = 0;	/* terminate kernel stack traces! */
439
440	prom_init("kernel", (void *)NULL);
441
442	/* User-set option overrides firmware value. */
443	if (bootprop_getval(PLAT_DR_OPTIONS_NAME, &prop_value) == 0) {
444		plat_dr_options = (uint64_t)prop_value;
445	}
446#if defined(__xpv)
447	/* No support of DR operations on xpv */
448	plat_dr_options = 0;
449#else	/* __xpv */
450	/* Flag PLAT_DR_FEATURE_ENABLED should only be set by DR driver. */
451	plat_dr_options &= ~PLAT_DR_FEATURE_ENABLED;
452#ifndef	__amd64
453	/* Only enable CPU/memory DR on 64 bits kernel. */
454	plat_dr_options &= ~PLAT_DR_FEATURE_MEMORY;
455	plat_dr_options &= ~PLAT_DR_FEATURE_CPU;
456#endif	/* __amd64 */
457#endif	/* __xpv */
458
459	/*
460	 * Get value of "plat_dr_physmax" boot option.
461	 * It overrides values calculated from MSCT or SRAT table.
462	 */
463	if (bootprop_getval(PLAT_DR_PHYSMAX_NAME, &prop_value) == 0) {
464		plat_dr_physmax = ((uint64_t)prop_value) >> PAGESHIFT;
465	}
466
467	/* Get value of boot_ncpus. */
468	if (bootprop_getval(BOOT_NCPUS_NAME, &prop_value) != 0) {
469		boot_ncpus = NCPU;
470	} else {
471		boot_ncpus = (int)prop_value;
472		if (boot_ncpus <= 0 || boot_ncpus > NCPU)
473			boot_ncpus = NCPU;
474	}
475
476	/*
477	 * Set max_ncpus and boot_max_ncpus to boot_ncpus if platform doesn't
478	 * support CPU DR operations.
479	 */
480	if (plat_dr_support_cpu() == 0) {
481		max_ncpus = boot_max_ncpus = boot_ncpus;
482	} else {
483		if (bootprop_getval(PLAT_MAX_NCPUS_NAME, &prop_value) != 0) {
484			max_ncpus = NCPU;
485		} else {
486			max_ncpus = (int)prop_value;
487			if (max_ncpus <= 0 || max_ncpus > NCPU) {
488				max_ncpus = NCPU;
489			}
490			if (boot_ncpus > max_ncpus) {
491				boot_ncpus = max_ncpus;
492			}
493		}
494
495		if (bootprop_getval(BOOT_MAX_NCPUS_NAME, &prop_value) != 0) {
496			boot_max_ncpus = boot_ncpus;
497		} else {
498			boot_max_ncpus = (int)prop_value;
499			if (boot_max_ncpus <= 0 || boot_max_ncpus > NCPU) {
500				boot_max_ncpus = boot_ncpus;
501			} else if (boot_max_ncpus > max_ncpus) {
502				boot_max_ncpus = max_ncpus;
503			}
504		}
505	}
506
507	/*
508	 * Initialize the lgrp framework
509	 */
510	lgrp_init(LGRP_INIT_STAGE1);
511
512	if (boothowto & RB_HALT) {
513		prom_printf("unix: kernel halted by -h flag\n");
514		prom_enter_mon();
515	}
516
517	ASSERT_STACK_ALIGNED();
518
519	/*
520	 * Fill out cpu_ucode_info.  Update microcode if necessary.
521	 */
522	ucode_check(CPU);
523	cpuid_pass_ucode(CPU, x86_featureset);
524
525	if (workaround_errata(CPU) != 0)
526		panic("critical workaround(s) missing for boot cpu");
527}
528
529
530void
531mach_modpath(char *path, const char *filename)
532{
533	/*
534	 * Construct the directory path from the filename.
535	 */
536
537	int len;
538	char *p;
539	const char isastr[] = "/amd64";
540	size_t isalen = strlen(isastr);
541
542	len = strlen(SYSTEM_BOOT_PATH "/kernel");
543	(void) strcpy(path, SYSTEM_BOOT_PATH "/kernel ");
544	path += len + 1;
545
546	if ((p = strrchr(filename, '/')) == NULL)
547		return;
548
549	while (p > filename && *(p - 1) == '/')
550		p--;	/* remove trailing '/' characters */
551	if (p == filename)
552		p++;	/* so "/" -is- the modpath in this case */
553
554	/*
555	 * Remove optional isa-dependent directory name - the module
556	 * subsystem will put this back again (!)
557	 */
558	len = p - filename;
559	if (len > isalen &&
560	    strncmp(&filename[len - isalen], isastr, isalen) == 0)
561		p -= isalen;
562
563	/*
564	 * "/platform/mumblefrotz" + " " + MOD_DEFPATH
565	 */
566	len += (p - filename) + 1 + strlen(MOD_DEFPATH) + 1;
567	(void) strncpy(path, filename, p - filename);
568}
569