1/*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21/*
22 * Copyright (c) 2006, 2010, Oracle and/or its affiliates. All rights reserved.
23 */
24
25#ifndef	_SYS_NXGE_NXGE_PHY_HW_H
26#define	_SYS_NXGE_NXGE_PHY_HW_H
27
28#ifdef	__cplusplus
29extern "C" {
30#endif
31
32#include <nxge_defs.h>
33
34/*
35 * Clause 45 and Clause 22 port/phy addresses 0 through 5 are reserved
36 * for on-chip serdes. So here the starting port is 6.
37 */
38#define	NXGE_MAX_PHY_PORTS		32
39#define	NXGE_EXT_PHY_PORT_ST		6
40
41#define	NXGE_PMA_PMD_DEV_ADDR		1
42#define	NXGE_PCS_DEV_ADDR		3
43#define	NXGE_DEV_ID_REG_1		2
44#define	NXGE_DEV_ID_REG_2		3
45#define	NXGE_PHY_ID_REG_1		2
46#define	NXGE_PHY_ID_REG_2		3
47
48#define	BCM8704_CHIP_ID			0x8704
49#define	BCM8706_CHIP_ID			0x8706
50#define	MRVL88X201X_CHIP_ID		0x5043
51#define	NLP2020_CHIP_ID			0x0211
52
53/*
54 * Description of BCM_PHY_ID_MASK:
55 * The first nibble (bits 0 through 3) is changed with every revision
56 * of the silicon. So these bits are masked out to support future revisions
57 * of the same chip. The third nibble (bits 8 through 11) is changed for
58 * different chips of the same family. So these bits are masked out to
59 * support chips of the same family.
60 */
61#define	BCM_PHY_ID_MASK			0xfffff0f0
62#define	BCM8704_DEV_ID			0x206033
63#define	BCM5464R_PHY_ID			0x2060b1
64#define	BCM8706_DEV_ID			0x206035
65#define	BCM5482_PHY_ID			0x143bcb1
66#define	MARVELL_88X_201X_DEV_ID		0x1410d24
67#define	MARVELL_88X201X_PHY_ID	(MARVELL_88X_201X_DEV_ID & BCM_PHY_ID_MASK)
68#define	PHY_BCM8704_FAMILY		(BCM8704_DEV_ID & BCM_PHY_ID_MASK)
69#define	PHY_BCM5464R_FAMILY		(BCM5464R_PHY_ID & BCM_PHY_ID_MASK)
70#define	PHY_BCM5482_FAMILY		(BCM5482_PHY_ID & BCM_PHY_ID_MASK)
71/*
72 * The default value is 0xa19410, after masking out model and revision
73 * (bits[9:0]) use 0xa19400 for any model or revision of the TN1010
74 */
75#define	TN1010_DEV_ID			0xa19400
76/*
77 * Description of TN1010_DEV_ID_MASK:
78 * The device ID assigned to Teranetics is stored in TN1010 register
79 * 1.2 and register 1.3 except bits[9:4] of register 1.3 for model number
80 * and bits[3:0] of register 1.3 for revision numbers. Use mask 0xfffffc00
81 * to mask off model number and revision number and keep TN1010's device
82 * identifier
83 */
84#define	TN1010_DEV_ID_MASK		0xfffffc00
85/*
86 * The Netlogic device ID and mask:
87 * The device ID assigned to Netlogic is stored in AEL2020 register
88 * 1.2 and register 1.3 except bits[7:4] of register 1.3 have the model number
89 * and bits[3:0] of register 1.3 have the revision number. Use mask 0xffffff00
90 * to mask off model number and revision number and keep AEL2020 device
91 * identifier
92 */
93#define	NLP2020_DEV_ID			0x3429000
94#define	NLP2020_DEV_ID_MASK		0xffffff00
95
96#define	CLAUSE_45_TYPE	1
97#define	CLAUSE_22_TYPE	2
98
99/* IEEE802.3 Clause45 and Clause22 MDIO port addresses */
100#define	NEPTUNE_CLAUSE22_PORT_ADDR_BASE		10
101#define	NEPTUNE_CLAUSE45_PORT_ADDR_BASE		8
102#define	N2_CLAUSE45_PORT_ADDR_BASE		16
103#define	MRVL88X2011_NEPTUNE_PORT_ADDR_BASE	8
104
105/*
106 * Phy address for the second NIU port on Goa NEM card can be either
107 * 20 or 17
108 */
109#define	GOA_CLAUSE45_PORT_ADDR_BASE		16
110#define	ALT_GOA_CLAUSE45_PORT1_ADDR		20
111
112/*
113 * Phy addresses for AEL2020 used in QSFP for RF systems
114 */
115#define	NLP2020_CL45_PORT0_ADDR0	0x10
116#define	NLP2020_CL45_PORT0_ADDR1	0x12
117#define	NLP2020_CL45_PORT0_ADDR2	0x15
118#define	NLP2020_CL45_PORT0_ADDR3	0x17
119#define	NLP2020_CL45_PORT1_ADDR0	0x11
120#define	NLP2020_CL45_PORT1_ADDR1	0x13
121#define	NLP2020_CL45_PORT1_ADDR2	0x14
122#define	NLP2020_CL45_PORT1_ADDR3	0x16
123
124/*
125 * Phy addresses for Maramba support. Support for P0 will eventually
126 * be removed.
127 */
128#define	MARAMBA_P0_CLAUSE22_PORT_ADDR_BASE	10
129#define	MARAMBA_P1_CLAUSE22_PORT_ADDR_BASE	26
130#define	MARAMBA_CLAUSE45_PORT_ADDR_BASE		16
131
132#define	BCM8704_PMA_PMD_DEV_ADDR		1
133#define	BCM8704_PCS_DEV_ADDR			3
134#define	BCM8704_USER_DEV3_ADDR			3
135#define	BCM8704_PHYXS_ADDR			4
136#define	BCM8704_USER_DEV4_ADDR			4
137
138/* Definitions for BCM 5464R PHY chip */
139
140#define	BCM5464R_PHY_ECR	16
141#define	BCM5464R_PHY_ESR	17
142#define	BCM5464R_RXERR_CNT	18
143#define	BCM5464R_FALSECS_CNT	19
144#define	BCM5464R_RX_NOTOK_CNT	20
145#define	BCM5464R_ER_DATA	21
146#define	BCM5464R_RES		22
147#define	BCM5464R_ER_ACC		23
148#define	BCM5464R_AUX_CTL	24
149#define	BCM5464R_AUX_S		25
150#define	BCM5464R_INTR_S		26
151#define	BCM5464R_INTR_M		27
152#define	BCM5464R_MISC		28
153#define	BCM5464R_MISC1		29
154#define	BCM5464R_TESTR1		30
155
156#define	PHY_BCM_5464R_OUI	0x001018
157#define	PHY_BCM_5464R_MODEL	0x0B
158
159/* MARVELL PHY Definitions */
160/* REG Offsets */
161#define	MRVL_88X2011_USER_DEV1_ADDR	1
162#define	MRVL_88X2011_USER_DEV2_ADDR	2
163#define	MRVL_88X2011_USER_DEV3_ADDR	3
164#define	MRVL_88X2011_USER_DEV4_ADDR	4
165#define	MRVL_88X2011_PMA_PMD_CTL_1	0x0000
166#define	MRVL_88X2011_PMA_PMD_STAT_1	0x0001
167#define	MRVL_88X2011_10G_PMD_STAT_2	0x0008
168#define	MRVL_88X2011_10G_PMD_TX_DIS	0x0009
169#define	MRVL_88X2011_10G_XGXS_LANE_STAT	0x0018
170#define	MRVL_88X2011_GEN_CTL		0x8300
171#define	MRVL_88X2011_LED_BLINK_CTL	0x8303
172#define	MRVL_88X2011_LED_8_TO_11_CTL	0x8306
173
174/* MRVL88X2011 register control */
175#define	MRVL_88X2011_ENA_PMDTX		0x0000
176#define	MRVL_88X2011_ENA_XFPREFCLK	0x0001
177#define	MRVL_88X2011_LOOPBACK		0x1
178#define	MRVL_88X2011_LED_ACT		0x1
179#define	MRVL_88X2011_LNK_STATUS_OK	0x4
180#define	MRVL_88X2011_LED_BLK_MASK	0x70
181#define	MRVL_88X2011_LED_BLK_SHIFT	4
182#define	MRVL_88X2011_LED_BLK34MS	0x0
183#define	MRVL_88X2011_LED_BLK67MS	0x1
184#define	MRVL_88X2011_LED_BLK134MS	0x2
185#define	MRVL_88X2011_LED_BLK269MS	0x3
186#define	MRVL_88X2011_LED_BLK538MS	0x4
187#define	MRVL_88X2011_LED_CTL_OFF	0x0
188#define	MRVL_88X2011_LED_CTL_PCS_ERR	0x2
189#define	MRVL_88X2011_LED_CTL_PCS_ACT	0x5
190#define	MRVL_88X2011_LED_CTL_MASK	0x7
191#define	MRVL_88X2011_LED(n, v)		((v)<<((n)*4))
192#define	MRVL_88X2011_LED_STAT(n, v)	((v)>>((n)*4))
193
194/*
195 * MII Register 16:  PHY Extended Control Register
196 */
197
198typedef	union _mii_phy_ecr_t {
199	uint16_t value;
200	struct {
201#ifdef _BIT_FIELDS_HTOL
202		uint16_t mac_phy_if_mode	: 1;
203		uint16_t dis_automdicross	: 1;
204		uint16_t tx_dis			: 1;
205		uint16_t intr_dis		: 1;
206		uint16_t force_intr		: 1;
207		uint16_t bypass_encdec		: 1;
208		uint16_t bypass_scrdes		: 1;
209		uint16_t bypass_mlt3		: 1;
210		uint16_t bypass_rx_sym		: 1;
211		uint16_t reset_scr		: 1;
212		uint16_t en_led_traffic		: 1;
213		uint16_t force_leds_on		: 1;
214		uint16_t force_leds_off		: 1;
215		uint16_t res			: 2;
216		uint16_t gmii_fifo_elas		: 1;
217#else
218		uint16_t gmii_fifo_elas		: 1;
219		uint16_t res			: 2;
220		uint16_t force_leds_off		: 1;
221		uint16_t force_leds_on		: 1;
222		uint16_t en_led_traffic		: 1;
223		uint16_t reset_scr		: 1;
224		uint16_t bypass_rx_sym		: 1;
225		uint16_t bypass_mlt3		: 1;
226		uint16_t bypass_scrdes		: 1;
227		uint16_t bypass_encdec		: 1;
228		uint16_t force_intr		: 1;
229		uint16_t intr_dis		: 1;
230		uint16_t tx_dis			: 1;
231		uint16_t dis_automdicross	: 1;
232		uint16_t mac_phy_if_mode	: 1;
233#endif
234	} bits;
235} mii_phy_ecr_t, *p_mii_phy_ecr_t;
236
237/*
238 * MII Register 17:  PHY Extended Status Register
239 */
240typedef	union _mii_phy_esr_t {
241	uint16_t value;
242	struct {
243#ifdef _BIT_FIELDS_HTOL
244		uint16_t anbpsfm		: 1;
245		uint16_t wsdwngr		: 1;
246		uint16_t mdi_crst		: 1;
247		uint16_t intr_s			: 1;
248		uint16_t rmt_rx_s		: 1;
249		uint16_t loc_rx_s		: 1;
250		uint16_t locked			: 1;
251		uint16_t link_s			: 1;
252		uint16_t crc_err		: 1;
253		uint16_t cext_err		: 1;
254		uint16_t bad_ssd		: 1;
255		uint16_t bad_esd		: 1;
256		uint16_t rx_err			: 1;
257		uint16_t tx_err			: 1;
258		uint16_t lock_err		: 1;
259		uint16_t mlt3_cerr		: 1;
260#else
261		uint16_t mlt3_cerr		: 1;
262		uint16_t lock_err		: 1;
263		uint16_t tx_err			: 1;
264		uint16_t rx_err			: 1;
265		uint16_t bad_esd		: 1;
266		uint16_t bad_ssd		: 1;
267		uint16_t cext_err		: 1;
268		uint16_t crc_err		: 1;
269		uint16_t link_s			: 1;
270		uint16_t locked			: 1;
271		uint16_t loc_rx_s		: 1;
272		uint16_t rmt_rx_s		: 1;
273		uint16_t intr_s			: 1;
274		uint16_t mdi_crst		: 1;
275		uint16_t wsdwngr		: 1;
276		uint16_t anbpsfm		: 1;
277#endif
278	} bits;
279} mii_phy_esr_t, *p_mii_phy_esr_t;
280
281/*
282 * MII Register 18:  Receive Error Counter Register
283 */
284typedef	union _mii_rxerr_cnt_t {
285	uint16_t value;
286	struct {
287		uint16_t rx_err_cnt		: 16;
288	} bits;
289} mii_rxerr_cnt_t, *p_mii_rxerr_cnt_t;
290
291/*
292 * MII Register 19:  False Carrier Sense Counter Register
293 */
294typedef	union _mii_falsecs_cnt_t {
295	uint16_t value;
296	struct {
297#ifdef _BIT_FIELDS_HTOL
298		uint16_t res			: 8;
299		uint16_t false_cs_cnt		: 8;
300#else
301		uint16_t false_cs_cnt		: 8;
302		uint16_t res			: 8;
303#endif
304	} bits;
305} mii_falsecs_cnt_t, *p_mii_falsecs_cnt_t;
306
307/*
308 * MII Register 20:  Receiver NOT_OK Counter Register
309 */
310typedef	union _mii_rx_notok_cnt_t {
311	uint16_t value;
312	struct {
313#ifdef _BIT_FIELDS_HTOL
314		uint16_t l_rx_notok_cnt		: 8;
315		uint16_t r_rx_notok_cnt		: 8;
316#else
317		uint16_t r_rx_notok_cnt		: 8;
318		uint16_t l_rx_notok_cnt		: 8;
319#endif
320	} bits;
321} mii_rx_notok_cnt_t, *p_mii_rx_notok_t;
322
323/*
324 * MII Register 21:  Expansion Register Data Register
325 */
326typedef	union _mii_er_data_t {
327	uint16_t value;
328	struct {
329		uint16_t reg_data;
330	} bits;
331} mii_er_data_t, *p_mii_er_data_t;
332
333/*
334 * MII Register 23:  Expansion Register Access Register
335 */
336typedef	union _mii_er_acc_t {
337	struct {
338#ifdef _BIT_FIELDS_HTOL
339		uint16_t res			: 4;
340		uint16_t er_sel			: 4;
341		uint16_t er_acc			: 8;
342#else
343		uint16_t er_acc			: 8;
344		uint16_t er_sel			: 4;
345		uint16_t res			: 4;
346#endif
347	} bits;
348} mii_er_acc_t, *p_mii_er_acc_t;
349
350#define	EXP_RXTX_PKT_CNT		0x0
351#define	EXP_INTR_STAT			0x1
352#define	MULTICOL_LED_SEL		0x4
353#define	MULTICOL_LED_FLASH_RATE_CTL	0x5
354#define	MULTICOL_LED_BLINK_CTL		0x6
355#define	CABLE_DIAG_CTL			0x10
356#define	CABLE_DIAG_RES			0x11
357#define	CABLE_DIAG_LEN_CH_2_1		0x12
358#define	CABLE_DIAG_LEN_CH_4_3		0x13
359
360/*
361 * MII Register 24:  Auxiliary Control Register
362 */
363typedef	union _mii_aux_ctl_t {
364	uint16_t value;
365	struct {
366#ifdef _BIT_FIELDS_HTOL
367		uint16_t ext_lb			: 1;
368		uint16_t ext_pkt_len		: 1;
369		uint16_t edge_rate_ctl_1000	: 2;
370		uint16_t res			: 1;
371		uint16_t write_1		: 1;
372		uint16_t res1			: 2;
373		uint16_t dis_partial_resp	: 1;
374		uint16_t res2			: 1;
375		uint16_t edge_rate_ctl_100	: 2;
376		uint16_t diag_mode		: 1;
377		uint16_t shadow_reg_sel		: 3;
378#else
379		uint16_t shadow_reg_sel		: 3;
380		uint16_t diag_mode		: 1;
381		uint16_t edge_rate_ctl_100	: 2;
382		uint16_t res2			: 1;
383		uint16_t dis_partial_resp	: 1;
384		uint16_t res1			: 2;
385		uint16_t write_1		: 1;
386		uint16_t res			: 1;
387		uint16_t edge_rate_ctl_1000	: 2;
388		uint16_t ext_pkt_len		: 1;
389		uint16_t ext_lb			: 1;
390#endif
391	} bits;
392} mii_aux_ctl_t, *p_mii_aux_ctl_t;
393
394#define	AUX_REG				0x0
395#define	AUX_10BASET			0x1
396#define	AUX_PWR_CTL			0x2
397#define	AUX_MISC_TEST			0x4
398#define	AUX_MISC_CTL			0x7
399
400/*
401 * MII Register 25:  Auxiliary Status Summary Register
402 */
403typedef	union _mii_aux_s_t {
404	uint16_t value;
405	struct {
406#ifdef _BIT_FIELDS_HTOL
407		uint16_t an_complete		: 1;
408		uint16_t an_complete_ack	: 1;
409		uint16_t an_ack_detect		: 1;
410		uint16_t an_ability_detect	: 1;
411		uint16_t an_np_wait		: 1;
412		uint16_t an_hcd			: 3;
413		uint16_t pd_fault		: 1;
414		uint16_t rmt_fault		: 1;
415		uint16_t an_page_rx		: 1;
416		uint16_t lp_an_ability		: 1;
417		uint16_t lp_np_ability		: 1;
418		uint16_t link_s			: 1;
419		uint16_t pause_res_rx_dir	: 1;
420		uint16_t pause_res_tx_dir	: 1;
421#else
422		uint16_t pause_res_tx_dir	: 1;
423		uint16_t pause_res_rx_dir	: 1;
424		uint16_t link_s			: 1;
425		uint16_t lp_np_ability		: 1;
426		uint16_t lp_an_ability		: 1;
427		uint16_t an_page_rx		: 1;
428		uint16_t rmt_fault		: 1;
429		uint16_t pd_fault		: 1;
430		uint16_t an_hcd			: 3;
431		uint16_t an_np_wait		: 1;
432		uint16_t an_ability_detect	: 1;
433		uint16_t an_ack_detect		: 1;
434		uint16_t an_complete_ack	: 1;
435		uint16_t an_complete		: 1;
436#endif
437	} bits;
438} mii_aux_s_t, *p_mii_aux_s_t;
439
440/*
441 * MII Register 26, 27:  Interrupt Status and Mask Registers
442 */
443typedef	union _mii_intr_t {
444	uint16_t value;
445	struct {
446#ifdef _BIT_FIELDS_HTOL
447		uint16_t res			: 1;
448		uint16_t illegal_pair_swap	: 1;
449		uint16_t mdix_status_change	: 1;
450		uint16_t exceed_hicnt_thres	: 1;
451		uint16_t exceed_locnt_thres	: 1;
452		uint16_t an_page_rx		: 1;
453		uint16_t hcd_nolink		: 1;
454		uint16_t no_hcd			: 1;
455		uint16_t neg_unsupported_hcd	: 1;
456		uint16_t scr_sync_err		: 1;
457		uint16_t rmt_rx_status_change	: 1;
458		uint16_t loc_rx_status_change	: 1;
459		uint16_t duplex_mode_change	: 1;
460		uint16_t link_speed_change	: 1;
461		uint16_t link_status_change	: 1;
462		uint16_t crc_err		: 1;
463#else
464		uint16_t crc_err		: 1;
465		uint16_t link_status_change	: 1;
466		uint16_t link_speed_change	: 1;
467		uint16_t duplex_mode_change	: 1;
468		uint16_t loc_rx_status_change	: 1;
469		uint16_t rmt_rx_status_change	: 1;
470		uint16_t scr_sync_err		: 1;
471		uint16_t neg_unsupported_hcd	: 1;
472		uint16_t no_hcd			: 1;
473		uint16_t hcd_nolink		: 1;
474		uint16_t an_page_rx		: 1;
475		uint16_t exceed_locnt_thres	: 1;
476		uint16_t exceed_hicnt_thres	: 1;
477		uint16_t mdix_status_change	: 1;
478		uint16_t illegal_pair_swap	: 1;
479		uint16_t res			: 1;
480#endif
481	} bits;
482} mii_intr_t, *p_mii_intr_t;
483
484/*
485 * MII Register 28:  Register 1C Access Register
486 */
487typedef	union _mii_misc_t {
488	uint16_t value;
489	struct {
490#ifdef _BIT_FIELDS_HTOL
491		uint16_t w_en			: 1;
492		uint16_t shadow_reg_sel		: 5;
493		uint16_t data			: 10;
494#else
495		uint16_t data			: 10;
496		uint16_t shadow_reg_sel		: 5;
497		uint16_t w_en			: 1;
498#endif
499	} bits;
500} mii_misc_t, *p_mii_misc_t;
501
502#define	LINK_LED_MODE			0x2
503#define	CLK_ALIGN_CTL			0x3
504#define	WIRE_SP_RETRY			0x4
505#define	CLK125				0x5
506#define	LED_STATUS			0x8
507#define	LED_CONTROL			0x9
508#define	AUTO_PWR_DOWN			0xA
509#define	LED_SEL1			0xD
510#define	LED_SEL2			0xE
511
512/*
513 * MII Register 29:  Master/Slave Seed / HCD Status Register
514 */
515
516typedef	union _mii_misc1_t {
517	uint16_t value;
518	struct {
519#ifdef _BIT_FIELDS_HTOL
520		uint16_t en_shadow_reg		: 1;
521		uint16_t data			: 15;
522#else
523		uint16_t data			: 15;
524		uint16_t en_shadow_reg		: 1;
525#endif
526	} bits;
527} mii_misc1_t, *p_mii_misc1_t;
528
529/*
530 * MII Register 30:  Test Register 1
531 */
532
533typedef	union _mii_test1_t {
534	uint16_t value;
535	struct {
536#ifdef _BIT_FIELDS_HTOL
537		uint16_t crc_err_cnt_sel	: 1;
538		uint16_t res			: 7;
539		uint16_t manual_swap_mdi_st	: 1;
540		uint16_t res1			: 7;
541#else
542		uint16_t res1			: 7;
543		uint16_t manual_swap_mdi_st	: 1;
544		uint16_t res			: 7;
545		uint16_t crc_err_cnt_sel	: 1;
546#endif
547	} bits;
548} mii_test1_t, *p_mii_test1_t;
549
550
551/* Definitions of BCM8704 */
552
553#define	BCM8704_PMD_CONTROL_REG			0
554#define	BCM8704_PMD_STATUS_REG			0x1
555#define	BCM8704_PMD_ID_0_REG			0x2
556#define	BCM8704_PMD_ID_1_REG			0x3
557#define	BCM8704_PMD_SPEED_ABIL_REG		0x4
558#define	BCM8704_PMD_DEV_IN_PKG1_REG		0x5
559#define	BCM8704_PMD_DEV_IN_PKG2_REG		0x6
560#define	BCM8704_PMD_CONTROL2_REG		0x7
561#define	BCM8704_PMD_STATUS2_REG			0x8
562#define	BCM8704_PMD_TRANSMIT_DIS_REG		0x9
563#define	BCM8704_PMD_RECEIVE_SIG_DETECT		0xa
564#define	BCM8704_PMD_ORG_UNIQUE_ID_0_REG		0xe
565#define	BCM8704_PMD_ORG_UNIQUE_ID_1_REG		0xf
566#define	BCM8704_PCS_CONTROL_REG			0
567#define	BCM8704_PCS_STATUS1_REG			0x1
568#define	BCM8704_PCS_ID_0_REG			0x2
569#define	BCM8704_PCS_ID_1_REG			0x3
570#define	BCM8704_PCS_SPEED_ABILITY_REG		0x4
571#define	BCM8704_PCS_DEV_IN_PKG1_REG		0x5
572#define	BCM8704_PCS_DEV_IN_PKG2_REG		0x6
573#define	BCM8704_PCS_CONTROL2_REG		0x7
574#define	BCM8704_PCS_STATUS2_REG			0x8
575#define	BCM8704_PCS_ORG_UNIQUE_ID_0_REG		0xe
576#define	BCM8704_PCS_ORG_UNIQUE_ID_1_REG		0xf
577#define	BCM8704_PCS_STATUS_REG			0x18
578#define	BCM8704_10GBASE_R_PCS_STATUS_REG	0x20
579#define	BCM8704_10GBASE_R_PCS_STATUS2_REG	0x21
580#define	BCM8704_PHYXS_CONTROL_REG		0
581#define	BCM8704_PHYXS_STATUS_REG		0x1
582#define	BCM8704_PHY_ID_0_REG			0x2
583#define	BCM8704_PHY_ID_1_REG			0x3
584#define	BCM8704_PHYXS_SPEED_ABILITY_REG		0x4
585#define	BCM8704_PHYXS_DEV_IN_PKG2_REG		0x5
586#define	BCM8704_PHYXS_DEV_IN_PKG1_REG		0x6
587#define	BCM8704_PHYXS_STATUS2_REG		0x8
588#define	BCM8704_PHYXS_ORG_UNIQUE_ID_0_REG	0xe
589#define	BCM8704_PHYXS_ORG_UNIQUE_ID_1_REG	0xf
590#define	BCM8704_PHYXS_XGXS_LANE_STATUS_REG	0x18
591#define	BCM8704_PHYXS_XGXS_TEST_CONTROL_REG	0x19
592#define	BCM8704_USER_CONTROL_REG		0xC800
593#define	BCM8704_USER_ANALOG_CLK_REG		0xC801
594#define	BCM8704_USER_PMD_RX_CONTROL_REG		0xC802
595#define	BCM8704_USER_PMD_TX_CONTROL_REG		0xC803
596#define	BCM8704_USER_ANALOG_STATUS0_REG		0xC804
597#define	BCM8704_CHIP_ID_REG			0xC807
598#define	BCM8704_USER_OPTICS_DIGITAL_CTRL_REG	0xC808
599#define	BCM8704_USER_RX2_CONTROL1_REG		0x80C6
600#define	BCM8704_USER_RX1_CONTROL1_REG		0x80D6
601#define	BCM8704_USER_RX0_CONTROL1_REG		0x80E6
602#define	BCM8704_USER_TX_ALARM_STATUS_REG	0x9004
603
604/* Rx Channel Control1 Register bits */
605#define	BCM8704_RXPOL_FLIP			0x20
606
607typedef	union _phyxs_control {
608	uint16_t value;
609	struct {
610#ifdef _BIT_FIELDS_HTOL
611		uint16_t reset			: 1;
612		uint16_t loopback		: 1;
613		uint16_t speed_sel2		: 1;
614		uint16_t res2			: 1;
615		uint16_t low_power		: 1;
616		uint16_t res1			: 4;
617		uint16_t speed_sel1		: 1;
618		uint16_t speed_sel0		: 4;
619		uint16_t res0			: 2;
620#else
621		uint16_t res0			: 2;
622		uint16_t speed_sel0		: 4;
623		uint16_t speed_sel1		: 1;
624		uint16_t res1			: 4;
625		uint16_t low_power		: 1;
626		uint16_t res2			: 1;
627		uint16_t speed_sel2		: 1;
628		uint16_t loopback		: 1;
629		uint16_t reset			: 1;
630#endif
631	} bits;
632} phyxs_control_t, *p_phyxs_control_t, pcs_control_t, *p_pcs_control_t;
633
634
635/* PMD/Optics Digital Control Register (Dev=3 Addr=0xc800) */
636
637typedef	union _control {
638	uint16_t value;
639	struct {
640#ifdef _BIT_FIELDS_HTOL
641		uint16_t optxenb_lvl		: 1;
642		uint16_t optxrst_lvl		: 1;
643		uint16_t opbiasflt_lvl		: 1;
644		uint16_t obtmpflt_lvl		: 1;
645		uint16_t opprflt_lvl		: 1;
646		uint16_t optxflt_lvl		: 1;
647		uint16_t optrxlos_lvl		: 1;
648		uint16_t oprxflt_lvl		: 1;
649		uint16_t optxon_lvl		: 1;
650		uint16_t res1			: 7;
651#else
652		uint16_t res1			: 7;
653		uint16_t optxon_lvl		: 1;
654		uint16_t oprxflt_lvl		: 1;
655		uint16_t optrxlos_lvl		: 1;
656		uint16_t optxflt_lvl		: 1;
657		uint16_t opprflt_lvl		: 1;
658		uint16_t obtmpflt_lvl		: 1;
659		uint16_t opbiasflt_lvl		: 1;
660		uint16_t optxrst_lvl		: 1;
661		uint16_t optxenb_lvl		: 1;
662#endif
663	} bits;
664} control_t, *p_control_t;
665
666typedef	union _pmd_tx_control {
667	uint16_t value;
668	struct {
669#ifdef _BIT_FIELDS_HTOL
670		uint16_t res1			: 7;
671		uint16_t xfp_clken		: 1;
672		uint16_t tx_dac_txd		: 2;
673		uint16_t tx_dac_txck		: 2;
674		uint16_t tsd_lpwren		: 1;
675		uint16_t tsck_lpwren		: 1;
676		uint16_t cmu_lpwren		: 1;
677		uint16_t sfiforst		: 1;
678#else
679		uint16_t sfiforst		: 1;
680		uint16_t cmu_lpwren		: 1;
681		uint16_t tsck_lpwren		: 1;
682		uint16_t tsd_lpwren		: 1;
683		uint16_t tx_dac_txck		: 2;
684		uint16_t tx_dac_txd		: 2;
685		uint16_t xfp_clken		: 1;
686		uint16_t res1			: 7;
687#endif
688	} bits;
689} pmd_tx_control_t, *p_pmd_tx_control_t;
690
691
692/* PMD/Optics Digital Control Register (Dev=3 Addr=0xc808) */
693
694typedef	union _optics_dcntr {
695	uint16_t value;
696	struct {
697#ifdef _BIT_FIELDS_HTOL
698		uint16_t fault_mode		: 1;
699		uint16_t tx_pwrdown		: 1;
700		uint16_t rx_pwrdown		: 1;
701		uint16_t ext_flt_en		: 1;
702		uint16_t opt_rst		: 1;
703		uint16_t pcs_tx_inv_b		: 1;
704		uint16_t pcs_rx_inv		: 1;
705		uint16_t res3			: 2;
706		uint16_t gpio_sel		: 2;
707		uint16_t res2			: 1;
708		uint16_t lpbk_err_dis		: 1;
709		uint16_t res1			: 2;
710		uint16_t txonoff_pwdwn_dis	: 1;
711#else
712		uint16_t txonoff_pwdwn_dis	: 1;
713		uint16_t res1			: 2;
714		uint16_t lpbk_err_dis		: 1;
715		uint16_t res2			: 1;
716		uint16_t gpio_sel		: 2;
717		uint16_t res3			: 2;
718		uint16_t pcs_rx_inv		: 1;
719		uint16_t pcs_tx_inv_b		: 1;
720		uint16_t opt_rst		: 1;
721		uint16_t ext_flt_en		: 1;
722		uint16_t rx_pwrdown		: 1;
723		uint16_t tx_pwrdown		: 1;
724		uint16_t fault_mode		: 1;
725#endif
726	} bits;
727} optics_dcntr_t, *p_optics_dcntr_t;
728
729/* PMD Receive Signal Detect Register (Dev = 1 Register Address = 0x000A) */
730
731#define	PMD_RX_SIG_DET3			0x10
732#define	PMD_RX_SIG_DET2			0x08
733#define	PMD_RX_SIG_DET1			0x04
734#define	PMD_RX_SIG_DET0			0x02
735#define	GLOB_PMD_RX_SIG_OK		0x01
736
737/* 10GBase-R PCS Status Register (Dev = 3, Register Address = 0x0020) */
738
739#define	PCS_10GBASE_RX_LINK_STATUS	0x1000
740#define	PCS_PRBS31_ABLE			0x0004
741#define	PCS_10GBASE_R_HI_BER		0x0002
742#define	PCS_10GBASE_R_PCS_BLK_LOCK	0x0001
743
744/* XGXS Lane Status Register (Dev = 4, Register Address = 0x0018) */
745
746#define	XGXS_LANE_ALIGN_STATUS		0x1000
747#define	XGXS_PATTERN_TEST_ABILITY	0x0800
748#define	XGXS_LANE3_SYNC			0x0008
749#define	XGXS_LANE2_SYNC			0x0004
750#define	XGXS_LANE1_SYNC			0x0002
751#define	XGXS_LANE0_SYNC			0x0001
752#define	XGXS_LANE_STAT_MAGIC		0x0400
753
754
755/* Teranetics TN1010 Definitions */
756
757/* Teranetics TN1010 PHY MMD Addresses */
758#define	TN1010_PMA_PMD_DEV_ADDR		1
759#define	TN1010_PCS_DEV_ADDR		3
760#define	TN1010_PHYXS_DEV_ADDR		4
761#define	TN1010_AUTONEG_DEV_ADDR		7
762#define	TN1010_VENDOR_MMD1_DEV_ADDR	30
763
764/* TN1010 PCS Control Register */
765typedef union _tn1010_pcs_ctrl {
766	uint16_t value;
767	struct {
768#ifdef _BIT_FIELDS_HTOL
769		uint16_t reset			: 1;    /* bit 15 */
770		uint16_t loopback		: 1;	/* bit 14 */
771		uint16_t speed_sel2		: 1;
772		uint16_t res2			: 1;
773		uint16_t low_power		: 1;
774		uint16_t res1			: 4;
775		uint16_t speed_sel1		: 1;    /* bit 6 */
776		uint16_t speed_sel0		: 4;    /* bits[5:2] */
777		uint16_t res0			: 2;
778#else
779		uint16_t res0			: 2;
780		uint16_t speed_sel0		: 4;    /* bits[5:2] */
781		uint16_t speed_sel1		: 1;    /* bit 6 */
782		uint16_t res1			: 4;
783		uint16_t low_power		: 1;
784		uint16_t res2			: 1;
785		uint16_t speed_sel2		: 1;
786		uint16_t loopback		: 1;	/* bit 14 */
787		uint16_t reset			: 1;    /* bit 15 */
788#endif
789	} bits;
790} tn1010_phyxs_ctrl_t, *p_tn1010_phyxs_ctrl_t;
791
792/* TN1010 PHY XS Control Register */
793typedef union _tn1010_phyxs_ctrl {
794	uint16_t value;
795	struct {
796#ifdef _BIT_FIELDS_HTOL
797		uint16_t reset			: 1;    /* bit 15 */
798		uint16_t loopback		: 1;	/* bit 14 */
799		uint16_t speed_sel2		: 1;
800		uint16_t res2			: 1;
801		uint16_t low_power		: 1;
802		uint16_t res1			: 4;
803		uint16_t speed_sel1		: 1;    /* bit 6 */
804		uint16_t speed_sel0		: 4;    /* bits[5:2] */
805		uint16_t res0			: 2;
806#else
807		uint16_t res0			: 2;
808		uint16_t speed_sel0		: 4;    /* bits[5:2] */
809		uint16_t speed_sel1		: 1;    /* bit 6 */
810		uint16_t res1			: 4;
811		uint16_t low_power		: 1;
812		uint16_t res2			: 1;
813		uint16_t speed_sel2		: 1;
814		uint16_t loopback		: 1;	/* bit 14 */
815		uint16_t reset			: 1;    /* bit 15 */
816#endif
817	} bits;
818} tn1010_pcs_ctrl_t, *p_tn1010_pcs_ctrl_t;
819
820/* TN1010 VENDOR MMD1 GPHY Control register 30.310 */
821#define	TN1010_SGMII_LOOPBACK			1
822#define	TN1010_DEEP_LOOPBACK			2
823
824#define	TN1010_PMD_CONTROL_REG			0
825#define	TN1010_PMD_STATUS_REG			1
826#define	TN1010_PMD_ID_HIGH_REG			2
827#define	TN1010_PMD_ID_LOW_REG			3
828#define	TN1010_PMD_SPEED_ABIL_REG		4
829#define	TN1010_PMD_DEV_IN_PKG1_REG		5
830#define	TN1010_PMD_DEV_IN_PKG2_REG		6
831#define	TN1010_PMD_CONTROL2_REG			7
832#define	TN1010_PMD_STATUS2_REG			8
833#define	TN1010_PMD_TRANSMIT_DIS_REG		9
834#define	TN1010_PMD_RECEIVE_SIG_DETECT		10
835#define	TN1010_PMD_ORG_UNIQUE_ID_0_REG		14
836#define	TN1010_PMD_ORG_UNIQUE_ID_1_REG		15
837#define	TN1010_PCS_CONTROL_REG			0
838#define	TN1010_PCS_STATUS1_REG			1
839#define	TN1010_PCS_ID_HIGH_REG			2
840#define	TN1010_PCS_ID_LOW_REG			3
841#define	TN1010_PCS_SPEED_ABILITY_REG		4
842#define	TN1010_PCS_DEV_IN_PKG1_REG		5
843#define	TN1010_PCS_DEV_IN_PKG2_REG		6
844#define	TN1010_PCS_CONTROL2_REG			7
845#define	TN1010_PCS_STATUS2_REG			8
846#define	TN1010_PCS_ORG_UNIQUE_ID_0_REG		14
847#define	TN1010_PCS_ORG_UNIQUE_ID_1_REG		15
848#define	TN1010_PCS_10GBASE_R_T_STATUS1_REG	32
849#define	TN1010_PCS_10GBASE_R_T_STATUS2_REG	33
850#define	TN1010_PHYXS_CONTROL_REG		0
851#define	TN1010_PHYXS_STATUS_REG			1
852#define	TN1010_PHY_ID_HIGH_REG			2
853#define	TN1010_PHY_ID_LOW_REG			3
854#define	TN1010_PHYXS_SPEED_ABILITY_REG		4
855#define	TN1010_PHYXS_DEV_IN_PKG2_REG		5
856#define	TN1010_PHYXS_DEV_IN_PKG1_REG		6
857#define	TN1010_PHYXS_STATUS2_REG		8
858#define	TN1010_PHYXS_ORG_UNIQUE_ID_0_REG	14
859#define	TN1010_PHYXS_ORG_UNIQUE_ID_1_REG	15
860#define	TN1010_PHYXS_XGXS_LANE_STATUS_REG	24
861#define	TN1010_PHYXS_XGXS_TEST_CONTROL_REG	25
862
863#define	TN1010_AUTONEG_CONTROL_REG		0
864#define	TN1010_AUTONEG_STATUS_REG		1
865#define	TN1010_AUTONEG_ID_HIGH_REG		2
866#define	TN1010_AUTONEG_ID_LOW_REG		3
867#define	TN1010_AUTONEG_DEV_IN_PKG1_REG		5
868#define	TN1010_AUTUNEG_DEV_IN_PKG2_REG		6
869#define	TN1010_AUTONEG_ORG_UNIQUE_ID_0_REG	14
870#define	TN1010_AUTONEG_ORG_UNIQUE_ID_1_REG	15
871#define	TN1010_AUTONEG_ADVERTISE_REG		16
872#define	TN1010_AUTONEG_PARTNER_ABILITY_REG	19
873
874#define	TN1010_VENDOR_MMD1_CONTROL_REG		0
875#define	TN1010_VENDOR_MMD1_STATUS_REG		1
876#define	TN1010_VENDOR_MMD1_ID_HIGH		2
877#define	TN1010_VENDOR_MMD1_ID_LOW		3
878#define	TN1010_VENDOR_MMD1_DEV_STATUS_REG	8
879#define	TN1010_VENDOR_MMD1_FNS_CONTROL_RER	9
880#define	TN1010_VENDOR_MMD1_PKG_ID_0_REG		14
881#define	TN1010_VENDOR_MMD1_PKG_ID_1_REG		15
882#define	TN1010_VENDOR_MMD1_GPHY_CTRL		310
883
884/* Bits definitions of TN1010_AUTONEG_CONTROL_REG */
885#define	TN1010_AN_CTRL_RESET_BIT	0x8000	/* Reset */
886#define	TN1010_AN_CTRL_EN_BIT		0x1000	/* Enable autoneg */
887#define	TN1010_AN_CTRL_RESTART_BIT	0x200	/* Restart autoneg */
888#define	TN1010_AN_LINK_STAT_BIT		0x4	/* Link status */
889
890/* Bits definitions of TN1010_PHYXS_CONTROL_REG	*/
891#define	TN1010_VENDOR_MMD1_AN_STAT_BITS		0xC0
892
893/*
894 * Shift right 6 bits so bits[7:6] becomes [1:0].
895 * Bits[7:6] of TN1010_VENDOR_MND1_STATUS_REG are for autoneg status
896 * 00 in progress
897 * 01 completed
898 * 10 reserved
899 * 11 failed
900 */
901#define	TN1010_VENDOR_MMD1_AN_STAT_SHIFT	6
902
903/* Bit 4 of TN1010_VENDOR_MMD1_STATUS_REG is speed. 0: 10G, 1: 1G */
904#define	TN1010_VENDOR_MMD1_AN_SPEED_BIT		0x10
905
906/* Shift right 4 bits so bit4 becomes bit0 */
907#define	TN1010_VENDOR_MMD1_AN_SPEED_SHIFT	4
908
909/*
910 * Definitions for Netlogic AEL2020 PHY
911 */
912#define	NLP2020_PMA_PMD_ADDR		1
913#define	NLP2020_PMA_PMD_CTL_REG		0
914#define	NLP2020_PMA_PMD_PHY_RST		0x8000
915
916#define	NLP2020_PMA_PMD_STAT1_REG	0x0001
917#define	NLP2020_PMA_PMD_LINK_UP		0x0004
918
919#define	NLP2020_PMA_PMD_RX_SIG_DET_REG	0x000A
920#define	NLP2020_PMA_PMD_RX_SIG_ON	0x0001
921
922#define	NLP2020_PMA_PMD_STAT2_REG	0x0008
923
924#define	NLP2020_OPT_SET_REG		0xC017
925#define	NLP2020_RXLOS_ACT_H		0x0020
926
927#define	NLP2020_TX_DRV_CTL1_REG		0xC241
928#define	NLP2020_TX_DRV_CTL1_PREEMP_EN	0xA000
929
930#define	NLP2020_TX_DRV_CTL2_REG		0xC243
931#define	NLP2020_TX_DRV_CTL2_EMP_VAL	0xFFD3
932
933#define	NLP2020_UC_CTL_REG		0xD092
934#define	NLP2020_UC_CTL_STOP		1
935#define	NLP2020_UC_CTL_START		0
936
937#define	NLP2020_UC_PC_START_REG		0xD080
938#define	NLP2020_UC_PC_START_VAL		0x100
939
940#define	NLP2020_PHY_PCS_ADDR		3
941#define	NLP2020_PHY_PCS_STAT1_REG	0x0001
942#define	NLP2020_PHY_PCS_LINK_UP		0x0004
943
944#define	NLP2020_PHY_PCS_10GBR_STAT1_REG		0x0020
945#define	NLP2020_PHY_PCS_10GBR_RX_LINK_UP	0x1000
946
947#define	NLP2020_PHY_PCS_STAT2_REG	0x0008
948
949#define	NLP2020_PHY_XS_ADDR		4
950#define	NLP2020_PHY_XS_STAT1_REG	0x0001
951#define	NLP2020_PHY_XS_LINK_UP		0x0004
952
953#define	NLP2020_PHY_XS_LN_ST_REG	0x0018
954#define	NLP2020_PHY_XS_LN_ALIGN_SYNC	0x100f
955
956#define	NLP2020_PHY_XS_STAT2_REG	0x0008
957
958#define	NLP2020_GPIO_ADDR		1
959#define	NLP2020_GPIO_CTL_REG		0xC108
960#define	NLP2020_GPIO_STAT_REG		0xC10C
961#define	NLP2020_GPIO_STAT_MD_SHIFT	0x0004
962#define	NLP2020_GPIO_STAT_MD_MASK	0x00f0
963#define	NLP2020_GPIO_PT3_CFG_REG	0xC113
964
965#define	NLP2020_GPIO_ACT		0x0a00
966#define	NLP2020_GPIO_INACT		0x0b00
967
968#define	NLP2020_I2C_SNOOP_DEV_ADDR	1
969#define	NLP2020_I2C_SNOOP_ADDR_REG	0xC30A
970#define	NLP2020_I2C_SNOOP_DATA_REG	0xC30B
971#define	NLP2020_I2C_SNOOP_STAT_REG	0xC30C
972#define	NLP2020_XCVR_I2C_ADDR		0x00A0
973#define	NLP2020_XCVR_I2C_ADDR_SH	0x0008
974
975/*
976 * QSFP defines
977 */
978#define	SFPP_COPPER_TWINAX	0x21
979#define	SFPP_FIBER		0x7
980#define	QSFP_FIBER		0xC
981#define	QSFP_COPPER_TWINAX	0x21
982
983#define	QSFP_MSA_CONN_REG	 130
984#define	QSFP_MSA_LPM_REG	 93
985#define	QSFP_MSA_LEN_REG	 0x92
986#define	QSFP_MSA_LPM_HIGH	 0x1
987
988typedef enum {
989	NXGE_NLP_CONN_FIBER,
990	NXGE_NLP_CONN_COPPER_LT_7M,
991	NXGE_NLP_CONN_COPPER_7M_ABOVE
992} nxge_nlp_conn_t;
993
994/*
995 * struct for PHY addr-value pairs
996 */
997typedef struct _nxge_nlp_initseq_t {
998	uint32_t	dev_reg;
999	uint16_t	val;
1000} nxge_nlp_initseq_t, *p_nxge_nlp_initseq_t;
1001
1002/*
1003 * struct for PHY dev, register and value triple properties
1004 */
1005typedef struct _nxge_phy_mdio_val_t {
1006	uint16_t	dev;
1007	uint16_t	reg;
1008	uint16_t	val;
1009} nxge_phy_mdio_val_t, *p_nxge_phy_mdio_val_t;
1010
1011/*
1012 * struct for PHY register configurable property
1013 */
1014typedef struct _nxge_phy_prop_t {
1015	int	cnt;
1016	p_nxge_phy_mdio_val_t arr;
1017} nxge_phy_prop_t, *p_nxge_phy_prop_t;
1018
1019#ifdef	__cplusplus
1020}
1021#endif
1022
1023#endif	/* _SYS_NXGE_NXGE_PHY_HW_H */
1024