144961713Sgirish /* 244961713Sgirish * CDDL HEADER START 344961713Sgirish * 444961713Sgirish * The contents of this file are subject to the terms of the 544961713Sgirish * Common Development and Distribution License (the "License"). 644961713Sgirish * You may not use this file except in compliance with the License. 744961713Sgirish * 844961713Sgirish * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 944961713Sgirish * or http://www.opensolaris.org/os/licensing. 1044961713Sgirish * See the License for the specific language governing permissions 1144961713Sgirish * and limitations under the License. 1244961713Sgirish * 1344961713Sgirish * When distributing Covered Code, include this CDDL HEADER in each 1444961713Sgirish * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 1544961713Sgirish * If applicable, add the following below this CDDL HEADER, with the 1644961713Sgirish * fields enclosed by brackets "[]" replaced with your own identifying 1744961713Sgirish * information: Portions Copyright [yyyy] [name of copyright owner] 1844961713Sgirish * 1944961713Sgirish * CDDL HEADER END 2044961713Sgirish */ 2144961713Sgirish /* 22*678453a8Sspeer * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 2344961713Sgirish * Use is subject to license terms. 2444961713Sgirish */ 2544961713Sgirish 2644961713Sgirish #ifndef _SYS_NXGE_NXGE_COMMON_IMPL_H 2744961713Sgirish #define _SYS_NXGE_NXGE_COMMON_IMPL_H 2844961713Sgirish 2944961713Sgirish #pragma ident "%Z%%M% %I% %E% SMI" 3044961713Sgirish 3144961713Sgirish #ifdef __cplusplus 3244961713Sgirish extern "C" { 3344961713Sgirish #endif 3444961713Sgirish 3544961713Sgirish #define NPI_REGH(npi_handle) (npi_handle.regh) 3644961713Sgirish #define NPI_REGP(npi_handle) (npi_handle.regp) 3744961713Sgirish 3844961713Sgirish #if defined(NXGE_DEBUG_DMA) || defined(NXGE_DEBUG_TXC) 3944961713Sgirish #define __NXGE_STATIC 4044961713Sgirish #define __NXGE_INLINE 4144961713Sgirish #else 4244961713Sgirish #define __NXGE_STATIC static 4344961713Sgirish #define __NXGE_INLINE inline 4444961713Sgirish #endif 4544961713Sgirish 4644961713Sgirish #ifdef AXIS_DEBUG 4744961713Sgirish #define AXIS_WAIT (100000) 4844961713Sgirish #define AXIS_LONG_WAIT (100000) 4944961713Sgirish #define AXIS_WAIT_W (80000) 5044961713Sgirish #define AXIS_WAIT_R (100000) 5144961713Sgirish #define AXIS_WAIT_LOOP (4000) 5244961713Sgirish #define AXIS_WAIT_PER_LOOP (AXIS_WAIT_R/AXIS_WAIT_LOOP) 5344961713Sgirish #endif 5444961713Sgirish 5514ea4bb7Ssd #define NO_DEBUG 0x0000000000000000ULL 5614ea4bb7Ssd #define MDT_CTL 0x0000000000000001ULL 5714ea4bb7Ssd #define RX_CTL 0x0000000000000002ULL 5814ea4bb7Ssd #define TX_CTL 0x0000000000000004ULL 5914ea4bb7Ssd #define OBP_CTL 0x0000000000000008ULL 6044961713Sgirish 6114ea4bb7Ssd #define VPD_CTL 0x0000000000000010ULL 6214ea4bb7Ssd #define DDI_CTL 0x0000000000000020ULL 6314ea4bb7Ssd #define MEM_CTL 0x0000000000000040ULL 6414ea4bb7Ssd #define SAP_CTL 0x0000000000000080ULL 6544961713Sgirish 6614ea4bb7Ssd #define IOC_CTL 0x0000000000000100ULL 6714ea4bb7Ssd #define MOD_CTL 0x0000000000000200ULL 6814ea4bb7Ssd #define DMA_CTL 0x0000000000000400ULL 6914ea4bb7Ssd #define STR_CTL 0x0000000000000800ULL 7044961713Sgirish 7114ea4bb7Ssd #define INT_CTL 0x0000000000001000ULL 7214ea4bb7Ssd #define SYSERR_CTL 0x0000000000002000ULL 7314ea4bb7Ssd #define KST_CTL 0x0000000000004000ULL 7414ea4bb7Ssd #define PCS_CTL 0x0000000000008000ULL 7544961713Sgirish 7614ea4bb7Ssd #define MII_CTL 0x0000000000010000ULL 7714ea4bb7Ssd #define MIF_CTL 0x0000000000020000ULL 7814ea4bb7Ssd #define FCRAM_CTL 0x0000000000040000ULL 7914ea4bb7Ssd #define MAC_CTL 0x0000000000080000ULL 8044961713Sgirish 8114ea4bb7Ssd #define IPP_CTL 0x0000000000100000ULL 8214ea4bb7Ssd #define DMA2_CTL 0x0000000000200000ULL 8314ea4bb7Ssd #define RX2_CTL 0x0000000000400000ULL 8414ea4bb7Ssd #define TX2_CTL 0x0000000000800000ULL 8544961713Sgirish 8614ea4bb7Ssd #define MEM2_CTL 0x0000000001000000ULL 8714ea4bb7Ssd #define MEM3_CTL 0x0000000002000000ULL 8814ea4bb7Ssd #define NXGE_CTL 0x0000000004000000ULL 8914ea4bb7Ssd #define NDD_CTL 0x0000000008000000ULL 9014ea4bb7Ssd #define NDD2_CTL 0x0000000010000000ULL 9144961713Sgirish 9214ea4bb7Ssd #define TCAM_CTL 0x0000000020000000ULL 9314ea4bb7Ssd #define CFG_CTL 0x0000000040000000ULL 9414ea4bb7Ssd #define CFG2_CTL 0x0000000080000000ULL 9544961713Sgirish 9614ea4bb7Ssd #define FFLP_CTL TCAM_CTL | FCRAM_CTL 9744961713Sgirish 9814ea4bb7Ssd #define VIR_CTL 0x0000000100000000ULL 9914ea4bb7Ssd #define VIR2_CTL 0x0000000200000000ULL 10044961713Sgirish 101*678453a8Sspeer #define HIO_CTL 0x0000000400000000ULL 102*678453a8Sspeer 10314ea4bb7Ssd #define NXGE_NOTE 0x0000001000000000ULL 10414ea4bb7Ssd #define NXGE_ERR_CTL 0x0000002000000000ULL 10544961713Sgirish 10614ea4bb7Ssd #define DUMP_ALWAYS 0x2000000000000000ULL 10744961713Sgirish 10844961713Sgirish /* NPI Debug and Error defines */ 10914ea4bb7Ssd #define NPI_RDC_CTL 0x0000000000000001ULL 11014ea4bb7Ssd #define NPI_TDC_CTL 0x0000000000000002ULL 11114ea4bb7Ssd #define NPI_TXC_CTL 0x0000000000000004ULL 11214ea4bb7Ssd #define NPI_IPP_CTL 0x0000000000000008ULL 11344961713Sgirish 11414ea4bb7Ssd #define NPI_XPCS_CTL 0x0000000000000010ULL 11514ea4bb7Ssd #define NPI_PCS_CTL 0x0000000000000020ULL 11614ea4bb7Ssd #define NPI_ESR_CTL 0x0000000000000040ULL 11714ea4bb7Ssd #define NPI_BMAC_CTL 0x0000000000000080ULL 11814ea4bb7Ssd #define NPI_XMAC_CTL 0x0000000000000100ULL 11914ea4bb7Ssd #define NPI_MAC_CTL NPI_BMAC_CTL | NPI_XMAC_CTL 12044961713Sgirish 12114ea4bb7Ssd #define NPI_ZCP_CTL 0x0000000000000200ULL 12214ea4bb7Ssd #define NPI_TCAM_CTL 0x0000000000000400ULL 12314ea4bb7Ssd #define NPI_FCRAM_CTL 0x0000000000000800ULL 12414ea4bb7Ssd #define NPI_FFLP_CTL NPI_TCAM_CTL | NPI_FCRAM_CTL 12544961713Sgirish 12614ea4bb7Ssd #define NPI_VIR_CTL 0x0000000000001000ULL 12714ea4bb7Ssd #define NPI_PIO_CTL 0x0000000000002000ULL 12814ea4bb7Ssd #define NPI_VIO_CTL 0x0000000000004000ULL 12944961713Sgirish 13014ea4bb7Ssd #define NPI_REG_CTL 0x0000000040000000ULL 13114ea4bb7Ssd #define NPI_CTL 0x0000000080000000ULL 13214ea4bb7Ssd #define NPI_ERR_CTL 0x0000000080000000ULL 13344961713Sgirish 13414ea4bb7Ssd #if defined(SOLARIS) && defined(_KERNEL) 13544961713Sgirish 13644961713Sgirish #include <sys/types.h> 13744961713Sgirish #include <sys/ddi.h> 13844961713Sgirish #include <sys/sunddi.h> 13944961713Sgirish #include <sys/dditypes.h> 14044961713Sgirish #include <sys/ethernet.h> 14144961713Sgirish 14244961713Sgirish #ifdef NXGE_DEBUG 14344961713Sgirish #define NXGE_DEBUG_MSG(params) nxge_debug_msg params 14444961713Sgirish #else 14544961713Sgirish #define NXGE_DEBUG_MSG(params) 14644961713Sgirish #endif 14744961713Sgirish 14814ea4bb7Ssd #if 1 14944961713Sgirish #define NXGE_ERROR_MSG(params) nxge_debug_msg params 15044961713Sgirish #define NXGE_WARN_MSG(params) nxge_debug_msg params 15144961713Sgirish #else 15244961713Sgirish #define NXGE_ERROR_MSG(params) 15344961713Sgirish #define NXGE_WARN_MSG(params) 15444961713Sgirish #endif 15544961713Sgirish 15644961713Sgirish typedef kmutex_t nxge_os_mutex_t; 15744961713Sgirish typedef krwlock_t nxge_os_rwlock_t; 15844961713Sgirish 15944961713Sgirish typedef dev_info_t nxge_dev_info_t; 16044961713Sgirish typedef ddi_iblock_cookie_t nxge_intr_cookie_t; 16144961713Sgirish 16244961713Sgirish typedef ddi_acc_handle_t nxge_os_acc_handle_t; 16344961713Sgirish typedef nxge_os_acc_handle_t npi_reg_handle_t; 164adfcba55Sjoycey #if defined(__i386) 165adfcba55Sjoycey typedef uint32_t npi_reg_ptr_t; 166adfcba55Sjoycey #else 167adfcba55Sjoycey typedef uint64_t npi_reg_ptr_t; 168adfcba55Sjoycey #endif 16944961713Sgirish 17044961713Sgirish typedef ddi_dma_handle_t nxge_os_dma_handle_t; 17144961713Sgirish typedef struct _nxge_dma_common_t nxge_os_dma_common_t; 17244961713Sgirish typedef struct _nxge_block_mv_t nxge_os_block_mv_t; 17344961713Sgirish typedef frtn_t nxge_os_frtn_t; 17444961713Sgirish 17544961713Sgirish #define NXGE_MUTEX_DRIVER MUTEX_DRIVER 17614ea4bb7Ssd #define MUTEX_INIT(lock, name, type, arg) \ 17714ea4bb7Ssd mutex_init(lock, name, type, arg) 17844961713Sgirish #define MUTEX_ENTER(lock) mutex_enter(lock) 17944961713Sgirish #define MUTEX_TRY_ENTER(lock) mutex_tryenter(lock) 18044961713Sgirish #define MUTEX_EXIT(lock) mutex_exit(lock) 18144961713Sgirish #define MUTEX_DESTROY(lock) mutex_destroy(lock) 18244961713Sgirish 18344961713Sgirish #define RW_INIT(lock, name, type, arg) rw_init(lock, name, type, arg) 18444961713Sgirish #define RW_ENTER_WRITER(lock) rw_enter(lock, RW_WRITER) 18544961713Sgirish #define RW_ENTER_READER(lock) rw_enter(lock, RW_READER) 18644961713Sgirish #define RW_TRY_ENTER(lock, type) rw_tryenter(lock, type) 18744961713Sgirish #define RW_EXIT(lock) rw_exit(lock) 18844961713Sgirish #define RW_DESTROY(lock) rw_destroy(lock) 18944961713Sgirish #define KMEM_ALLOC(size, flag) kmem_alloc(size, flag) 19044961713Sgirish #define KMEM_ZALLOC(size, flag) kmem_zalloc(size, flag) 19144961713Sgirish #define KMEM_FREE(buf, size) kmem_free(buf, size) 19244961713Sgirish 19344961713Sgirish #define NXGE_DELAY(microseconds) (drv_usecwait(microseconds)) 19444961713Sgirish 19514ea4bb7Ssd #define NXGE_PIO_READ8(handle, devaddr, offset) \ 19644961713Sgirish (ddi_get8(handle, (uint8_t *)((caddr_t)devaddr + offset))) 19744961713Sgirish 19814ea4bb7Ssd #define NXGE_PIO_READ16(handle, devaddr, offset) \ 19944961713Sgirish (ddi_get16(handle, (uint16_t *)((caddr_t)devaddr + offset))) 20044961713Sgirish 20114ea4bb7Ssd #define NXGE_PIO_READ32(handle, devaddr, offset) \ 20244961713Sgirish (ddi_get32(handle, (uint32_t *)((caddr_t)devaddr + offset))) 20344961713Sgirish 20414ea4bb7Ssd #define NXGE_PIO_READ64(handle, devaddr, offset) \ 20544961713Sgirish (ddi_get64(handle, (uint64_t *)((caddr_t)devaddr + offset))) 20644961713Sgirish 20714ea4bb7Ssd #define NXGE_PIO_WRITE8(handle, devaddr, offset, data) \ 20844961713Sgirish (ddi_put8(handle, (uint8_t *)((caddr_t)devaddr + offset), data)) 20944961713Sgirish 21014ea4bb7Ssd #define NXGE_PIO_WRITE16(handle, devaddr, offset, data) \ 21144961713Sgirish (ddi_get16(handle, (uint16_t *)((caddr_t)devaddr + offset), data)) 21244961713Sgirish 21344961713Sgirish #define NXGE_PIO_WRITE32(handle, devaddr, offset, data) \ 21444961713Sgirish (ddi_put32(handle, (uint32_t *)((caddr_t)devaddr + offset), data)) 21544961713Sgirish 21614ea4bb7Ssd #define NXGE_PIO_WRITE64(handle, devaddr, offset, data) \ 21744961713Sgirish (ddi_put64(handle, (uint64_t *)((caddr_t)devaddr + offset), data)) 21844961713Sgirish 21914ea4bb7Ssd #define NXGE_NPI_PIO_READ8(npi_handle, offset) \ 22014ea4bb7Ssd (ddi_get8(NPI_REGH(npi_handle), \ 22144961713Sgirish (uint8_t *)(NPI_REGP(npi_handle) + offset))) 22244961713Sgirish 22314ea4bb7Ssd #define NXGE_NPI_PIO_READ16(npi_handle, offset) \ 22414ea4bb7Ssd (ddi_get16(NPI_REGH(npi_handle), \ 22544961713Sgirish (uint16_t *)(NPI_REGP(npi_handle) + offset))) 22644961713Sgirish 22714ea4bb7Ssd #define NXGE_NPI_PIO_READ32(npi_handle, offset) \ 22814ea4bb7Ssd (ddi_get32(NPI_REGH(npi_handle), \ 22944961713Sgirish (uint32_t *)(NPI_REGP(npi_handle) + offset))) 23044961713Sgirish 231adfcba55Sjoycey #if defined(__i386) 232adfcba55Sjoycey #define NXGE_NPI_PIO_READ64(npi_handle, offset) \ 233adfcba55Sjoycey (ddi_get64(NPI_REGH(npi_handle), \ 234adfcba55Sjoycey (uint64_t *)(NPI_REGP(npi_handle) + (uint32_t)offset))) 235adfcba55Sjoycey #else 23644961713Sgirish #define NXGE_NPI_PIO_READ64(npi_handle, offset) \ 23744961713Sgirish (ddi_get64(NPI_REGH(npi_handle), \ 23844961713Sgirish (uint64_t *)(NPI_REGP(npi_handle) + offset))) 239adfcba55Sjoycey #endif 24044961713Sgirish 24144961713Sgirish #define NXGE_NPI_PIO_WRITE8(npi_handle, offset, data) \ 24244961713Sgirish (ddi_put8(NPI_REGH(npi_handle), \ 24344961713Sgirish (uint8_t *)(NPI_REGP(npi_handle) + offset), data)) 24444961713Sgirish 24544961713Sgirish #define NXGE_NPI_PIO_WRITE16(npi_handle, offset, data) \ 24644961713Sgirish (ddi_put16(NPI_REGH(npi_handle), \ 24744961713Sgirish (uint16_t *)(NPI_REGP(npi_handle) + offset), data)) 24844961713Sgirish 24944961713Sgirish #define NXGE_NPI_PIO_WRITE32(npi_handle, offset, data) \ 25044961713Sgirish (ddi_put32(NPI_REGH(npi_handle), \ 25144961713Sgirish (uint32_t *)(NPI_REGP(npi_handle) + offset), data)) 25244961713Sgirish 253adfcba55Sjoycey #if defined(__i386) 254adfcba55Sjoycey #define NXGE_NPI_PIO_WRITE64(npi_handle, offset, data) \ 255adfcba55Sjoycey (ddi_put64(NPI_REGH(npi_handle), \ 256adfcba55Sjoycey (uint64_t *)(NPI_REGP(npi_handle) + (uint32_t)offset), data)) 257adfcba55Sjoycey #else 25844961713Sgirish #define NXGE_NPI_PIO_WRITE64(npi_handle, offset, data) \ 25944961713Sgirish (ddi_put64(NPI_REGH(npi_handle), \ 26044961713Sgirish (uint64_t *)(NPI_REGP(npi_handle) + offset), data)) 261adfcba55Sjoycey #endif 26244961713Sgirish 26344961713Sgirish #define NXGE_MEM_PIO_READ8(npi_handle) \ 26444961713Sgirish (ddi_get8(NPI_REGH(npi_handle), (uint8_t *)NPI_REGP(npi_handle))) 26544961713Sgirish 26644961713Sgirish #define NXGE_MEM_PIO_READ16(npi_handle) \ 26744961713Sgirish (ddi_get16(NPI_REGH(npi_handle), (uint16_t *)NPI_REGP(npi_handle))) 26844961713Sgirish 26944961713Sgirish #define NXGE_MEM_PIO_READ32(npi_handle) \ 27044961713Sgirish (ddi_get32(NPI_REGH(npi_handle), (uint32_t *)NPI_REGP(npi_handle))) 27144961713Sgirish 27244961713Sgirish #define NXGE_MEM_PIO_READ64(npi_handle) \ 27344961713Sgirish (ddi_get64(NPI_REGH(npi_handle), (uint64_t *)NPI_REGP(npi_handle))) 27444961713Sgirish 27544961713Sgirish #define NXGE_MEM_PIO_WRITE8(npi_handle, data) \ 27644961713Sgirish (ddi_put8(NPI_REGH(npi_handle), (uint8_t *)NPI_REGP(npi_handle), data)) 27744961713Sgirish 27844961713Sgirish #define NXGE_MEM_PIO_WRITE16(npi_handle, data) \ 27944961713Sgirish (ddi_put16(NPI_REGH(npi_handle), \ 28044961713Sgirish (uint16_t *)NPI_REGP(npi_handle), data)) 28144961713Sgirish 28244961713Sgirish #define NXGE_MEM_PIO_WRITE32(npi_handle, data) \ 28344961713Sgirish (ddi_put32(NPI_REGH(npi_handle), \ 28444961713Sgirish (uint32_t *)NPI_REGP(npi_handle), data)) 28544961713Sgirish 28644961713Sgirish #define NXGE_MEM_PIO_WRITE64(npi_handle, data) \ 28744961713Sgirish (ddi_put64(NPI_REGH(npi_handle), \ 28844961713Sgirish (uint64_t *)NPI_REGP(npi_handle), data)) 28944961713Sgirish 29044961713Sgirish #define SERVICE_LOST DDI_SERVICE_LOST 29144961713Sgirish #define SERVICE_DEGRADED DDI_SERVICE_DEGRADED 29244961713Sgirish #define SERVICE_UNAFFECTED DDI_SERVICE_UNAFFECTED 29344961713Sgirish #define SERVICE_RESTORED DDI_SERVICE_RESTORED 29444961713Sgirish 29544961713Sgirish #define DATAPATH_FAULT DDI_DATAPATH_FAULT 29644961713Sgirish #define DEVICE_FAULT DDI_DEVICE_FAULT 29744961713Sgirish #define EXTERNAL_FAULT DDI_EXTERNAL_FAULT 29844961713Sgirish 29944961713Sgirish #define NOTE_LINK_UP DL_NOTE_LINK_UP 30044961713Sgirish #define NOTE_LINK_DOWN DL_NOTE_LINK_DOWN 30144961713Sgirish #define NOTE_SPEED DL_NOTE_SPEED 30244961713Sgirish #define NOTE_PHYS_ADDR DL_NOTE_PHYS_ADDR 30344961713Sgirish #define NOTE_AGGR_AVAIL DL_NOTE_AGGR_AVAIL 30444961713Sgirish #define NOTE_AGGR_UNAVAIL DL_NOTE_AGGR_UNAVAIL 30544961713Sgirish 30644961713Sgirish #define FM_REPORT_FAULT(nxgep, impact, location, msg)\ 30744961713Sgirish ddi_dev_report_fault(nxgep->dip, impact, location, msg) 30844961713Sgirish #define FM_CHECK_DEV_HANDLE(nxgep)\ 30944961713Sgirish ddi_check_acc_handle(nxgep->dev_regs->nxge_regh) 31044961713Sgirish #define FM_GET_DEVSTATE(nxgep)\ 31144961713Sgirish ddi_get_devstate(nxgep->dip) 31244961713Sgirish #define FM_SERVICE_RESTORED(nxgep)\ 31344961713Sgirish ddi_fm_service_impact(nxgep->dip, DDI_SERVICE_RESTORED) 31444961713Sgirish #define NXGE_FM_REPORT_ERROR(nxgep, portn, chan, ereport_id)\ 31544961713Sgirish nxge_fm_report_error(nxgep, portn, chan, ereport_id) 31614ea4bb7Ssd #define FM_CHECK_ACC_HANDLE(nxgep, handle)\ 31714ea4bb7Ssd fm_check_acc_handle(handle) 31814ea4bb7Ssd #define FM_CHECK_DMA_HANDLE(nxgep, handle)\ 31914ea4bb7Ssd fm_check_dma_handle(handle) 32044961713Sgirish 32144961713Sgirish #endif 32244961713Sgirish 32344961713Sgirish #if defined(REG_TRACE) 32444961713Sgirish #define NXGE_REG_RD64(handle, offset, val_p) {\ 32544961713Sgirish *(val_p) = NXGE_NPI_PIO_READ64(handle, offset);\ 32644961713Sgirish npi_rtrace_update(handle, B_FALSE, &npi_rtracebuf, (uint32_t)offset, \ 32744961713Sgirish (uint64_t)(*(val_p)));\ 32844961713Sgirish } 32944961713Sgirish #elif defined(REG_SHOW) 33044961713Sgirish /* 33144961713Sgirish * Send 0xbadbad to tell rs_show_reg that we do not have 33244961713Sgirish * a valid RTBUF index to pass 33344961713Sgirish */ 33444961713Sgirish #define NXGE_REG_RD64(handle, offset, val_p) {\ 33544961713Sgirish *(val_p) = NXGE_NPI_PIO_READ64(handle, offset);\ 33644961713Sgirish rt_show_reg(0xbadbad, B_FALSE, (uint32_t)offset, (uint64_t)(*(val_p)));\ 33744961713Sgirish } 33844961713Sgirish #elif defined(AXIS_DEBUG) && !defined(LEGION) 33944961713Sgirish #define NXGE_REG_RD64(handle, offset, val_p) {\ 34044961713Sgirish int n; \ 34144961713Sgirish for (n = 0; n < AXIS_WAIT_LOOP; n++) { \ 34244961713Sgirish *(val_p) = 0; \ 34344961713Sgirish *(val_p) = NXGE_NPI_PIO_READ64(handle, offset);\ 34444961713Sgirish if (*(val_p) != (~0)) { \ 34544961713Sgirish break; \ 34644961713Sgirish } \ 34744961713Sgirish drv_usecwait(AXIS_WAIT_PER_LOOP); \ 34844961713Sgirish if (n < 20) { \ 34944961713Sgirish cmn_err(CE_WARN, "NXGE_REG_RD64: loop %d " \ 35044961713Sgirish "REG 0x%x(0x%llx)", \ 35144961713Sgirish n, offset, *val_p);\ 35244961713Sgirish } \ 35344961713Sgirish } \ 35444961713Sgirish if (n >= AXIS_WAIT_LOOP) { \ 35544961713Sgirish cmn_err(CE_WARN, "(FATAL)NXGE_REG_RD64 on offset 0x%x " \ 35644961713Sgirish "with -1!!!", offset); \ 35744961713Sgirish } \ 35844961713Sgirish } 35944961713Sgirish #else 36044961713Sgirish 36144961713Sgirish #define NXGE_REG_RD64(handle, offset, val_p) {\ 36244961713Sgirish *(val_p) = NXGE_NPI_PIO_READ64(handle, offset);\ 36344961713Sgirish } 36444961713Sgirish #endif 36544961713Sgirish 36644961713Sgirish /* 36744961713Sgirish * In COSIM mode, we could loop for very long time when polling 36844961713Sgirish * for the completion of a Clause45 frame MDIO operations. Display 36944961713Sgirish * one rtrace line for each poll can result in messy screen. Add 37044961713Sgirish * this MACRO for no rtrace show. 37144961713Sgirish */ 37244961713Sgirish #define NXGE_REG_RD64_NO_SHOW(handle, offset, val_p) {\ 37344961713Sgirish *(val_p) = NXGE_NPI_PIO_READ64(handle, offset);\ 37444961713Sgirish } 37544961713Sgirish 37644961713Sgirish 37744961713Sgirish #if defined(REG_TRACE) 37844961713Sgirish #define NXGE_REG_WR64(handle, offset, val) {\ 37944961713Sgirish NXGE_NPI_PIO_WRITE64(handle, (offset), (val));\ 38044961713Sgirish npi_rtrace_update(handle, B_TRUE, &npi_rtracebuf, (uint32_t)offset,\ 38144961713Sgirish (uint64_t)(val));\ 38244961713Sgirish } 38344961713Sgirish #elif defined(REG_SHOW) 38444961713Sgirish /* 38544961713Sgirish * Send 0xbadbad to tell rs_show_reg that we do not have 38644961713Sgirish * a valid RTBUF index to pass 38744961713Sgirish */ 38844961713Sgirish #define NXGE_REG_WR64(handle, offset, val) {\ 38944961713Sgirish NXGE_NPI_PIO_WRITE64(handle, offset, (val));\ 39044961713Sgirish rt_show_reg(0xbadbad, B_TRUE, (uint32_t)offset, (uint64_t)(val));\ 39144961713Sgirish } 39244961713Sgirish #else 39344961713Sgirish #define NXGE_REG_WR64(handle, offset, val) {\ 39444961713Sgirish NXGE_NPI_PIO_WRITE64(handle, (offset), (val));\ 39544961713Sgirish } 39644961713Sgirish #endif 39744961713Sgirish 39844961713Sgirish #ifdef __cplusplus 39944961713Sgirish } 40044961713Sgirish #endif 40144961713Sgirish 40244961713Sgirish #endif /* _SYS_NXGE_NXGE_COMMON_IMPL_H */ 403