1/*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22/*
23 * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
24 * Use is subject to license terms.
25 */
26
27#ifndef	_SYS_NXGE_NXGE_COMMON_IMPL_H
28#define	_SYS_NXGE_NXGE_COMMON_IMPL_H
29
30#ifdef	__cplusplus
31extern "C" {
32#endif
33
34#define	NPI_REGH(npi_handle)		(npi_handle.regh)
35#define	NPI_REGP(npi_handle)		(npi_handle.regp)
36
37#if defined(NXGE_DEBUG_DMA) || defined(NXGE_DEBUG_TXC)
38#define	__NXGE_STATIC
39#define	__NXGE_INLINE
40#else
41#define	__NXGE_STATIC			static
42#define	__NXGE_INLINE			inline
43#endif
44
45#ifdef	AXIS_DEBUG
46#define	AXIS_WAIT			(100000)
47#define	AXIS_LONG_WAIT			(100000)
48#define	AXIS_WAIT_W			(80000)
49#define	AXIS_WAIT_R			(100000)
50#define	AXIS_WAIT_LOOP			(4000)
51#define	AXIS_WAIT_PER_LOOP		(AXIS_WAIT_R/AXIS_WAIT_LOOP)
52#endif
53
54#define	NO_DEBUG	0x0000000000000000ULL
55#define	MDT_CTL		0x0000000000000001ULL
56#define	RX_CTL		0x0000000000000002ULL
57#define	TX_CTL		0x0000000000000004ULL
58#define	OBP_CTL		0x0000000000000008ULL
59
60#define	VPD_CTL		0x0000000000000010ULL
61#define	DDI_CTL		0x0000000000000020ULL
62#define	MEM_CTL		0x0000000000000040ULL
63#define	SAP_CTL		0x0000000000000080ULL
64
65#define	IOC_CTL		0x0000000000000100ULL
66#define	MOD_CTL		0x0000000000000200ULL
67#define	DMA_CTL		0x0000000000000400ULL
68#define	STR_CTL		0x0000000000000800ULL
69
70#define	INT_CTL		0x0000000000001000ULL
71#define	SYSERR_CTL	0x0000000000002000ULL
72#define	KST_CTL		0x0000000000004000ULL
73#define	PCS_CTL		0x0000000000008000ULL
74
75#define	MII_CTL		0x0000000000010000ULL
76#define	MIF_CTL		0x0000000000020000ULL
77#define	FCRAM_CTL	0x0000000000040000ULL
78#define	MAC_CTL		0x0000000000080000ULL
79
80#define	IPP_CTL		0x0000000000100000ULL
81#define	DMA2_CTL	0x0000000000200000ULL
82#define	RX2_CTL		0x0000000000400000ULL
83#define	TX2_CTL		0x0000000000800000ULL
84
85#define	MEM2_CTL	0x0000000001000000ULL
86#define	MEM3_CTL	0x0000000002000000ULL
87#define	NXGE_CTL	0x0000000004000000ULL
88#define	NDD_CTL		0x0000000008000000ULL
89#define	NDD2_CTL	0x0000000010000000ULL
90
91#define	TCAM_CTL	0x0000000020000000ULL
92#define	CFG_CTL		0x0000000040000000ULL
93#define	CFG2_CTL	0x0000000080000000ULL
94
95#define	FFLP_CTL	TCAM_CTL | FCRAM_CTL
96
97#define	VIR_CTL		0x0000000100000000ULL
98#define	VIR2_CTL	0x0000000200000000ULL
99
100#define	HIO_CTL		0x0000000400000000ULL
101
102#define	NXGE_NOTE	0x0000001000000000ULL
103#define	NXGE_ERR_CTL	0x0000002000000000ULL
104
105#define	DUMP_ALWAYS	0x2000000000000000ULL
106
107/* NPI Debug and Error defines */
108#define	NPI_RDC_CTL	0x0000000000000001ULL
109#define	NPI_TDC_CTL	0x0000000000000002ULL
110#define	NPI_TXC_CTL	0x0000000000000004ULL
111#define	NPI_IPP_CTL	0x0000000000000008ULL
112
113#define	NPI_XPCS_CTL	0x0000000000000010ULL
114#define	NPI_PCS_CTL	0x0000000000000020ULL
115#define	NPI_ESR_CTL	0x0000000000000040ULL
116#define	NPI_BMAC_CTL	0x0000000000000080ULL
117#define	NPI_XMAC_CTL	0x0000000000000100ULL
118#define	NPI_MAC_CTL	NPI_BMAC_CTL | NPI_XMAC_CTL
119
120#define	NPI_ZCP_CTL	0x0000000000000200ULL
121#define	NPI_TCAM_CTL	0x0000000000000400ULL
122#define	NPI_FCRAM_CTL	0x0000000000000800ULL
123#define	NPI_FFLP_CTL	NPI_TCAM_CTL | NPI_FCRAM_CTL
124
125#define	NPI_VIR_CTL	0x0000000000001000ULL
126#define	NPI_PIO_CTL	0x0000000000002000ULL
127#define	NPI_VIO_CTL	0x0000000000004000ULL
128
129#define	NPI_REG_CTL	0x0000000040000000ULL
130#define	NPI_CTL		0x0000000080000000ULL
131#define	NPI_ERR_CTL	0x0000000080000000ULL
132
133#include <sys/types.h>
134#include <sys/ddi.h>
135#include <sys/sunddi.h>
136#include <sys/dditypes.h>
137#include <sys/ethernet.h>
138
139#ifdef NXGE_DEBUG
140#define	NXGE_DEBUG_MSG(params) nxge_debug_msg params
141#else
142#define	NXGE_DEBUG_MSG(params)
143#endif
144
145#define	NXGE_ERROR_MSG(params)	nxge_debug_msg params
146#define	NXGE_WARN_MSG(params)	nxge_debug_msg params
147
148typedef kmutex_t			nxge_os_mutex_t;
149typedef	krwlock_t			nxge_os_rwlock_t;
150
151typedef	dev_info_t			nxge_dev_info_t;
152typedef	ddi_iblock_cookie_t 		nxge_intr_cookie_t;
153
154typedef ddi_acc_handle_t		nxge_os_acc_handle_t;
155typedef	nxge_os_acc_handle_t		npi_reg_handle_t;
156#if defined(__i386)
157typedef	uint32_t			npi_reg_ptr_t;
158#else
159typedef uint64_t			npi_reg_ptr_t;
160#endif
161
162typedef ddi_dma_handle_t		nxge_os_dma_handle_t;
163typedef struct _nxge_dma_common_t	nxge_os_dma_common_t;
164typedef struct _nxge_block_mv_t		nxge_os_block_mv_t;
165typedef frtn_t				nxge_os_frtn_t;
166
167#define	NXGE_MUTEX_DRIVER		MUTEX_DRIVER
168#define	MUTEX_INIT(lock, name, type, arg) \
169	mutex_init(lock, name, type, arg)
170#define	MUTEX_ENTER(lock)		mutex_enter(lock)
171#define	MUTEX_TRY_ENTER(lock)		mutex_tryenter(lock)
172#define	MUTEX_EXIT(lock)		mutex_exit(lock)
173#define	MUTEX_DESTROY(lock)		mutex_destroy(lock)
174
175#define	RW_INIT(lock, name, type, arg)	rw_init(lock, name, type, arg)
176#define	RW_ENTER_WRITER(lock)		rw_enter(lock, RW_WRITER)
177#define	RW_ENTER_READER(lock)		rw_enter(lock, RW_READER)
178#define	RW_TRY_ENTER(lock, type)	rw_tryenter(lock, type)
179#define	RW_EXIT(lock)			rw_exit(lock)
180#define	RW_DESTROY(lock)		rw_destroy(lock)
181#define	KMEM_ALLOC(size, flag)		kmem_alloc(size, flag)
182#define	KMEM_ZALLOC(size, flag)		kmem_zalloc(size, flag)
183#define	KMEM_FREE(buf, size)		kmem_free(buf, size)
184
185#define	NXGE_DELAY(microseconds)	 (drv_usecwait(microseconds))
186
187#define	NXGE_PIO_READ8(handle, devaddr, offset) \
188	(ddi_get8(handle, (uint8_t *)((caddr_t)devaddr + offset)))
189
190#define	NXGE_PIO_READ16(handle, devaddr, offset) \
191	(ddi_get16(handle, (uint16_t *)((caddr_t)devaddr + offset)))
192
193#define	NXGE_PIO_READ32(handle, devaddr, offset) \
194	(ddi_get32(handle, (uint32_t *)((caddr_t)devaddr + offset)))
195
196#define	NXGE_PIO_READ64(handle, devaddr, offset) \
197	(ddi_get64(handle, (uint64_t *)((caddr_t)devaddr + offset)))
198
199#define	NXGE_PIO_WRITE8(handle, devaddr, offset, data) \
200	(ddi_put8(handle, (uint8_t *)((caddr_t)devaddr + offset), data))
201
202#define	NXGE_PIO_WRITE16(handle, devaddr, offset, data) \
203	(ddi_get16(handle, (uint16_t *)((caddr_t)devaddr + offset), data))
204
205#define	NXGE_PIO_WRITE32(handle, devaddr, offset, data)	\
206	(ddi_put32(handle, (uint32_t *)((caddr_t)devaddr + offset), data))
207
208#define	NXGE_PIO_WRITE64(handle, devaddr, offset, data) \
209	(ddi_put64(handle, (uint64_t *)((caddr_t)devaddr + offset), data))
210
211#define	NXGE_NPI_PIO_READ8(npi_handle, offset) \
212	(ddi_get8(NPI_REGH(npi_handle),	\
213	(uint8_t *)(NPI_REGP(npi_handle) + offset)))
214
215#define	NXGE_NPI_PIO_READ16(npi_handle, offset) \
216	(ddi_get16(NPI_REGH(npi_handle), \
217	(uint16_t *)(NPI_REGP(npi_handle) + offset)))
218
219#define	NXGE_NPI_PIO_READ32(npi_handle, offset) \
220	(ddi_get32(NPI_REGH(npi_handle), \
221	(uint32_t *)(NPI_REGP(npi_handle) + offset)))
222
223#if defined(__i386)
224#define	NXGE_NPI_PIO_READ64(npi_handle, offset)		\
225	(ddi_get64(NPI_REGH(npi_handle),		\
226	(uint64_t *)(NPI_REGP(npi_handle) + (uint32_t)offset)))
227#else
228#define	NXGE_NPI_PIO_READ64(npi_handle, offset)		\
229	(ddi_get64(NPI_REGH(npi_handle),		\
230	(uint64_t *)(NPI_REGP(npi_handle) + offset)))
231#endif
232
233#define	NXGE_NPI_PIO_WRITE8(npi_handle, offset, data)	\
234	(ddi_put8(NPI_REGH(npi_handle),			\
235	(uint8_t *)(NPI_REGP(npi_handle) + offset), data))
236
237#define	NXGE_NPI_PIO_WRITE16(npi_handle, offset, data)	\
238	(ddi_put16(NPI_REGH(npi_handle),		\
239	(uint16_t *)(NPI_REGP(npi_handle) + offset), data))
240
241#define	NXGE_NPI_PIO_WRITE32(npi_handle, offset, data)	\
242	(ddi_put32(NPI_REGH(npi_handle),		\
243	(uint32_t *)(NPI_REGP(npi_handle) + offset), data))
244
245#if defined(__i386)
246#define	NXGE_NPI_PIO_WRITE64(npi_handle, offset, data)	\
247	(ddi_put64(NPI_REGH(npi_handle),		\
248	(uint64_t *)(NPI_REGP(npi_handle) + (uint32_t)offset), data))
249#else
250#define	NXGE_NPI_PIO_WRITE64(npi_handle, offset, data)	\
251	(ddi_put64(NPI_REGH(npi_handle),		\
252	(uint64_t *)(NPI_REGP(npi_handle) + offset), data))
253#endif
254
255#define	NXGE_MEM_PIO_READ8(npi_handle)		\
256	(ddi_get8(NPI_REGH(npi_handle), (uint8_t *)NPI_REGP(npi_handle)))
257
258#define	NXGE_MEM_PIO_READ16(npi_handle)		\
259	(ddi_get16(NPI_REGH(npi_handle), (uint16_t *)NPI_REGP(npi_handle)))
260
261#define	NXGE_MEM_PIO_READ32(npi_handle)		\
262	(ddi_get32(NPI_REGH(npi_handle), (uint32_t *)NPI_REGP(npi_handle)))
263
264#define	NXGE_MEM_PIO_READ64(npi_handle)		\
265	(ddi_get64(NPI_REGH(npi_handle), (uint64_t *)NPI_REGP(npi_handle)))
266
267#define	NXGE_MEM_PIO_WRITE8(npi_handle, data)	\
268	(ddi_put8(NPI_REGH(npi_handle), (uint8_t *)NPI_REGP(npi_handle), data))
269
270#define	NXGE_MEM_PIO_WRITE16(npi_handle, data)	\
271		(ddi_put16(NPI_REGH(npi_handle),	\
272		(uint16_t *)NPI_REGP(npi_handle), data))
273
274#define	NXGE_MEM_PIO_WRITE32(npi_handle, data)	\
275		(ddi_put32(NPI_REGH(npi_handle),	\
276		(uint32_t *)NPI_REGP(npi_handle), data))
277
278#define	NXGE_MEM_PIO_WRITE64(npi_handle, data)	\
279		(ddi_put64(NPI_REGH(npi_handle),	\
280		(uint64_t *)NPI_REGP(npi_handle), data))
281
282#define	SERVICE_LOST		DDI_SERVICE_LOST
283#define	SERVICE_DEGRADED	DDI_SERVICE_DEGRADED
284#define	SERVICE_UNAFFECTED	DDI_SERVICE_UNAFFECTED
285#define	SERVICE_RESTORED	DDI_SERVICE_RESTORED
286
287#define	DATAPATH_FAULT		DDI_DATAPATH_FAULT
288#define	DEVICE_FAULT		DDI_DEVICE_FAULT
289#define	EXTERNAL_FAULT		DDI_EXTERNAL_FAULT
290
291#define	NOTE_LINK_UP		DL_NOTE_LINK_UP
292#define	NOTE_LINK_DOWN		DL_NOTE_LINK_DOWN
293#define	NOTE_SPEED		DL_NOTE_SPEED
294#define	NOTE_PHYS_ADDR		DL_NOTE_PHYS_ADDR
295#define	NOTE_AGGR_AVAIL		DL_NOTE_AGGR_AVAIL
296#define	NOTE_AGGR_UNAVAIL	DL_NOTE_AGGR_UNAVAIL
297
298#define	FM_REPORT_FAULT(nxgep, impact, location, msg)\
299		ddi_dev_report_fault(nxgep->dip, impact, location, msg)
300#define	FM_CHECK_DEV_HANDLE(nxgep)\
301		ddi_check_acc_handle(nxgep->dev_regs->nxge_regh)
302#define	FM_GET_DEVSTATE(nxgep)\
303		ddi_get_devstate(nxgep->dip)
304#define	FM_SERVICE_RESTORED(nxgep)\
305		ddi_fm_service_impact(nxgep->dip, DDI_SERVICE_RESTORED)
306#define	NXGE_FM_REPORT_ERROR(nxgep, portn, chan, ereport_id)\
307		nxge_fm_report_error(nxgep, portn, chan, ereport_id)
308#define	FM_CHECK_ACC_HANDLE(nxgep, handle)\
309		fm_check_acc_handle(handle)
310#define	FM_CHECK_DMA_HANDLE(nxgep, handle)\
311		fm_check_dma_handle(handle)
312
313#if defined(REG_TRACE)
314#define	NXGE_REG_RD64(handle, offset, val_p) {\
315	*(val_p) = NXGE_NPI_PIO_READ64(handle, offset);\
316	npi_rtrace_update(handle, B_FALSE, &npi_rtracebuf, (uint32_t)offset, \
317			(uint64_t)(*(val_p)));\
318}
319#elif defined(REG_SHOW)
320	/*
321	 * Send 0xbadbad to tell rs_show_reg that we do not have
322	 * a valid RTBUF index to pass
323	 */
324#define	NXGE_REG_RD64(handle, offset, val_p) {\
325	*(val_p) = NXGE_NPI_PIO_READ64(handle, offset);\
326	rt_show_reg(0xbadbad, B_FALSE, (uint32_t)offset, (uint64_t)(*(val_p)));\
327}
328#else
329#define	NXGE_REG_RD64(handle, offset, val_p) {\
330	*(val_p) = NXGE_NPI_PIO_READ64(handle, offset);\
331}
332#endif
333
334#if defined(REG_TRACE)
335#define	NXGE_REG_WR64(handle, offset, val) {\
336	NXGE_NPI_PIO_WRITE64(handle, (offset), (val));\
337	npi_rtrace_update(handle, B_TRUE, &npi_rtracebuf, (uint32_t)offset,\
338				(uint64_t)(val));\
339}
340#elif defined(REG_SHOW)
341/*
342 * Send 0xbadbad to tell rs_show_reg that we do not have
343 * a valid RTBUF index to pass
344 */
345#define	NXGE_REG_WR64(handle, offset, val) {\
346	NXGE_NPI_PIO_WRITE64(handle, offset, (val));\
347	rt_show_reg(0xbadbad, B_TRUE, (uint32_t)offset, (uint64_t)(val));\
348}
349#else
350#define	NXGE_REG_WR64(handle, offset, val) {\
351	NXGE_NPI_PIO_WRITE64(handle, (offset), (val));\
352}
353#endif
354
355#ifdef	__cplusplus
356}
357#endif
358
359#endif	/* _SYS_NXGE_NXGE_COMMON_IMPL_H */
360