1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 * 21 * Copyright (c) 2002-2006 Neterion, Inc. 22 */ 23 24 #ifndef XGE_HAL_DEVICE_H 25 #define XGE_HAL_DEVICE_H 26 27 #include "xge-os-pal.h" 28 #include "xge-queue.h" 29 #include "xgehal-event.h" 30 #include "xgehal-config.h" 31 #include "xgehal-regs.h" 32 #include "xgehal-channel.h" 33 #include "xgehal-stats.h" 34 #include "xgehal-ring.h" 35 36 __EXTERN_BEGIN_DECLS 37 38 #define XGE_HAL_VPD_LENGTH 80 39 #define XGE_HAL_CARD_XENA_VPD_ADDR 0x50 40 #define XGE_HAL_CARD_HERC_VPD_ADDR 0x80 41 #define XGE_HAL_VPD_READ_COMPLETE 0x80 42 #define XGE_HAL_VPD_BUFFER_SIZE 128 43 #define XGE_HAL_DEVICE_XMSI_WAIT_MAX_MILLIS 500 44 #define XGE_HAL_DEVICE_CMDMEM_WAIT_MAX_MILLIS 500 45 #define XGE_HAL_DEVICE_QUIESCENT_WAIT_MAX_MILLIS 500 46 #define XGE_HAL_DEVICE_FAULT_WAIT_MAX_MILLIS 50 47 #define XGE_HAL_DEVICE_RESET_WAIT_MAX_MILLIS 250 48 #define XGE_HAL_DEVICE_SPDM_READY_WAIT_MAX_MILLIS 250 /* TODO */ 49 50 #define XGE_HAL_MAGIC 0x12345678 51 #define XGE_HAL_DEAD 0xDEADDEAD 52 #define XGE_HAL_DUMP_BUF_SIZE 0x4000 53 54 #define XGE_HAL_LRO_MAX_BUCKETS 32 55 56 /** 57 * enum xge_hal_card_e - Xframe adapter type. 58 * @XGE_HAL_CARD_UNKNOWN: Unknown device. 59 * @XGE_HAL_CARD_XENA: Xframe I device. 60 * @XGE_HAL_CARD_HERC: Xframe II (PCI-266Mhz) device. 61 * @XGE_HAL_CARD_TITAN: Xframe ER (PCI-266Mhz) device. 62 * 63 * Enumerates Xframe adapter types. The corresponding PCI device 64 * IDs are listed in the file xgehal-defs.h. 65 * (See XGE_PCI_DEVICE_ID_XENA_1, etc.) 66 * 67 * See also: xge_hal_device_check_id(). 68 */ 69 typedef enum xge_hal_card_e { 70 XGE_HAL_CARD_UNKNOWN = 0, 71 XGE_HAL_CARD_XENA = 1, 72 XGE_HAL_CARD_HERC = 2, 73 XGE_HAL_CARD_TITAN = 3, 74 } xge_hal_card_e; 75 76 /** 77 * struct xge_hal_device_attr_t - Device memory spaces. 78 * @regh0: BAR0 mapped memory handle (Solaris), or simply PCI device @pdev 79 * (Linux and the rest.) 80 * @regh1: BAR1 mapped memory handle. Same comment as above. 81 * @bar0: BAR0 virtual address. 82 * @bar1: BAR1 virtual address. 83 * @irqh: IRQ handle (Solaris). 84 * @cfgh: Configuration space handle (Solaris), or PCI device @pdev (Linux). 85 * @pdev: PCI device object. 86 * 87 * Device memory spaces. Includes configuration, BAR0, BAR1, etc. per device 88 * mapped memories. Also, includes a pointer to OS-specific PCI device object. 89 */ 90 typedef struct xge_hal_device_attr_t { 91 pci_reg_h regh0; 92 pci_reg_h regh1; 93 pci_reg_h regh2; 94 char *bar0; 95 char *bar1; 96 char *bar2; 97 pci_irq_h irqh; 98 pci_cfg_h cfgh; 99 pci_dev_h pdev; 100 } xge_hal_device_attr_t; 101 102 /** 103 * enum xge_hal_device_link_state_e - Link state enumeration. 104 * @XGE_HAL_LINK_NONE: Invalid link state. 105 * @XGE_HAL_LINK_DOWN: Link is down. 106 * @XGE_HAL_LINK_UP: Link is up. 107 * 108 */ 109 typedef enum xge_hal_device_link_state_e { 110 XGE_HAL_LINK_NONE, 111 XGE_HAL_LINK_DOWN, 112 XGE_HAL_LINK_UP 113 } xge_hal_device_link_state_e; 114 115 116 /** 117 * enum xge_hal_pci_mode_e - PIC bus speed and mode specific enumeration. 118 * @XGE_HAL_PCI_33MHZ_MODE: 33 MHZ pci mode. 119 * @XGE_HAL_PCI_66MHZ_MODE: 66 MHZ pci mode. 120 * @XGE_HAL_PCIX_M1_66MHZ_MODE: PCIX M1 66MHZ mode. 121 * @XGE_HAL_PCIX_M1_100MHZ_MODE: PCIX M1 100MHZ mode. 122 * @XGE_HAL_PCIX_M1_133MHZ_MODE: PCIX M1 133MHZ mode. 123 * @XGE_HAL_PCIX_M2_66MHZ_MODE: PCIX M2 66MHZ mode. 124 * @XGE_HAL_PCIX_M2_100MHZ_MODE: PCIX M2 100MHZ mode. 125 * @XGE_HAL_PCIX_M2_133MHZ_MODE: PCIX M3 133MHZ mode. 126 * @XGE_HAL_PCIX_M1_RESERVED: PCIX M1 reserved mode. 127 * @XGE_HAL_PCIX_M1_66MHZ_NS: PCIX M1 66MHZ mode not supported. 128 * @XGE_HAL_PCIX_M1_100MHZ_NS: PCIX M1 100MHZ mode not supported. 129 * @XGE_HAL_PCIX_M1_133MHZ_NS: PCIX M1 133MHZ not supported. 130 * @XGE_HAL_PCIX_M2_RESERVED: PCIX M2 reserved. 131 * @XGE_HAL_PCIX_533_RESERVED: PCIX 533 reserved. 132 * @XGE_HAL_PCI_BASIC_MODE: PCI basic mode, XENA specific value. 133 * @XGE_HAL_PCIX_BASIC_MODE: PCIX basic mode, XENA specific value. 134 * @XGE_HAL_PCI_INVALID_MODE: Invalid PCI or PCIX mode. 135 * 136 */ 137 typedef enum xge_hal_pci_mode_e { 138 XGE_HAL_PCI_33MHZ_MODE = 0x0, 139 XGE_HAL_PCI_66MHZ_MODE = 0x1, 140 XGE_HAL_PCIX_M1_66MHZ_MODE = 0x2, 141 XGE_HAL_PCIX_M1_100MHZ_MODE = 0x3, 142 XGE_HAL_PCIX_M1_133MHZ_MODE = 0x4, 143 XGE_HAL_PCIX_M2_66MHZ_MODE = 0x5, 144 XGE_HAL_PCIX_M2_100MHZ_MODE = 0x6, 145 XGE_HAL_PCIX_M2_133MHZ_MODE = 0x7, 146 XGE_HAL_PCIX_M1_RESERVED = 0x8, 147 XGE_HAL_PCIX_M1_66MHZ_NS = 0xA, 148 XGE_HAL_PCIX_M1_100MHZ_NS = 0xB, 149 XGE_HAL_PCIX_M1_133MHZ_NS = 0xC, 150 XGE_HAL_PCIX_M2_RESERVED = 0xD, 151 XGE_HAL_PCIX_533_RESERVED = 0xE, 152 XGE_HAL_PCI_BASIC_MODE = 0x10, 153 XGE_HAL_PCIX_BASIC_MODE = 0x11, 154 XGE_HAL_PCI_INVALID_MODE = 0x12, 155 } xge_hal_pci_mode_e; 156 157 /** 158 * enum xge_hal_pci_bus_frequency_e - PCI bus frequency enumeration. 159 * @XGE_HAL_PCI_BUS_FREQUENCY_33MHZ: PCI bus frequency 33MHZ 160 * @XGE_HAL_PCI_BUS_FREQUENCY_66MHZ: PCI bus frequency 66MHZ 161 * @XGE_HAL_PCI_BUS_FREQUENCY_100MHZ: PCI bus frequency 100MHZ 162 * @XGE_HAL_PCI_BUS_FREQUENCY_133MHZ: PCI bus frequency 133MHZ 163 * @XGE_HAL_PCI_BUS_FREQUENCY_200MHZ: PCI bus frequency 200MHZ 164 * @XGE_HAL_PCI_BUS_FREQUENCY_250MHZ: PCI bus frequency 250MHZ 165 * @XGE_HAL_PCI_BUS_FREQUENCY_266MHZ: PCI bus frequency 266MHZ 166 * @XGE_HAL_PCI_BUS_FREQUENCY_UNKNOWN: Unrecognized PCI bus frequency value. 167 * 168 */ 169 typedef enum xge_hal_pci_bus_frequency_e { 170 XGE_HAL_PCI_BUS_FREQUENCY_33MHZ = 33, 171 XGE_HAL_PCI_BUS_FREQUENCY_66MHZ = 66, 172 XGE_HAL_PCI_BUS_FREQUENCY_100MHZ = 100, 173 XGE_HAL_PCI_BUS_FREQUENCY_133MHZ = 133, 174 XGE_HAL_PCI_BUS_FREQUENCY_200MHZ = 200, 175 XGE_HAL_PCI_BUS_FREQUENCY_250MHZ = 250, 176 XGE_HAL_PCI_BUS_FREQUENCY_266MHZ = 266, 177 XGE_HAL_PCI_BUS_FREQUENCY_UNKNOWN = 0 178 } xge_hal_pci_bus_frequency_e; 179 180 /** 181 * enum xge_hal_pci_bus_width_e - PCI bus width enumeration. 182 * @XGE_HAL_PCI_BUS_WIDTH_64BIT: 64 bit bus width. 183 * @XGE_HAL_PCI_BUS_WIDTH_32BIT: 32 bit bus width. 184 * @XGE_HAL_PCI_BUS_WIDTH_UNKNOWN: unknown bus width. 185 * 186 */ 187 typedef enum xge_hal_pci_bus_width_e { 188 XGE_HAL_PCI_BUS_WIDTH_64BIT = 0, 189 XGE_HAL_PCI_BUS_WIDTH_32BIT = 1, 190 XGE_HAL_PCI_BUS_WIDTH_UNKNOWN = 2, 191 } xge_hal_pci_bus_width_e; 192 193 #if defined (XGE_HAL_CONFIG_LRO) 194 195 #define IP_TOTAL_LENGTH_OFFSET 2 196 #define IP_FAST_PATH_HDR_MASK 0x45 197 #define TCP_FAST_PATH_HDR_MASK1 0x50 198 #define TCP_FAST_PATH_HDR_MASK2 0x10 199 #define TCP_FAST_PATH_HDR_MASK3 0x18 200 #define IP_SOURCE_ADDRESS_OFFSET 12 201 #define IP_DESTINATION_ADDRESS_OFFSET 16 202 #define TCP_DESTINATION_PORT_OFFSET 2 203 #define TCP_SOURCE_PORT_OFFSET 0 204 #define TCP_DATA_OFFSET_OFFSET 12 205 #define TCP_WINDOW_OFFSET 14 206 #define TCP_SEQUENCE_NUMBER_OFFSET 4 207 #define TCP_ACKNOWLEDGEMENT_NUMBER_OFFSET 8 208 209 typedef struct tcplro { 210 u16 source; 211 u16 dest; 212 u32 seq; 213 u32 ack_seq; 214 u8 doff_res; 215 u8 ctrl; 216 u16 window; 217 u16 check; 218 u16 urg_ptr; 219 } tcplro_t; 220 221 typedef struct iplro { 222 u8 version_ihl; 223 u8 tos; 224 u16 tot_len; 225 u16 id; 226 u16 frag_off; 227 u8 ttl; 228 u8 protocol; 229 u16 check; 230 u32 saddr; 231 u32 daddr; 232 /*The options start here. */ 233 } iplro_t; 234 235 /* 236 * LRO object, one per each LRO session. 237 */ 238 typedef struct lro { 239 /* non-linear: contains scatter-gather list of 240 xframe-mapped received buffers */ 241 OS_NETSTACK_BUF os_buf; 242 OS_NETSTACK_BUF os_buf_end; 243 244 /* link layer header of the first frame; 245 remains intack throughout the processing */ 246 u8 *ll_hdr; 247 248 /* IP header - gets _collapsed_ */ 249 iplro_t *ip_hdr; 250 251 /* transport header - gets _collapsed_ */ 252 tcplro_t *tcp_hdr; 253 254 /* Next tcp sequence number */ 255 u32 tcp_next_seq_num; 256 /* Current tcp seq & ack */ 257 u32 tcp_seq_num; 258 u32 tcp_ack_num; 259 260 /* total number of accumulated (so far) frames */ 261 int sg_num; 262 263 /* total data length */ 264 int total_length; 265 266 /* receive side hash value, available from Hercules */ 267 u32 rth_value; 268 269 /* In use */ 270 u8 in_use; 271 272 /* Total length of the fragments clubbed with the inital frame */ 273 u32 frags_len; 274 275 /* LRO frame contains time stamp, if (ts_off != -1) */ 276 int ts_off; 277 278 } lro_t; 279 #endif 280 281 /* 282 * xge_hal_spdm_entry_t 283 * 284 * Represents a single spdm entry in the SPDM table. 285 */ 286 typedef struct xge_hal_spdm_entry_t { 287 xge_hal_ipaddr_t src_ip; 288 xge_hal_ipaddr_t dst_ip; 289 u32 jhash_value; 290 u16 l4_sp; 291 u16 l4_dp; 292 u16 spdm_entry; 293 u8 in_use; 294 u8 is_tcp; 295 u8 is_ipv4; 296 u8 tgt_queue; 297 } xge_hal_spdm_entry_t; 298 299 #if defined(XGE_HAL_CONFIG_LRO) 300 typedef struct { 301 lro_t lro_pool[XGE_HAL_LRO_MAX_BUCKETS]; 302 int lro_next_idx; 303 lro_t *lro_recent; 304 } xge_hal_lro_desc_t; 305 #endif 306 /* 307 * xge_hal_vpd_data_t 308 * 309 * Represents vpd capabilty structure 310 */ 311 typedef struct xge_hal_vpd_data_t { 312 u8 product_name[XGE_HAL_VPD_LENGTH]; 313 u8 serial_num[XGE_HAL_VPD_LENGTH]; 314 } xge_hal_vpd_data_t; 315 316 /* 317 * xge_hal_device_t 318 * 319 * HAL device object. Represents Xframe. 320 */ 321 typedef struct { 322 unsigned int magic; 323 pci_reg_h regh0; 324 pci_reg_h regh1; 325 pci_reg_h regh2; 326 char *bar0; 327 char *isrbar0; 328 char *bar1; 329 char *bar2; 330 pci_irq_h irqh; 331 pci_cfg_h cfgh; 332 pci_dev_h pdev; 333 xge_hal_pci_config_t pci_config_space; 334 xge_hal_pci_config_t pci_config_space_bios; 335 xge_hal_device_config_t config; 336 xge_list_t free_channels; 337 xge_list_t fifo_channels; 338 xge_list_t ring_channels; 339 volatile int is_initialized; 340 volatile int terminating; 341 xge_hal_stats_t stats; 342 macaddr_t macaddr[1]; 343 xge_queue_h queueh; 344 volatile int mcast_refcnt; 345 int is_promisc; 346 volatile xge_hal_device_link_state_e link_state; 347 void *upper_layer_info; 348 xge_hal_device_attr_t orig_attr; 349 u16 device_id; 350 u8 revision; 351 int msi_enabled; 352 int hw_is_initialized; 353 u64 inject_serr; 354 u64 inject_ecc; 355 u8 inject_bad_tcode; 356 int inject_bad_tcode_for_chan_type; 357 int reset_needed_after_close; 358 int tti_enabled; 359 xge_hal_tti_config_t bimodal_tti[XGE_HAL_MAX_RING_NUM]; 360 int bimodal_timer_val_us; 361 int bimodal_urange_a_en; 362 int bimodal_intr_cnt; 363 char *spdm_mem_base; 364 u16 spdm_max_entries; 365 xge_hal_spdm_entry_t **spdm_table; 366 spinlock_t spdm_lock; 367 #if defined(XGE_HAL_CONFIG_LRO) 368 xge_hal_lro_desc_t lro_desc[XGE_HAL_MAX_RING_NUM]; 369 #endif 370 spinlock_t xena_post_lock; 371 372 /* bimodal workload stats */ 373 int irq_workload_rxd[XGE_HAL_MAX_RING_NUM]; 374 int irq_workload_rxcnt[XGE_HAL_MAX_RING_NUM]; 375 int irq_workload_rxlen[XGE_HAL_MAX_RING_NUM]; 376 int irq_workload_txd[XGE_HAL_MAX_FIFO_NUM]; 377 int irq_workload_txcnt[XGE_HAL_MAX_FIFO_NUM]; 378 int irq_workload_txlen[XGE_HAL_MAX_FIFO_NUM]; 379 380 int mtu_first_time_set; 381 u64 rxufca_lbolt; 382 u64 rxufca_lbolt_time; 383 u64 rxufca_intr_thres; 384 char* dump_buf; 385 xge_hal_pci_mode_e pci_mode; 386 xge_hal_pci_bus_frequency_e bus_frequency; 387 xge_hal_pci_bus_width_e bus_width; 388 xge_hal_vpd_data_t vpd_data; 389 volatile int in_poll; 390 u64 msix_vector_table[XGE_HAL_MAX_MSIX_MESSAGES_WITH_ADDR]; 391 } xge_hal_device_t; 392 393 394 /* ========================== PRIVATE API ================================= */ 395 396 void 397 __hal_device_event_queued(void *data, int event_type); 398 399 xge_hal_status_e 400 __hal_device_set_swapper(xge_hal_device_t *hldev); 401 402 xge_hal_status_e 403 __hal_device_rth_it_configure(xge_hal_device_t *hldev); 404 405 xge_hal_status_e 406 __hal_device_rth_spdm_configure(xge_hal_device_t *hldev); 407 408 xge_hal_status_e 409 __hal_verify_pcc_idle(xge_hal_device_t *hldev, u64 adp_status); 410 411 xge_hal_status_e 412 __hal_device_handle_pic(xge_hal_device_t *hldev, u64 reason); 413 414 xge_hal_status_e 415 __hal_read_spdm_entry_line(xge_hal_device_t *hldev, u8 spdm_line, 416 u16 spdm_entry, u64 *spdm_line_val); 417 418 void __hal_pio_mem_write32_upper(pci_dev_h pdev, pci_reg_h regh, u32 val, 419 void *addr); 420 421 void __hal_pio_mem_write32_lower(pci_dev_h pdev, pci_reg_h regh, u32 val, 422 void *addr); 423 void __hal_device_get_vpd_data(xge_hal_device_t *hldev); 424 425 xge_hal_status_e 426 __hal_device_handle_txpic(xge_hal_device_t *hldev, u64 reason); 427 428 xge_hal_status_e 429 __hal_device_handle_txdma(xge_hal_device_t *hldev, u64 reason); 430 431 xge_hal_status_e 432 __hal_device_handle_txmac(xge_hal_device_t *hldev, u64 reason); 433 434 xge_hal_status_e 435 __hal_device_handle_txxgxs(xge_hal_device_t *hldev, u64 reason); 436 437 xge_hal_status_e 438 __hal_device_handle_rxpic(xge_hal_device_t *hldev, u64 reason); 439 440 xge_hal_status_e 441 __hal_device_handle_rxdma(xge_hal_device_t *hldev, u64 reason); 442 443 xge_hal_status_e 444 __hal_device_handle_rxmac(xge_hal_device_t *hldev, u64 reason); 445 446 xge_hal_status_e 447 __hal_device_handle_rxxgxs(xge_hal_device_t *hldev, u64 reason); 448 449 xge_hal_status_e 450 __hal_device_handle_mc(xge_hal_device_t *hldev, u64 reason); 451 452 xge_hal_status_e 453 __hal_device_register_poll(xge_hal_device_t *hldev, u64 *reg, int op, u64 mask, 454 int max_millis); 455 xge_hal_status_e 456 __hal_device_rts_mac_configure(xge_hal_device_t *hldev); 457 458 xge_hal_status_e 459 __hal_device_rts_qos_configure(xge_hal_device_t *hldev); 460 461 xge_hal_status_e 462 __hal_device_rts_port_configure(xge_hal_device_t *hldev); 463 464 xge_hal_status_e 465 __hal_device_rti_configure(xge_hal_device_t *hldev, int runtime); 466 467 void 468 __hal_device_msi_intr_endis(xge_hal_device_t *hldev, int flag); 469 470 void 471 __hal_device_msix_intr_endis(xge_hal_device_t *hldev, 472 xge_hal_channel_t *channel, int flag); 473 474 /* =========================== PUBLIC API ================================= */ 475 476 unsigned int 477 __hal_fix_time_ival_herc(xge_hal_device_t *hldev, 478 unsigned int time_ival); 479 xge_hal_status_e 480 xge_hal_rts_rth_itable_set(xge_hal_device_t *hldev, u8 *itable, 481 u32 itable_size); 482 483 void 484 xge_hal_rts_rth_set(xge_hal_device_t *hldev, u8 def_q, u64 hash_type, 485 u16 bucket_size); 486 487 void 488 xge_hal_rts_rth_init(xge_hal_device_t *hldev); 489 490 void 491 xge_hal_rts_rth_clr(xge_hal_device_t *hldev); 492 493 void 494 xge_hal_rts_rth_start(xge_hal_device_t *hldev); 495 496 void 497 xge_hal_rts_rth_stop(xge_hal_device_t *hldev); 498 499 void 500 xge_hal_device_rts_rth_key_set(xge_hal_device_t *hldev, u8 KeySize, u8 *Key); 501 502 xge_hal_status_e 503 xge_hal_device_rts_mac_enable(xge_hal_device_h devh, int index, macaddr_t macaddr); 504 505 xge_hal_status_e 506 xge_hal_device_rts_mac_disable(xge_hal_device_h devh, int index); 507 508 int xge_hal_reinitialize_hw(xge_hal_device_t * hldev); 509 510 xge_hal_status_e xge_hal_fix_rldram_ecc_error(xge_hal_device_t * hldev); 511 /** 512 * xge_hal_device_rti_reconfigure 513 * @hldev: Hal Device 514 */ 515 static inline xge_hal_status_e 516 xge_hal_device_rti_reconfigure(xge_hal_device_t *hldev) 517 { 518 return __hal_device_rti_configure(hldev, 1); 519 } 520 521 /** 522 * xge_hal_device_rts_port_reconfigure 523 * @hldev: Hal Device 524 */ 525 static inline xge_hal_status_e 526 xge_hal_device_rts_port_reconfigure(xge_hal_device_t *hldev) 527 { 528 return __hal_device_rts_port_configure(hldev); 529 } 530 531 /** 532 * xge_hal_device_is_initialized - Returns 0 if device is not 533 * initialized, non-zero otherwise. 534 * @devh: HAL device handle. 535 * 536 * Returns 0 if device is not initialized, non-zero otherwise. 537 */ 538 static inline int 539 xge_hal_device_is_initialized(xge_hal_device_h devh) 540 { 541 return ((xge_hal_device_t*)devh)->is_initialized; 542 } 543 544 545 /** 546 * xge_hal_device_in_poll - non-zero, if xge_hal_device_poll() is executing. 547 * @devh: HAL device handle. 548 * 549 * Returns non-zero if xge_hal_device_poll() is executing, and 0 - otherwise. 550 */ 551 static inline int 552 xge_hal_device_in_poll(xge_hal_device_h devh) 553 { 554 return ((xge_hal_device_t*)devh)->in_poll; 555 } 556 557 558 /** 559 * xge_hal_device_inject_ecc - Inject ECC error. 560 * @devh: HAL device, pointer to xge_hal_device_t structure. 561 * @err_reg: Contains the error register. 562 * 563 * This function is used to inject ECC error into the driver flow. 564 * This facility can be used to test the driver flow in the 565 * case of ECC error is reported by the firmware. 566 * 567 * Returns: void 568 * See also: xge_hal_device_inject_serr(), 569 * xge_hal_device_inject_bad_tcode() 570 */ 571 static inline void 572 xge_hal_device_inject_ecc(xge_hal_device_h devh, u64 err_reg) 573 { 574 ((xge_hal_device_t*)devh)->inject_ecc = err_reg; 575 } 576 577 578 /** 579 * xge_hal_device_inject_serr - Inject SERR error. 580 * @devh: HAL device, pointer to xge_hal_device_t structure. 581 * @err_reg: Contains the error register. 582 * 583 * This function is used to inject SERR error into the driver flow. 584 * This facility can be used to test the driver flow in the 585 * case of SERR error is reported by firmware. 586 * 587 * Returns: void 588 * See also: xge_hal_device_inject_ecc(), 589 * xge_hal_device_inject_bad_tcode() 590 */ 591 static inline void 592 xge_hal_device_inject_serr(xge_hal_device_h devh, u64 err_reg) 593 { 594 ((xge_hal_device_t*)devh)->inject_serr = err_reg; 595 } 596 597 598 /** 599 * xge_hal_device_inject_bad_tcode - Inject Bad transfer code. 600 * @devh: HAL device, pointer to xge_hal_device_t structure. 601 * @chan_type: Channel type (fifo/ring). 602 * @t_code: Transfer code. 603 * 604 * This function is used to inject bad (Tx/Rx Data)transfer code 605 * into the driver flow. 606 * 607 * This facility can be used to test the driver flow in the 608 * case of bad transfer code reported by firmware for a Tx/Rx data 609 * transfer. 610 * 611 * Returns: void 612 * See also: xge_hal_device_inject_ecc(), xge_hal_device_inject_serr() 613 */ 614 static inline void 615 xge_hal_device_inject_bad_tcode(xge_hal_device_h devh, int chan_type, u8 t_code) 616 { 617 ((xge_hal_device_t*)devh)->inject_bad_tcode_for_chan_type = chan_type; 618 ((xge_hal_device_t*)devh)->inject_bad_tcode = t_code; 619 } 620 621 void xge_hal_device_msi_enable(xge_hal_device_h devh); 622 623 /* 624 * xge_hal_device_msi_mode - Is MSI enabled? 625 * @devh: HAL device handle. 626 * 627 * Returns 0 if MSI is enabled for the specified device, 628 * non-zero otherwise. 629 */ 630 static inline int 631 xge_hal_device_msi_mode(xge_hal_device_h devh) 632 { 633 return ((xge_hal_device_t*)devh)->msi_enabled; 634 } 635 636 /** 637 * xge_hal_device_queue - Get per-device event queue. 638 * @devh: HAL device handle. 639 * 640 * Returns: event queue associated with the specified HAL device. 641 */ 642 static inline xge_queue_h 643 xge_hal_device_queue (xge_hal_device_h devh) 644 { 645 return ((xge_hal_device_t*)devh)->queueh; 646 } 647 648 /** 649 * xge_hal_device_attr - Get original (user-specified) device 650 * attributes. 651 * @devh: HAL device handle. 652 * 653 * Returns: original (user-specified) device attributes. 654 */ 655 static inline xge_hal_device_attr_t* 656 xge_hal_device_attr(xge_hal_device_h devh) 657 { 658 return &((xge_hal_device_t*)devh)->orig_attr; 659 } 660 661 /** 662 * xge_hal_device_private_set - Set ULD context. 663 * @devh: HAL device handle. 664 * @data: pointer to ULD context 665 * 666 * Use HAL device to set upper-layer driver (ULD) context. 667 * 668 * See also: xge_hal_device_from_private(), xge_hal_device_private() 669 */ 670 static inline void 671 xge_hal_device_private_set(xge_hal_device_h devh, void *data) 672 { 673 ((xge_hal_device_t*)devh)->upper_layer_info = data; 674 } 675 676 /** 677 * xge_hal_device_private - Get ULD context. 678 * @devh: HAL device handle. 679 * 680 * Use HAL device to get upper-layer driver (ULD) context. 681 * 682 * Returns: ULD context. 683 * 684 * See also: xge_hal_device_from_private(), xge_hal_device_private_set() 685 */ 686 static inline void* 687 xge_hal_device_private(xge_hal_device_h devh) 688 { 689 return ((xge_hal_device_t*)devh)->upper_layer_info; 690 } 691 692 /** 693 * xge_hal_device_from_private - Get HAL device object from private. 694 * @info_ptr: ULD context. 695 * 696 * Use ULD context to get HAL device. 697 * 698 * Returns: Device handle. 699 * 700 * See also: xge_hal_device_private(), xge_hal_device_private_set() 701 */ 702 static inline xge_hal_device_h 703 xge_hal_device_from_private(void *info_ptr) 704 { 705 return xge_container_of((void ** ) info_ptr, xge_hal_device_t, 706 upper_layer_info); 707 } 708 709 /** 710 * xge_hal_device_mtu_check - check MTU value for ranges 711 * @hldev: the device 712 * @new_mtu: new MTU value to check 713 * 714 * Will do sanity check for new MTU value. 715 * 716 * Returns: XGE_HAL_OK - success. 717 * XGE_HAL_ERR_INVALID_MTU_SIZE - MTU is invalid. 718 * 719 * See also: xge_hal_device_mtu_set() 720 */ 721 static inline xge_hal_status_e 722 xge_hal_device_mtu_check(xge_hal_device_t *hldev, int new_mtu) 723 { 724 if ((new_mtu < XGE_HAL_MIN_MTU) || (new_mtu > XGE_HAL_MAX_MTU)) { 725 return XGE_HAL_ERR_INVALID_MTU_SIZE; 726 } 727 728 return XGE_HAL_OK; 729 } 730 731 void xge_hal_device_bcast_enable(xge_hal_device_h devh); 732 733 void xge_hal_device_bcast_disable(xge_hal_device_h devh); 734 735 void xge_hal_device_terminating(xge_hal_device_h devh); 736 737 xge_hal_status_e xge_hal_device_initialize(xge_hal_device_t *hldev, 738 xge_hal_device_attr_t *attr, xge_hal_device_config_t *config); 739 740 void xge_hal_device_terminate(xge_hal_device_t *hldev); 741 742 xge_hal_status_e xge_hal_device_reset(xge_hal_device_t *hldev); 743 744 xge_hal_status_e xge_hal_device_macaddr_get(xge_hal_device_t *hldev, 745 int index, macaddr_t *macaddr); 746 747 xge_hal_status_e xge_hal_device_macaddr_set(xge_hal_device_t *hldev, 748 int index, macaddr_t macaddr); 749 750 xge_hal_status_e xge_hal_device_macaddr_clear(xge_hal_device_t *hldev, 751 int index); 752 753 int xge_hal_device_macaddr_find(xge_hal_device_t *hldev, macaddr_t wanted); 754 755 xge_hal_status_e xge_hal_device_mtu_set(xge_hal_device_t *hldev, int new_mtu); 756 757 xge_hal_status_e xge_hal_device_status(xge_hal_device_t *hldev, u64 *hw_status); 758 759 void xge_hal_device_intr_enable(xge_hal_device_t *hldev); 760 761 void xge_hal_device_intr_disable(xge_hal_device_t *hldev); 762 763 xge_hal_status_e xge_hal_device_mcast_enable(xge_hal_device_t *hldev); 764 765 xge_hal_status_e xge_hal_device_mcast_disable(xge_hal_device_t *hldev); 766 767 void xge_hal_device_promisc_enable(xge_hal_device_t *hldev); 768 769 void xge_hal_device_promisc_disable(xge_hal_device_t *hldev); 770 771 xge_hal_status_e xge_hal_device_disable(xge_hal_device_t *hldev); 772 773 xge_hal_status_e xge_hal_device_enable(xge_hal_device_t *hldev); 774 775 xge_hal_status_e xge_hal_device_handle_tcode(xge_hal_channel_h channelh, 776 xge_hal_dtr_h dtrh, 777 u8 t_code); 778 779 xge_hal_status_e xge_hal_device_link_state(xge_hal_device_h devh, 780 xge_hal_device_link_state_e *ls); 781 782 void xge_hal_device_sched_timer(xge_hal_device_h devh, int interval_us, 783 int one_shot); 784 785 void xge_hal_device_poll(xge_hal_device_h devh); 786 787 xge_hal_card_e xge_hal_device_check_id(xge_hal_device_h devh); 788 789 int xge_hal_device_is_slot_freeze(xge_hal_device_h devh); 790 791 xge_hal_status_e 792 xge_hal_device_pci_info_get(xge_hal_device_h devh, xge_hal_pci_mode_e *pci_mode, 793 xge_hal_pci_bus_frequency_e *bus_frequency, 794 xge_hal_pci_bus_width_e *bus_width); 795 796 xge_hal_status_e 797 xge_hal_spdm_entry_add(xge_hal_device_h devh, xge_hal_ipaddr_t *src_ip, 798 xge_hal_ipaddr_t *dst_ip, u16 l4_sp, u16 l4_dp, 799 u8 is_tcp, u8 is_ipv4, u8 tgt_queue); 800 801 xge_hal_status_e 802 xge_hal_spdm_entry_remove(xge_hal_device_h devh, xge_hal_ipaddr_t *src_ip, 803 xge_hal_ipaddr_t *dst_ip, u16 l4_sp, u16 l4_dp, 804 u8 is_tcp, u8 is_ipv4); 805 806 xge_hal_status_e 807 xge_hal_device_rts_section_enable(xge_hal_device_h devh, int index); 808 809 int 810 xge_hal_device_is_closed (xge_hal_device_h devh); 811 812 /* private functions, don't use them in ULD */ 813 814 void __hal_serial_mem_write64(xge_hal_device_t *hldev, u64 value, u64 *reg); 815 816 u64 __hal_serial_mem_read64(xge_hal_device_t *hldev, u64 *reg); 817 818 819 /* Some function protoypes for MSI implementation. */ 820 xge_hal_status_e 821 xge_hal_channel_msi_set (xge_hal_channel_h channelh, int msi, 822 u32 msg_val); 823 void 824 xge_hal_mask_msi(xge_hal_device_t *hldev); 825 826 void 827 xge_hal_unmask_msi(xge_hal_channel_h channelh); 828 829 xge_hal_status_e 830 xge_hal_channel_msix_set(xge_hal_channel_h channelh, int msix_idx); 831 832 xge_hal_status_e 833 xge_hal_mask_msix(xge_hal_device_h devh, int msi_id); 834 835 xge_hal_status_e 836 xge_hal_unmask_msix(xge_hal_device_h devh, int msi_id); 837 838 #if defined(XGE_HAL_CONFIG_LRO) 839 xge_hal_status_e 840 xge_hal_lro_init(u32 lro_scale, xge_hal_device_t *hldev); 841 842 void 843 xge_hal_lro_terminate(u32 lro_scale, xge_hal_device_t *hldev); 844 #endif 845 846 #if defined(XGE_DEBUG_FP) && (XGE_DEBUG_FP & XGE_DEBUG_FP_DEVICE) 847 #define __HAL_STATIC_DEVICE 848 #define __HAL_INLINE_DEVICE 849 850 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE int 851 xge_hal_device_rev(xge_hal_device_t *hldev); 852 853 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE xge_hal_status_e 854 xge_hal_device_begin_irq(xge_hal_device_t *hldev, u64 *reason); 855 856 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void 857 xge_hal_device_clear_rx(xge_hal_device_t *hldev); 858 859 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void 860 xge_hal_device_clear_tx(xge_hal_device_t *hldev); 861 862 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE xge_hal_status_e 863 xge_hal_device_continue_irq(xge_hal_device_t *hldev); 864 865 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE xge_hal_status_e 866 xge_hal_device_handle_irq(xge_hal_device_t *hldev); 867 868 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE char * 869 xge_hal_device_bar0(xge_hal_device_t *hldev); 870 871 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE char * 872 xge_hal_device_isrbar0(xge_hal_device_t *hldev); 873 874 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE char * 875 xge_hal_device_bar1(xge_hal_device_t *hldev); 876 877 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void 878 xge_hal_device_bar0_set(xge_hal_device_t *hldev, char *bar0); 879 880 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void 881 xge_hal_device_isrbar0_set(xge_hal_device_t *hldev, char *isrbar0); 882 883 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void 884 xge_hal_device_bar1_set(xge_hal_device_t *hldev, xge_hal_channel_h channelh, 885 char *bar1); 886 887 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void 888 xge_hal_device_mask_tx(xge_hal_device_t *hldev); 889 890 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void 891 xge_hal_device_mask_rx(xge_hal_device_t *hldev); 892 893 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void 894 xge_hal_device_mask_all(xge_hal_device_t *hldev); 895 896 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void 897 xge_hal_device_unmask_tx(xge_hal_device_t *hldev); 898 899 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void 900 xge_hal_device_unmask_rx(xge_hal_device_t *hldev); 901 902 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void 903 xge_hal_device_unmask_all(xge_hal_device_t *hldev); 904 905 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE xge_hal_status_e 906 xge_hal_device_poll_tx_channels(xge_hal_device_t *hldev, int *got_tx); 907 908 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE xge_hal_status_e 909 xge_hal_device_poll_rx_channels(xge_hal_device_t *hldev, int *got_rx); 910 911 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE xge_hal_status_e 912 xge_hal_device_poll_rx_channel(xge_hal_channel_t *channel, int *got_rx); 913 914 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE xge_hal_status_e 915 xge_hal_device_poll_tx_channel(xge_hal_channel_t *channel, int *got_tx); 916 917 #if defined (XGE_HAL_CONFIG_LRO) 918 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL u8 919 __hal_header_parse_token_u8(u8 *string,u16 offset); 920 921 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL u16 922 __hal_header_parse_token_u16(u8 *string,u16 offset); 923 924 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL u32 925 __hal_header_parse_token_u32(u8 *string,u16 offset); 926 927 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL void 928 __hal_header_update_u8(u8 *string, u16 offset, u8 val); 929 930 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL void 931 __hal_header_update_u16(u8 *string, u16 offset, u16 val); 932 933 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL void 934 __hal_header_update_u32(u8 *string, u16 offset, u32 val); 935 936 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL u16 937 __hal_tcp_seg_len(iplro_t *ip, tcplro_t *tcp); 938 939 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e 940 __hal_ip_lro_capable(iplro_t *ip, xge_hal_dtr_info_t *ext_info); 941 942 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e 943 __hal_tcp_lro_capable(iplro_t *ip, tcplro_t *tcp, lro_t *lro, int *ts_off); 944 945 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e 946 __hal_lro_capable(u8 *buffer, iplro_t **ip, tcplro_t **tcp, 947 xge_hal_dtr_info_t *ext_info); 948 949 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e 950 __hal_get_lro_session(u8 *eth_hdr, iplro_t *ip, tcplro_t *tcp, lro_t **lro, 951 xge_hal_dtr_info_t *ext_info, xge_hal_device_t *hldev, 952 xge_hal_lro_desc_t *ring_lro, lro_t **lro_end3); 953 954 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e 955 __hal_lro_under_optimal_thresh(iplro_t *ip, tcplro_t *tcp, lro_t *lro, 956 xge_hal_device_t *hldev); 957 958 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e 959 __hal_collapse_ip_hdr(iplro_t *ip, tcplro_t *tcp, lro_t *lro, 960 xge_hal_device_t *hldev); 961 962 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e 963 __hal_collapse_tcp_hdr(iplro_t *ip, tcplro_t *tcp, lro_t *lro, 964 xge_hal_device_t *hldev); 965 966 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e 967 __hal_append_lro(iplro_t *ip, tcplro_t **tcp, u32 *seg_len, lro_t *lro, 968 xge_hal_device_t *hldev); 969 970 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e 971 xge_hal_lro_process_rx(int ring, u8 *eth_hdr, u8 *ip_hdr, tcplro_t **tcp, 972 u32 *seglen, lro_t **p_lro, 973 xge_hal_dtr_info_t *ext_info, xge_hal_device_t *hldev, 974 lro_t **lro_end3); 975 976 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e 977 xge_hal_accumulate_large_rx(u8 *buffer, tcplro_t **tcp, u32 *seglen, 978 lro_t **lro, xge_hal_dtr_info_t *ext_info, 979 xge_hal_device_t *hldev, lro_t **lro_end3); 980 981 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL lro_t * 982 xge_hal_lro_next_session (xge_hal_device_t *hldev, int ring); 983 984 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL lro_t * 985 xge_hal_lro_get_next_session(xge_hal_device_t *hldev); 986 987 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL void 988 __hal_open_lro_session (u8 *buffer, iplro_t *ip, tcplro_t *tcp, lro_t **lro, 989 xge_hal_device_t *hldev, xge_hal_lro_desc_t *ring_lro, 990 int slot, u32 tcp_seg_len, int ts_off); 991 992 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL int 993 __hal_lro_get_free_slot (xge_hal_lro_desc_t *ring_lro); 994 #endif 995 996 #else /* XGE_FASTPATH_EXTERN */ 997 #define __HAL_STATIC_DEVICE static 998 #define __HAL_INLINE_DEVICE inline 999 #include "xgehal-device-fp.c" 1000 #endif /* XGE_FASTPATH_INLINE */ 1001 1002 1003 __EXTERN_END_DECLS 1004 1005 #endif /* XGE_HAL_DEVICE_H */ 1006