1/*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 *
21 * Copyright (c) 2002-2006 Neterion, Inc.
22 */
23
24/*
25 * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
26 * Use is subject to license terms.
27 */
28
29#ifndef XGE_HAL_DEVICE_H
30#define XGE_HAL_DEVICE_H
31
32#include "xge-os-pal.h"
33#include "xge-queue.h"
34#include "xgehal-event.h"
35#include "xgehal-config.h"
36#include "xgehal-regs.h"
37#include "xgehal-channel.h"
38#include "xgehal-stats.h"
39#include "xgehal-ring.h"
40
41__EXTERN_BEGIN_DECLS
42
43#define XGE_HAL_VPD_LENGTH                              80
44#define XGE_HAL_CARD_XENA_VPD_ADDR                      0x50
45#define XGE_HAL_CARD_HERC_VPD_ADDR                      0x80
46#define XGE_HAL_VPD_READ_COMPLETE                       0x80
47#define XGE_HAL_VPD_BUFFER_SIZE                         128
48#define XGE_HAL_DEVICE_XMSI_WAIT_MAX_MILLIS		500
49#define XGE_HAL_DEVICE_CMDMEM_WAIT_MAX_MILLIS		500
50#define XGE_HAL_DEVICE_QUIESCENT_WAIT_MAX_MILLIS	500
51#define XGE_HAL_DEVICE_FAULT_WAIT_MAX_MILLIS		50
52#define XGE_HAL_DEVICE_RESET_WAIT_MAX_MILLIS		250
53#define XGE_HAL_DEVICE_SPDM_READY_WAIT_MAX_MILLIS	250  /* TODO */
54
55#define XGE_HAL_MAGIC					0x12345678
56#define XGE_HAL_DEAD					0xDEADDEAD
57#define XGE_HAL_DUMP_BUF_SIZE                           0x4000
58
59#define XGE_HAL_LRO_MAX_BUCKETS				32
60
61/**
62 * enum xge_hal_card_e - Xframe adapter type.
63 * @XGE_HAL_CARD_UNKNOWN: Unknown device.
64 * @XGE_HAL_CARD_XENA: Xframe I device.
65 * @XGE_HAL_CARD_HERC: Xframe II (PCI-266Mhz) device.
66 * @XGE_HAL_CARD_TITAN: Xframe ER (PCI-266Mhz) device.
67 *
68 * Enumerates Xframe adapter types. The corresponding PCI device
69 * IDs are listed in the file xgehal-defs.h.
70 * (See XGE_PCI_DEVICE_ID_XENA_1, etc.)
71 *
72 * See also: xge_hal_device_check_id().
73 */
74typedef enum xge_hal_card_e {
75	XGE_HAL_CARD_UNKNOWN	= 0,
76	XGE_HAL_CARD_XENA	= 1,
77	XGE_HAL_CARD_HERC	= 2,
78	XGE_HAL_CARD_TITAN	= 3,
79} xge_hal_card_e;
80
81/**
82 * struct xge_hal_device_attr_t - Device memory spaces.
83 * @regh0: BAR0 mapped memory handle (Solaris), or simply PCI device @pdev
84 *         (Linux and the rest.)
85 * @regh1: BAR1 mapped memory handle. Same comment as above.
86 * @bar0: BAR0 virtual address.
87 * @bar1: BAR1 virtual address.
88 * @irqh: IRQ handle (Solaris).
89 * @cfgh: Configuration space handle (Solaris), or PCI device @pdev (Linux).
90 * @pdev: PCI device object.
91 *
92 * Device memory spaces. Includes configuration, BAR0, BAR1, etc. per device
93 * mapped memories. Also, includes a pointer to OS-specific PCI device object.
94 */
95typedef struct xge_hal_device_attr_t {
96	pci_reg_h		regh0;
97	pci_reg_h		regh1;
98	pci_reg_h		regh2;
99	char			*bar0;
100	char			*bar1;
101	char			*bar2;
102	pci_irq_h		irqh;
103	pci_cfg_h		cfgh;
104	pci_dev_h		pdev;
105} xge_hal_device_attr_t;
106
107/**
108 * enum xge_hal_device_link_state_e - Link state enumeration.
109 * @XGE_HAL_LINK_NONE: Invalid link state.
110 * @XGE_HAL_LINK_DOWN: Link is down.
111 * @XGE_HAL_LINK_UP: Link is up.
112 *
113 */
114typedef enum xge_hal_device_link_state_e {
115	XGE_HAL_LINK_NONE,
116	XGE_HAL_LINK_DOWN,
117	XGE_HAL_LINK_UP
118} xge_hal_device_link_state_e;
119
120
121/**
122 * enum xge_hal_pci_mode_e - PIC bus speed and mode specific enumeration.
123 * @XGE_HAL_PCI_33MHZ_MODE:		33 MHZ pci mode.
124 * @XGE_HAL_PCI_66MHZ_MODE:		66 MHZ pci mode.
125 * @XGE_HAL_PCIX_M1_66MHZ_MODE:		PCIX M1 66MHZ mode.
126 * @XGE_HAL_PCIX_M1_100MHZ_MODE:	PCIX M1 100MHZ mode.
127 * @XGE_HAL_PCIX_M1_133MHZ_MODE:	PCIX M1 133MHZ mode.
128 * @XGE_HAL_PCIX_M2_66MHZ_MODE:		PCIX M2 66MHZ mode.
129 * @XGE_HAL_PCIX_M2_100MHZ_MODE:	PCIX M2 100MHZ mode.
130 * @XGE_HAL_PCIX_M2_133MHZ_MODE:	PCIX M3 133MHZ mode.
131 * @XGE_HAL_PCIX_M1_RESERVED:		PCIX M1 reserved mode.
132 * @XGE_HAL_PCIX_M1_66MHZ_NS:		PCIX M1 66MHZ mode not supported.
133 * @XGE_HAL_PCIX_M1_100MHZ_NS:		PCIX M1 100MHZ mode not supported.
134 * @XGE_HAL_PCIX_M1_133MHZ_NS:		PCIX M1 133MHZ not supported.
135 * @XGE_HAL_PCIX_M2_RESERVED:		PCIX M2 reserved.
136 * @XGE_HAL_PCIX_533_RESERVED:		PCIX 533 reserved.
137 * @XGE_HAL_PCI_BASIC_MODE:		PCI basic mode, XENA specific value.
138 * @XGE_HAL_PCIX_BASIC_MODE:		PCIX basic mode, XENA specific value.
139 * @XGE_HAL_PCI_INVALID_MODE:		Invalid PCI or PCIX mode.
140 *
141 */
142typedef enum xge_hal_pci_mode_e {
143	XGE_HAL_PCI_33MHZ_MODE		= 0x0,
144	XGE_HAL_PCI_66MHZ_MODE		= 0x1,
145	XGE_HAL_PCIX_M1_66MHZ_MODE	= 0x2,
146	XGE_HAL_PCIX_M1_100MHZ_MODE	= 0x3,
147	XGE_HAL_PCIX_M1_133MHZ_MODE	= 0x4,
148	XGE_HAL_PCIX_M2_66MHZ_MODE	= 0x5,
149	XGE_HAL_PCIX_M2_100MHZ_MODE	= 0x6,
150	XGE_HAL_PCIX_M2_133MHZ_MODE	= 0x7,
151	XGE_HAL_PCIX_M1_RESERVED	= 0x8,
152	XGE_HAL_PCIX_M1_66MHZ_NS	= 0xA,
153	XGE_HAL_PCIX_M1_100MHZ_NS	= 0xB,
154	XGE_HAL_PCIX_M1_133MHZ_NS	= 0xC,
155	XGE_HAL_PCIX_M2_RESERVED	= 0xD,
156	XGE_HAL_PCIX_533_RESERVED	= 0xE,
157	XGE_HAL_PCI_BASIC_MODE		= 0x10,
158	XGE_HAL_PCIX_BASIC_MODE		= 0x11,
159	XGE_HAL_PCI_INVALID_MODE	= 0x12,
160} xge_hal_pci_mode_e;
161
162/**
163 * enum xge_hal_pci_bus_frequency_e - PCI bus frequency enumeration.
164 * @XGE_HAL_PCI_BUS_FREQUENCY_33MHZ:	PCI bus frequency 33MHZ
165 * @XGE_HAL_PCI_BUS_FREQUENCY_66MHZ:	PCI bus frequency 66MHZ
166 * @XGE_HAL_PCI_BUS_FREQUENCY_100MHZ:	PCI bus frequency 100MHZ
167 * @XGE_HAL_PCI_BUS_FREQUENCY_133MHZ:	PCI bus frequency 133MHZ
168 * @XGE_HAL_PCI_BUS_FREQUENCY_200MHZ:	PCI bus frequency 200MHZ
169 * @XGE_HAL_PCI_BUS_FREQUENCY_250MHZ:	PCI bus frequency 250MHZ
170 * @XGE_HAL_PCI_BUS_FREQUENCY_266MHZ:	PCI bus frequency 266MHZ
171 * @XGE_HAL_PCI_BUS_FREQUENCY_UNKNOWN:	Unrecognized PCI bus frequency value.
172 *
173 */
174typedef enum xge_hal_pci_bus_frequency_e {
175	XGE_HAL_PCI_BUS_FREQUENCY_33MHZ		= 33,
176	XGE_HAL_PCI_BUS_FREQUENCY_66MHZ		= 66,
177	XGE_HAL_PCI_BUS_FREQUENCY_100MHZ	= 100,
178	XGE_HAL_PCI_BUS_FREQUENCY_133MHZ	= 133,
179	XGE_HAL_PCI_BUS_FREQUENCY_200MHZ	= 200,
180	XGE_HAL_PCI_BUS_FREQUENCY_250MHZ	= 250,
181	XGE_HAL_PCI_BUS_FREQUENCY_266MHZ	= 266,
182	XGE_HAL_PCI_BUS_FREQUENCY_UNKNOWN	= 0
183} xge_hal_pci_bus_frequency_e;
184
185/**
186 * enum xge_hal_pci_bus_width_e - PCI bus width enumeration.
187 * @XGE_HAL_PCI_BUS_WIDTH_64BIT:	64 bit bus width.
188 * @XGE_HAL_PCI_BUS_WIDTH_32BIT:	32 bit bus width.
189 * @XGE_HAL_PCI_BUS_WIDTH_UNKNOWN:  unknown bus width.
190 *
191 */
192typedef enum xge_hal_pci_bus_width_e {
193	XGE_HAL_PCI_BUS_WIDTH_64BIT	= 0,
194	XGE_HAL_PCI_BUS_WIDTH_32BIT	= 1,
195	XGE_HAL_PCI_BUS_WIDTH_UNKNOWN	= 2,
196} xge_hal_pci_bus_width_e;
197
198#if defined (XGE_HAL_CONFIG_LRO)
199
200#define IP_TOTAL_LENGTH_OFFSET			2
201#define IP_FAST_PATH_HDR_MASK			0x45
202#define TCP_FAST_PATH_HDR_MASK1			0x50
203#define TCP_FAST_PATH_HDR_MASK2			0x10
204#define TCP_FAST_PATH_HDR_MASK3			0x18
205#define IP_SOURCE_ADDRESS_OFFSET		12
206#define IP_DESTINATION_ADDRESS_OFFSET		16
207#define TCP_DESTINATION_PORT_OFFSET		2
208#define TCP_SOURCE_PORT_OFFSET			0
209#define TCP_DATA_OFFSET_OFFSET			12
210#define TCP_WINDOW_OFFSET			14
211#define TCP_SEQUENCE_NUMBER_OFFSET		4
212#define TCP_ACKNOWLEDGEMENT_NUMBER_OFFSET	8
213
214typedef struct tcplro {
215	u16   source;
216	u16   dest;
217	u32   seq;
218	u32   ack_seq;
219	u8    doff_res;
220	u8    ctrl;
221	u16   window;
222	u16   check;
223	u16   urg_ptr;
224} tcplro_t;
225
226typedef struct iplro {
227	u8    version_ihl;
228	u8    tos;
229	u16   tot_len;
230	u16   id;
231	u16   frag_off;
232	u8    ttl;
233	u8    protocol;
234	u16   check;
235	u32   saddr;
236	u32   daddr;
237	/*The options start here. */
238} iplro_t;
239
240/*
241 * LRO object, one per each LRO session.
242*/
243typedef struct lro {
244	/* non-linear: contains scatter-gather list of
245	xframe-mapped received buffers */
246	OS_NETSTACK_BUF		os_buf;
247	OS_NETSTACK_BUF		os_buf_end;
248
249	/* link layer header of the first frame;
250	remains intack throughout the processing */
251	u8			*ll_hdr;
252
253	/* IP header - gets _collapsed_ */
254	iplro_t			*ip_hdr;
255
256	/* transport header - gets _collapsed_ */
257	tcplro_t		*tcp_hdr;
258
259	/* Next tcp sequence number */
260	u32			tcp_next_seq_num;
261	/* Current tcp seq & ack */
262	u32			tcp_seq_num;
263	u32			tcp_ack_num;
264
265	/* total number of accumulated (so far) frames */
266	int			sg_num;
267
268	/* total data length */
269	int			total_length;
270
271	/* receive side hash value, available from Hercules */
272	u32			rth_value;
273
274	/* In use */
275	u8			in_use;
276
277	/* Total length of the fragments clubbed with the inital frame */
278	u32			frags_len;
279
280	/* LRO frame contains time stamp, if (ts_off != -1) */
281	int 			ts_off;
282
283} lro_t;
284#endif
285
286/*
287 * xge_hal_spdm_entry_t
288 *
289 * Represents a single spdm entry in the SPDM table.
290 */
291typedef struct xge_hal_spdm_entry_t {
292	xge_hal_ipaddr_t  src_ip;
293	xge_hal_ipaddr_t  dst_ip;
294	u32 jhash_value;
295	u16 l4_sp;
296	u16 l4_dp;
297	u16 spdm_entry;
298	u8  in_use;
299	u8  is_tcp;
300	u8  is_ipv4;
301	u8  tgt_queue;
302} xge_hal_spdm_entry_t;
303
304#if defined(XGE_HAL_CONFIG_LRO)
305typedef struct {
306	lro_t			lro_pool[XGE_HAL_LRO_MAX_BUCKETS];
307	int			lro_next_idx;
308	lro_t			*lro_recent;
309} xge_hal_lro_desc_t;
310#endif
311/*
312 * xge_hal_vpd_data_t
313 *
314 * Represents vpd capabilty structure
315 */
316typedef struct xge_hal_vpd_data_t {
317        u8      product_name[XGE_HAL_VPD_LENGTH];
318        u8      serial_num[XGE_HAL_VPD_LENGTH];
319} xge_hal_vpd_data_t;
320
321/*
322 * xge_hal_device_t
323 *
324 * HAL device object. Represents Xframe.
325 */
326typedef struct {
327	unsigned int		magic;
328	pci_reg_h		regh0;
329	pci_reg_h		regh1;
330	pci_reg_h		regh2;
331	char			*bar0;
332	char			*isrbar0;
333	char			*bar1;
334	char			*bar2;
335	pci_irq_h		irqh;
336	pci_cfg_h		cfgh;
337	pci_dev_h		pdev;
338	xge_hal_pci_config_t	pci_config_space;
339	xge_hal_pci_config_t	pci_config_space_bios;
340	xge_hal_device_config_t	config;
341	xge_list_t		free_channels;
342	xge_list_t		fifo_channels;
343	xge_list_t		ring_channels;
344	volatile int		is_initialized;
345	volatile int		terminating;
346	xge_hal_stats_t		stats;
347	macaddr_t		macaddr[1];
348	xge_queue_h		queueh;
349	volatile int		mcast_refcnt;
350	int			is_promisc;
351	volatile xge_hal_device_link_state_e	link_state;
352	void			*upper_layer_info;
353	xge_hal_device_attr_t	orig_attr;
354	u16			device_id;
355	u8			revision;
356	int			msi_enabled;
357	int			hw_is_initialized;
358	u64			inject_serr;
359	u64			inject_ecc;
360	u8			inject_bad_tcode;
361	int			inject_bad_tcode_for_chan_type;
362        int                     reset_needed_after_close;
363	int			tti_enabled;
364	xge_hal_tti_config_t	bimodal_tti[XGE_HAL_MAX_RING_NUM];
365	int			bimodal_timer_val_us;
366	int			bimodal_urange_a_en;
367	int			bimodal_intr_cnt;
368	char			*spdm_mem_base;
369	u16			spdm_max_entries;
370	xge_hal_spdm_entry_t	**spdm_table;
371	spinlock_t		spdm_lock;
372#if defined(XGE_HAL_CONFIG_LRO)
373        xge_hal_lro_desc_t      lro_desc[XGE_HAL_MAX_RING_NUM];
374#endif
375	spinlock_t		xena_post_lock;
376
377	/* bimodal workload stats */
378	int			irq_workload_rxd[XGE_HAL_MAX_RING_NUM];
379	int			irq_workload_rxcnt[XGE_HAL_MAX_RING_NUM];
380	int			irq_workload_rxlen[XGE_HAL_MAX_RING_NUM];
381	int			irq_workload_txd[XGE_HAL_MAX_FIFO_NUM];
382	int			irq_workload_txcnt[XGE_HAL_MAX_FIFO_NUM];
383	int			irq_workload_txlen[XGE_HAL_MAX_FIFO_NUM];
384
385	int			mtu_first_time_set;
386	u64			rxufca_lbolt;
387	u64			rxufca_lbolt_time;
388	u64			rxufca_intr_thres;
389	char*                   dump_buf;
390	xge_hal_pci_mode_e	pci_mode;
391	xge_hal_pci_bus_frequency_e bus_frequency;
392	xge_hal_pci_bus_width_e	bus_width;
393	xge_hal_vpd_data_t      vpd_data;
394	volatile int		in_poll;
395	u64			msix_vector_table[XGE_HAL_MAX_MSIX_MESSAGES_WITH_ADDR];
396} xge_hal_device_t;
397
398
399/* ========================== PRIVATE API ================================= */
400
401void
402__hal_device_event_queued(void *data, int event_type);
403
404xge_hal_status_e
405__hal_device_set_swapper(xge_hal_device_t *hldev);
406
407xge_hal_status_e
408__hal_device_rth_it_configure(xge_hal_device_t *hldev);
409
410xge_hal_status_e
411__hal_device_rth_spdm_configure(xge_hal_device_t *hldev);
412
413xge_hal_status_e
414__hal_verify_pcc_idle(xge_hal_device_t *hldev, u64 adp_status);
415
416xge_hal_status_e
417__hal_device_handle_pic(xge_hal_device_t *hldev, u64 reason);
418
419xge_hal_status_e
420__hal_read_spdm_entry_line(xge_hal_device_t *hldev, u8 spdm_line,
421                        u16 spdm_entry, u64 *spdm_line_val);
422
423void __hal_pio_mem_write32_upper(pci_dev_h pdev, pci_reg_h regh, u32 val,
424			void *addr);
425
426void __hal_pio_mem_write32_lower(pci_dev_h pdev, pci_reg_h regh, u32 val,
427			void *addr);
428void __hal_device_get_vpd_data(xge_hal_device_t *hldev);
429
430xge_hal_status_e
431__hal_device_handle_txpic(xge_hal_device_t *hldev, u64 reason);
432
433xge_hal_status_e
434__hal_device_handle_txdma(xge_hal_device_t *hldev, u64 reason);
435
436xge_hal_status_e
437__hal_device_handle_txmac(xge_hal_device_t *hldev, u64 reason);
438
439xge_hal_status_e
440__hal_device_handle_txxgxs(xge_hal_device_t *hldev, u64 reason);
441
442xge_hal_status_e
443__hal_device_handle_rxpic(xge_hal_device_t *hldev, u64 reason);
444
445xge_hal_status_e
446__hal_device_handle_rxdma(xge_hal_device_t *hldev, u64 reason);
447
448xge_hal_status_e
449__hal_device_handle_rxmac(xge_hal_device_t *hldev, u64 reason);
450
451xge_hal_status_e
452__hal_device_handle_rxxgxs(xge_hal_device_t *hldev, u64 reason);
453
454xge_hal_status_e
455__hal_device_handle_mc(xge_hal_device_t *hldev, u64 reason);
456
457xge_hal_status_e
458__hal_device_register_poll(xge_hal_device_t *hldev, u64 *reg, int op, u64 mask,
459			int max_millis);
460xge_hal_status_e
461__hal_device_rts_mac_configure(xge_hal_device_t *hldev);
462
463xge_hal_status_e
464__hal_device_rts_qos_configure(xge_hal_device_t *hldev);
465
466xge_hal_status_e
467__hal_device_rts_port_configure(xge_hal_device_t *hldev);
468
469xge_hal_status_e
470__hal_device_rti_configure(xge_hal_device_t *hldev, int runtime);
471
472void
473__hal_device_msi_intr_endis(xge_hal_device_t *hldev, int flag);
474
475void
476__hal_device_msix_intr_endis(xge_hal_device_t *hldev,
477			      xge_hal_channel_t *channel, int flag);
478
479/* =========================== PUBLIC API ================================= */
480
481unsigned int
482__hal_fix_time_ival_herc(xge_hal_device_t *hldev,
483			 unsigned int time_ival);
484xge_hal_status_e
485xge_hal_rts_rth_itable_set(xge_hal_device_t *hldev, u8 *itable,
486		u32 itable_size);
487
488void
489xge_hal_rts_rth_set(xge_hal_device_t *hldev, u8 def_q, u64 hash_type,
490		u16 bucket_size);
491
492void
493xge_hal_rts_rth_init(xge_hal_device_t *hldev);
494
495void
496xge_hal_rts_rth_clr(xge_hal_device_t *hldev);
497
498void
499xge_hal_rts_rth_start(xge_hal_device_t *hldev);
500
501void
502xge_hal_rts_rth_stop(xge_hal_device_t *hldev);
503
504void
505xge_hal_device_rts_rth_key_set(xge_hal_device_t *hldev, u8 KeySize, u8 *Key);
506
507xge_hal_status_e
508xge_hal_device_rts_mac_enable(xge_hal_device_h devh, int index, macaddr_t macaddr);
509
510xge_hal_status_e
511xge_hal_device_rts_mac_disable(xge_hal_device_h devh, int index);
512
513int xge_hal_reinitialize_hw(xge_hal_device_t * hldev);
514
515xge_hal_status_e xge_hal_fix_rldram_ecc_error(xge_hal_device_t * hldev);
516/**
517 * xge_hal_device_rti_reconfigure
518 * @hldev: Hal Device
519 */
520static inline xge_hal_status_e
521xge_hal_device_rti_reconfigure(xge_hal_device_t *hldev)
522{
523	return __hal_device_rti_configure(hldev, 1);
524}
525
526/**
527 * xge_hal_device_rts_port_reconfigure
528 * @hldev: Hal Device
529 */
530static inline xge_hal_status_e
531xge_hal_device_rts_port_reconfigure(xge_hal_device_t *hldev)
532{
533	return __hal_device_rts_port_configure(hldev);
534}
535
536/**
537 * xge_hal_device_is_initialized - Returns 0 if device is not
538 * initialized, non-zero otherwise.
539 * @devh: HAL device handle.
540 *
541 * Returns 0 if device is not initialized, non-zero otherwise.
542 */
543static inline int
544xge_hal_device_is_initialized(xge_hal_device_h devh)
545{
546	return ((xge_hal_device_t*)devh)->is_initialized;
547}
548
549
550/**
551 * xge_hal_device_in_poll - non-zero, if xge_hal_device_poll() is executing.
552 * @devh: HAL device handle.
553 *
554 * Returns non-zero if xge_hal_device_poll() is executing, and 0 - otherwise.
555 */
556static inline int
557xge_hal_device_in_poll(xge_hal_device_h devh)
558{
559	return ((xge_hal_device_t*)devh)->in_poll;
560}
561
562
563/**
564 * xge_hal_device_inject_ecc - Inject ECC error.
565 * @devh: HAL device, pointer to xge_hal_device_t structure.
566 * @err_reg: Contains the error register.
567 *
568 * This function is used to inject ECC error into the driver flow.
569 * This facility can be used to test the driver flow in the
570 * case of ECC error is reported by the firmware.
571 *
572 * Returns: void
573 * See also: xge_hal_device_inject_serr(),
574 * xge_hal_device_inject_bad_tcode()
575 */
576static inline void
577xge_hal_device_inject_ecc(xge_hal_device_h devh, u64 err_reg)
578{
579        ((xge_hal_device_t*)devh)->inject_ecc = err_reg;
580}
581
582
583/**
584 * xge_hal_device_inject_serr - Inject SERR error.
585 * @devh: HAL device, pointer to xge_hal_device_t structure.
586 * @err_reg: Contains the error register.
587 *
588 * This function is used to inject SERR error into the driver flow.
589 * This facility can be used to test the driver flow in the
590 * case of SERR error is reported by firmware.
591 *
592 * Returns: void
593 * See also: xge_hal_device_inject_ecc(),
594 * xge_hal_device_inject_bad_tcode()
595 */
596static inline void
597xge_hal_device_inject_serr(xge_hal_device_h devh, u64 err_reg)
598{
599        ((xge_hal_device_t*)devh)->inject_serr = err_reg;
600}
601
602
603/**
604 * xge_hal_device_inject_bad_tcode - Inject  Bad transfer code.
605 * @devh: HAL device, pointer to xge_hal_device_t structure.
606 * @chan_type: Channel type (fifo/ring).
607 * @t_code: Transfer code.
608 *
609 * This function is used to inject bad (Tx/Rx Data)transfer code
610 * into the driver flow.
611 *
612 * This facility can be used to test the driver flow in the
613 * case of bad transfer code reported by firmware for a Tx/Rx data
614 * transfer.
615 *
616 * Returns: void
617 * See also: xge_hal_device_inject_ecc(), xge_hal_device_inject_serr()
618 */
619static inline void
620xge_hal_device_inject_bad_tcode(xge_hal_device_h devh, int chan_type, u8 t_code)
621{
622        ((xge_hal_device_t*)devh)->inject_bad_tcode_for_chan_type = chan_type;
623        ((xge_hal_device_t*)devh)->inject_bad_tcode = t_code;
624}
625
626void xge_hal_device_msi_enable(xge_hal_device_h	devh);
627
628/*
629 * xge_hal_device_msi_mode - Is MSI enabled?
630 * @devh: HAL device handle.
631 *
632 * Returns 0 if MSI is enabled for the specified device,
633 * non-zero otherwise.
634 */
635static inline int
636xge_hal_device_msi_mode(xge_hal_device_h devh)
637{
638	return ((xge_hal_device_t*)devh)->msi_enabled;
639}
640
641/**
642 * xge_hal_device_queue - Get per-device event queue.
643 * @devh: HAL device handle.
644 *
645 * Returns: event queue associated with the specified HAL device.
646 */
647static inline xge_queue_h
648xge_hal_device_queue (xge_hal_device_h devh)
649{
650	return ((xge_hal_device_t*)devh)->queueh;
651}
652
653/**
654 * xge_hal_device_attr - Get original (user-specified) device
655 * attributes.
656 * @devh: HAL device handle.
657 *
658 * Returns: original (user-specified) device attributes.
659 */
660static inline xge_hal_device_attr_t*
661xge_hal_device_attr(xge_hal_device_h devh)
662{
663	return &((xge_hal_device_t*)devh)->orig_attr;
664}
665
666/**
667 * xge_hal_device_private_set - Set ULD context.
668 * @devh: HAL device handle.
669 * @data: pointer to ULD context
670 *
671 * Use HAL device to set upper-layer driver (ULD) context.
672 *
673 * See also: xge_hal_device_from_private(), xge_hal_device_private()
674 */
675static inline void
676xge_hal_device_private_set(xge_hal_device_h devh, void *data)
677{
678	((xge_hal_device_t*)devh)->upper_layer_info = data;
679}
680
681/**
682 * xge_hal_device_private - Get ULD context.
683 * @devh: HAL device handle.
684 *
685 * Use HAL device to get upper-layer driver (ULD) context.
686 *
687 * Returns:  ULD context.
688 *
689 * See also: xge_hal_device_from_private(), xge_hal_device_private_set()
690 */
691static inline void*
692xge_hal_device_private(xge_hal_device_h devh)
693{
694	return ((xge_hal_device_t*)devh)->upper_layer_info;
695}
696
697/**
698 * xge_hal_device_from_private - Get HAL device object from private.
699 * @info_ptr: ULD context.
700 *
701 * Use ULD context to get HAL device.
702 *
703 * Returns:  Device handle.
704 *
705 * See also: xge_hal_device_private(), xge_hal_device_private_set()
706 */
707static inline xge_hal_device_h
708xge_hal_device_from_private(void *info_ptr)
709{
710	return xge_container_of((void ** ) info_ptr, xge_hal_device_t,
711	upper_layer_info);
712}
713
714/**
715 * xge_hal_device_mtu_check - check MTU value for ranges
716 * @hldev: the device
717 * @new_mtu: new MTU value to check
718 *
719 * Will do sanity check for new MTU value.
720 *
721 * Returns: XGE_HAL_OK - success.
722 * XGE_HAL_ERR_INVALID_MTU_SIZE - MTU is invalid.
723 *
724 * See also: xge_hal_device_mtu_set()
725 */
726static inline xge_hal_status_e
727xge_hal_device_mtu_check(xge_hal_device_t *hldev, int new_mtu)
728{
729	if ((new_mtu < XGE_HAL_MIN_MTU) || (new_mtu > XGE_HAL_MAX_MTU)) {
730		return XGE_HAL_ERR_INVALID_MTU_SIZE;
731	}
732
733	return XGE_HAL_OK;
734}
735
736void xge_hal_device_bcast_enable(xge_hal_device_h devh);
737
738void xge_hal_device_bcast_disable(xge_hal_device_h devh);
739
740void xge_hal_device_terminating(xge_hal_device_h devh);
741
742xge_hal_status_e xge_hal_device_initialize(xge_hal_device_t *hldev,
743		xge_hal_device_attr_t *attr, xge_hal_device_config_t *config);
744
745void xge_hal_device_terminate(xge_hal_device_t *hldev);
746
747xge_hal_status_e xge_hal_device_reset(xge_hal_device_t *hldev);
748
749xge_hal_status_e xge_hal_device_macaddr_get(xge_hal_device_t *hldev,
750		int index,  macaddr_t *macaddr);
751
752xge_hal_status_e xge_hal_device_macaddr_set(xge_hal_device_t *hldev,
753		int index,  macaddr_t macaddr);
754
755xge_hal_status_e xge_hal_device_macaddr_clear(xge_hal_device_t *hldev,
756		int index);
757
758int xge_hal_device_macaddr_find(xge_hal_device_t *hldev, macaddr_t wanted);
759
760xge_hal_status_e xge_hal_device_mtu_set(xge_hal_device_t *hldev, int new_mtu);
761
762xge_hal_status_e xge_hal_device_status(xge_hal_device_t *hldev, u64 *hw_status);
763
764void xge_hal_device_intr_enable(xge_hal_device_t *hldev);
765
766void xge_hal_device_intr_disable(xge_hal_device_t *hldev);
767
768xge_hal_status_e xge_hal_device_mcast_enable(xge_hal_device_t *hldev);
769
770xge_hal_status_e xge_hal_device_mcast_disable(xge_hal_device_t *hldev);
771
772void xge_hal_device_promisc_enable(xge_hal_device_t *hldev);
773
774void xge_hal_device_promisc_disable(xge_hal_device_t *hldev);
775
776xge_hal_status_e xge_hal_device_disable(xge_hal_device_t *hldev);
777
778xge_hal_status_e xge_hal_device_enable(xge_hal_device_t *hldev);
779
780xge_hal_status_e xge_hal_device_handle_tcode(xge_hal_channel_h channelh,
781					     xge_hal_dtr_h dtrh,
782					     u8 t_code);
783
784xge_hal_status_e xge_hal_device_link_state(xge_hal_device_h devh,
785			xge_hal_device_link_state_e *ls);
786
787void xge_hal_device_sched_timer(xge_hal_device_h devh, int interval_us,
788			int one_shot);
789
790void xge_hal_device_poll(xge_hal_device_h devh);
791
792xge_hal_card_e xge_hal_device_check_id(xge_hal_device_h devh);
793
794int xge_hal_device_is_slot_freeze(xge_hal_device_h devh);
795
796void xge_hal_device_quiesce(xge_hal_device_t *hldev, xge_hal_device_h devh);
797
798xge_hal_status_e
799xge_hal_device_pci_info_get(xge_hal_device_h devh, xge_hal_pci_mode_e *pci_mode,
800			xge_hal_pci_bus_frequency_e *bus_frequency,
801			xge_hal_pci_bus_width_e *bus_width);
802
803xge_hal_status_e
804xge_hal_spdm_entry_add(xge_hal_device_h devh, xge_hal_ipaddr_t *src_ip,
805			xge_hal_ipaddr_t *dst_ip, u16 l4_sp, u16 l4_dp,
806			u8 is_tcp, u8 is_ipv4, u8 tgt_queue);
807
808xge_hal_status_e
809xge_hal_spdm_entry_remove(xge_hal_device_h devh, xge_hal_ipaddr_t *src_ip,
810			xge_hal_ipaddr_t *dst_ip, u16 l4_sp, u16 l4_dp,
811			u8 is_tcp, u8 is_ipv4);
812
813xge_hal_status_e
814xge_hal_device_rts_section_enable(xge_hal_device_h devh, int index);
815
816int
817xge_hal_device_is_closed (xge_hal_device_h devh);
818
819/* private functions, don't use them in ULD */
820
821void __hal_serial_mem_write64(xge_hal_device_t *hldev, u64 value, u64 *reg);
822
823u64 __hal_serial_mem_read64(xge_hal_device_t *hldev, u64 *reg);
824
825
826/* Some function protoypes for MSI implementation. */
827xge_hal_status_e
828xge_hal_channel_msi_set (xge_hal_channel_h channelh, int msi,
829			 u32 msg_val);
830void
831xge_hal_mask_msi(xge_hal_device_t *hldev);
832
833void
834xge_hal_unmask_msi(xge_hal_channel_h channelh);
835
836xge_hal_status_e
837xge_hal_channel_msix_set(xge_hal_channel_h channelh, int msix_idx);
838
839xge_hal_status_e
840xge_hal_mask_msix(xge_hal_device_h devh, int msi_id);
841
842xge_hal_status_e
843xge_hal_unmask_msix(xge_hal_device_h devh, int msi_id);
844
845#if defined(XGE_HAL_CONFIG_LRO)
846xge_hal_status_e
847xge_hal_lro_init(u32 lro_scale, xge_hal_device_t *hldev);
848
849void
850xge_hal_lro_terminate(u32 lro_scale, xge_hal_device_t *hldev);
851#endif
852
853#if defined(XGE_DEBUG_FP) && (XGE_DEBUG_FP & XGE_DEBUG_FP_DEVICE)
854#define __HAL_STATIC_DEVICE
855#define __HAL_INLINE_DEVICE
856
857__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE int
858xge_hal_device_rev(xge_hal_device_t *hldev);
859
860__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE xge_hal_status_e
861xge_hal_device_begin_irq(xge_hal_device_t *hldev, u64 *reason);
862
863__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void
864xge_hal_device_clear_rx(xge_hal_device_t *hldev);
865
866__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void
867xge_hal_device_clear_tx(xge_hal_device_t *hldev);
868
869__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE xge_hal_status_e
870xge_hal_device_continue_irq(xge_hal_device_t *hldev);
871
872__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE xge_hal_status_e
873xge_hal_device_handle_irq(xge_hal_device_t *hldev);
874
875__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE char *
876xge_hal_device_bar0(xge_hal_device_t *hldev);
877
878__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE char *
879xge_hal_device_isrbar0(xge_hal_device_t *hldev);
880
881__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE char *
882xge_hal_device_bar1(xge_hal_device_t *hldev);
883
884__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void
885xge_hal_device_bar0_set(xge_hal_device_t *hldev, char *bar0);
886
887__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void
888xge_hal_device_isrbar0_set(xge_hal_device_t *hldev, char *isrbar0);
889
890__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void
891xge_hal_device_bar1_set(xge_hal_device_t *hldev, xge_hal_channel_h channelh,
892		char *bar1);
893
894__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void
895xge_hal_device_mask_tx(xge_hal_device_t *hldev);
896
897__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void
898xge_hal_device_mask_rx(xge_hal_device_t *hldev);
899
900__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void
901xge_hal_device_mask_all(xge_hal_device_t *hldev);
902
903__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void
904xge_hal_device_unmask_tx(xge_hal_device_t *hldev);
905
906__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void
907xge_hal_device_unmask_rx(xge_hal_device_t *hldev);
908
909__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void
910xge_hal_device_unmask_all(xge_hal_device_t *hldev);
911
912__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE xge_hal_status_e
913xge_hal_device_poll_tx_channels(xge_hal_device_t *hldev, int *got_tx);
914
915__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE xge_hal_status_e
916xge_hal_device_poll_rx_channels(xge_hal_device_t *hldev, int *got_rx);
917
918__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE xge_hal_status_e
919xge_hal_device_poll_rx_channel(xge_hal_channel_t *channel, int *got_rx);
920
921__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE xge_hal_status_e
922xge_hal_device_poll_tx_channel(xge_hal_channel_t *channel, int *got_tx);
923
924#if defined (XGE_HAL_CONFIG_LRO)
925__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL u8
926__hal_header_parse_token_u8(u8 *string,u16 offset);
927
928__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL u16
929__hal_header_parse_token_u16(u8 *string,u16 offset);
930
931__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL u32
932__hal_header_parse_token_u32(u8 *string,u16 offset);
933
934__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL void
935__hal_header_update_u8(u8 *string, u16 offset, u8 val);
936
937__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL void
938__hal_header_update_u16(u8 *string, u16 offset, u16 val);
939
940__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL void
941__hal_header_update_u32(u8 *string, u16 offset, u32 val);
942
943__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL u16
944__hal_tcp_seg_len(iplro_t *ip, tcplro_t *tcp);
945
946__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e
947__hal_ip_lro_capable(iplro_t *ip, xge_hal_dtr_info_t *ext_info);
948
949__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e
950__hal_tcp_lro_capable(iplro_t *ip, tcplro_t *tcp, lro_t *lro, int *ts_off);
951
952__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e
953__hal_lro_capable(u8 *buffer, iplro_t **ip, tcplro_t **tcp,
954		xge_hal_dtr_info_t *ext_info);
955
956__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e
957__hal_get_lro_session(u8 *eth_hdr, iplro_t *ip, tcplro_t *tcp, lro_t **lro,
958		xge_hal_dtr_info_t *ext_info, xge_hal_device_t *hldev,
959		xge_hal_lro_desc_t *ring_lro, lro_t **lro_end3);
960
961__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e
962__hal_lro_under_optimal_thresh(iplro_t *ip, tcplro_t *tcp, lro_t *lro,
963		xge_hal_device_t *hldev);
964
965__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e
966__hal_collapse_ip_hdr(iplro_t *ip, tcplro_t *tcp, lro_t *lro,
967		xge_hal_device_t *hldev);
968
969__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e
970__hal_collapse_tcp_hdr(iplro_t *ip, tcplro_t *tcp, lro_t *lro,
971		xge_hal_device_t *hldev);
972
973__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e
974__hal_append_lro(iplro_t *ip, tcplro_t **tcp, u32 *seg_len, lro_t *lro,
975		xge_hal_device_t *hldev);
976
977__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e
978xge_hal_lro_process_rx(int ring, u8 *eth_hdr, u8 *ip_hdr, tcplro_t **tcp,
979                       u32 *seglen, lro_t **p_lro,
980                       xge_hal_dtr_info_t *ext_info, xge_hal_device_t *hldev,
981                       lro_t **lro_end3);
982
983__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e
984xge_hal_accumulate_large_rx(u8 *buffer, tcplro_t **tcp, u32 *seglen,
985		lro_t **lro, xge_hal_dtr_info_t *ext_info,
986		xge_hal_device_t *hldev, lro_t **lro_end3);
987
988__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL lro_t	*
989xge_hal_lro_next_session (xge_hal_device_t *hldev, int ring);
990
991__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL lro_t *
992xge_hal_lro_get_next_session(xge_hal_device_t *hldev);
993
994__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL void
995__hal_open_lro_session (u8 *buffer, iplro_t *ip, tcplro_t *tcp, lro_t **lro,
996                        xge_hal_device_t *hldev, xge_hal_lro_desc_t *ring_lro,
997                        int slot, u32 tcp_seg_len, int ts_off);
998
999__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL int
1000__hal_lro_get_free_slot (xge_hal_lro_desc_t	*ring_lro);
1001#endif
1002
1003#else /* XGE_FASTPATH_EXTERN */
1004#define __HAL_STATIC_DEVICE static
1005#define __HAL_INLINE_DEVICE inline
1006#include "xgehal-device-fp.c"
1007#endif /* XGE_FASTPATH_INLINE */
1008
1009
1010__EXTERN_END_DECLS
1011
1012#endif /* XGE_HAL_DEVICE_H */
1013