1*1e091e43SHans Rosenfeld /* 2*1e091e43SHans Rosenfeld * This file and its contents are supplied under the terms of the 3*1e091e43SHans Rosenfeld * Common Development and Distribution License ("CDDL"), version 1.0. 4*1e091e43SHans Rosenfeld * You may only use this file in accordance with the terms of version 5*1e091e43SHans Rosenfeld * 1.0 of the CDDL. 6*1e091e43SHans Rosenfeld * 7*1e091e43SHans Rosenfeld * A full copy of the text of the CDDL should have accompanied this 8*1e091e43SHans Rosenfeld * source. A copy of the CDDL is also available via the Internet at 9*1e091e43SHans Rosenfeld * http://www.illumos.org/license/CDDL. 10*1e091e43SHans Rosenfeld */ 11*1e091e43SHans Rosenfeld 12*1e091e43SHans Rosenfeld /* 13*1e091e43SHans Rosenfeld * Copyright 2023 Racktop Systems, Inc. 14*1e091e43SHans Rosenfeld */ 15*1e091e43SHans Rosenfeld #ifndef _LMRC_REG_H 16*1e091e43SHans Rosenfeld #define _LMRC_REG_H 17*1e091e43SHans Rosenfeld 18*1e091e43SHans Rosenfeld #include <sys/bitext.h> 19*1e091e43SHans Rosenfeld #include <sys/debug.h> 20*1e091e43SHans Rosenfeld #include <sys/stddef.h> 21*1e091e43SHans Rosenfeld 22*1e091e43SHans Rosenfeld typedef struct lmrc_raid_mfa_io_req_desc lmrc_raid_mfa_io_req_desc_t; 23*1e091e43SHans Rosenfeld typedef union lmrc_atomic_req_desc lmrc_atomic_req_desc_t; 24*1e091e43SHans Rosenfeld typedef union lmrc_req_desc lmrc_req_desc_t; 25*1e091e43SHans Rosenfeld 26*1e091e43SHans Rosenfeld typedef union lmrc_mfi_cap lmrc_mfi_cap_t; 27*1e091e43SHans Rosenfeld typedef union lmrc_mfi_sgl lmrc_mfi_sgl_t; 28*1e091e43SHans Rosenfeld typedef struct lmrc_mfi_header lmrc_mfi_header_t; 29*1e091e43SHans Rosenfeld typedef struct lmrc_mfi_init_payload lmrc_mfi_init_payload_t; 30*1e091e43SHans Rosenfeld typedef struct lmrc_mfi_io_payload lmrc_mfi_io_payload_t; 31*1e091e43SHans Rosenfeld typedef struct lmrc_mfi_pthru_payload lmrc_mfi_pthru_payload_t; 32*1e091e43SHans Rosenfeld typedef struct lmrc_mfi_dcmd_payload lmrc_mfi_dcmd_payload_t; 33*1e091e43SHans Rosenfeld typedef struct lmrc_mfi_abort_payload lmrc_mfi_abort_payload_t; 34*1e091e43SHans Rosenfeld typedef struct lmrc_mfi_frame lmrc_mfi_frame_t; 35*1e091e43SHans Rosenfeld 36*1e091e43SHans Rosenfeld typedef struct lmrc_aen lmrc_aen_t; 37*1e091e43SHans Rosenfeld typedef union lmrc_evt_class_locale lmrc_evt_class_locale_t; 38*1e091e43SHans Rosenfeld typedef struct lmrc_evt_log_info lmrc_evt_log_info_t; 39*1e091e43SHans Rosenfeld typedef struct lmrc_evtarg_ld lmrc_evtarg_ld_t; 40*1e091e43SHans Rosenfeld typedef struct lmrc_evtarg_pd lmrc_evtarg_pd_t; 41*1e091e43SHans Rosenfeld typedef struct lmrc_evt lmrc_evt_t; 42*1e091e43SHans Rosenfeld 43*1e091e43SHans Rosenfeld typedef struct lmrc_ctrl_prop lmrc_ctrl_prop_t; 44*1e091e43SHans Rosenfeld typedef struct lmrc_image_comp lmrc_image_comp_t; 45*1e091e43SHans Rosenfeld typedef struct lmrc_ctrl_info lmrc_ctrl_info_t; 46*1e091e43SHans Rosenfeld 47*1e091e43SHans Rosenfeld #include "lmrc_raid.h" 48*1e091e43SHans Rosenfeld 49*1e091e43SHans Rosenfeld /* PCI device IDs of Gen 3.5 Controllers */ 50*1e091e43SHans Rosenfeld #define LMRC_VENTURA 0x0014 51*1e091e43SHans Rosenfeld #define LMRC_CRUSADER 0x0015 52*1e091e43SHans Rosenfeld #define LMRC_HARPOON 0x0016 53*1e091e43SHans Rosenfeld #define LMRC_TOMCAT 0x0017 54*1e091e43SHans Rosenfeld #define LMRC_VENTURA_4PORT 0x001B 55*1e091e43SHans Rosenfeld #define LMRC_CRUSADER_4PORT 0x001C 56*1e091e43SHans Rosenfeld #define LMRC_AERO_10E0 0x10E0 57*1e091e43SHans Rosenfeld #define LMRC_AERO_10E1 0x10E1 58*1e091e43SHans Rosenfeld #define LMRC_AERO_10E2 0x10E2 59*1e091e43SHans Rosenfeld #define LMRC_AERO_10E3 0x10E3 60*1e091e43SHans Rosenfeld #define LMRC_AERO_10E4 0x10E4 61*1e091e43SHans Rosenfeld #define LMRC_AERO_10E5 0x10E5 62*1e091e43SHans Rosenfeld #define LMRC_AERO_10E6 0x10E6 63*1e091e43SHans Rosenfeld #define LMRC_AERO_10E7 0x10E7 64*1e091e43SHans Rosenfeld 65*1e091e43SHans Rosenfeld /* 66*1e091e43SHans Rosenfeld * Message Frame Defines 67*1e091e43SHans Rosenfeld */ 68*1e091e43SHans Rosenfeld #define LMRC_SENSE_LEN 96 69*1e091e43SHans Rosenfeld 70*1e091e43SHans Rosenfeld #define LMRC_MPI2_RAID_DEFAULT_IO_FRAME_SIZE 256 71*1e091e43SHans Rosenfeld 72*1e091e43SHans Rosenfeld #define LMRC_SPECIFIC_MPI2_FUNCTION(x) \ 73*1e091e43SHans Rosenfeld (MPI2_FUNCTION_MIN_PRODUCT_SPECIFIC + (x)) 74*1e091e43SHans Rosenfeld #define LMRC_MPI2_FUNCTION_PASSTHRU_IO_REQUEST LMRC_SPECIFIC_MPI2_FUNCTION(0) 75*1e091e43SHans Rosenfeld #define LMRC_MPI2_FUNCTION_LD_IO_REQUEST LMRC_SPECIFIC_MPI2_FUNCTION(1) 76*1e091e43SHans Rosenfeld 77*1e091e43SHans Rosenfeld 78*1e091e43SHans Rosenfeld #define LMRC_MAX_MFI_CMDS 16 79*1e091e43SHans Rosenfeld #define LMRC_MAX_IOCTL_CMDS 3 80*1e091e43SHans Rosenfeld 81*1e091e43SHans Rosenfeld /* 82*1e091e43SHans Rosenfeld * Firmware Status Register 83*1e091e43SHans Rosenfeld * For Ventura and Aero controllers, this is outbound scratch pad register 0. 84*1e091e43SHans Rosenfeld */ 85*1e091e43SHans Rosenfeld #define LMRC_FW_RESET_REQUIRED(reg) (bitx32((reg), 0, 0) != 0) 86*1e091e43SHans Rosenfeld #define LMRC_FW_RESET_ADAPTER(reg) (bitx32((reg), 1, 1) != 0) 87*1e091e43SHans Rosenfeld #define LMRC_FW_MAX_CMD(reg) bitx32((reg), 15, 0) 88*1e091e43SHans Rosenfeld #define LMRC_FW_MSIX_ENABLED(reg) (bitx32((reg), 26, 26) != 0) 89*1e091e43SHans Rosenfeld #define LMRC_FW_STATE(reg) bitx32((reg), 31, 28) 90*1e091e43SHans Rosenfeld 91*1e091e43SHans Rosenfeld /* outbound scratch pad register 1 */ 92*1e091e43SHans Rosenfeld #define LMRC_MAX_CHAIN_SIZE(reg) bitx32((reg), 9, 5) 93*1e091e43SHans Rosenfeld #define LMRC_MAX_REPLY_QUEUES_EXT(reg) bitx32((reg), 21, 14) 94*1e091e43SHans Rosenfeld #define LMRC_EXT_CHAIN_SIZE_SUPPORT(reg) (bitx32((reg), 22, 22) != 0) 95*1e091e43SHans Rosenfeld #define LMRC_RDPQ_MODE_SUPPORT(reg) (bitx32((reg), 23, 23) != 0) 96*1e091e43SHans Rosenfeld #define LMRC_SYNC_CACHE_SUPPORT(reg) (bitx32((reg), 24, 24) != 0) 97*1e091e43SHans Rosenfeld #define LMRC_ATOMIC_DESCRIPTOR_SUPPORT(reg) (bitx32((reg), 24, 24) != 0) 98*1e091e43SHans Rosenfeld #define LMRC_64BIT_DMA_SUPPORT(reg) (bitx32((reg), 25, 25) != 0) 99*1e091e43SHans Rosenfeld #define LMRC_INTR_COALESCING_SUPPORT(reg) (bitx32((reg), 26, 26) != 0) 100*1e091e43SHans Rosenfeld 101*1e091e43SHans Rosenfeld #define LMRC_256K_IO 128 102*1e091e43SHans Rosenfeld #define LMRC_1MB_IO (LMRC_256K_IO * 4) 103*1e091e43SHans Rosenfeld 104*1e091e43SHans Rosenfeld /* outbound scratch pad register 2 */ 105*1e091e43SHans Rosenfeld #define LMRC_MAX_RAID_MAP_SZ(reg) bitx32((reg), 24, 16) 106*1e091e43SHans Rosenfeld 107*1e091e43SHans Rosenfeld /* outbound scratch pad register 3 */ 108*1e091e43SHans Rosenfeld #define LMRC_NVME_PAGE_SHIFT(reg) bitx32((reg), 7, 0) 109*1e091e43SHans Rosenfeld #define LMRC_DEFAULT_NVME_PAGE_SHIFT 12 110*1e091e43SHans Rosenfeld 111*1e091e43SHans Rosenfeld /* 112*1e091e43SHans Rosenfeld * Firmware Interface 113*1e091e43SHans Rosenfeld * 114*1e091e43SHans Rosenfeld * MFI stands for MegaRAID SAS FW Interface. This is just a moniker 115*1e091e43SHans Rosenfeld * for the protocol between the software and the firmware. Commands are 116*1e091e43SHans Rosenfeld * issued using "message frames". 117*1e091e43SHans Rosenfeld */ 118*1e091e43SHans Rosenfeld /* 119*1e091e43SHans Rosenfeld * FW posts its state in the upper 4 bits of the status register, extracted 120*1e091e43SHans Rosenfeld * with LMRC_FW_STATE(reg). 121*1e091e43SHans Rosenfeld */ 122*1e091e43SHans Rosenfeld #define LMRC_FW_STATE_UNDEFINED 0x0 123*1e091e43SHans Rosenfeld #define LMRC_FW_STATE_BB_INIT 0x1 124*1e091e43SHans Rosenfeld #define LMRC_FW_STATE_FW_INIT 0x4 125*1e091e43SHans Rosenfeld #define LMRC_FW_STATE_WAIT_HANDSHAKE 0x6 126*1e091e43SHans Rosenfeld #define LMRC_FW_STATE_FW_INIT_2 0x7 127*1e091e43SHans Rosenfeld #define LMRC_FW_STATE_DEVICE_SCAN 0x8 128*1e091e43SHans Rosenfeld #define LMRC_FW_STATE_BOOT_MSG_PENDING 0x9 129*1e091e43SHans Rosenfeld #define LMRC_FW_STATE_FLUSH_CACHE 0xa 130*1e091e43SHans Rosenfeld #define LMRC_FW_STATE_READY 0xb 131*1e091e43SHans Rosenfeld #define LMRC_FW_STATE_OPERATIONAL 0xc 132*1e091e43SHans Rosenfeld #define LMRC_FW_STATE_FAULT 0xf 133*1e091e43SHans Rosenfeld 134*1e091e43SHans Rosenfeld /* 135*1e091e43SHans Rosenfeld * During FW init, clear pending cmds & reset state using the doorbell register 136*1e091e43SHans Rosenfeld * 137*1e091e43SHans Rosenfeld * ABORT: Abort all pending cmds 138*1e091e43SHans Rosenfeld * READY: Move from OPERATIONAL to READY state; discard queue info 139*1e091e43SHans Rosenfeld * MFIMODE: Discard (possible) low MFA posted in 64-bit mode (??) 140*1e091e43SHans Rosenfeld * CLEAR_HANDSHAKE: FW is waiting for HANDSHAKE from BIOS or Driver 141*1e091e43SHans Rosenfeld * HOTPLUG: Resume from Hotplug 142*1e091e43SHans Rosenfeld * MFI_STOP_ADP: Send signal to FW to stop processing 143*1e091e43SHans Rosenfeld */ 144*1e091e43SHans Rosenfeld #define MFI_INIT_ABORT 0x00000001 145*1e091e43SHans Rosenfeld #define MFI_INIT_READY 0x00000002 146*1e091e43SHans Rosenfeld #define MFI_INIT_MFIMODE 0x00000004 147*1e091e43SHans Rosenfeld #define MFI_INIT_CLEAR_HANDSHAKE 0x00000008 148*1e091e43SHans Rosenfeld #define MFI_INIT_HOTPLUG 0x00000010 149*1e091e43SHans Rosenfeld #define MFI_STOP_ADP 0x00000020 150*1e091e43SHans Rosenfeld #define MFI_RESET_FLAGS (MFI_INIT_READY|MFI_INIT_MFIMODE|MFI_INIT_ABORT) 151*1e091e43SHans Rosenfeld 152*1e091e43SHans Rosenfeld /* 153*1e091e43SHans Rosenfeld * MFI frame flags 154*1e091e43SHans Rosenfeld */ 155*1e091e43SHans Rosenfeld #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001 156*1e091e43SHans Rosenfeld #define MFI_FRAME_SGL64 0x0002 157*1e091e43SHans Rosenfeld #define MFI_FRAME_SENSE64 0x0004 158*1e091e43SHans Rosenfeld #define MFI_FRAME_DIR_NONE 0 159*1e091e43SHans Rosenfeld #define MFI_FRAME_DIR_WRITE 0x0008 160*1e091e43SHans Rosenfeld #define MFI_FRAME_DIR_READ 0x0010 161*1e091e43SHans Rosenfeld #define MFI_FRAME_DIR_BOTH 0x0018 162*1e091e43SHans Rosenfeld #define MFI_FRAME_IEEE 0x0020 163*1e091e43SHans Rosenfeld 164*1e091e43SHans Rosenfeld /* 165*1e091e43SHans Rosenfeld * MFI command opcodes 166*1e091e43SHans Rosenfeld */ 167*1e091e43SHans Rosenfeld #define MFI_CMD_INIT 0x00 168*1e091e43SHans Rosenfeld #define MFI_CMD_LD_READ 0x01 169*1e091e43SHans Rosenfeld #define MFI_CMD_LD_WRITE 0x02 170*1e091e43SHans Rosenfeld #define MFI_CMD_LD_SCSI_IO 0x03 171*1e091e43SHans Rosenfeld #define MFI_CMD_PD_SCSI_IO 0x04 172*1e091e43SHans Rosenfeld #define MFI_CMD_DCMD 0x05 173*1e091e43SHans Rosenfeld #define MFI_CMD_ABORT 0x06 174*1e091e43SHans Rosenfeld #define MFI_CMD_SMP 0x07 175*1e091e43SHans Rosenfeld #define MFI_CMD_STP 0x08 176*1e091e43SHans Rosenfeld #define MFI_CMD_INVALID 0xff 177*1e091e43SHans Rosenfeld 178*1e091e43SHans Rosenfeld /* 179*1e091e43SHans Rosenfeld * MFI command status completion codes 180*1e091e43SHans Rosenfeld */ 181*1e091e43SHans Rosenfeld #define MFI_STAT_OK 0x00 182*1e091e43SHans Rosenfeld #define MFI_STAT_INVALID_CMD 0x01 183*1e091e43SHans Rosenfeld #define MFI_STAT_INVALID_DCMD 0x02 184*1e091e43SHans Rosenfeld #define MFI_STAT_INVALID_PARAMETER 0x03 185*1e091e43SHans Rosenfeld #define MFI_STAT_INVALID_SEQUENCE_NUMBER 0x04 186*1e091e43SHans Rosenfeld #define MFI_STAT_ABORT_NOT_POSSIBLE 0x05 187*1e091e43SHans Rosenfeld #define MFI_STAT_APP_HOST_CODE_NOT_FOUND 0x06 188*1e091e43SHans Rosenfeld #define MFI_STAT_APP_IN_USE 0x07 189*1e091e43SHans Rosenfeld #define MFI_STAT_APP_NOT_INITIALIZED 0x08 190*1e091e43SHans Rosenfeld #define MFI_STAT_ARRAY_INDEX_INVALID 0x09 191*1e091e43SHans Rosenfeld #define MFI_STAT_ARRAY_ROW_NOT_EMPTY 0x0a 192*1e091e43SHans Rosenfeld #define MFI_STAT_CONFIG_RESOURCE_CONFLICT 0x0b 193*1e091e43SHans Rosenfeld #define MFI_STAT_DEVICE_NOT_FOUND 0x0c 194*1e091e43SHans Rosenfeld #define MFI_STAT_DRIVE_TOO_SMALL 0x0d 195*1e091e43SHans Rosenfeld #define MFI_STAT_FLASH_ALLOC_FAIL 0x0e 196*1e091e43SHans Rosenfeld #define MFI_STAT_FLASH_BUSY 0x0f 197*1e091e43SHans Rosenfeld #define MFI_STAT_FLASH_ERROR 0x10 198*1e091e43SHans Rosenfeld #define MFI_STAT_FLASH_IMAGE_BAD 0x11 199*1e091e43SHans Rosenfeld #define MFI_STAT_FLASH_IMAGE_INCOMPLETE 0x12 200*1e091e43SHans Rosenfeld #define MFI_STAT_FLASH_NOT_OPEN 0x13 201*1e091e43SHans Rosenfeld #define MFI_STAT_FLASH_NOT_STARTED 0x14 202*1e091e43SHans Rosenfeld #define MFI_STAT_FLUSH_FAILED 0x15 203*1e091e43SHans Rosenfeld #define MFI_STAT_HOST_CODE_NOT_FOUNT 0x16 204*1e091e43SHans Rosenfeld #define MFI_STAT_LD_CC_IN_PROGRESS 0x17 205*1e091e43SHans Rosenfeld #define MFI_STAT_LD_INIT_IN_PROGRESS 0x18 206*1e091e43SHans Rosenfeld #define MFI_STAT_LD_LBA_OUT_OF_RANGE 0x19 207*1e091e43SHans Rosenfeld #define MFI_STAT_LD_MAX_CONFIGURED 0x1a 208*1e091e43SHans Rosenfeld #define MFI_STAT_LD_NOT_OPTIMAL 0x1b 209*1e091e43SHans Rosenfeld #define MFI_STAT_LD_RBLD_IN_PROGRESS 0x1c 210*1e091e43SHans Rosenfeld #define MFI_STAT_LD_RECON_IN_PROGRESS 0x1d 211*1e091e43SHans Rosenfeld #define MFI_STAT_LD_WRONG_RAID_LEVEL 0x1e 212*1e091e43SHans Rosenfeld #define MFI_STAT_MAX_SPARES_EXCEEDED 0x1f 213*1e091e43SHans Rosenfeld #define MFI_STAT_MEMORY_NOT_AVAILABLE 0x20 214*1e091e43SHans Rosenfeld #define MFI_STAT_MFC_HW_ERROR 0x21 215*1e091e43SHans Rosenfeld #define MFI_STAT_NO_HW_PRESENT 0x22 216*1e091e43SHans Rosenfeld #define MFI_STAT_NOT_FOUND 0x23 217*1e091e43SHans Rosenfeld #define MFI_STAT_NOT_IN_ENCL 0x24 218*1e091e43SHans Rosenfeld #define MFI_STAT_PD_CLEAR_IN_PROGRESS 0x25 219*1e091e43SHans Rosenfeld #define MFI_STAT_PD_TYPE_WRONG 0x26 220*1e091e43SHans Rosenfeld #define MFI_STAT_PR_DISABLED 0x27 221*1e091e43SHans Rosenfeld #define MFI_STAT_ROW_INDEX_INVALID 0x28 222*1e091e43SHans Rosenfeld #define MFI_STAT_SAS_CONFIG_INVALID_ACTION 0x29 223*1e091e43SHans Rosenfeld #define MFI_STAT_SAS_CONFIG_INVALID_DATA 0x2a 224*1e091e43SHans Rosenfeld #define MFI_STAT_SAS_CONFIG_INVALID_PAGE 0x2b 225*1e091e43SHans Rosenfeld #define MFI_STAT_SAS_CONFIG_INVALID_TYPE 0x2c 226*1e091e43SHans Rosenfeld #define MFI_STAT_SCSI_DONE_WITH_ERROR 0x2d 227*1e091e43SHans Rosenfeld #define MFI_STAT_SCSI_IO_FAILED 0x2e 228*1e091e43SHans Rosenfeld #define MFI_STAT_SCSI_RESERVATION_CONFLICT 0x2f 229*1e091e43SHans Rosenfeld #define MFI_STAT_SHUTDOWN_FAILED 0x30 230*1e091e43SHans Rosenfeld #define MFI_STAT_TIME_NOT_SET 0x31 231*1e091e43SHans Rosenfeld #define MFI_STAT_WRONG_STATE 0x32 232*1e091e43SHans Rosenfeld #define MFI_STAT_LD_OFFLINE 0x33 233*1e091e43SHans Rosenfeld #define MFI_STAT_PEER_NOTIFICATION_REJECTED 0x34 234*1e091e43SHans Rosenfeld #define MFI_STAT_PEER_NOTIFICATION_FAILED 0x35 235*1e091e43SHans Rosenfeld #define MFI_STAT_RESERVATION_IN_PROGRESS 0x36 236*1e091e43SHans Rosenfeld #define MFI_STAT_I2C_ERRORS_DETECTED 0x37 237*1e091e43SHans Rosenfeld #define MFI_STAT_PCI_ERRORS_DETECTED 0x38 238*1e091e43SHans Rosenfeld #define MFI_STAT_CONFIG_SEQ_MISMATCH 0x67 239*1e091e43SHans Rosenfeld 240*1e091e43SHans Rosenfeld #define MFI_STAT_INVALID_STATUS 0xFF 241*1e091e43SHans Rosenfeld 242*1e091e43SHans Rosenfeld /* 243*1e091e43SHans Rosenfeld * MFI DCMDs 244*1e091e43SHans Rosenfeld */ 245*1e091e43SHans Rosenfeld #define LMRC_DCMD_CTRL_GET_INFO 0x01010000 246*1e091e43SHans Rosenfeld #define LMRC_DCMD_CTRL_EVENT_GET_INFO 0x01040100 247*1e091e43SHans Rosenfeld #define LMRC_DCMD_CTRL_EVENT_WAIT 0x01040500 248*1e091e43SHans Rosenfeld #define LMRC_DCMD_CTRL_SHUTDOWN 0x01050000 249*1e091e43SHans Rosenfeld #define LMRC_DCMD_PD_GET_INFO 0x02020000 250*1e091e43SHans Rosenfeld #define LMRC_DCMD_PD_LIST_QUERY 0x02010100 251*1e091e43SHans Rosenfeld #define LMRC_DCMD_SYSTEM_PD_MAP_GET_INFO 0x0200e102 252*1e091e43SHans Rosenfeld #define LMRC_DCMD_LD_MAP_GET_INFO 0x0300e101 253*1e091e43SHans Rosenfeld #define LMRC_DCMD_LD_GET_LIST 0x03010000 254*1e091e43SHans Rosenfeld #define LMRC_DCMD_LD_LIST_QUERY 0x03010100 255*1e091e43SHans Rosenfeld 256*1e091e43SHans Rosenfeld #define LMRC_PD_QUERY_TYPE_ALL 0 257*1e091e43SHans Rosenfeld #define LMRC_PD_QUERY_TYPE_STATE 1 258*1e091e43SHans Rosenfeld #define LMRC_PD_QUERY_TYPE_POWER_STATE 2 259*1e091e43SHans Rosenfeld #define LMRC_PD_QUERY_TYPE_MEDIA_TYPE 3 260*1e091e43SHans Rosenfeld #define LMRC_PD_QUERY_TYPE_SPEED 4 261*1e091e43SHans Rosenfeld #define LMRC_PD_QUERY_TYPE_EXPOSED_TO_HOST 5 262*1e091e43SHans Rosenfeld 263*1e091e43SHans Rosenfeld #define LMRC_LD_QUERY_TYPE_ALL 0 264*1e091e43SHans Rosenfeld #define LMRC_LD_QUERY_TYPE_EXPOSED_TO_HOST 1 265*1e091e43SHans Rosenfeld #define LMRC_LD_QUERY_TYPE_USED_TGT_IDS 2 266*1e091e43SHans Rosenfeld #define LMRC_LD_QUERY_TYPE_CLUSTER_ACCESS 3 267*1e091e43SHans Rosenfeld #define LMRC_LD_QUERY_TYPE_CLUSTER_LOCALE 4 268*1e091e43SHans Rosenfeld 269*1e091e43SHans Rosenfeld #define LMRC_DCMD_MBOX_PEND_FLAG 0x01 270*1e091e43SHans Rosenfeld 271*1e091e43SHans Rosenfeld #define LMRC_MAX_PD_CHANNELS 1 272*1e091e43SHans Rosenfeld #define LMRC_MAX_LD_CHANNELS 1 273*1e091e43SHans Rosenfeld #define LMRC_MAX_DEV_PER_CHANNEL 256 274*1e091e43SHans Rosenfeld #define LMRC_MAX_PD \ 275*1e091e43SHans Rosenfeld (LMRC_MAX_PD_CHANNELS * LMRC_MAX_DEV_PER_CHANNEL) 276*1e091e43SHans Rosenfeld #define LMRC_MAX_LD \ 277*1e091e43SHans Rosenfeld (LMRC_MAX_LD_CHANNELS * LMRC_MAX_DEV_PER_CHANNEL) 278*1e091e43SHans Rosenfeld #define LMRC_MAX_TM_TARGETS (LMRC_MAX_PD + LMRC_MAX_LD) 279*1e091e43SHans Rosenfeld 280*1e091e43SHans Rosenfeld #define LMRC_DEFAULT_INIT_ID -1 281*1e091e43SHans Rosenfeld #define LMRC_MAX_LUN 8 282*1e091e43SHans Rosenfeld #define LMRC_DEFAULT_CMD_PER_LUN 256 283*1e091e43SHans Rosenfeld 284*1e091e43SHans Rosenfeld #define LMRC_MAX_REPLY_POST_HOST_INDEX 16 285*1e091e43SHans Rosenfeld 286*1e091e43SHans Rosenfeld 287*1e091e43SHans Rosenfeld /* By default, the firmware programs for 8k of memory */ 288*1e091e43SHans Rosenfeld #define LMRC_MFI_MIN_MEM 4096 289*1e091e43SHans Rosenfeld #define LMRC_MFI_DEF_MEM 8192 290*1e091e43SHans Rosenfeld #define LMRC_MFI_MAX_CMD 16 291*1e091e43SHans Rosenfeld 292*1e091e43SHans Rosenfeld 293*1e091e43SHans Rosenfeld #pragma pack(1) 294*1e091e43SHans Rosenfeld 295*1e091e43SHans Rosenfeld /* 296*1e091e43SHans Rosenfeld * MPT RAID MFA IO Descriptor. 297*1e091e43SHans Rosenfeld * 298*1e091e43SHans Rosenfeld * Note: The use of the lowest 8 bits for flags implies that an alignment 299*1e091e43SHans Rosenfeld * of 256 bytes is required for the physical address. 300*1e091e43SHans Rosenfeld */ 301*1e091e43SHans Rosenfeld struct lmrc_raid_mfa_io_req_desc { 302*1e091e43SHans Rosenfeld uint32_t RequestFlags:8; 303*1e091e43SHans Rosenfeld uint32_t MessageAddress1:24; /* bits 31:8 */ 304*1e091e43SHans Rosenfeld uint32_t MessageAddress2; /* bits 61:32 */ 305*1e091e43SHans Rosenfeld }; 306*1e091e43SHans Rosenfeld 307*1e091e43SHans Rosenfeld /* 308*1e091e43SHans Rosenfeld * unions of Request Descriptors 309*1e091e43SHans Rosenfeld */ 310*1e091e43SHans Rosenfeld union lmrc_atomic_req_desc { 311*1e091e43SHans Rosenfeld Mpi26AtomicRequestDescriptor_t rd_atomic; 312*1e091e43SHans Rosenfeld uint32_t rd_reg; 313*1e091e43SHans Rosenfeld }; 314*1e091e43SHans Rosenfeld 315*1e091e43SHans Rosenfeld union lmrc_req_desc { 316*1e091e43SHans Rosenfeld uint64_t rd_reg; 317*1e091e43SHans Rosenfeld 318*1e091e43SHans Rosenfeld struct { 319*1e091e43SHans Rosenfeld uint32_t rd_reg_lo; 320*1e091e43SHans Rosenfeld uint32_t rd_reg_hi; 321*1e091e43SHans Rosenfeld }; 322*1e091e43SHans Rosenfeld 323*1e091e43SHans Rosenfeld lmrc_atomic_req_desc_t rd_atomic; 324*1e091e43SHans Rosenfeld lmrc_raid_mfa_io_req_desc_t rd_mfa_io; 325*1e091e43SHans Rosenfeld }; 326*1e091e43SHans Rosenfeld 327*1e091e43SHans Rosenfeld 328*1e091e43SHans Rosenfeld union lmrc_mfi_cap { 329*1e091e43SHans Rosenfeld struct { 330*1e091e43SHans Rosenfeld uint32_t mc_support_fp_remote_lun:1; 331*1e091e43SHans Rosenfeld uint32_t mc_support_additional_msix:1; 332*1e091e43SHans Rosenfeld uint32_t mc_support_fastpath_wb:1; 333*1e091e43SHans Rosenfeld uint32_t mc_support_max_255lds:1; 334*1e091e43SHans Rosenfeld uint32_t mc_support_ndrive_r1_lb:1; 335*1e091e43SHans Rosenfeld uint32_t mc_support_core_affinity:1; 336*1e091e43SHans Rosenfeld uint32_t mc_support_security_protocol_cmds_fw:1; 337*1e091e43SHans Rosenfeld uint32_t mc_support_ext_queue_depth:1; 338*1e091e43SHans Rosenfeld uint32_t mc_support_ext_io_size:1; 339*1e091e43SHans Rosenfeld uint32_t mc_reserved:23; 340*1e091e43SHans Rosenfeld }; 341*1e091e43SHans Rosenfeld uint32_t mc_reg; 342*1e091e43SHans Rosenfeld }; 343*1e091e43SHans Rosenfeld CTASSERT(sizeof (lmrc_mfi_cap_t) == 4); 344*1e091e43SHans Rosenfeld 345*1e091e43SHans Rosenfeld union lmrc_mfi_sgl { 346*1e091e43SHans Rosenfeld struct { 347*1e091e43SHans Rosenfeld uint32_t ms32_phys_addr; 348*1e091e43SHans Rosenfeld uint32_t ms32_length; 349*1e091e43SHans Rosenfeld }; 350*1e091e43SHans Rosenfeld struct { 351*1e091e43SHans Rosenfeld uint64_t ms64_phys_addr; 352*1e091e43SHans Rosenfeld uint32_t ms64_length; 353*1e091e43SHans Rosenfeld }; 354*1e091e43SHans Rosenfeld }; 355*1e091e43SHans Rosenfeld 356*1e091e43SHans Rosenfeld struct lmrc_mfi_header { 357*1e091e43SHans Rosenfeld uint8_t mh_cmd; /* 0x00 */ 358*1e091e43SHans Rosenfeld uint8_t mh_sense_len; /* 0x01 */ 359*1e091e43SHans Rosenfeld uint8_t mh_cmd_status; /* 0x02 */ 360*1e091e43SHans Rosenfeld uint8_t mh_scsi_status; /* 0x03 */ 361*1e091e43SHans Rosenfeld 362*1e091e43SHans Rosenfeld union { 363*1e091e43SHans Rosenfeld lmrc_mfi_cap_t mh_drv_opts; /* 0x04 */ 364*1e091e43SHans Rosenfeld struct { 365*1e091e43SHans Rosenfeld uint8_t mh_target_id; /* 0x04 */ 366*1e091e43SHans Rosenfeld union { 367*1e091e43SHans Rosenfeld uint8_t mh_lun; /* 0x05 */ 368*1e091e43SHans Rosenfeld uint8_t mh_access_byte; /* 0x05 */ 369*1e091e43SHans Rosenfeld }; 370*1e091e43SHans Rosenfeld uint8_t mh_cdb_len; /* 0x06 */ 371*1e091e43SHans Rosenfeld uint8_t mh_sge_count; /* 0x07 */ 372*1e091e43SHans Rosenfeld }; 373*1e091e43SHans Rosenfeld }; 374*1e091e43SHans Rosenfeld 375*1e091e43SHans Rosenfeld uint32_t mh_context; /* 0x08 */ 376*1e091e43SHans Rosenfeld uint32_t mh_pad_0; /* 0x0c */ 377*1e091e43SHans Rosenfeld 378*1e091e43SHans Rosenfeld uint16_t mh_flags; /* 0x10 */ 379*1e091e43SHans Rosenfeld uint16_t mh_timeout; /* 0x12 */ 380*1e091e43SHans Rosenfeld union { 381*1e091e43SHans Rosenfeld uint32_t mh_data_xfer_len; /* 0x14 */ 382*1e091e43SHans Rosenfeld uint32_t mh_lba_count; /* 0x14 */ 383*1e091e43SHans Rosenfeld }; 384*1e091e43SHans Rosenfeld }; 385*1e091e43SHans Rosenfeld 386*1e091e43SHans Rosenfeld struct lmrc_mfi_init_payload { 387*1e091e43SHans Rosenfeld uint64_t mi_queue_info_new_phys_addr; /* 0x18 */ 388*1e091e43SHans Rosenfeld uint64_t mi_queue_info_old_phys_addr; /* 0x20 */ 389*1e091e43SHans Rosenfeld uint64_t mi_driver_ver_phys_addr; /* 0x28 */ 390*1e091e43SHans Rosenfeld }; 391*1e091e43SHans Rosenfeld 392*1e091e43SHans Rosenfeld struct lmrc_mfi_io_payload { 393*1e091e43SHans Rosenfeld uint64_t mio_sense_buf_phys_addr; /* 0x18 */ 394*1e091e43SHans Rosenfeld uint64_t mio_start_lba; /* 0x20 */ 395*1e091e43SHans Rosenfeld lmrc_mfi_sgl_t mio_sgl; /* 0x28 */ 396*1e091e43SHans Rosenfeld }; 397*1e091e43SHans Rosenfeld 398*1e091e43SHans Rosenfeld struct lmrc_mfi_pthru_payload { 399*1e091e43SHans Rosenfeld uint64_t mp_sense_buf_phys_addr; /* 0x18 */ 400*1e091e43SHans Rosenfeld uint8_t mp_cdb[16]; /* 0x20 */ 401*1e091e43SHans Rosenfeld lmrc_mfi_sgl_t mp_sgl; /* 0x30 */ 402*1e091e43SHans Rosenfeld }; 403*1e091e43SHans Rosenfeld 404*1e091e43SHans Rosenfeld struct lmrc_mfi_dcmd_payload { 405*1e091e43SHans Rosenfeld uint32_t md_opcode; /* 0x18 */ 406*1e091e43SHans Rosenfeld 407*1e091e43SHans Rosenfeld union { /* 0x1c */ 408*1e091e43SHans Rosenfeld uint8_t md_mbox_8[12]; 409*1e091e43SHans Rosenfeld uint16_t md_mbox_16[6]; 410*1e091e43SHans Rosenfeld uint32_t md_mbox_32[3]; 411*1e091e43SHans Rosenfeld }; 412*1e091e43SHans Rosenfeld 413*1e091e43SHans Rosenfeld lmrc_mfi_sgl_t md_sgl; /* 0x28 */ 414*1e091e43SHans Rosenfeld }; 415*1e091e43SHans Rosenfeld 416*1e091e43SHans Rosenfeld struct lmrc_mfi_abort_payload { 417*1e091e43SHans Rosenfeld uint32_t ma_abort_context; /* 0x18 */ 418*1e091e43SHans Rosenfeld uint32_t ma_pad_1; /* 0x1c */ 419*1e091e43SHans Rosenfeld uint64_t ma_abort_mfi_phys_addr; /* 0x20 */ 420*1e091e43SHans Rosenfeld }; 421*1e091e43SHans Rosenfeld 422*1e091e43SHans Rosenfeld struct lmrc_mfi_frame { 423*1e091e43SHans Rosenfeld lmrc_mfi_header_t mf_hdr; 424*1e091e43SHans Rosenfeld union { 425*1e091e43SHans Rosenfeld lmrc_mfi_init_payload_t mf_init; 426*1e091e43SHans Rosenfeld lmrc_mfi_io_payload_t mf_io; 427*1e091e43SHans Rosenfeld lmrc_mfi_pthru_payload_t mf_pthru; 428*1e091e43SHans Rosenfeld lmrc_mfi_dcmd_payload_t mf_dcmd; 429*1e091e43SHans Rosenfeld lmrc_mfi_abort_payload_t mf_abort; 430*1e091e43SHans Rosenfeld uint8_t mf_raw[64 - sizeof (lmrc_mfi_header_t)]; 431*1e091e43SHans Rosenfeld }; 432*1e091e43SHans Rosenfeld }; 433*1e091e43SHans Rosenfeld CTASSERT(offsetof(lmrc_mfi_frame_t, mf_init) == 0x18); 434*1e091e43SHans Rosenfeld CTASSERT(sizeof (lmrc_mfi_frame_t) == 64); 435*1e091e43SHans Rosenfeld 436*1e091e43SHans Rosenfeld struct lmrc_aen { 437*1e091e43SHans Rosenfeld uint16_t aen_host_no; 438*1e091e43SHans Rosenfeld uint16_t aen_cmd_status; 439*1e091e43SHans Rosenfeld uint32_t aen_seqnum; 440*1e091e43SHans Rosenfeld uint32_t aen_class_locale_word; 441*1e091e43SHans Rosenfeld }; 442*1e091e43SHans Rosenfeld 443*1e091e43SHans Rosenfeld /* 444*1e091e43SHans Rosenfeld * Asynchronous Event Notifications 445*1e091e43SHans Rosenfeld */ 446*1e091e43SHans Rosenfeld #define LMRC_EVT_CFG_CLEARED 0x0004 447*1e091e43SHans Rosenfeld #define LMRC_EVT_CTRL_PATROL_READ_COMPLETE 0x0023 448*1e091e43SHans Rosenfeld #define LMRC_EVT_CTRL_PATROL_READ_RESUMED 0x0026 449*1e091e43SHans Rosenfeld #define LMRC_EVT_CTRL_PATROL_READ_START 0x0027 450*1e091e43SHans Rosenfeld #define LMRC_EVT_LD_BG_INIT_PROGRESS 0x0034 451*1e091e43SHans Rosenfeld #define LMRC_EVT_LD_CC_COMPLETE 0x003a 452*1e091e43SHans Rosenfeld #define LMRC_EVT_LD_CC_PROGRESS 0x0041 453*1e091e43SHans Rosenfeld #define LMRC_EVT_LD_CC_STARTED 0x0042 454*1e091e43SHans Rosenfeld #define LMRC_EVT_LD_INIT_ABORTED 0x0043 455*1e091e43SHans Rosenfeld #define LMRC_EVT_LD_INIT_PROGRESS 0x0045 456*1e091e43SHans Rosenfeld #define LMRC_EVT_LD_FAST_INIT_STARTED 0x0046 457*1e091e43SHans Rosenfeld #define LMRC_EVT_LD_FULL_INIT_STARTED 0x0047 458*1e091e43SHans Rosenfeld #define LMRC_EVT_LD_INIT_COMPLETE 0x0048 459*1e091e43SHans Rosenfeld #define LMRC_EVT_LD_PROP_CHANGED 0x0049 460*1e091e43SHans Rosenfeld #define LMRC_EVT_LD_STATE_CHANGE 0x0051 461*1e091e43SHans Rosenfeld #define LMRC_EVT_PD_INSERTED 0x005b 462*1e091e43SHans Rosenfeld #define LMRC_EVT_PD_PATROL_READ_PROGRESS 0x005e 463*1e091e43SHans Rosenfeld #define LMRC_EVT_PD_REMOVED 0x0070 464*1e091e43SHans Rosenfeld #define LMRC_EVT_PD_CHANGED 0x0072 465*1e091e43SHans Rosenfeld #define LMRC_EVT_LD_CREATED 0x008a 466*1e091e43SHans Rosenfeld #define LMRC_EVT_LD_DELETED 0x008b 467*1e091e43SHans Rosenfeld #define LMRC_EVT_FOREIGN_CFG_IMPORTED 0x00db 468*1e091e43SHans Rosenfeld #define LMRC_EVT_LD_OPTIMAL 0x00f9 469*1e091e43SHans Rosenfeld #define LMRC_EVT_LD_OFFLINE 0x00fc 470*1e091e43SHans Rosenfeld #define LMRC_EVT_PD_RESET 0x010c 471*1e091e43SHans Rosenfeld #define LMRC_EVT_CTRL_PATROL_READ_CANT_START 0x0124 472*1e091e43SHans Rosenfeld #define LMRC_EVT_CTRL_PROP_CHANGED 0x012f 473*1e091e43SHans Rosenfeld #define LMRC_EVT_LD_BBT_CLEARED 0x014f 474*1e091e43SHans Rosenfeld #define LMRC_EVT_CTRL_HOST_BUS_SCAN_REQD 0x0152 475*1e091e43SHans Rosenfeld #define LMRC_EVT_LD_AVAILABLE 0x0172 476*1e091e43SHans Rosenfeld #define LMRC_EVT_CTRL_PERF_COLLECTION 0x017e 477*1e091e43SHans Rosenfeld #define LMRC_EVT_CTRL_BOOTDEV_SET 0x01ec 478*1e091e43SHans Rosenfeld #define LMRC_EVT_CTRL_BOOTDEV_RESET 0x01f3 479*1e091e43SHans Rosenfeld #define LMRC_EVT_CTRL_PERSONALITY_CHANGE 0x0206 480*1e091e43SHans Rosenfeld #define LMRC_EVT_CTRL_PERSONALITY_CHANGE_PEND 0x0222 481*1e091e43SHans Rosenfeld #define LMRC_EVT_CTRL_NR_OF_VALID_SNAPDUMP 0x024e 482*1e091e43SHans Rosenfeld 483*1e091e43SHans Rosenfeld #define LMRC_EVT_CLASS_DEBUG -2 484*1e091e43SHans Rosenfeld #define LMRC_EVT_CLASS_PROGRESS -1 485*1e091e43SHans Rosenfeld #define LMRC_EVT_CLASS_INFO 0 486*1e091e43SHans Rosenfeld #define LMRC_EVT_CLASS_WARNING 1 487*1e091e43SHans Rosenfeld #define LMRC_EVT_CLASS_CRITICAL 2 488*1e091e43SHans Rosenfeld #define LMRC_EVT_CLASS_FATAL 3 489*1e091e43SHans Rosenfeld #define LMRC_EVT_CLASS_DEAD 4 490*1e091e43SHans Rosenfeld 491*1e091e43SHans Rosenfeld #define LMRC_EVT_LOCALE_LD 0x0001 492*1e091e43SHans Rosenfeld #define LMRC_EVT_LOCALE_PD 0x0002 493*1e091e43SHans Rosenfeld #define LMRC_EVT_LOCALE_ENCL 0x0004 494*1e091e43SHans Rosenfeld #define LMRC_EVT_LOCALE_BBU 0x0008 495*1e091e43SHans Rosenfeld #define LMRC_EVT_LOCALE_SAS 0x0010 496*1e091e43SHans Rosenfeld #define LMRC_EVT_LOCALE_CTRL 0x0020 497*1e091e43SHans Rosenfeld #define LMRC_EVT_LOCALE_CONFIG 0x0040 498*1e091e43SHans Rosenfeld #define LMRC_EVT_LOCALE_CLUSTER 0x0080 499*1e091e43SHans Rosenfeld #define LMRC_EVT_LOCALE_ALL 0xffff 500*1e091e43SHans Rosenfeld 501*1e091e43SHans Rosenfeld union lmrc_evt_class_locale { 502*1e091e43SHans Rosenfeld struct { 503*1e091e43SHans Rosenfeld uint16_t ecl_locale; 504*1e091e43SHans Rosenfeld uint8_t ecl_rsvd; 505*1e091e43SHans Rosenfeld int8_t ecl_class; 506*1e091e43SHans Rosenfeld }; 507*1e091e43SHans Rosenfeld uint32_t ecl_word; 508*1e091e43SHans Rosenfeld }; 509*1e091e43SHans Rosenfeld 510*1e091e43SHans Rosenfeld struct lmrc_evt_log_info { 511*1e091e43SHans Rosenfeld uint32_t eli_newest_seqnum; 512*1e091e43SHans Rosenfeld uint32_t eli_oldest_seqnum; 513*1e091e43SHans Rosenfeld uint32_t eli_clear_seqnum; 514*1e091e43SHans Rosenfeld uint32_t eli_shutdown_seqnum; 515*1e091e43SHans Rosenfeld uint32_t eli_boot_seqnum; 516*1e091e43SHans Rosenfeld }; 517*1e091e43SHans Rosenfeld 518*1e091e43SHans Rosenfeld struct lmrc_evtarg_ld { 519*1e091e43SHans Rosenfeld uint16_t el_tgtid; 520*1e091e43SHans Rosenfeld uint8_t el_ld_id; 521*1e091e43SHans Rosenfeld uint8_t el_rsvd; 522*1e091e43SHans Rosenfeld }; 523*1e091e43SHans Rosenfeld 524*1e091e43SHans Rosenfeld struct lmrc_evtarg_pd { 525*1e091e43SHans Rosenfeld uint16_t ep_dev_id; 526*1e091e43SHans Rosenfeld uint8_t ep_enc_id; 527*1e091e43SHans Rosenfeld uint8_t ep_slot; 528*1e091e43SHans Rosenfeld }; 529*1e091e43SHans Rosenfeld 530*1e091e43SHans Rosenfeld struct lmrc_evt { 531*1e091e43SHans Rosenfeld uint32_t evt_seqnum; 532*1e091e43SHans Rosenfeld uint32_t evt_timestamp; 533*1e091e43SHans Rosenfeld uint32_t evt_code; 534*1e091e43SHans Rosenfeld uint16_t evt_locale; 535*1e091e43SHans Rosenfeld uint8_t evt_rsvd; 536*1e091e43SHans Rosenfeld int8_t evt_class; 537*1e091e43SHans Rosenfeld uint8_t evt_argtype; 538*1e091e43SHans Rosenfeld uint8_t evt_rsvd2[15]; 539*1e091e43SHans Rosenfeld union { 540*1e091e43SHans Rosenfeld lmrc_evtarg_ld_t evt_ld; 541*1e091e43SHans Rosenfeld lmrc_evtarg_pd_t evt_pd; 542*1e091e43SHans Rosenfeld char evt_str[96]; 543*1e091e43SHans Rosenfeld }; 544*1e091e43SHans Rosenfeld char evt_descr[128]; 545*1e091e43SHans Rosenfeld }; 546*1e091e43SHans Rosenfeld CTASSERT(sizeof (lmrc_evt_t) == 256); 547*1e091e43SHans Rosenfeld 548*1e091e43SHans Rosenfeld /* 549*1e091e43SHans Rosenfeld * SAS controller properties 550*1e091e43SHans Rosenfeld */ 551*1e091e43SHans Rosenfeld struct lmrc_ctrl_prop { 552*1e091e43SHans Rosenfeld uint16_t cp_seq_num; 553*1e091e43SHans Rosenfeld uint16_t cp_pred_fail_poll_interval; 554*1e091e43SHans Rosenfeld uint16_t cp_intr_throttle_count; 555*1e091e43SHans Rosenfeld uint16_t cp_intr_throttle_timeouts; 556*1e091e43SHans Rosenfeld uint8_t cp_rebuild_rate; 557*1e091e43SHans Rosenfeld uint8_t cp_patrol_read_rate; 558*1e091e43SHans Rosenfeld uint8_t cp_bgi_rate; 559*1e091e43SHans Rosenfeld uint8_t cp_cc_rate; 560*1e091e43SHans Rosenfeld uint8_t cp_recon_rate; 561*1e091e43SHans Rosenfeld uint8_t cp_cache_flush_interval; 562*1e091e43SHans Rosenfeld uint8_t cp_spinup_drv_count; 563*1e091e43SHans Rosenfeld uint8_t cp_spinup_delay; 564*1e091e43SHans Rosenfeld uint8_t cp_cluster_enable; 565*1e091e43SHans Rosenfeld uint8_t cp_coercion_mode; 566*1e091e43SHans Rosenfeld uint8_t cp_alarm_enable; 567*1e091e43SHans Rosenfeld uint8_t cp_disable_auto_rebuild; 568*1e091e43SHans Rosenfeld uint8_t cp_disable_battery_warn; 569*1e091e43SHans Rosenfeld uint8_t cp_ecc_bucket_size; 570*1e091e43SHans Rosenfeld uint16_t cp_ecc_bucket_leak_rate; 571*1e091e43SHans Rosenfeld uint8_t cp_restore_hotspare_on_insertion; 572*1e091e43SHans Rosenfeld uint8_t cp_expose_encl_devices; 573*1e091e43SHans Rosenfeld uint8_t cp_maintain_pd_fail_history; 574*1e091e43SHans Rosenfeld uint8_t cp_disallow_host_request_reordering; 575*1e091e43SHans Rosenfeld uint8_t cp_abort_cc_on_error; 576*1e091e43SHans Rosenfeld uint8_t cp_load_balance_mode; 577*1e091e43SHans Rosenfeld uint8_t cp_disable_auto_detect_backplane; 578*1e091e43SHans Rosenfeld uint8_t cp_snap_vd_space; 579*1e091e43SHans Rosenfeld 580*1e091e43SHans Rosenfeld struct { 581*1e091e43SHans Rosenfeld uint32_t cp_copy_back_disabled:1; 582*1e091e43SHans Rosenfeld uint32_t cp_smarter_enabled:1; 583*1e091e43SHans Rosenfeld uint32_t cp_pr_correct_unconfigured_areas:1; 584*1e091e43SHans Rosenfeld uint32_t cp_use_FDE_only:1; 585*1e091e43SHans Rosenfeld uint32_t cp_disable_NCQ:1; 586*1e091e43SHans Rosenfeld uint32_t cp_SSD_smarter_enabled:1; 587*1e091e43SHans Rosenfeld uint32_t cp_SSD_patrol_read_enabled:1; 588*1e091e43SHans Rosenfeld uint32_t cp_enable_spin_down_unconfigured:1; 589*1e091e43SHans Rosenfeld uint32_t cp_auto_enhanced_import:1; 590*1e091e43SHans Rosenfeld uint32_t cp_enable_secret_key_control:1; 591*1e091e43SHans Rosenfeld uint32_t cp_disable_online_ctrl_reset:1; 592*1e091e43SHans Rosenfeld uint32_t cp_allow_boot_with_pinned_cache:1; 593*1e091e43SHans Rosenfeld uint32_t cp_disable_spin_down_HS:1; 594*1e091e43SHans Rosenfeld uint32_t cp_enable_JBOD:1; 595*1e091e43SHans Rosenfeld uint32_t cp_disable_cache_bypass:1; 596*1e091e43SHans Rosenfeld uint32_t cp_use_disk_activity_for_locate:1; 597*1e091e43SHans Rosenfeld uint32_t cp_enable_PI:1; 598*1e091e43SHans Rosenfeld uint32_t cp_prevent_PI_import:1; 599*1e091e43SHans Rosenfeld uint32_t cp_use_global_spares_for_emergency:1; 600*1e091e43SHans Rosenfeld uint32_t cp_use_unconf_good_for_emergency:1; 601*1e091e43SHans Rosenfeld uint32_t cp_use_emergency_spares_for_smarter:1; 602*1e091e43SHans Rosenfeld uint32_t cp_force_sgpio_for_quad_only:1; 603*1e091e43SHans Rosenfeld uint32_t cp_enable_config_auto_balance:1; 604*1e091e43SHans Rosenfeld uint32_t cp_enable_virtual_cache:1; 605*1e091e43SHans Rosenfeld uint32_t cp_enable_auto_lock_recovery:1; 606*1e091e43SHans Rosenfeld uint32_t cp_disable_immediate_io:1; 607*1e091e43SHans Rosenfeld uint32_t cp_disable_T10_rebuild_assist:1; 608*1e091e43SHans Rosenfeld uint32_t cp_ignore64_ld_restriction:1; 609*1e091e43SHans Rosenfeld uint32_t cp_enable_sw_zone:1; 610*1e091e43SHans Rosenfeld uint32_t cp_limit_max_rate_SATA_3G:1; 611*1e091e43SHans Rosenfeld uint32_t cp_reserved:2; 612*1e091e43SHans Rosenfeld }; 613*1e091e43SHans Rosenfeld uint8_t cp_auto_snap_vd_space; 614*1e091e43SHans Rosenfeld uint8_t cp_view_space; 615*1e091e43SHans Rosenfeld uint16_t cp_spin_down_time; 616*1e091e43SHans Rosenfeld uint8_t cp_reserved2[24]; 617*1e091e43SHans Rosenfeld }; 618*1e091e43SHans Rosenfeld 619*1e091e43SHans Rosenfeld struct lmrc_image_comp { 620*1e091e43SHans Rosenfeld char ic_name[8]; 621*1e091e43SHans Rosenfeld char ic_version[32]; 622*1e091e43SHans Rosenfeld char ic_build_date[16]; 623*1e091e43SHans Rosenfeld char ic_built_time[16]; 624*1e091e43SHans Rosenfeld }; 625*1e091e43SHans Rosenfeld 626*1e091e43SHans Rosenfeld /* 627*1e091e43SHans Rosenfeld * SAS controller information 628*1e091e43SHans Rosenfeld */ 629*1e091e43SHans Rosenfeld struct lmrc_ctrl_info { 630*1e091e43SHans Rosenfeld /* PCI device information */ 631*1e091e43SHans Rosenfeld struct { 632*1e091e43SHans Rosenfeld uint16_t pci_vendor_id; 633*1e091e43SHans Rosenfeld uint16_t pci_device_id; 634*1e091e43SHans Rosenfeld uint16_t pci_sub_vendor_id; 635*1e091e43SHans Rosenfeld uint16_t pci_sub_device_id; 636*1e091e43SHans Rosenfeld uint8_t pci_reserved[24]; 637*1e091e43SHans Rosenfeld } ci_pci; 638*1e091e43SHans Rosenfeld 639*1e091e43SHans Rosenfeld /* Host interface information */ 640*1e091e43SHans Rosenfeld struct { 641*1e091e43SHans Rosenfeld uint8_t hi_PCIX:1; 642*1e091e43SHans Rosenfeld uint8_t hi_PCIE:1; 643*1e091e43SHans Rosenfeld uint8_t hi_iSCSI:1; 644*1e091e43SHans Rosenfeld uint8_t hi_SAS_3G:1; 645*1e091e43SHans Rosenfeld uint8_t hi_reserved_0:4; 646*1e091e43SHans Rosenfeld uint8_t hi_reserved_1[6]; 647*1e091e43SHans Rosenfeld uint8_t hi_port_count; 648*1e091e43SHans Rosenfeld uint64_t hi_port_addr[8]; 649*1e091e43SHans Rosenfeld } ci_host_interface; 650*1e091e43SHans Rosenfeld 651*1e091e43SHans Rosenfeld /* Target interface information */ 652*1e091e43SHans Rosenfeld struct { 653*1e091e43SHans Rosenfeld uint8_t di_SPI:1; 654*1e091e43SHans Rosenfeld uint8_t di_SAS_3G:1; 655*1e091e43SHans Rosenfeld uint8_t di_SATA_1_5G:1; 656*1e091e43SHans Rosenfeld uint8_t di_SATA_3G:1; 657*1e091e43SHans Rosenfeld uint8_t di_reserved_0:4; 658*1e091e43SHans Rosenfeld uint8_t di_reserved_1[6]; 659*1e091e43SHans Rosenfeld uint8_t di_port_count; 660*1e091e43SHans Rosenfeld uint64_t di_port_addr[8]; 661*1e091e43SHans Rosenfeld } ci_device_interface; 662*1e091e43SHans Rosenfeld 663*1e091e43SHans Rosenfeld uint32_t ci_image_check_word; 664*1e091e43SHans Rosenfeld 665*1e091e43SHans Rosenfeld uint32_t ci_image_component_count; 666*1e091e43SHans Rosenfeld lmrc_image_comp_t ci_image_component[8]; 667*1e091e43SHans Rosenfeld 668*1e091e43SHans Rosenfeld uint32_t ci_pending_image_component_count; 669*1e091e43SHans Rosenfeld lmrc_image_comp_t ci_pending_image_component[8]; 670*1e091e43SHans Rosenfeld 671*1e091e43SHans Rosenfeld uint8_t ci_max_arms; 672*1e091e43SHans Rosenfeld uint8_t ci_max_spans; 673*1e091e43SHans Rosenfeld uint8_t ci_max_arrays; 674*1e091e43SHans Rosenfeld uint8_t ci_max_lds; 675*1e091e43SHans Rosenfeld char ci_product_name[80]; 676*1e091e43SHans Rosenfeld char ci_serial_no[32]; 677*1e091e43SHans Rosenfeld 678*1e091e43SHans Rosenfeld /* 679*1e091e43SHans Rosenfeld * Hardware features 680*1e091e43SHans Rosenfeld */ 681*1e091e43SHans Rosenfeld struct { 682*1e091e43SHans Rosenfeld uint32_t hw_bbu:1; 683*1e091e43SHans Rosenfeld uint32_t hw_alarm:1; 684*1e091e43SHans Rosenfeld uint32_t hw_nvram:1; 685*1e091e43SHans Rosenfeld uint32_t hw_uart:1; 686*1e091e43SHans Rosenfeld uint32_t hw_reserved:28; 687*1e091e43SHans Rosenfeld } ci_hw_present; 688*1e091e43SHans Rosenfeld 689*1e091e43SHans Rosenfeld uint32_t current_fw_time; 690*1e091e43SHans Rosenfeld 691*1e091e43SHans Rosenfeld /* Maximum data transfer sizes */ 692*1e091e43SHans Rosenfeld uint16_t ci_max_concurrent_cmds; 693*1e091e43SHans Rosenfeld uint16_t ci_max_sge_count; 694*1e091e43SHans Rosenfeld uint32_t ci_max_request_size; 695*1e091e43SHans Rosenfeld 696*1e091e43SHans Rosenfeld /* Logical and physical device counts */ 697*1e091e43SHans Rosenfeld uint16_t ci_ld_present_count; 698*1e091e43SHans Rosenfeld uint16_t ci_ld_degraded_count; 699*1e091e43SHans Rosenfeld uint16_t ci_ld_offline_count; 700*1e091e43SHans Rosenfeld 701*1e091e43SHans Rosenfeld uint16_t ci_pd_present_count; 702*1e091e43SHans Rosenfeld uint16_t ci_pd_disk_present_count; 703*1e091e43SHans Rosenfeld uint16_t ci_pd_disk_pred_failure_count; 704*1e091e43SHans Rosenfeld uint16_t ci_pd_disk_failed_count; 705*1e091e43SHans Rosenfeld 706*1e091e43SHans Rosenfeld /* Memory size information */ 707*1e091e43SHans Rosenfeld uint16_t ci_nvram_size; 708*1e091e43SHans Rosenfeld uint16_t ci_memory_size; 709*1e091e43SHans Rosenfeld uint16_t ci_flash_size; 710*1e091e43SHans Rosenfeld 711*1e091e43SHans Rosenfeld /* Error counters */ 712*1e091e43SHans Rosenfeld uint16_t ci_mem_correctable_error_count; 713*1e091e43SHans Rosenfeld uint16_t ci_mem_uncorrectable_error_count; 714*1e091e43SHans Rosenfeld 715*1e091e43SHans Rosenfeld /* Cluster information */ 716*1e091e43SHans Rosenfeld uint8_t ci_cluster_permitted; 717*1e091e43SHans Rosenfeld uint8_t ci_cluster_active; 718*1e091e43SHans Rosenfeld 719*1e091e43SHans Rosenfeld /* Additional max data transfer sizes */ 720*1e091e43SHans Rosenfeld uint16_t ci_max_stripes_per_io; 721*1e091e43SHans Rosenfeld 722*1e091e43SHans Rosenfeld /* Controller capabilities structures */ 723*1e091e43SHans Rosenfeld struct { 724*1e091e43SHans Rosenfeld uint32_t rl_raid_level_0:1; 725*1e091e43SHans Rosenfeld uint32_t rl_raid_level_1:1; 726*1e091e43SHans Rosenfeld uint32_t rl_raid_level_5:1; 727*1e091e43SHans Rosenfeld uint32_t rl_raid_level_1E:1; 728*1e091e43SHans Rosenfeld uint32_t rl_raid_level_6:1; 729*1e091e43SHans Rosenfeld uint32_t rl_reserved:27; 730*1e091e43SHans Rosenfeld } ci_raid_levels; 731*1e091e43SHans Rosenfeld 732*1e091e43SHans Rosenfeld struct { 733*1e091e43SHans Rosenfeld uint32_t ao_rbld_rate:1; 734*1e091e43SHans Rosenfeld uint32_t ao_cc_rate:1; 735*1e091e43SHans Rosenfeld uint32_t ao_bgi_rate:1; 736*1e091e43SHans Rosenfeld uint32_t ao_recon_rate:1; 737*1e091e43SHans Rosenfeld uint32_t ao_patrol_rate:1; 738*1e091e43SHans Rosenfeld uint32_t ao_alarm_control:1; 739*1e091e43SHans Rosenfeld uint32_t ao_cluster_supported:1; 740*1e091e43SHans Rosenfeld uint32_t ao_bbu:1; 741*1e091e43SHans Rosenfeld uint32_t ao_spanning_allowed:1; 742*1e091e43SHans Rosenfeld uint32_t ao_dedicated_hotspares:1; 743*1e091e43SHans Rosenfeld uint32_t ao_revertible_hotspares:1; 744*1e091e43SHans Rosenfeld uint32_t ao_foreign_config_import:1; 745*1e091e43SHans Rosenfeld uint32_t ao_self_diagnostic:1; 746*1e091e43SHans Rosenfeld uint32_t ao_mixed_redundancy_arr:1; 747*1e091e43SHans Rosenfeld uint32_t ao_global_hot_spares:1; 748*1e091e43SHans Rosenfeld uint32_t ao_reserved:17; 749*1e091e43SHans Rosenfeld } ci_adapter_opts; 750*1e091e43SHans Rosenfeld 751*1e091e43SHans Rosenfeld struct { 752*1e091e43SHans Rosenfeld uint32_t ld_read_policy:1; 753*1e091e43SHans Rosenfeld uint32_t ld_write_policy:1; 754*1e091e43SHans Rosenfeld uint32_t ld_io_policy:1; 755*1e091e43SHans Rosenfeld uint32_t ld_access_policy:1; 756*1e091e43SHans Rosenfeld uint32_t ld_disk_cache_policy:1; 757*1e091e43SHans Rosenfeld uint32_t ld_reserved:27; 758*1e091e43SHans Rosenfeld } ci_ld_opts; 759*1e091e43SHans Rosenfeld 760*1e091e43SHans Rosenfeld struct { 761*1e091e43SHans Rosenfeld uint8_t raid_stripe_sz_min; 762*1e091e43SHans Rosenfeld uint8_t raid_stripe_sz_max; 763*1e091e43SHans Rosenfeld uint8_t raid_reserved[2]; 764*1e091e43SHans Rosenfeld } ci_raid_opts; 765*1e091e43SHans Rosenfeld 766*1e091e43SHans Rosenfeld struct { 767*1e091e43SHans Rosenfeld uint32_t pd_force_online:1; 768*1e091e43SHans Rosenfeld uint32_t pd_force_offline:1; 769*1e091e43SHans Rosenfeld uint32_t pd_force_rebuild:1; 770*1e091e43SHans Rosenfeld uint32_t pd_reserved:29; 771*1e091e43SHans Rosenfeld } ci_pd_opts; 772*1e091e43SHans Rosenfeld 773*1e091e43SHans Rosenfeld struct { 774*1e091e43SHans Rosenfeld uint32_t pd_ctrl_supports_sas:1; 775*1e091e43SHans Rosenfeld uint32_t pd_ctrl_supports_sata:1; 776*1e091e43SHans Rosenfeld uint32_t pd_allow_mix_in_encl:1; 777*1e091e43SHans Rosenfeld uint32_t pd_allow_mix_in_ld:1; 778*1e091e43SHans Rosenfeld uint32_t pd_allow_sata_in_cluster:1; 779*1e091e43SHans Rosenfeld uint32_t pd_reserved:27; 780*1e091e43SHans Rosenfeld } ci_pd_mix_support; 781*1e091e43SHans Rosenfeld 782*1e091e43SHans Rosenfeld /* ECC single-bit error bucket information */ 783*1e091e43SHans Rosenfeld uint8_t ci_ecc_bucket_count; 784*1e091e43SHans Rosenfeld uint8_t ci_reserved_2[11]; 785*1e091e43SHans Rosenfeld 786*1e091e43SHans Rosenfeld /* Controller properties */ 787*1e091e43SHans Rosenfeld lmrc_ctrl_prop_t ci_prop; 788*1e091e43SHans Rosenfeld 789*1e091e43SHans Rosenfeld char ci_package_version[0x60]; 790*1e091e43SHans Rosenfeld 791*1e091e43SHans Rosenfeld uint64_t ci_device_interface_port_addr2[8]; 792*1e091e43SHans Rosenfeld uint8_t ci_reserved3[128]; 793*1e091e43SHans Rosenfeld 794*1e091e43SHans Rosenfeld struct { 795*1e091e43SHans Rosenfeld uint16_t pd_min_pd_raid_level_0:4; 796*1e091e43SHans Rosenfeld uint16_t pd_max_pd_raid_level_0:12; 797*1e091e43SHans Rosenfeld 798*1e091e43SHans Rosenfeld uint16_t pd_min_pd_raid_level_1:4; 799*1e091e43SHans Rosenfeld uint16_t pd_max_pd_raid_level_1:12; 800*1e091e43SHans Rosenfeld 801*1e091e43SHans Rosenfeld uint16_t pd_min_pd_raid_level_5:4; 802*1e091e43SHans Rosenfeld uint16_t pd_max_pd_raid_level_5:12; 803*1e091e43SHans Rosenfeld 804*1e091e43SHans Rosenfeld uint16_t pd_min_pd_raid_level_1E:4; 805*1e091e43SHans Rosenfeld uint16_t pd_max_pd_raid_level_1E:12; 806*1e091e43SHans Rosenfeld 807*1e091e43SHans Rosenfeld uint16_t pd_min_pd_raid_level_6:4; 808*1e091e43SHans Rosenfeld uint16_t pd_max_pd_raid_level_6:12; 809*1e091e43SHans Rosenfeld 810*1e091e43SHans Rosenfeld uint16_t pd_min_pd_raid_level_10:4; 811*1e091e43SHans Rosenfeld uint16_t pd_max_pd_raid_level_10:12; 812*1e091e43SHans Rosenfeld 813*1e091e43SHans Rosenfeld uint16_t pd_min_pd_raid_level_50:4; 814*1e091e43SHans Rosenfeld uint16_t pd_max_pd_raid_level_50:12; 815*1e091e43SHans Rosenfeld 816*1e091e43SHans Rosenfeld uint16_t pd_min_pd_raid_level_60:4; 817*1e091e43SHans Rosenfeld uint16_t pd_max_pd_raid_level_60:12; 818*1e091e43SHans Rosenfeld 819*1e091e43SHans Rosenfeld uint16_t pd_min_pd_raid_level_1E_RLQ0:4; 820*1e091e43SHans Rosenfeld uint16_t pd_max_pd_raid_level_1E_RLQ0:12; 821*1e091e43SHans Rosenfeld 822*1e091e43SHans Rosenfeld uint16_t pd_min_pd_raid_level_1E0_RLQ0:4; 823*1e091e43SHans Rosenfeld uint16_t pd_max_pd_raid_level_1E0_RLQ0:12; 824*1e091e43SHans Rosenfeld 825*1e091e43SHans Rosenfeld uint16_t pd_reserved[6]; 826*1e091e43SHans Rosenfeld } ci_pds_for_raid_levels; 827*1e091e43SHans Rosenfeld 828*1e091e43SHans Rosenfeld uint16_t ci_max_pds; /* 0x780 */ 829*1e091e43SHans Rosenfeld uint16_t ci_max_ded_HSPs; /* 0x782 */ 830*1e091e43SHans Rosenfeld uint16_t ci_max_global_HSPs; /* 0x784 */ 831*1e091e43SHans Rosenfeld uint16_t ci_ddf_size; /* 0x786 */ 832*1e091e43SHans Rosenfeld uint8_t ci_max_lds_per_array; /* 0x788 */ 833*1e091e43SHans Rosenfeld uint8_t ci_partitions_in_DDF; /* 0x789 */ 834*1e091e43SHans Rosenfeld uint8_t ci_lock_key_binding; /* 0x78a */ 835*1e091e43SHans Rosenfeld uint8_t ci_max_PITs_per_ld; /* 0x78b */ 836*1e091e43SHans Rosenfeld uint8_t ci_max_views_per_ld; /* 0x78c */ 837*1e091e43SHans Rosenfeld uint8_t ci_max_target_id; /* 0x78d */ 838*1e091e43SHans Rosenfeld uint16_t ci_max_bvl_vd_size; /* 0x78e */ 839*1e091e43SHans Rosenfeld 840*1e091e43SHans Rosenfeld uint16_t ci_max_configurable_SSC_size; /* 0x790 */ 841*1e091e43SHans Rosenfeld uint16_t ci_current_SSC_size; /* 0x792 */ 842*1e091e43SHans Rosenfeld 843*1e091e43SHans Rosenfeld char ci_expander_fw_version[12]; /* 0x794 */ 844*1e091e43SHans Rosenfeld 845*1e091e43SHans Rosenfeld uint16_t ci_PFK_trial_time_remaining; /* 0x7A0 */ 846*1e091e43SHans Rosenfeld 847*1e091e43SHans Rosenfeld uint16_t ci_cache_memory_size; /* 0x7A2 */ 848*1e091e43SHans Rosenfeld 849*1e091e43SHans Rosenfeld struct { /* 0x7A4 */ 850*1e091e43SHans Rosenfeld uint32_t ao2_support_PI_controller:1; 851*1e091e43SHans Rosenfeld uint32_t ao2_support_ld_PI_type1:1; 852*1e091e43SHans Rosenfeld uint32_t ao2_support_ld_PI_type2:1; 853*1e091e43SHans Rosenfeld uint32_t ao2_support_ld_PI_type3:1; 854*1e091e43SHans Rosenfeld uint32_t ao2_support_ld_BBM_info:1; 855*1e091e43SHans Rosenfeld uint32_t ao2_support_shield_state:1; 856*1e091e43SHans Rosenfeld uint32_t ao2_block_SSD_write_cache_change:1; 857*1e091e43SHans Rosenfeld uint32_t ao2_support_suspend_resume_b_Gops:1; 858*1e091e43SHans Rosenfeld uint32_t ao2_support_emergency_spares:1; 859*1e091e43SHans Rosenfeld uint32_t ao2_support_set_link_speed:1; 860*1e091e43SHans Rosenfeld uint32_t ao2_support_boot_time_PFK_change:1; 861*1e091e43SHans Rosenfeld uint32_t ao2_support_JBOD:1; 862*1e091e43SHans Rosenfeld uint32_t ao2_disable_online_PFK_change:1; 863*1e091e43SHans Rosenfeld uint32_t ao2_support_perf_tuning:1; 864*1e091e43SHans Rosenfeld uint32_t ao2_support_SSD_patrol_read:1; 865*1e091e43SHans Rosenfeld uint32_t ao2_real_time_scheduler:1; 866*1e091e43SHans Rosenfeld 867*1e091e43SHans Rosenfeld uint32_t ao2_support_reset_now:1; 868*1e091e43SHans Rosenfeld uint32_t ao2_support_emulated_drives:1; 869*1e091e43SHans Rosenfeld uint32_t ao2_headless_mode:1; 870*1e091e43SHans Rosenfeld uint32_t ao2_dedicated_hot_spares_limited:1; 871*1e091e43SHans Rosenfeld 872*1e091e43SHans Rosenfeld uint32_t ao2_support_uneven_spans:1; 873*1e091e43SHans Rosenfeld uint32_t ao2_reserved:11; 874*1e091e43SHans Rosenfeld } ci_adapter_opts2; 875*1e091e43SHans Rosenfeld 876*1e091e43SHans Rosenfeld uint8_t ci_driver_version[32]; /* 0x7A8 */ 877*1e091e43SHans Rosenfeld uint8_t ci_max_DAP_d_count_spinup60; /* 0x7C8 */ 878*1e091e43SHans Rosenfeld uint8_t ci_temperature_ROC; /* 0x7C9 */ 879*1e091e43SHans Rosenfeld uint8_t ci_temperature_ctrl; /* 0x7CA */ 880*1e091e43SHans Rosenfeld uint8_t ci_reserved4; /* 0x7CB */ 881*1e091e43SHans Rosenfeld uint16_t ci_max_configurable_pds; /* 0x7CC */ 882*1e091e43SHans Rosenfeld 883*1e091e43SHans Rosenfeld uint8_t ci_reserved5[2]; /* 0x7CD reserved */ 884*1e091e43SHans Rosenfeld 885*1e091e43SHans Rosenfeld struct { 886*1e091e43SHans Rosenfeld uint32_t cl_peer_is_present:1; 887*1e091e43SHans Rosenfeld uint32_t cl_peer_is_incompatible:1; 888*1e091e43SHans Rosenfeld 889*1e091e43SHans Rosenfeld uint32_t cl_hw_incompatible:1; 890*1e091e43SHans Rosenfeld uint32_t cl_fw_version_mismatch:1; 891*1e091e43SHans Rosenfeld uint32_t cl_ctrl_prop_incompatible:1; 892*1e091e43SHans Rosenfeld uint32_t cl_premium_feature_mismatch:1; 893*1e091e43SHans Rosenfeld uint32_t cl_reserved:26; 894*1e091e43SHans Rosenfeld } ci_cluster; 895*1e091e43SHans Rosenfeld 896*1e091e43SHans Rosenfeld char ci_cluster_id[16]; /* 0x7D4 */ 897*1e091e43SHans Rosenfeld 898*1e091e43SHans Rosenfeld char ci_reserved6[4]; /* 0x7E4 RESERVED FOR IOV */ 899*1e091e43SHans Rosenfeld 900*1e091e43SHans Rosenfeld struct { /* 0x7E8 */ 901*1e091e43SHans Rosenfeld uint32_t ao3_support_personality_change:2; 902*1e091e43SHans Rosenfeld uint32_t ao3_support_thermal_poll_interval:1; 903*1e091e43SHans Rosenfeld uint32_t ao3_support_disable_immediate_IO:1; 904*1e091e43SHans Rosenfeld uint32_t ao3_support_T10_rebuild_assist:1; 905*1e091e43SHans Rosenfeld uint32_t ao3_support_max_ext_lds:1; 906*1e091e43SHans Rosenfeld uint32_t ao3_support_crash_dump:1; 907*1e091e43SHans Rosenfeld uint32_t ao3_support_sw_zone:1; 908*1e091e43SHans Rosenfeld uint32_t ao3_support_debug_queue:1; 909*1e091e43SHans Rosenfeld uint32_t ao3_support_NV_cache_erase:1; 910*1e091e43SHans Rosenfeld uint32_t ao3_support_force_to_512e:1; 911*1e091e43SHans Rosenfeld uint32_t ao3_support_HOQ_rebuild:1; 912*1e091e43SHans Rosenfeld uint32_t ao3_support_allowed_opsfor_drv_removal:1; 913*1e091e43SHans Rosenfeld uint32_t ao3_support_drv_activity_LED_setting:1; 914*1e091e43SHans Rosenfeld uint32_t ao3_support_NVDRAM:1; 915*1e091e43SHans Rosenfeld uint32_t ao3_support_force_flash:1; 916*1e091e43SHans Rosenfeld uint32_t ao3_support_disable_SES_monitoring:1; 917*1e091e43SHans Rosenfeld uint32_t ao3_support_cache_bypass_modes:1; 918*1e091e43SHans Rosenfeld uint32_t ao3_support_securityon_JBOD:1; 919*1e091e43SHans Rosenfeld uint32_t ao3_discard_cache_during_ld_delete:1; 920*1e091e43SHans Rosenfeld uint32_t ao3_support_TTY_log_compression:1; 921*1e091e43SHans Rosenfeld uint32_t ao3_support_CPLD_update:1; 922*1e091e43SHans Rosenfeld uint32_t ao3_support_disk_cache_setting_for_sys_pds:1; 923*1e091e43SHans Rosenfeld uint32_t ao3_support_extended_SSC_size:1; 924*1e091e43SHans Rosenfeld uint32_t ao3_use_seq_num_jbod_FP:1; 925*1e091e43SHans Rosenfeld uint32_t ao3_reserved:7; 926*1e091e43SHans Rosenfeld } ci_adapter_opts3; 927*1e091e43SHans Rosenfeld 928*1e091e43SHans Rosenfeld uint8_t ci_pad_cpld[16]; 929*1e091e43SHans Rosenfeld 930*1e091e43SHans Rosenfeld struct { 931*1e091e43SHans Rosenfeld uint16_t ao4_ctrl_info_ext_supported:1; 932*1e091e43SHans Rosenfeld uint16_t ao4_support_ibutton_less:1; 933*1e091e43SHans Rosenfeld uint16_t ao4_supported_enc_algo:1; 934*1e091e43SHans Rosenfeld uint16_t ao4_support_encrypted_mfc:1; 935*1e091e43SHans Rosenfeld uint16_t ao4_image_upload_supported:1; 936*1e091e43SHans Rosenfeld uint16_t ao4_support_SES_ctrl_in_multipath_cfg:1; 937*1e091e43SHans Rosenfeld uint16_t ao4_support_pd_map_target_id:1; 938*1e091e43SHans Rosenfeld uint16_t ao4_fw_swaps_bbu_vpd_info:1; 939*1e091e43SHans Rosenfeld uint16_t ao4_reserved:8; 940*1e091e43SHans Rosenfeld } ci_adapter_opts4; 941*1e091e43SHans Rosenfeld 942*1e091e43SHans Rosenfeld uint8_t ci_pad[0x800 - 0x7FE]; /* 0x7FE */ 943*1e091e43SHans Rosenfeld }; 944*1e091e43SHans Rosenfeld 945*1e091e43SHans Rosenfeld #pragma pack(0) 946*1e091e43SHans Rosenfeld 947*1e091e43SHans Rosenfeld /* 948*1e091e43SHans Rosenfeld * Request descriptor types, in addition to those defined by mpi2.h 949*1e091e43SHans Rosenfeld * 950*1e091e43SHans Rosenfeld * FreeBSD and Linux drivers shift these, while mpi2.h defines them 951*1e091e43SHans Rosenfeld * pre-shifted. The latter seems more sensible. 952*1e091e43SHans Rosenfeld * 953*1e091e43SHans Rosenfeld * XXX: LMRC_REQ_DESCRIPT_FLAGS_MFA has the same value as 954*1e091e43SHans Rosenfeld * MPI2_REQ_DESCRIPT_FLAGS_SCSI_TARGET. Why? 955*1e091e43SHans Rosenfeld */ 956*1e091e43SHans Rosenfeld #define LMRC_REQ_DESCRIPT_FLAGS_MFA 0x02 957*1e091e43SHans Rosenfeld #define LMRC_REQ_DESCRIPT_FLAGS_NO_LOCK 0x04 958*1e091e43SHans Rosenfeld #define LMRC_REQ_DESCRIPT_FLAGS_LD_IO 0x0e 959*1e091e43SHans Rosenfeld 960*1e091e43SHans Rosenfeld #define MPI2_TYPE_CUDA 0x2 961*1e091e43SHans Rosenfeld 962*1e091e43SHans Rosenfeld #endif /* _LMRC_REG_H */ 963