1 /* 2 * This file and its contents are supplied under the terms of the 3 * Common Development and Distribution License ("CDDL"), version 1.0. 4 * You may only use this file in accordance with the terms of version 5 * 1.0 of the CDDL. 6 * 7 * A full copy of the text of the CDDL should have accompanied this 8 * source. A copy of the CDDL is also available via the Internet at 9 * http://www.illumos.org/license/CDDL. 10 */ 11 12 /* 13 * Copyright 2023 Racktop Systems, Inc. 14 */ 15 #ifndef _LMRC_REG_H 16 #define _LMRC_REG_H 17 18 #include <sys/bitext.h> 19 #include <sys/debug.h> 20 #include <sys/stddef.h> 21 22 typedef struct lmrc_raid_mfa_io_req_desc lmrc_raid_mfa_io_req_desc_t; 23 typedef union lmrc_atomic_req_desc lmrc_atomic_req_desc_t; 24 typedef union lmrc_req_desc lmrc_req_desc_t; 25 26 typedef union lmrc_mfi_cap lmrc_mfi_cap_t; 27 typedef union lmrc_mfi_sgl lmrc_mfi_sgl_t; 28 typedef struct lmrc_mfi_header lmrc_mfi_header_t; 29 typedef struct lmrc_mfi_init_payload lmrc_mfi_init_payload_t; 30 typedef struct lmrc_mfi_io_payload lmrc_mfi_io_payload_t; 31 typedef struct lmrc_mfi_pthru_payload lmrc_mfi_pthru_payload_t; 32 typedef struct lmrc_mfi_dcmd_payload lmrc_mfi_dcmd_payload_t; 33 typedef struct lmrc_mfi_abort_payload lmrc_mfi_abort_payload_t; 34 typedef struct lmrc_mfi_frame lmrc_mfi_frame_t; 35 36 typedef struct lmrc_aen lmrc_aen_t; 37 typedef union lmrc_evt_class_locale lmrc_evt_class_locale_t; 38 typedef struct lmrc_evt_log_info lmrc_evt_log_info_t; 39 typedef struct lmrc_evtarg_ld lmrc_evtarg_ld_t; 40 typedef struct lmrc_evtarg_pd lmrc_evtarg_pd_t; 41 typedef struct lmrc_evt lmrc_evt_t; 42 43 typedef struct lmrc_ctrl_prop lmrc_ctrl_prop_t; 44 typedef struct lmrc_image_comp lmrc_image_comp_t; 45 typedef struct lmrc_ctrl_info lmrc_ctrl_info_t; 46 47 #include "lmrc_raid.h" 48 49 /* PCI device IDs of Gen 3.5 Controllers */ 50 #define LMRC_VENTURA 0x0014 51 #define LMRC_CRUSADER 0x0015 52 #define LMRC_HARPOON 0x0016 53 #define LMRC_TOMCAT 0x0017 54 #define LMRC_VENTURA_4PORT 0x001B 55 #define LMRC_CRUSADER_4PORT 0x001C 56 #define LMRC_AERO_10E0 0x10E0 57 #define LMRC_AERO_10E1 0x10E1 58 #define LMRC_AERO_10E2 0x10E2 59 #define LMRC_AERO_10E3 0x10E3 60 #define LMRC_AERO_10E4 0x10E4 61 #define LMRC_AERO_10E5 0x10E5 62 #define LMRC_AERO_10E6 0x10E6 63 #define LMRC_AERO_10E7 0x10E7 64 65 /* 66 * Message Frame Defines 67 */ 68 #define LMRC_SENSE_LEN 96 69 70 #define LMRC_MPI2_RAID_DEFAULT_IO_FRAME_SIZE 256 71 72 #define LMRC_SPECIFIC_MPI2_FUNCTION(x) \ 73 (MPI2_FUNCTION_MIN_PRODUCT_SPECIFIC + (x)) 74 #define LMRC_MPI2_FUNCTION_PASSTHRU_IO_REQUEST LMRC_SPECIFIC_MPI2_FUNCTION(0) 75 #define LMRC_MPI2_FUNCTION_LD_IO_REQUEST LMRC_SPECIFIC_MPI2_FUNCTION(1) 76 77 78 #define LMRC_MAX_MFI_CMDS 16 79 #define LMRC_MAX_IOCTL_CMDS 3 80 81 /* 82 * Firmware Status Register 83 * For Ventura and Aero controllers, this is outbound scratch pad register 0. 84 */ 85 #define LMRC_FW_RESET_REQUIRED(reg) (bitx32((reg), 0, 0) != 0) 86 #define LMRC_FW_RESET_ADAPTER(reg) (bitx32((reg), 1, 1) != 0) 87 #define LMRC_FW_MAX_CMD(reg) bitx32((reg), 15, 0) 88 #define LMRC_FW_MSIX_ENABLED(reg) (bitx32((reg), 26, 26) != 0) 89 #define LMRC_FW_STATE(reg) bitx32((reg), 31, 28) 90 91 /* outbound scratch pad register 1 */ 92 #define LMRC_MAX_CHAIN_SIZE(reg) bitx32((reg), 9, 5) 93 #define LMRC_MAX_REPLY_QUEUES_EXT(reg) bitx32((reg), 21, 14) 94 #define LMRC_EXT_CHAIN_SIZE_SUPPORT(reg) (bitx32((reg), 22, 22) != 0) 95 #define LMRC_RDPQ_MODE_SUPPORT(reg) (bitx32((reg), 23, 23) != 0) 96 #define LMRC_SYNC_CACHE_SUPPORT(reg) (bitx32((reg), 24, 24) != 0) 97 #define LMRC_ATOMIC_DESCRIPTOR_SUPPORT(reg) (bitx32((reg), 24, 24) != 0) 98 #define LMRC_64BIT_DMA_SUPPORT(reg) (bitx32((reg), 25, 25) != 0) 99 #define LMRC_INTR_COALESCING_SUPPORT(reg) (bitx32((reg), 26, 26) != 0) 100 101 #define LMRC_256K_IO 128 102 #define LMRC_1MB_IO (LMRC_256K_IO * 4) 103 104 /* outbound scratch pad register 2 */ 105 #define LMRC_MAX_RAID_MAP_SZ(reg) bitx32((reg), 24, 16) 106 107 /* outbound scratch pad register 3 */ 108 #define LMRC_NVME_PAGE_SHIFT(reg) bitx32((reg), 7, 0) 109 #define LMRC_DEFAULT_NVME_PAGE_SHIFT 12 110 111 /* 112 * Firmware Interface 113 * 114 * MFI stands for MegaRAID SAS FW Interface. This is just a moniker 115 * for the protocol between the software and the firmware. Commands are 116 * issued using "message frames". 117 */ 118 /* 119 * FW posts its state in the upper 4 bits of the status register, extracted 120 * with LMRC_FW_STATE(reg). 121 */ 122 #define LMRC_FW_STATE_UNDEFINED 0x0 123 #define LMRC_FW_STATE_BB_INIT 0x1 124 #define LMRC_FW_STATE_FW_INIT 0x4 125 #define LMRC_FW_STATE_WAIT_HANDSHAKE 0x6 126 #define LMRC_FW_STATE_FW_INIT_2 0x7 127 #define LMRC_FW_STATE_DEVICE_SCAN 0x8 128 #define LMRC_FW_STATE_BOOT_MSG_PENDING 0x9 129 #define LMRC_FW_STATE_FLUSH_CACHE 0xa 130 #define LMRC_FW_STATE_READY 0xb 131 #define LMRC_FW_STATE_OPERATIONAL 0xc 132 #define LMRC_FW_STATE_FAULT 0xf 133 134 /* 135 * During FW init, clear pending cmds & reset state using the doorbell register 136 * 137 * ABORT: Abort all pending cmds 138 * READY: Move from OPERATIONAL to READY state; discard queue info 139 * MFIMODE: Discard (possible) low MFA posted in 64-bit mode (??) 140 * CLEAR_HANDSHAKE: FW is waiting for HANDSHAKE from BIOS or Driver 141 * HOTPLUG: Resume from Hotplug 142 * MFI_STOP_ADP: Send signal to FW to stop processing 143 */ 144 #define MFI_INIT_ABORT 0x00000001 145 #define MFI_INIT_READY 0x00000002 146 #define MFI_INIT_MFIMODE 0x00000004 147 #define MFI_INIT_CLEAR_HANDSHAKE 0x00000008 148 #define MFI_INIT_HOTPLUG 0x00000010 149 #define MFI_STOP_ADP 0x00000020 150 #define MFI_RESET_FLAGS (MFI_INIT_READY|MFI_INIT_MFIMODE|MFI_INIT_ABORT) 151 152 /* 153 * MFI frame flags 154 */ 155 #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001 156 #define MFI_FRAME_SGL64 0x0002 157 #define MFI_FRAME_SENSE64 0x0004 158 #define MFI_FRAME_DIR_NONE 0 159 #define MFI_FRAME_DIR_WRITE 0x0008 160 #define MFI_FRAME_DIR_READ 0x0010 161 #define MFI_FRAME_DIR_BOTH 0x0018 162 #define MFI_FRAME_IEEE 0x0020 163 164 /* 165 * MFI command opcodes 166 */ 167 #define MFI_CMD_INIT 0x00 168 #define MFI_CMD_LD_READ 0x01 169 #define MFI_CMD_LD_WRITE 0x02 170 #define MFI_CMD_LD_SCSI_IO 0x03 171 #define MFI_CMD_PD_SCSI_IO 0x04 172 #define MFI_CMD_DCMD 0x05 173 #define MFI_CMD_ABORT 0x06 174 #define MFI_CMD_SMP 0x07 175 #define MFI_CMD_STP 0x08 176 #define MFI_CMD_INVALID 0xff 177 178 /* 179 * MFI command status completion codes 180 */ 181 #define MFI_STAT_OK 0x00 182 #define MFI_STAT_INVALID_CMD 0x01 183 #define MFI_STAT_INVALID_DCMD 0x02 184 #define MFI_STAT_INVALID_PARAMETER 0x03 185 #define MFI_STAT_INVALID_SEQUENCE_NUMBER 0x04 186 #define MFI_STAT_ABORT_NOT_POSSIBLE 0x05 187 #define MFI_STAT_APP_HOST_CODE_NOT_FOUND 0x06 188 #define MFI_STAT_APP_IN_USE 0x07 189 #define MFI_STAT_APP_NOT_INITIALIZED 0x08 190 #define MFI_STAT_ARRAY_INDEX_INVALID 0x09 191 #define MFI_STAT_ARRAY_ROW_NOT_EMPTY 0x0a 192 #define MFI_STAT_CONFIG_RESOURCE_CONFLICT 0x0b 193 #define MFI_STAT_DEVICE_NOT_FOUND 0x0c 194 #define MFI_STAT_DRIVE_TOO_SMALL 0x0d 195 #define MFI_STAT_FLASH_ALLOC_FAIL 0x0e 196 #define MFI_STAT_FLASH_BUSY 0x0f 197 #define MFI_STAT_FLASH_ERROR 0x10 198 #define MFI_STAT_FLASH_IMAGE_BAD 0x11 199 #define MFI_STAT_FLASH_IMAGE_INCOMPLETE 0x12 200 #define MFI_STAT_FLASH_NOT_OPEN 0x13 201 #define MFI_STAT_FLASH_NOT_STARTED 0x14 202 #define MFI_STAT_FLUSH_FAILED 0x15 203 #define MFI_STAT_HOST_CODE_NOT_FOUNT 0x16 204 #define MFI_STAT_LD_CC_IN_PROGRESS 0x17 205 #define MFI_STAT_LD_INIT_IN_PROGRESS 0x18 206 #define MFI_STAT_LD_LBA_OUT_OF_RANGE 0x19 207 #define MFI_STAT_LD_MAX_CONFIGURED 0x1a 208 #define MFI_STAT_LD_NOT_OPTIMAL 0x1b 209 #define MFI_STAT_LD_RBLD_IN_PROGRESS 0x1c 210 #define MFI_STAT_LD_RECON_IN_PROGRESS 0x1d 211 #define MFI_STAT_LD_WRONG_RAID_LEVEL 0x1e 212 #define MFI_STAT_MAX_SPARES_EXCEEDED 0x1f 213 #define MFI_STAT_MEMORY_NOT_AVAILABLE 0x20 214 #define MFI_STAT_MFC_HW_ERROR 0x21 215 #define MFI_STAT_NO_HW_PRESENT 0x22 216 #define MFI_STAT_NOT_FOUND 0x23 217 #define MFI_STAT_NOT_IN_ENCL 0x24 218 #define MFI_STAT_PD_CLEAR_IN_PROGRESS 0x25 219 #define MFI_STAT_PD_TYPE_WRONG 0x26 220 #define MFI_STAT_PR_DISABLED 0x27 221 #define MFI_STAT_ROW_INDEX_INVALID 0x28 222 #define MFI_STAT_SAS_CONFIG_INVALID_ACTION 0x29 223 #define MFI_STAT_SAS_CONFIG_INVALID_DATA 0x2a 224 #define MFI_STAT_SAS_CONFIG_INVALID_PAGE 0x2b 225 #define MFI_STAT_SAS_CONFIG_INVALID_TYPE 0x2c 226 #define MFI_STAT_SCSI_DONE_WITH_ERROR 0x2d 227 #define MFI_STAT_SCSI_IO_FAILED 0x2e 228 #define MFI_STAT_SCSI_RESERVATION_CONFLICT 0x2f 229 #define MFI_STAT_SHUTDOWN_FAILED 0x30 230 #define MFI_STAT_TIME_NOT_SET 0x31 231 #define MFI_STAT_WRONG_STATE 0x32 232 #define MFI_STAT_LD_OFFLINE 0x33 233 #define MFI_STAT_PEER_NOTIFICATION_REJECTED 0x34 234 #define MFI_STAT_PEER_NOTIFICATION_FAILED 0x35 235 #define MFI_STAT_RESERVATION_IN_PROGRESS 0x36 236 #define MFI_STAT_I2C_ERRORS_DETECTED 0x37 237 #define MFI_STAT_PCI_ERRORS_DETECTED 0x38 238 #define MFI_STAT_CONFIG_SEQ_MISMATCH 0x67 239 240 #define MFI_STAT_INVALID_STATUS 0xFF 241 242 /* 243 * MFI DCMDs 244 */ 245 #define LMRC_DCMD_CTRL_GET_INFO 0x01010000 246 #define LMRC_DCMD_CTRL_EVENT_GET_INFO 0x01040100 247 #define LMRC_DCMD_CTRL_EVENT_WAIT 0x01040500 248 #define LMRC_DCMD_CTRL_SHUTDOWN 0x01050000 249 #define LMRC_DCMD_PD_GET_INFO 0x02020000 250 #define LMRC_DCMD_PD_LIST_QUERY 0x02010100 251 #define LMRC_DCMD_SYSTEM_PD_MAP_GET_INFO 0x0200e102 252 #define LMRC_DCMD_LD_MAP_GET_INFO 0x0300e101 253 #define LMRC_DCMD_LD_GET_LIST 0x03010000 254 #define LMRC_DCMD_LD_LIST_QUERY 0x03010100 255 256 #define LMRC_PD_QUERY_TYPE_ALL 0 257 #define LMRC_PD_QUERY_TYPE_STATE 1 258 #define LMRC_PD_QUERY_TYPE_POWER_STATE 2 259 #define LMRC_PD_QUERY_TYPE_MEDIA_TYPE 3 260 #define LMRC_PD_QUERY_TYPE_SPEED 4 261 #define LMRC_PD_QUERY_TYPE_EXPOSED_TO_HOST 5 262 263 #define LMRC_LD_QUERY_TYPE_ALL 0 264 #define LMRC_LD_QUERY_TYPE_EXPOSED_TO_HOST 1 265 #define LMRC_LD_QUERY_TYPE_USED_TGT_IDS 2 266 #define LMRC_LD_QUERY_TYPE_CLUSTER_ACCESS 3 267 #define LMRC_LD_QUERY_TYPE_CLUSTER_LOCALE 4 268 269 #define LMRC_DCMD_MBOX_PEND_FLAG 0x01 270 271 #define LMRC_MAX_PD_CHANNELS 1 272 #define LMRC_MAX_LD_CHANNELS 1 273 #define LMRC_MAX_DEV_PER_CHANNEL 256 274 #define LMRC_MAX_PD \ 275 (LMRC_MAX_PD_CHANNELS * LMRC_MAX_DEV_PER_CHANNEL) 276 #define LMRC_MAX_LD \ 277 (LMRC_MAX_LD_CHANNELS * LMRC_MAX_DEV_PER_CHANNEL) 278 #define LMRC_MAX_TM_TARGETS (LMRC_MAX_PD + LMRC_MAX_LD) 279 280 #define LMRC_DEFAULT_INIT_ID -1 281 #define LMRC_MAX_LUN 8 282 #define LMRC_DEFAULT_CMD_PER_LUN 256 283 284 #define LMRC_MAX_REPLY_POST_HOST_INDEX 16 285 286 287 /* By default, the firmware programs for 8k of memory */ 288 #define LMRC_MFI_MIN_MEM 4096 289 #define LMRC_MFI_DEF_MEM 8192 290 #define LMRC_MFI_MAX_CMD 16 291 292 293 #pragma pack(1) 294 295 /* 296 * MPT RAID MFA IO Descriptor. 297 * 298 * Note: The use of the lowest 8 bits for flags implies that an alignment 299 * of 256 bytes is required for the physical address. 300 */ 301 struct lmrc_raid_mfa_io_req_desc { 302 uint32_t RequestFlags:8; 303 uint32_t MessageAddress1:24; /* bits 31:8 */ 304 uint32_t MessageAddress2; /* bits 61:32 */ 305 }; 306 307 /* 308 * unions of Request Descriptors 309 */ 310 union lmrc_atomic_req_desc { 311 Mpi26AtomicRequestDescriptor_t rd_atomic; 312 uint32_t rd_reg; 313 }; 314 315 union lmrc_req_desc { 316 uint64_t rd_reg; 317 318 struct { 319 uint32_t rd_reg_lo; 320 uint32_t rd_reg_hi; 321 }; 322 323 lmrc_atomic_req_desc_t rd_atomic; 324 lmrc_raid_mfa_io_req_desc_t rd_mfa_io; 325 }; 326 327 328 union lmrc_mfi_cap { 329 struct { 330 uint32_t mc_support_fp_remote_lun:1; 331 uint32_t mc_support_additional_msix:1; 332 uint32_t mc_support_fastpath_wb:1; 333 uint32_t mc_support_max_255lds:1; 334 uint32_t mc_support_ndrive_r1_lb:1; 335 uint32_t mc_support_core_affinity:1; 336 uint32_t mc_support_security_protocol_cmds_fw:1; 337 uint32_t mc_support_ext_queue_depth:1; 338 uint32_t mc_support_ext_io_size:1; 339 uint32_t mc_reserved:23; 340 }; 341 uint32_t mc_reg; 342 }; 343 CTASSERT(sizeof (lmrc_mfi_cap_t) == 4); 344 345 union lmrc_mfi_sgl { 346 struct { 347 uint32_t ms32_phys_addr; 348 uint32_t ms32_length; 349 }; 350 struct { 351 uint64_t ms64_phys_addr; 352 uint32_t ms64_length; 353 }; 354 }; 355 356 struct lmrc_mfi_header { 357 uint8_t mh_cmd; /* 0x00 */ 358 uint8_t mh_sense_len; /* 0x01 */ 359 uint8_t mh_cmd_status; /* 0x02 */ 360 uint8_t mh_scsi_status; /* 0x03 */ 361 362 union { 363 lmrc_mfi_cap_t mh_drv_opts; /* 0x04 */ 364 struct { 365 uint8_t mh_target_id; /* 0x04 */ 366 union { 367 uint8_t mh_lun; /* 0x05 */ 368 uint8_t mh_access_byte; /* 0x05 */ 369 }; 370 uint8_t mh_cdb_len; /* 0x06 */ 371 uint8_t mh_sge_count; /* 0x07 */ 372 }; 373 }; 374 375 uint32_t mh_context; /* 0x08 */ 376 uint32_t mh_pad_0; /* 0x0c */ 377 378 uint16_t mh_flags; /* 0x10 */ 379 uint16_t mh_timeout; /* 0x12 */ 380 union { 381 uint32_t mh_data_xfer_len; /* 0x14 */ 382 uint32_t mh_lba_count; /* 0x14 */ 383 }; 384 }; 385 386 struct lmrc_mfi_init_payload { 387 uint64_t mi_queue_info_new_phys_addr; /* 0x18 */ 388 uint64_t mi_queue_info_old_phys_addr; /* 0x20 */ 389 uint64_t mi_driver_ver_phys_addr; /* 0x28 */ 390 }; 391 392 struct lmrc_mfi_io_payload { 393 uint64_t mio_sense_buf_phys_addr; /* 0x18 */ 394 uint64_t mio_start_lba; /* 0x20 */ 395 lmrc_mfi_sgl_t mio_sgl; /* 0x28 */ 396 }; 397 398 struct lmrc_mfi_pthru_payload { 399 uint64_t mp_sense_buf_phys_addr; /* 0x18 */ 400 uint8_t mp_cdb[16]; /* 0x20 */ 401 lmrc_mfi_sgl_t mp_sgl; /* 0x30 */ 402 }; 403 404 struct lmrc_mfi_dcmd_payload { 405 uint32_t md_opcode; /* 0x18 */ 406 407 union { /* 0x1c */ 408 uint8_t md_mbox_8[12]; 409 uint16_t md_mbox_16[6]; 410 uint32_t md_mbox_32[3]; 411 }; 412 413 lmrc_mfi_sgl_t md_sgl; /* 0x28 */ 414 }; 415 416 struct lmrc_mfi_abort_payload { 417 uint32_t ma_abort_context; /* 0x18 */ 418 uint32_t ma_pad_1; /* 0x1c */ 419 uint64_t ma_abort_mfi_phys_addr; /* 0x20 */ 420 }; 421 422 struct lmrc_mfi_frame { 423 lmrc_mfi_header_t mf_hdr; 424 union { 425 lmrc_mfi_init_payload_t mf_init; 426 lmrc_mfi_io_payload_t mf_io; 427 lmrc_mfi_pthru_payload_t mf_pthru; 428 lmrc_mfi_dcmd_payload_t mf_dcmd; 429 lmrc_mfi_abort_payload_t mf_abort; 430 uint8_t mf_raw[64 - sizeof (lmrc_mfi_header_t)]; 431 }; 432 }; 433 CTASSERT(offsetof(lmrc_mfi_frame_t, mf_init) == 0x18); 434 CTASSERT(sizeof (lmrc_mfi_frame_t) == 64); 435 436 struct lmrc_aen { 437 uint16_t aen_host_no; 438 uint16_t aen_cmd_status; 439 uint32_t aen_seqnum; 440 uint32_t aen_class_locale_word; 441 }; 442 443 /* 444 * Asynchronous Event Notifications 445 */ 446 #define LMRC_EVT_CFG_CLEARED 0x0004 447 #define LMRC_EVT_CTRL_PATROL_READ_COMPLETE 0x0023 448 #define LMRC_EVT_CTRL_PATROL_READ_RESUMED 0x0026 449 #define LMRC_EVT_CTRL_PATROL_READ_START 0x0027 450 #define LMRC_EVT_LD_BG_INIT_PROGRESS 0x0034 451 #define LMRC_EVT_LD_CC_COMPLETE 0x003a 452 #define LMRC_EVT_LD_CC_PROGRESS 0x0041 453 #define LMRC_EVT_LD_CC_STARTED 0x0042 454 #define LMRC_EVT_LD_INIT_ABORTED 0x0043 455 #define LMRC_EVT_LD_INIT_PROGRESS 0x0045 456 #define LMRC_EVT_LD_FAST_INIT_STARTED 0x0046 457 #define LMRC_EVT_LD_FULL_INIT_STARTED 0x0047 458 #define LMRC_EVT_LD_INIT_COMPLETE 0x0048 459 #define LMRC_EVT_LD_PROP_CHANGED 0x0049 460 #define LMRC_EVT_LD_STATE_CHANGE 0x0051 461 #define LMRC_EVT_PD_INSERTED 0x005b 462 #define LMRC_EVT_PD_PATROL_READ_PROGRESS 0x005e 463 #define LMRC_EVT_PD_REMOVED 0x0070 464 #define LMRC_EVT_PD_CHANGED 0x0072 465 #define LMRC_EVT_LD_CREATED 0x008a 466 #define LMRC_EVT_LD_DELETED 0x008b 467 #define LMRC_EVT_FOREIGN_CFG_IMPORTED 0x00db 468 #define LMRC_EVT_LD_OPTIMAL 0x00f9 469 #define LMRC_EVT_LD_OFFLINE 0x00fc 470 #define LMRC_EVT_PD_RESET 0x010c 471 #define LMRC_EVT_CTRL_PATROL_READ_CANT_START 0x0124 472 #define LMRC_EVT_CTRL_PROP_CHANGED 0x012f 473 #define LMRC_EVT_LD_BBT_CLEARED 0x014f 474 #define LMRC_EVT_CTRL_HOST_BUS_SCAN_REQD 0x0152 475 #define LMRC_EVT_LD_AVAILABLE 0x0172 476 #define LMRC_EVT_CTRL_PERF_COLLECTION 0x017e 477 #define LMRC_EVT_CTRL_BOOTDEV_SET 0x01ec 478 #define LMRC_EVT_CTRL_BOOTDEV_RESET 0x01f3 479 #define LMRC_EVT_CTRL_PERSONALITY_CHANGE 0x0206 480 #define LMRC_EVT_CTRL_PERSONALITY_CHANGE_PEND 0x0222 481 #define LMRC_EVT_CTRL_NR_OF_VALID_SNAPDUMP 0x024e 482 483 #define LMRC_EVT_CLASS_DEBUG -2 484 #define LMRC_EVT_CLASS_PROGRESS -1 485 #define LMRC_EVT_CLASS_INFO 0 486 #define LMRC_EVT_CLASS_WARNING 1 487 #define LMRC_EVT_CLASS_CRITICAL 2 488 #define LMRC_EVT_CLASS_FATAL 3 489 #define LMRC_EVT_CLASS_DEAD 4 490 491 #define LMRC_EVT_LOCALE_LD 0x0001 492 #define LMRC_EVT_LOCALE_PD 0x0002 493 #define LMRC_EVT_LOCALE_ENCL 0x0004 494 #define LMRC_EVT_LOCALE_BBU 0x0008 495 #define LMRC_EVT_LOCALE_SAS 0x0010 496 #define LMRC_EVT_LOCALE_CTRL 0x0020 497 #define LMRC_EVT_LOCALE_CONFIG 0x0040 498 #define LMRC_EVT_LOCALE_CLUSTER 0x0080 499 #define LMRC_EVT_LOCALE_ALL 0xffff 500 501 union lmrc_evt_class_locale { 502 struct { 503 uint16_t ecl_locale; 504 uint8_t ecl_rsvd; 505 int8_t ecl_class; 506 }; 507 uint32_t ecl_word; 508 }; 509 510 struct lmrc_evt_log_info { 511 uint32_t eli_newest_seqnum; 512 uint32_t eli_oldest_seqnum; 513 uint32_t eli_clear_seqnum; 514 uint32_t eli_shutdown_seqnum; 515 uint32_t eli_boot_seqnum; 516 }; 517 518 struct lmrc_evtarg_ld { 519 uint16_t el_tgtid; 520 uint8_t el_ld_id; 521 uint8_t el_rsvd; 522 }; 523 524 struct lmrc_evtarg_pd { 525 uint16_t ep_dev_id; 526 uint8_t ep_enc_id; 527 uint8_t ep_slot; 528 }; 529 530 struct lmrc_evt { 531 uint32_t evt_seqnum; 532 uint32_t evt_timestamp; 533 uint32_t evt_code; 534 uint16_t evt_locale; 535 uint8_t evt_rsvd; 536 int8_t evt_class; 537 uint8_t evt_argtype; 538 uint8_t evt_rsvd2[15]; 539 union { 540 lmrc_evtarg_ld_t evt_ld; 541 lmrc_evtarg_pd_t evt_pd; 542 char evt_str[96]; 543 }; 544 char evt_descr[128]; 545 }; 546 CTASSERT(sizeof (lmrc_evt_t) == 256); 547 548 /* 549 * SAS controller properties 550 */ 551 struct lmrc_ctrl_prop { 552 uint16_t cp_seq_num; 553 uint16_t cp_pred_fail_poll_interval; 554 uint16_t cp_intr_throttle_count; 555 uint16_t cp_intr_throttle_timeouts; 556 uint8_t cp_rebuild_rate; 557 uint8_t cp_patrol_read_rate; 558 uint8_t cp_bgi_rate; 559 uint8_t cp_cc_rate; 560 uint8_t cp_recon_rate; 561 uint8_t cp_cache_flush_interval; 562 uint8_t cp_spinup_drv_count; 563 uint8_t cp_spinup_delay; 564 uint8_t cp_cluster_enable; 565 uint8_t cp_coercion_mode; 566 uint8_t cp_alarm_enable; 567 uint8_t cp_disable_auto_rebuild; 568 uint8_t cp_disable_battery_warn; 569 uint8_t cp_ecc_bucket_size; 570 uint16_t cp_ecc_bucket_leak_rate; 571 uint8_t cp_restore_hotspare_on_insertion; 572 uint8_t cp_expose_encl_devices; 573 uint8_t cp_maintain_pd_fail_history; 574 uint8_t cp_disallow_host_request_reordering; 575 uint8_t cp_abort_cc_on_error; 576 uint8_t cp_load_balance_mode; 577 uint8_t cp_disable_auto_detect_backplane; 578 uint8_t cp_snap_vd_space; 579 580 struct { 581 uint32_t cp_copy_back_disabled:1; 582 uint32_t cp_smarter_enabled:1; 583 uint32_t cp_pr_correct_unconfigured_areas:1; 584 uint32_t cp_use_FDE_only:1; 585 uint32_t cp_disable_NCQ:1; 586 uint32_t cp_SSD_smarter_enabled:1; 587 uint32_t cp_SSD_patrol_read_enabled:1; 588 uint32_t cp_enable_spin_down_unconfigured:1; 589 uint32_t cp_auto_enhanced_import:1; 590 uint32_t cp_enable_secret_key_control:1; 591 uint32_t cp_disable_online_ctrl_reset:1; 592 uint32_t cp_allow_boot_with_pinned_cache:1; 593 uint32_t cp_disable_spin_down_HS:1; 594 uint32_t cp_enable_JBOD:1; 595 uint32_t cp_disable_cache_bypass:1; 596 uint32_t cp_use_disk_activity_for_locate:1; 597 uint32_t cp_enable_PI:1; 598 uint32_t cp_prevent_PI_import:1; 599 uint32_t cp_use_global_spares_for_emergency:1; 600 uint32_t cp_use_unconf_good_for_emergency:1; 601 uint32_t cp_use_emergency_spares_for_smarter:1; 602 uint32_t cp_force_sgpio_for_quad_only:1; 603 uint32_t cp_enable_config_auto_balance:1; 604 uint32_t cp_enable_virtual_cache:1; 605 uint32_t cp_enable_auto_lock_recovery:1; 606 uint32_t cp_disable_immediate_io:1; 607 uint32_t cp_disable_T10_rebuild_assist:1; 608 uint32_t cp_ignore64_ld_restriction:1; 609 uint32_t cp_enable_sw_zone:1; 610 uint32_t cp_limit_max_rate_SATA_3G:1; 611 uint32_t cp_reserved:2; 612 }; 613 uint8_t cp_auto_snap_vd_space; 614 uint8_t cp_view_space; 615 uint16_t cp_spin_down_time; 616 uint8_t cp_reserved2[24]; 617 }; 618 619 struct lmrc_image_comp { 620 char ic_name[8]; 621 char ic_version[32]; 622 char ic_build_date[16]; 623 char ic_built_time[16]; 624 }; 625 626 /* 627 * SAS controller information 628 */ 629 struct lmrc_ctrl_info { 630 /* PCI device information */ 631 struct { 632 uint16_t pci_vendor_id; 633 uint16_t pci_device_id; 634 uint16_t pci_sub_vendor_id; 635 uint16_t pci_sub_device_id; 636 uint8_t pci_reserved[24]; 637 } ci_pci; 638 639 /* Host interface information */ 640 struct { 641 uint8_t hi_PCIX:1; 642 uint8_t hi_PCIE:1; 643 uint8_t hi_iSCSI:1; 644 uint8_t hi_SAS_3G:1; 645 uint8_t hi_reserved_0:4; 646 uint8_t hi_reserved_1[6]; 647 uint8_t hi_port_count; 648 uint64_t hi_port_addr[8]; 649 } ci_host_interface; 650 651 /* Target interface information */ 652 struct { 653 uint8_t di_SPI:1; 654 uint8_t di_SAS_3G:1; 655 uint8_t di_SATA_1_5G:1; 656 uint8_t di_SATA_3G:1; 657 uint8_t di_reserved_0:4; 658 uint8_t di_reserved_1[6]; 659 uint8_t di_port_count; 660 uint64_t di_port_addr[8]; 661 } ci_device_interface; 662 663 uint32_t ci_image_check_word; 664 665 uint32_t ci_image_component_count; 666 lmrc_image_comp_t ci_image_component[8]; 667 668 uint32_t ci_pending_image_component_count; 669 lmrc_image_comp_t ci_pending_image_component[8]; 670 671 uint8_t ci_max_arms; 672 uint8_t ci_max_spans; 673 uint8_t ci_max_arrays; 674 uint8_t ci_max_lds; 675 char ci_product_name[80]; 676 char ci_serial_no[32]; 677 678 /* 679 * Hardware features 680 */ 681 struct { 682 uint32_t hw_bbu:1; 683 uint32_t hw_alarm:1; 684 uint32_t hw_nvram:1; 685 uint32_t hw_uart:1; 686 uint32_t hw_reserved:28; 687 } ci_hw_present; 688 689 uint32_t current_fw_time; 690 691 /* Maximum data transfer sizes */ 692 uint16_t ci_max_concurrent_cmds; 693 uint16_t ci_max_sge_count; 694 uint32_t ci_max_request_size; 695 696 /* Logical and physical device counts */ 697 uint16_t ci_ld_present_count; 698 uint16_t ci_ld_degraded_count; 699 uint16_t ci_ld_offline_count; 700 701 uint16_t ci_pd_present_count; 702 uint16_t ci_pd_disk_present_count; 703 uint16_t ci_pd_disk_pred_failure_count; 704 uint16_t ci_pd_disk_failed_count; 705 706 /* Memory size information */ 707 uint16_t ci_nvram_size; 708 uint16_t ci_memory_size; 709 uint16_t ci_flash_size; 710 711 /* Error counters */ 712 uint16_t ci_mem_correctable_error_count; 713 uint16_t ci_mem_uncorrectable_error_count; 714 715 /* Cluster information */ 716 uint8_t ci_cluster_permitted; 717 uint8_t ci_cluster_active; 718 719 /* Additional max data transfer sizes */ 720 uint16_t ci_max_stripes_per_io; 721 722 /* Controller capabilities structures */ 723 struct { 724 uint32_t rl_raid_level_0:1; 725 uint32_t rl_raid_level_1:1; 726 uint32_t rl_raid_level_5:1; 727 uint32_t rl_raid_level_1E:1; 728 uint32_t rl_raid_level_6:1; 729 uint32_t rl_reserved:27; 730 } ci_raid_levels; 731 732 struct { 733 uint32_t ao_rbld_rate:1; 734 uint32_t ao_cc_rate:1; 735 uint32_t ao_bgi_rate:1; 736 uint32_t ao_recon_rate:1; 737 uint32_t ao_patrol_rate:1; 738 uint32_t ao_alarm_control:1; 739 uint32_t ao_cluster_supported:1; 740 uint32_t ao_bbu:1; 741 uint32_t ao_spanning_allowed:1; 742 uint32_t ao_dedicated_hotspares:1; 743 uint32_t ao_revertible_hotspares:1; 744 uint32_t ao_foreign_config_import:1; 745 uint32_t ao_self_diagnostic:1; 746 uint32_t ao_mixed_redundancy_arr:1; 747 uint32_t ao_global_hot_spares:1; 748 uint32_t ao_reserved:17; 749 } ci_adapter_opts; 750 751 struct { 752 uint32_t ld_read_policy:1; 753 uint32_t ld_write_policy:1; 754 uint32_t ld_io_policy:1; 755 uint32_t ld_access_policy:1; 756 uint32_t ld_disk_cache_policy:1; 757 uint32_t ld_reserved:27; 758 } ci_ld_opts; 759 760 struct { 761 uint8_t raid_stripe_sz_min; 762 uint8_t raid_stripe_sz_max; 763 uint8_t raid_reserved[2]; 764 } ci_raid_opts; 765 766 struct { 767 uint32_t pd_force_online:1; 768 uint32_t pd_force_offline:1; 769 uint32_t pd_force_rebuild:1; 770 uint32_t pd_reserved:29; 771 } ci_pd_opts; 772 773 struct { 774 uint32_t pd_ctrl_supports_sas:1; 775 uint32_t pd_ctrl_supports_sata:1; 776 uint32_t pd_allow_mix_in_encl:1; 777 uint32_t pd_allow_mix_in_ld:1; 778 uint32_t pd_allow_sata_in_cluster:1; 779 uint32_t pd_reserved:27; 780 } ci_pd_mix_support; 781 782 /* ECC single-bit error bucket information */ 783 uint8_t ci_ecc_bucket_count; 784 uint8_t ci_reserved_2[11]; 785 786 /* Controller properties */ 787 lmrc_ctrl_prop_t ci_prop; 788 789 char ci_package_version[0x60]; 790 791 uint64_t ci_device_interface_port_addr2[8]; 792 uint8_t ci_reserved3[128]; 793 794 struct { 795 uint16_t pd_min_pd_raid_level_0:4; 796 uint16_t pd_max_pd_raid_level_0:12; 797 798 uint16_t pd_min_pd_raid_level_1:4; 799 uint16_t pd_max_pd_raid_level_1:12; 800 801 uint16_t pd_min_pd_raid_level_5:4; 802 uint16_t pd_max_pd_raid_level_5:12; 803 804 uint16_t pd_min_pd_raid_level_1E:4; 805 uint16_t pd_max_pd_raid_level_1E:12; 806 807 uint16_t pd_min_pd_raid_level_6:4; 808 uint16_t pd_max_pd_raid_level_6:12; 809 810 uint16_t pd_min_pd_raid_level_10:4; 811 uint16_t pd_max_pd_raid_level_10:12; 812 813 uint16_t pd_min_pd_raid_level_50:4; 814 uint16_t pd_max_pd_raid_level_50:12; 815 816 uint16_t pd_min_pd_raid_level_60:4; 817 uint16_t pd_max_pd_raid_level_60:12; 818 819 uint16_t pd_min_pd_raid_level_1E_RLQ0:4; 820 uint16_t pd_max_pd_raid_level_1E_RLQ0:12; 821 822 uint16_t pd_min_pd_raid_level_1E0_RLQ0:4; 823 uint16_t pd_max_pd_raid_level_1E0_RLQ0:12; 824 825 uint16_t pd_reserved[6]; 826 } ci_pds_for_raid_levels; 827 828 uint16_t ci_max_pds; /* 0x780 */ 829 uint16_t ci_max_ded_HSPs; /* 0x782 */ 830 uint16_t ci_max_global_HSPs; /* 0x784 */ 831 uint16_t ci_ddf_size; /* 0x786 */ 832 uint8_t ci_max_lds_per_array; /* 0x788 */ 833 uint8_t ci_partitions_in_DDF; /* 0x789 */ 834 uint8_t ci_lock_key_binding; /* 0x78a */ 835 uint8_t ci_max_PITs_per_ld; /* 0x78b */ 836 uint8_t ci_max_views_per_ld; /* 0x78c */ 837 uint8_t ci_max_target_id; /* 0x78d */ 838 uint16_t ci_max_bvl_vd_size; /* 0x78e */ 839 840 uint16_t ci_max_configurable_SSC_size; /* 0x790 */ 841 uint16_t ci_current_SSC_size; /* 0x792 */ 842 843 char ci_expander_fw_version[12]; /* 0x794 */ 844 845 uint16_t ci_PFK_trial_time_remaining; /* 0x7A0 */ 846 847 uint16_t ci_cache_memory_size; /* 0x7A2 */ 848 849 struct { /* 0x7A4 */ 850 uint32_t ao2_support_PI_controller:1; 851 uint32_t ao2_support_ld_PI_type1:1; 852 uint32_t ao2_support_ld_PI_type2:1; 853 uint32_t ao2_support_ld_PI_type3:1; 854 uint32_t ao2_support_ld_BBM_info:1; 855 uint32_t ao2_support_shield_state:1; 856 uint32_t ao2_block_SSD_write_cache_change:1; 857 uint32_t ao2_support_suspend_resume_b_Gops:1; 858 uint32_t ao2_support_emergency_spares:1; 859 uint32_t ao2_support_set_link_speed:1; 860 uint32_t ao2_support_boot_time_PFK_change:1; 861 uint32_t ao2_support_JBOD:1; 862 uint32_t ao2_disable_online_PFK_change:1; 863 uint32_t ao2_support_perf_tuning:1; 864 uint32_t ao2_support_SSD_patrol_read:1; 865 uint32_t ao2_real_time_scheduler:1; 866 867 uint32_t ao2_support_reset_now:1; 868 uint32_t ao2_support_emulated_drives:1; 869 uint32_t ao2_headless_mode:1; 870 uint32_t ao2_dedicated_hot_spares_limited:1; 871 872 uint32_t ao2_support_uneven_spans:1; 873 uint32_t ao2_reserved:11; 874 } ci_adapter_opts2; 875 876 uint8_t ci_driver_version[32]; /* 0x7A8 */ 877 uint8_t ci_max_DAP_d_count_spinup60; /* 0x7C8 */ 878 uint8_t ci_temperature_ROC; /* 0x7C9 */ 879 uint8_t ci_temperature_ctrl; /* 0x7CA */ 880 uint8_t ci_reserved4; /* 0x7CB */ 881 uint16_t ci_max_configurable_pds; /* 0x7CC */ 882 883 uint8_t ci_reserved5[2]; /* 0x7CD reserved */ 884 885 struct { 886 uint32_t cl_peer_is_present:1; 887 uint32_t cl_peer_is_incompatible:1; 888 889 uint32_t cl_hw_incompatible:1; 890 uint32_t cl_fw_version_mismatch:1; 891 uint32_t cl_ctrl_prop_incompatible:1; 892 uint32_t cl_premium_feature_mismatch:1; 893 uint32_t cl_reserved:26; 894 } ci_cluster; 895 896 char ci_cluster_id[16]; /* 0x7D4 */ 897 898 char ci_reserved6[4]; /* 0x7E4 RESERVED FOR IOV */ 899 900 struct { /* 0x7E8 */ 901 uint32_t ao3_support_personality_change:2; 902 uint32_t ao3_support_thermal_poll_interval:1; 903 uint32_t ao3_support_disable_immediate_IO:1; 904 uint32_t ao3_support_T10_rebuild_assist:1; 905 uint32_t ao3_support_max_ext_lds:1; 906 uint32_t ao3_support_crash_dump:1; 907 uint32_t ao3_support_sw_zone:1; 908 uint32_t ao3_support_debug_queue:1; 909 uint32_t ao3_support_NV_cache_erase:1; 910 uint32_t ao3_support_force_to_512e:1; 911 uint32_t ao3_support_HOQ_rebuild:1; 912 uint32_t ao3_support_allowed_opsfor_drv_removal:1; 913 uint32_t ao3_support_drv_activity_LED_setting:1; 914 uint32_t ao3_support_NVDRAM:1; 915 uint32_t ao3_support_force_flash:1; 916 uint32_t ao3_support_disable_SES_monitoring:1; 917 uint32_t ao3_support_cache_bypass_modes:1; 918 uint32_t ao3_support_securityon_JBOD:1; 919 uint32_t ao3_discard_cache_during_ld_delete:1; 920 uint32_t ao3_support_TTY_log_compression:1; 921 uint32_t ao3_support_CPLD_update:1; 922 uint32_t ao3_support_disk_cache_setting_for_sys_pds:1; 923 uint32_t ao3_support_extended_SSC_size:1; 924 uint32_t ao3_use_seq_num_jbod_FP:1; 925 uint32_t ao3_reserved:7; 926 } ci_adapter_opts3; 927 928 uint8_t ci_pad_cpld[16]; 929 930 struct { 931 uint16_t ao4_ctrl_info_ext_supported:1; 932 uint16_t ao4_support_ibutton_less:1; 933 uint16_t ao4_supported_enc_algo:1; 934 uint16_t ao4_support_encrypted_mfc:1; 935 uint16_t ao4_image_upload_supported:1; 936 uint16_t ao4_support_SES_ctrl_in_multipath_cfg:1; 937 uint16_t ao4_support_pd_map_target_id:1; 938 uint16_t ao4_fw_swaps_bbu_vpd_info:1; 939 uint16_t ao4_reserved:8; 940 } ci_adapter_opts4; 941 942 uint8_t ci_pad[0x800 - 0x7FE]; /* 0x7FE */ 943 }; 944 945 #pragma pack(0) 946 947 /* 948 * Request descriptor types, in addition to those defined by mpi2.h 949 * 950 * FreeBSD and Linux drivers shift these, while mpi2.h defines them 951 * pre-shifted. The latter seems more sensible. 952 * 953 * XXX: LMRC_REQ_DESCRIPT_FLAGS_MFA has the same value as 954 * MPI2_REQ_DESCRIPT_FLAGS_SCSI_TARGET. Why? 955 */ 956 #define LMRC_REQ_DESCRIPT_FLAGS_MFA 0x02 957 #define LMRC_REQ_DESCRIPT_FLAGS_NO_LOCK 0x04 958 #define LMRC_REQ_DESCRIPT_FLAGS_LD_IO 0x0e 959 960 #define MPI2_TYPE_CUDA 0x2 961 962 #endif /* _LMRC_REG_H */ 963