1 /* 2 * This file and its contents are supplied under the terms of the 3 * Common Development and Distribution License ("CDDL"), version 1.0. 4 * You may only use this file in accordance with the terms of version 5 * 1.0 of the CDDL. 6 * 7 * A full copy of the text of the CDDL should have accompanied this 8 * source. A copy of the CDDL is also available via the Internet at 9 * http://www.illumos.org/license/CDDL. 10 */ 11 12 /* 13 * Copyright 2023 Racktop Systems, Inc. 14 */ 15 16 #ifndef _LMRC_PHYS_H 17 #define _LMRC_PHYS_H 18 19 #include <sys/types.h> 20 #include <sys/debug.h> 21 22 typedef struct lmrc_pd_info lmrc_pd_info_t; 23 typedef struct lmrc_pd_cfg lmrc_pd_cfg_t; 24 typedef struct lmrc_pd_map lmrc_pd_map_t; 25 typedef struct lmrc_pd_addr lmrc_pd_addr_t; 26 typedef struct lmrc_pd_list lmrc_pd_list_t; 27 28 #include "lmrc.h" 29 #include "lmrc_raid.h" 30 31 #pragma pack(1) 32 33 /* 34 * PD info 35 */ 36 struct lmrc_pd_info { 37 uint16_t pd_dev_id; 38 uint16_t pd_seqnum; 39 uint8_t pd_inq[96]; 40 uint8_t pd_vpd83[64]; 41 uint8_t pd_notsup; 42 uint8_t pd_scsi_dev_type; 43 44 union { 45 uint8_t pd_conn_port_bitmap; 46 uint8_t pd_conn_port_num; 47 }; 48 49 uint8_t pd_dev_speed; 50 uint32_t pd_media_err_cnt; 51 uint32_t pd_other_err_cnt; 52 uint32_t pd_pred_fail_cnt; 53 uint32_t pd_last_pred_fail_evt_seqnum; 54 55 uint16_t pd_fw_state; 56 uint8_t pd_disabled_for_removal; 57 uint8_t pd_link_speed; 58 59 struct { 60 uint32_t pd_forced_pd_guid:1; 61 uint32_t pd_in_vd:1; 62 uint32_t pd_is_global_spare:1; 63 uint32_t pd_is_spare:1; 64 uint32_t pd_is_foreign:1; 65 uint32_t pd_rsvd:7; 66 uint32_t pd_intf:4; 67 uint32_t pd_rsvd2:16; 68 } pd_ddf_type; 69 70 struct { 71 uint8_t pi_count; 72 uint8_t pi_path_broken:4; 73 uint8_t pi_rsvd:3; 74 uint8_t pi_wide_port_cap:1; 75 uint8_t pi_conn_idx[2]; 76 uint8_t pi_rsvd2[4]; 77 uint64_t pi_sas_addr[2]; 78 uint8_t pi_rsvd3[16]; 79 } pd_pathinfo; 80 81 uint64_t pd_raw_size; 82 uint64_t pd_non_coerced_size; 83 uint64_t pd_coerced_size; 84 85 uint16_t pd_encl_dev_id; 86 uint8_t pd_encl_idx; 87 88 union { 89 uint8_t pd_slot_num; 90 uint8_t pd_encl_conn_idx; 91 }; 92 93 struct { 94 uint32_t pp_active_rbld:1; 95 uint32_t pp_active_patrol:1; 96 uint32_t pp_active_clear:1; 97 uint32_t pp_active_copyback:1; 98 uint32_t pp_active_erase:1; 99 uint32_t pp_active_locate:1; 100 uint32_t pp_active_rsvd:26; 101 102 uint16_t pp_rbld_progress; 103 uint16_t pp_rbld_elapsed; 104 uint16_t pp_patrol_progress; 105 uint16_t pp_patrol_elapsed; 106 uint16_t pp_erase_progress; 107 uint16_t pp_erase_elapsed; 108 109 uint32_t pp_pause_rbld:1; 110 uint32_t pp_pause_patrol:1; 111 uint32_t pp_pause_clear:1; 112 uint32_t pp_pause_copyback:1; 113 uint32_t pp_pause_erase:1; 114 uint32_t pp_pause_rsvd:27; 115 116 uint32_t pp_rsvd[3]; 117 } pd_progress; 118 119 uint8_t pd_bad_block_table_full; 120 uint8_t pd_unusable_in_current_config; 121 uint8_t pd_vpd83ext[64]; 122 uint8_t pd_powerstate; 123 uint8_t pd_encl_pos; 124 uint32_t pd_allowed_ops; 125 uint16_t pd_copyback_partner_id; 126 uint16_t pd_encl_partner_dev_id; 127 128 struct { 129 uint16_t ps_fde_capable:1; 130 uint16_t ps_fde_enabled:1; 131 uint16_t ps_secured:1; 132 uint16_t ps_locked:1; 133 uint16_t ps_foreign:1; 134 uint16_t ps_needs_EKM:1; 135 uint16_t ps_rsvd:10; 136 } pd_security; 137 138 uint8_t pd_mediatype; 139 uint8_t pd_not_certified; 140 uint8_t pd_bridge_vendor[8]; 141 uint8_t pd_bridge_product_id[16]; 142 uint8_t pd_bridge_product_rev[4]; 143 uint8_t pd_sat_bridge_exists; 144 145 uint8_t pd_interface_type; 146 uint8_t pd_temperature; 147 uint8_t pd_emulated_blocksize; 148 uint16_t pd_userdata_blocksize; 149 uint16_t pd_rsvd; 150 151 struct { 152 uint32_t pp_pi_type:3; 153 uint32_t pp_pi_formatted:1; 154 uint32_t pp_pi_eligible:1; 155 uint32_t pp_ncq:1; 156 uint32_t pp_wce:1; 157 uint32_t pp_comm_spare:1; 158 uint32_t pp_emerg_spare:1; 159 uint32_t pp_ineligible_for_sscd:1; 160 uint32_t pp_ineligible_for_ld:1; 161 uint32_t pp_use_ss_erase_type:1; 162 uint32_t pp_wce_unchanged:1; 163 uint32_t pp_support_scsi_unmap:1; 164 uint32_t pp_rsvd:18; 165 } pd_prop; 166 167 uint64_t pd_shield_diag_compl_time; 168 uint8_t pd_shield_counter; 169 170 uint8_t pd_link_speed_other; 171 uint8_t pd_rsvd2[2]; 172 173 struct { 174 uint32_t bbm_err_count_supported:1; 175 uint32_t bbm_err_count:31; 176 } pd_bbm_err; 177 178 uint8_t pd_rsvd3[512 - 428]; 179 }; 180 181 /* 182 * PD config map 183 */ 184 struct lmrc_pd_cfg { 185 uint16_t pd_seqnum; 186 uint16_t pd_devhdl; 187 struct { 188 uint8_t pd_tm_capable:1; 189 uint8_t pd_rsvd:7; 190 }; 191 uint8_t pd_rsvd2; 192 uint16_t pd_tgtid; 193 }; 194 195 struct lmrc_pd_map { 196 uint32_t pm_size; 197 uint32_t pm_count; 198 lmrc_pd_cfg_t pm_pdcfg[0]; 199 }; 200 201 /* 202 * PD address list 203 */ 204 struct lmrc_pd_addr { 205 uint16_t pa_dev_id; 206 uint16_t pa_enc_id; 207 208 union { 209 struct { 210 uint8_t pa_enc_idx; 211 uint8_t pa_slot_num; 212 }; 213 struct { 214 uint8_t pa_enc_pos; 215 uint8_t pa_enc_conn_idx; 216 }; 217 }; 218 uint8_t pa_scsi_dev_type; 219 union { 220 uint8_t pa_conn_port_bitmap; 221 uint8_t pa_conn_port_numbers; 222 }; 223 uint64_t pa_sas_addr[2]; 224 }; 225 226 #define LMRC_PD_STATE_UNCONFIGURED_GOOD 0x00 227 #define LMRC_PD_STATE_UNCONFIGURED_BAD 0x01 228 #define LMRC_PD_STATE_HOT_SPARE 0x02 229 #define LMRC_PD_STATE_OFFLINE 0x10 230 #define LMRC_PD_STATE_FAILED 0x11 231 #define LMRC_PD_STATE_REBUILD 0x14 232 #define LMRC_PD_STATE_ONLINE 0x18 233 #define LMRC_PD_STATE_COPYBACK 0x20 234 #define LMRC_PD_STATE_SYSTEM 0x40 235 236 struct lmrc_pd_list { 237 uint32_t pl_size; 238 uint32_t pl_count; 239 lmrc_pd_addr_t pl_addr[0]; 240 }; 241 #pragma pack(0) 242 243 int lmrc_setup_pdmap(lmrc_t *); 244 void lmrc_free_pdmap(lmrc_t *); 245 246 boolean_t lmrc_pd_tm_capable(lmrc_t *, uint16_t); 247 248 int lmrc_get_pd_list(lmrc_t *); 249 250 int lmrc_phys_attach(dev_info_t *); 251 int lmrc_phys_detach(dev_info_t *); 252 253 int lmrc_phys_aen_handler(lmrc_t *, lmrc_evt_t *); 254 255 #endif /* _LMRC_PHYS_H */ 256