17e3dbbacSRobert Mustacchi--------------------- 27e3dbbacSRobert MustacchiThis package contains performance monitoring event lists for Intel processors, as well as a mapping file 37e3dbbacSRobert Mustacchito help match event lists to processor Family/Model/Stepping codes. 47e3dbbacSRobert Mustacchi--------------------- 57e3dbbacSRobert Mustacchi 67e3dbbacSRobert MustacchiThe event lists are available in 2 formats: 77e3dbbacSRobert Mustacchi Tab delimited (.tsv) 87e3dbbacSRobert Mustacchi Json (.json) 97e3dbbacSRobert Mustacchi 107e3dbbacSRobert MustacchiEvent lists are created per microarchitecture, and each has a version. Versions are listed in the event list 117e3dbbacSRobert Mustacchiname as well as the header for each file. For some microarchitectures, up to three different event lists will 127e3dbbacSRobert Mustacchibe available. These event lists correspond to the types of events that can be collected: 137e3dbbacSRobert Mustacchi 147e3dbbacSRobert Mustacchicore - Contains events counted from within a logical processor core. 157e3dbbacSRobert Mustacchioffcore - Contains matrix events counted from the core, but measuring responses that come from offcore. 167e3dbbacSRobert Mustacchi 177e3dbbacSRobert MustacchiThe event list filename indicates which type of list it contains, and follows this format: 187e3dbbacSRobert Mustacchi<microarchitecture-codename>_<core/offcore>_<version> 197e3dbbacSRobert Mustacchi 207e3dbbacSRobert MustacchiNew version releases will be announced in the mail list perfmon-announce@lists.01.org 217e3dbbacSRobert Mustacchi 227e3dbbacSRobert MustacchiDifferent microarchitectures provide different performance monitoring capabilities, so field names and categories 237e3dbbacSRobert Mustacchiof events may vary. 247e3dbbacSRobert Mustacchi 25c18e9bc3SRobert Mustacchi--------------------- 26c18e9bc3SRobert MustacchiLicensing Information 27c18e9bc3SRobert Mustacchi--------------------- 28*43449cdcSRobert MustacchiThe following files are distributed under the terms of the 3-clause BSD license: 29c18e9bc3SRobert Mustacchi 30c18e9bc3SRobert Mustacchi- Mapfile.csv 31c18e9bc3SRobert Mustacchi- All .tsv files 32*43449cdcSRobert Mustacchi- All .json files 33c18e9bc3SRobert Mustacchi 34c18e9bc3SRobert MustacchiCopyright (C) 2018 Intel Corporation 35*43449cdcSRobert Mustacchi� 36c18e9bc3SRobert MustacchiRedistribution and use in source and binary forms, with or without modification, 37c18e9bc3SRobert Mustacchiare permitted provided that the following conditions are met: 38*43449cdcSRobert Mustacchi� 39c18e9bc3SRobert Mustacchi1. Redistributions of source code must retain the above copyright notice, 40*43449cdcSRobert Mustacchi�� this list of conditions and the following disclaimer. 41c18e9bc3SRobert Mustacchi2. Redistributions in binary form must reproduce the above copyright notice, 42*43449cdcSRobert Mustacchi�� this list of conditions and the following disclaimer in the documentation 43*43449cdcSRobert Mustacchi�� and/or other materials provided with the distribution. 44c18e9bc3SRobert Mustacchi3. Neither the name of the copyright holder nor the names of its contributors 45*43449cdcSRobert Mustacchi�� may be used to endorse or promote products derived from this software 46*43449cdcSRobert Mustacchi�� without specific prior written permission. 47*43449cdcSRobert Mustacchi� 48c18e9bc3SRobert MustacchiTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 49c18e9bc3SRobert MustacchiAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 50c18e9bc3SRobert MustacchiTHE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 51*43449cdcSRobert MustacchiARE DISCLAIMED.� IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS 52c18e9bc3SRobert MustacchiBE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, 53c18e9bc3SRobert MustacchiOR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 54c18e9bc3SRobert MustacchiOF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 55c18e9bc3SRobert MustacchiOR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 56c18e9bc3SRobert MustacchiWHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 57c18e9bc3SRobert MustacchiOR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 58c18e9bc3SRobert MustacchiEVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 59*43449cdcSRobert Mustacchi� 60c18e9bc3SRobert MustacchiSPDX-License-Identifier: BSD-3-Clause 61c18e9bc3SRobert Mustacchi 62c18e9bc3SRobert Mustacchi 63c18e9bc3SRobert MustacchiOther files in this package are ALL RIGHTS RESERVED. 64c18e9bc3SRobert Mustacchi 65c18e9bc3SRobert Mustacchi 667e3dbbacSRobert Mustacchi--------------------- 677e3dbbacSRobert MustacchiEvent List Field Defitions: 687e3dbbacSRobert Mustacchi--------------------- 697e3dbbacSRobert MustacchiBelow is a list of the fields/headers in the event files and a description of how SW tools should 707e3dbbacSRobert Mustacchiinterpret these values. A particular event list from this package may not contain all the fields described 717e3dbbacSRobert Mustacchibelow. For more detailed information of the Performance monitoring unit please refer to chapters 18 and 19 727e3dbbacSRobert Mustacchiof Intel� 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide, Part 2. 737e3dbbacSRobert Mustacchi 747e3dbbacSRobert Mustacchihttp://www.intel.com/content/www/us/en/processors/architectures-software-developer-manuals.html 757e3dbbacSRobert Mustacchi 767e3dbbacSRobert Mustacchi 777e3dbbacSRobert Mustacchi----EventCode---- 787e3dbbacSRobert MustacchiThis field maps to the Event Select field in the IA32_PERFEVTSELx[7:0]MSRs. The set of values for this field 797e3dbbacSRobert Mustacchiis defined architecturally. Each value corresponds to an event logic unit and should be used with a unit 807e3dbbacSRobert Mustacchimask value to obtain an architectural performance event. 817e3dbbacSRobert Mustacchi 827e3dbbacSRobert Mustacchi----UMask---- 837e3dbbacSRobert MustacchiThis field maps to the Unit Mask filed in the IA32_PERFEVTSELx[15:8] MSRs. It further qualifies the event logic 847e3dbbacSRobert Mustacchiunit selected in the event select field to detect a specific micro-architectural condition. 857e3dbbacSRobert Mustacchi 867e3dbbacSRobert Mustacchi----EventName---- 877e3dbbacSRobert MustacchiIt is a string of characters to identify the programming of an event. 887e3dbbacSRobert Mustacchi 897e3dbbacSRobert Mustacchi----BriefDescription---- 907e3dbbacSRobert MustacchiThis field contains a description of what is being counted by a particular event. 917e3dbbacSRobert Mustacchi 927e3dbbacSRobert Mustacchi----PublicDescription---- 937e3dbbacSRobert MustacchiIn some cases, this field will contain a more detailed description of what is counted by an event. 947e3dbbacSRobert Mustacchi 957e3dbbacSRobert Mustacchi----Counter---- 967e3dbbacSRobert MustacchiThis field lists the fixed (PERF_FIXED_CTRX) or programmable (IA32_PMCX) counters that can be used to count the event. 977e3dbbacSRobert Mustacchi 987e3dbbacSRobert Mustacchi----CounterHTOff---- 997e3dbbacSRobert MustacchiThis field lists the counters where this event can be sampled when Intel� Hyper-Threading Technology (Intel� HT Technology) is 1007e3dbbacSRobert Mustacchidisabled. When Intel� HT Technology is disabled, some processor cores gain access to the programmable counters of the second 1017e3dbbacSRobert Mustacchithread, making a total of eight programmable counters available. The additional counters will be numbered 4,5,6,7. Fixed counter 1027e3dbbacSRobert Mustacchibehavior remains unaffected. 1037e3dbbacSRobert Mustacchi 1047e3dbbacSRobert Mustacchi----PEBScounters---- 1057e3dbbacSRobert MustacchiThis field is only relevant to PEBS events. It lists the counters where the event can be sampled when it is programmed as a PEBS event. 1067e3dbbacSRobert Mustacchi 1077e3dbbacSRobert Mustacchi----SampleAfterValue---- 1087e3dbbacSRobert MustacchiSample After Value (SAV) is the value that can be pre-loaded into the counter registers to set the point at which they will overflow. 1097e3dbbacSRobert MustacchiTo make the counter overflow after N occurrences of the event, it should be loaded with (0xFF..FF � N) or �(N-1). On overflow a 1107e3dbbacSRobert Mustacchihardware interrupt is generated through the Local APIC and additional architectural state can be collected in the interrupt handler. 1117e3dbbacSRobert MustacchiThis is useful in event-based sampling. This field gives a recommended default overflow value, which may be adjusted based on 1127e3dbbacSRobert Mustacchiworkload or tool preference. 1137e3dbbacSRobert Mustacchi 1147e3dbbacSRobert Mustacchi----MSRIndex---- 1157e3dbbacSRobert MustacchiAdditional MSRs may be required for programming certain events. This field gives the address of such MSRS. 1167e3dbbacSRobert MustacchiPotential values are: 1177e3dbbacSRobert Mustacchi0x3F6: MSR_PEBS_LD_LAT - used to configure the Load Latency Perforamnce Monitoring Facility 1187e3dbbacSRobert Mustacchi0x1A6/0x1A7: MSR_OFFCORE_RSP_X - used to configure the offcore response events 1197e3dbbacSRobert Mustacchi 1207e3dbbacSRobert Mustacchi----MSRValue---- 1217e3dbbacSRobert MustacchiWhen an MSRIndex is used (indicated by the MSRIndex column), this field will contain the value that needs to be loaded into the 1227e3dbbacSRobert Mustacchiregister whose address is given in MSRIndex column. For example, in the case of the load latency events, MSRValue defines the 1237e3dbbacSRobert Mustacchilatency threshold value to write into the MSR defined in MSRIndex (0x3F6). 1247e3dbbacSRobert Mustacchi 1257e3dbbacSRobert Mustacchi----CollectPEBSRecord---- 1267e3dbbacSRobert MustacchiApplies to processors that support both precise and non-precise events in Processor Event Based Sampling, such as Goldmont. 1277e3dbbacSRobert Mustacchi0: The event cannot be programmed to collect a PEBS record. 1287e3dbbacSRobert Mustacchi1: The event may be programmed to collect a PEBS record, but caution is advised. 1297e3dbbacSRobert MustacchiFor instance, PEBS collection of this event may consume limited PEBS resources whereas interrupt-based sampling may be sufficient for the usage model. 1307e3dbbacSRobert Mustacchi2: The event may programmed to collect a PEBS record, and due to the nature of the event, PEBS collection may be preferred. For instance, 1317e3dbbacSRobert MustacchiPEBS collection of Goldmont�s HW_INTERUPTS.RECIEVED event is recommended because the hardware interrupt being counted may lead to the masking of 1327e3dbbacSRobert Mustacchiinterrupts which would interfere with interrupt-based sampling. 1337e3dbbacSRobert Mustacchi 1347e3dbbacSRobert Mustacchi 1357e3dbbacSRobert Mustacchi ----TakenAlone---- 1367e3dbbacSRobert MustacchiThis field is set for an event which can only be sampled or counted by itself, meaning that when this event is being collected, 1377e3dbbacSRobert Mustacchithe remaining programmable counters are not available to count any other events. 1387e3dbbacSRobert Mustacchi 1397e3dbbacSRobert Mustacchi----CounterMask---- 1407e3dbbacSRobert MustacchiThis field maps to the Counter Mask (CMASK) field in IA32_PERFEVTSELx[31:24] MSR. 1417e3dbbacSRobert Mustacchi 1427e3dbbacSRobert Mustacchi----Invert---- 1437e3dbbacSRobert MustacchiThis field corresponds to the Invert Counter Mask (INV) field in IA32_PERFEVTSELx[23] MSR. 1447e3dbbacSRobert Mustacchi 1457e3dbbacSRobert Mustacchi----AnyThread---- 1467e3dbbacSRobert MustacchiThis field corresponds to the Any Thread (ANY) bit of IA32_PERFEVTSELx[21] MSR. 1477e3dbbacSRobert Mustacchi 1487e3dbbacSRobert Mustacchi----EdgeDetect---- 1497e3dbbacSRobert MustacchiThis field corresponds to the Edge Detect (E) bit of IA32_PERFEVTSELx[18] MSR. 1507e3dbbacSRobert Mustacchi 1517e3dbbacSRobert Mustacchi----PEBS---- 1527e3dbbacSRobert MustacchiA '0' in this field means that the event cannot collect a PEBS record with a Precise IP. A '1' in this field means that the event is a 1537e3dbbacSRobert Mustacchiprecise event and can be programmed in one of two ways � as a regular event or as a PEBS event. And a '2' in this field means 1547e3dbbacSRobert Mustacchithat the event can only be programmed as a PEBS event. 1557e3dbbacSRobert Mustacchi 1567e3dbbacSRobert Mustacchi----PRECISE_STORE---- 1577e3dbbacSRobert MustacchiA '1' in this field means the event uses the Precise Store feature and Bit 3 and bit 63 in IA32_PEBS_ENABLE MSR must be set 1587e3dbbacSRobert Mustacchito enable IA32_PMC3 as a PEBS counter and enable the precise store facility respectively. Processors based on SandyBridge and 1597e3dbbacSRobert MustacchiIvyBridge micro-architecture offer a precise store capability that provides a means to profile store memory references in 1607e3dbbacSRobert Mustacchithe system. 1617e3dbbacSRobert Mustacchi 1627e3dbbacSRobert Mustacchi----DATA_LA---- 1637e3dbbacSRobert MustacchiA '1' in this field means that when the event is configured as a PEBS event, the Data Linear Address facility is supported. 1647e3dbbacSRobert MustacchiThe Data Linear Address facility is a new feature added to Haswell as a replacement or extension of the precise store facility 1657e3dbbacSRobert Mustacchiin SNB. 1667e3dbbacSRobert Mustacchi 1677e3dbbacSRobert Mustacchi----L1_HIT_INDICATION---- 1687e3dbbacSRobert MustacchiA '1' in this field means that when the event is configured as a PEBS event, the DCU hit field of the PEBS record is set to 1 1697e3dbbacSRobert Mustacchiwhen the store hits in the L1 cache and 0 when it misses. 1707e3dbbacSRobert Mustacchi 1717e3dbbacSRobert Mustacchi----Errata---- 1727e3dbbacSRobert MustacchiThis field lists the known bugs that apply to the events. For the latest, up to date errata refer to 1737e3dbbacSRobert Mustacchi 1747e3dbbacSRobert MustacchiHaswell: 1757e3dbbacSRobert Mustacchihttp://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/4th-gen-core-family-mobile-specification-update.pdf 1767e3dbbacSRobert Mustacchi 1777e3dbbacSRobert MustacchiIvyBridge: 1787e3dbbacSRobert Mustacchihttps://www-ssl.intel.com/content/dam/www/public/us/en/documents/specification-updates/3rd-gen-core-desktop-specification-update.pdf 1797e3dbbacSRobert Mustacchi 1807e3dbbacSRobert MustacchiSandyBridge: 1817e3dbbacSRobert Mustacchihttps://www-ssl.intel.com/content/dam/www/public/us/en/documents/specification-updates/2nd-gen-core-family-mobile-specification-update.pdf 1827e3dbbacSRobert Mustacchi 1837e3dbbacSRobert Mustacchi----offcore---- 1847e3dbbacSRobert MustacchiThis field is specific to the json format. There is only 1 file for core and offcore events in this format. This field is set to 1 for offcore events 1857e3dbbacSRobert Mustacchiand 0 for core events. 1867e3dbbacSRobert Mustacchi 1877e3dbbacSRobert Mustacchi--------------------- 1887e3dbbacSRobert MustacchiFor additional information: 1897e3dbbacSRobert Mustacchi--------------------- 1907e3dbbacSRobert MustacchiIntel Platform Monitoring Homepage 1917e3dbbacSRobert Mustacchihttp://software.intel.com/en-us/platform-monitoring/ 1927e3dbbacSRobert Mustacchi 1937e3dbbacSRobert Mustacchihttp://software.intel.com/en-us/articles/performance-monitoring-on-intel-xeon-processor-e5-family 1947e3dbbacSRobert Mustacchi 1957e3dbbacSRobert Mustacchihttp://software.intel.com/en-us/articles/monitoring-integrated-memory-controller-requests-in-the-2nd-3rd-and-4th-generation-intel 1967e3dbbacSRobert Mustacchi 1977e3dbbacSRobert Mustacchihttp://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/4th-gen-core-family-desktop-specification-update.pdf 1987e3dbbacSRobert Mustacchi 1997e3dbbacSRobert Mustacchi--------------------- 2007e3dbbacSRobert MustacchiFor questions: 2017e3dbbacSRobert Mustacchi--------------------- 2027e3dbbacSRobert Mustacchiemail perfmon-discuss@lists.01.org 2037e3dbbacSRobert Mustacchi 2047e3dbbacSRobert Mustacchi--------------------- 2057e3dbbacSRobert MustacchiNotices: 2067e3dbbacSRobert Mustacchi--------------------- 2077e3dbbacSRobert MustacchiINFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, 2087e3dbbacSRobert MustacchiTO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH 2097e3dbbacSRobert MustacchiPRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF 2107e3dbbacSRobert MustacchiINTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY 2117e3dbbacSRobert MustacchiPATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. 2127e3dbbacSRobert Mustacchi 2137e3dbbacSRobert MustacchiA "Mission Critical Application" is any application in which failure of the Intel Product could result, directly or indirectly, in 2147e3dbbacSRobert Mustacchipersonal injury or death. SHOULD YOU PURCHASE OR USE INTEL'S PRODUCTS FOR ANY SUCH MISSION CRITICAL APPLICATION, YOU SHALL INDEMNIFY 2157e3dbbacSRobert MustacchiAND HOLD INTEL AND ITS SUBSIDIARIES, SUBCONTRACTORS AND AFFILIATES, AND THE DIRECTORS, OFFICERS, AND EMPLOYEES OF EACH, HARMLESS AGAINST 2167e3dbbacSRobert MustacchiALL CLAIMS COSTS, DAMAGES, AND EXPENSES AND REASONABLE ATTORNEYS' FEES ARISING OUT OF, DIRECTLY OR INDIRECTLY, ANY CLAIM OF PRODUCT 2177e3dbbacSRobert MustacchiLIABILITY, PERSONAL INJURY, OR DEATH ARISING IN ANY WAY OUT OF SUCH MISSION CRITICAL APPLICATION, WHETHER OR NOT INTEL OR ITS SUBCONTRACTOR 2187e3dbbacSRobert MustacchiWAS NEGLIGENT IN THE DESIGN, MANUFACTURE, OR WARNING OF THE INTEL PRODUCT OR ANY OF ITS PARTS. 2197e3dbbacSRobert Mustacchi 2207e3dbbacSRobert MustacchiIntel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or 2217e3dbbacSRobert Mustacchicharacteristics of any features or instructions marked "reserved" or "undefined". Intel reserves these for future definition and shall have 2227e3dbbacSRobert Mustacchino responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The information here is subject to 2237e3dbbacSRobert Mustacchichange without notice. Do not finalize a design with this information. 2247e3dbbacSRobert Mustacchi 2257e3dbbacSRobert MustacchiThe products described in this document may contain design defects or errors known as errata which may cause the product to deviate from 2267e3dbbacSRobert Mustacchipublished specifications. Current characterized errata are available on request. 2277e3dbbacSRobert Mustacchi 2287e3dbbacSRobert MustacchiContact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. 2297e3dbbacSRobert Mustacchi 2307e3dbbacSRobert MustacchiCopies of documents which have an order number and are referenced in this document, or other Intel literature, may be obtained by calling 2317e3dbbacSRobert Mustacchi1-800-548-4725, or go to: http://www.intel.com/design/literature.htm 2327e3dbbacSRobert Mustacchi 233*43449cdcSRobert MustacchiCopyright � 2014 Intel Corporation. All rights reserved.