2This package contains performance monitoring event lists for Intel processors, as well as a mapping file
3to help match event lists to processor Family/Model/Stepping codes.
6The event lists are available in 2 formats:
7 Tab delimited (.tsv)
8 Json (.json)
10Event lists are created per microarchitecture, and each has a version. Versions are listed in the event list
11name as well as the header for each file. For some microarchitectures, up to three different event lists will
12be available. These event lists correspond to the types of events that can be collected:
14core - Contains events counted from within a logical processor core.
15offcore - Contains matrix events counted from the core, but measuring responses that come from offcore.
17The event list filename indicates which type of list it contains, and follows this format:
20New version releases will be announced in the mail list firstname.lastname@example.org
22Different microarchitectures provide different performance monitoring capabilities, so field names and categories
23of events may vary.
28The following files are distributed under the terms of the 3-clause BSD license:
31- All .tsv files
32- All .json files
34Copyright (C) 2018 Intel Corporation
36Redistribution and use in source and binary forms, with or without modification,
37are permitted provided that the following conditions are met:
391. Redistributions of source code must retain the above copyright notice,
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412. Redistributions in binary form must reproduce the above copyright notice,
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45�� may be used to endorse or promote products derived from this software
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48THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
49AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
50THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
51ARE DISCLAIMED.� IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS
52BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
53OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
54OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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57OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
58EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
63Other files in this package are ALL RIGHTS RESERVED.
67Event List Field Defitions:
69Below is a list of the fields/headers in the event files and a description of how SW tools should
70interpret these values. A particular event list from this package may not contain all the fields described
71below. For more detailed information of the Performance monitoring unit please refer to chapters 18 and 19
72of Intel� 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide, Part 2.
78This field maps to the Event Select field in the IA32_PERFEVTSELx[7:0]MSRs. The set of values for this field
79is defined architecturally. Each value corresponds to an event logic unit and should be used with a unit
80mask value to obtain an architectural performance event.
83This field maps to the Unit Mask filed in the IA32_PERFEVTSELx[15:8] MSRs. It further qualifies the event logic
84unit selected in the event select field to detect a specific micro-architectural condition.
87It is a string of characters to identify the programming of an event.
90This field contains a description of what is being counted by a particular event.
93In some cases, this field will contain a more detailed description of what is counted by an event.
96This field lists the fixed (PERF_FIXED_CTRX) or programmable (IA32_PMCX) counters that can be used to count the event.
99This field lists the counters where this event can be sampled when Intel� Hyper-Threading Technology (Intel� HT Technology) is
100disabled. When Intel� HT Technology is disabled, some processor cores gain access to the programmable counters of the second
101thread, making a total of eight programmable counters available. The additional counters will be numbered 4,5,6,7. Fixed counter
102behavior remains unaffected.
105This field is only relevant to PEBS events. It lists the counters where the event can be sampled when it is programmed as a PEBS event.
108Sample After Value (SAV) is the value that can be pre-loaded into the counter registers to set the point at which they will overflow.
109To make the counter overflow after N occurrences of the event, it should be loaded with (0xFF..FF � N) or �(N-1). On overflow a
110hardware interrupt is generated through the Local APIC and additional architectural state can be collected in the interrupt handler.
111This is useful in event-based sampling. This field gives a recommended default overflow value, which may be adjusted based on
112workload or tool preference.
115Additional MSRs may be required for programming certain events. This field gives the address of such MSRS.
116Potential values are:
1170x3F6: MSR_PEBS_LD_LAT - used to configure the Load Latency Perforamnce Monitoring Facility
1180x1A6/0x1A7: MSR_OFFCORE_RSP_X - used to configure the offcore response events
121When an MSRIndex is used (indicated by the MSRIndex column), this field will contain the value that needs to be loaded into the
122register whose address is given in MSRIndex column. For example, in the case of the load latency events, MSRValue defines the
123latency threshold value to write into the MSR defined in MSRIndex (0x3F6).
126Applies to processors that support both precise and non-precise events in Processor Event Based Sampling, such as Goldmont.
1270: The event cannot be programmed to collect a PEBS record.
1281: The event may be programmed to collect a PEBS record, but caution is advised.
129For instance, PEBS collection of this event may consume limited PEBS resources whereas interrupt-based sampling may be sufficient for the usage model.
1302: The event may programmed to collect a PEBS record, and due to the nature of the event, PEBS collection may be preferred. For instance,
131PEBS collection of Goldmont�s HW_INTERUPTS.RECIEVED event is recommended because the hardware interrupt being counted may lead to the masking of
132interrupts which would interfere with interrupt-based sampling.
136This field is set for an event which can only be sampled or counted by itself, meaning that when this event is being collected,
137the remaining programmable counters are not available to count any other events.
140This field maps to the Counter Mask (CMASK) field in IA32_PERFEVTSELx[31:24] MSR.
143This field corresponds to the Invert Counter Mask (INV) field in IA32_PERFEVTSELx MSR.
146This field corresponds to the Any Thread (ANY) bit of IA32_PERFEVTSELx MSR.
149This field corresponds to the Edge Detect (E) bit of IA32_PERFEVTSELx MSR.
152A '0' in this field means that the event cannot collect a PEBS record with a Precise IP. A '1' in this field means that the event is a
153precise event and can be programmed in one of two ways � as a regular event or as a PEBS event. And a '2' in this field means
154that the event can only be programmed as a PEBS event.
157A '1' in this field means the event uses the Precise Store feature and Bit 3 and bit 63 in IA32_PEBS_ENABLE MSR must be set
158to enable IA32_PMC3 as a PEBS counter and enable the precise store facility respectively. Processors based on SandyBridge and
159IvyBridge micro-architecture offer a precise store capability that provides a means to profile store memory references in
163A '1' in this field means that when the event is configured as a PEBS event, the Data Linear Address facility is supported.
164The Data Linear Address facility is a new feature added to Haswell as a replacement or extension of the precise store facility
168A '1' in this field means that when the event is configured as a PEBS event, the DCU hit field of the PEBS record is set to 1
169when the store hits in the L1 cache and 0 when it misses.
172This field lists the known bugs that apply to the events. For the latest, up to date errata refer to
184This field is specific to the json format. There is only 1 file for core and offcore events in this format. This field is set to 1 for offcore events
185and 0 for core events.
188For additional information:
190Intel Platform Monitoring Homepage
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