xref: /illumos-gate/usr/src/data/perfmon/SNR/snowridgex_uncore_v1.10.json (revision 43449cdc)

[
  {
    "Unit": "CHA",
    "EventCode": "0x00",
    "UMask": "0x00",
    "PortMask": "0x00",
    "FCMask": "0x00",
    "UMaskExt": "0x00",
    "EventName": "UNC_CHA_CLOCKTICKS",
    "BriefDescription": "Clockticks of the uncore caching and home agent (CHA)",
    "PublicDescription": "Clockticks of the uncore caching and home agent (CHA)",
    "Counter": "0,1,2,3",
    "MSRValue": "0x00",
    "ELLC": "0",
    "Filter": "na",
    "ExtSel": "0",
    "Deprecated": "0",
    "FILTER_VALUE": "0",
    "CounterType": "PGMABLE"
  },
  {
    "Unit": "CHA",
    "EventCode": "0x35",
    "UMask": "0x01",
    "PortMask": "0x00",
    "FCMask": "0x00",
    "UMaskExt": "0xC001FE",
    "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS",
    "BriefDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC",
    "PublicDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
    "Counter": "0,1,2,3",
    "MSRValue": "0x00",
    "ELLC": "0",
    "Filter": "na",
    "ExtSel": "0",
    "Deprecated": "0",
    "FILTER_VALUE": "0",
    "CounterType": "PGMABLE"
  },
  {
    "Unit": "CHA",
    "EventCode": "0x35",
    "UMask": "0x01",
    "PortMask": "0x00",
    "FCMask": "0x00",
    "UMaskExt": "0xC80FFE",
    "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD",
    "BriefDescription": "TOR Inserts : CRds issued by iA Cores that Missed the LLC",
    "PublicDescription": "TOR Inserts : CRds issued by iA Cores that Missed the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
    "Counter": "0,1,2,3",
    "MSRValue": "0x00",
    "ELLC": "0",
    "Filter": "na",
    "ExtSel": "0",
    "Deprecated": "0",
    "FILTER_VALUE": "0",
    "CounterType": "PGMABLE"
  },
  {
    "Unit": "CHA",
    "EventCode": "0x35",
    "UMask": "0x01",
    "PortMask": "0x00",
    "FCMask": "0x00",
    "UMaskExt": "0xC807FE",
    "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO",
    "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC",
    "PublicDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
    "Counter": "0,1,2,3",
    "MSRValue": "0x00",
    "ELLC": "0",
    "Filter": "na",
    "ExtSel": "0",
    "Deprecated": "0",
    "FILTER_VALUE": "0",
    "CounterType": "PGMABLE"
  },
  {
    "Unit": "CHA",
    "EventCode": "0x35",
    "UMask": "0x01",
    "PortMask": "0x00",
    "FCMask": "0x00",
    "UMaskExt": "0xC88FFE",
    "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF",
    "BriefDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC",
    "PublicDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
    "Counter": "0,1,2,3",
    "MSRValue": "0x00",
    "ELLC": "0",
    "Filter": "na",
    "ExtSel": "0",
    "Deprecated": "0",
    "FILTER_VALUE": "0",
    "CounterType": "PGMABLE"
  },
  {
    "Unit": "CHA",
    "EventCode": "0x35",
    "UMask": "0x01",
    "PortMask": "0x00",
    "FCMask": "0x00",
    "UMaskExt": "0xC827FE",
    "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT",
    "BriefDescription": "TOR Inserts : DRd_Opt issued by iA Cores that missed the LLC",
    "PublicDescription": "TOR Inserts : DRd_Opt issued by iA Cores that missed the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
    "Counter": "0,1,2,3",
    "MSRValue": "0x00",
    "ELLC": "0",
    "Filter": "na",
    "ExtSel": "0",
    "Deprecated": "0",
    "FILTER_VALUE": "0",
    "CounterType": "PGMABLE"
  },
  {
    "Unit": "CHA",
    "EventCode": "0x35",
    "UMask": "0x01",
    "PortMask": "0x00",
    "FCMask": "0x00",
    "UMaskExt": "0xC8A7FE",
    "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF",
    "BriefDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cores that missed the LLC",
    "PublicDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cores that missed the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
    "Counter": "0,1,2,3",
    "MSRValue": "0x00",
    "ELLC": "0",
    "Filter": "na",
    "ExtSel": "0",
    "Deprecated": "0",
    "FILTER_VALUE": "0",
    "CounterType": "PGMABLE"
  },
  {
    "Unit": "CHA",
    "EventCode": "0x35",
    "UMask": "0x01",
    "PortMask": "0x00",
    "FCMask": "0x00",
    "UMaskExt": "0xC887FE",
    "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF",
    "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC",
    "PublicDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
    "Counter": "0,1,2,3",
    "MSRValue": "0x00",
    "ELLC": "0",
    "Filter": "na",
    "ExtSel": "0",
    "Deprecated": "0",
    "FILTER_VALUE": "0",
    "CounterType": "PGMABLE"
  },
  {
    "Unit": "CHA",
    "EventCode": "0x35",
    "UMask": "0x01",
    "PortMask": "0x00",
    "FCMask": "0x00",
    "UMaskExt": "0xC86FFE",
    "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCIL",
    "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores that Missed the LLC",
    "PublicDescription": "TOR Inserts : WCiLs issued by iA Cores that Missed the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
    "Counter": "0,1,2,3",
    "MSRValue": "0x00",
    "ELLC": "0",
    "Filter": "na",
    "ExtSel": "0",
    "Deprecated": "0",
    "FILTER_VALUE": "0",
    "CounterType": "PGMABLE"
  },
  {
    "Unit": "CHA",
    "EventCode": "0x35",
    "UMask": "0x01",
    "PortMask": "0x00",
    "FCMask": "0x00",
    "UMaskExt": "0xC867FE",
    "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCILF",
    "BriefDescription": "TOR Inserts : WCiLF issued by iA Cores that Missed the LLC",
    "PublicDescription": "TOR Inserts : WCiLF issued by iA Cores that Missed the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
    "Counter": "0,1,2,3",
    "MSRValue": "0x00",
    "ELLC": "0",
    "Filter": "na",
    "ExtSel": "0",
    "Deprecated": "0",
    "FILTER_VALUE": "0",
    "CounterType": "PGMABLE"
  },
  {
    "Unit": "IIO",
    "EventCode": "0x01",
    "UMask": "0x00",
    "PortMask": "0x00",
    "FCMask": "0x00",
    "UMaskExt": "0x00",
    "EventName": "UNC_IIO_CLOCKTICKS",
    "BriefDescription": "Clockticks of the integrated IO (IIO) traffic controller",
    "PublicDescription": "Clockticks of the integrated IO (IIO) traffic controller",
    "Counter": "0,1,2,3",
    "MSRValue": "0x00",
    "ELLC": "0",
    "Filter": "na",
    "ExtSel": "0",
    "Deprecated": "0",
    "FILTER_VALUE": "0",
    "CounterType": "PGMABLE"
  },
  {
    "Unit": "IIO",
    "EventCode": "0x83",
    "UMask": "0x01",
    "PortMask": "0x01",
    "FCMask": "0x07",
    "UMaskExt": "0x00",
    "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0",
    "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
    "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
    "Counter": "0,1",
    "MSRValue": "0x00",
    "ELLC": "0",
    "Filter": "na",
    "ExtSel": "0",
    "Deprecated": "0",
    "FILTER_VALUE": "0",
    "CounterType": "PGMABLE"
  },
  {
    "Unit": "IIO",
    "EventCode": "0x83",
    "UMask": "0x01",
    "PortMask": "0x02",
    "FCMask": "0x07",
    "UMaskExt": "0x00",
    "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1",
    "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
    "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1",
    "Counter": "0,1",
    "MSRValue": "0x00",
    "ELLC": "0",
    "Filter": "na",
    "ExtSel": "0",
    "Deprecated": "0",
    "FILTER_VALUE": "0",
    "CounterType": "PGMABLE"
  },
  {
    "Unit": "IIO",
    "EventCode": "0x83",
    "UMask": "0x01",
    "PortMask": "0x04",
    "FCMask": "0x07",
    "UMaskExt": "0x00",
    "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2",
    "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
    "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
    "Counter": "0,1",
    "MSRValue": "0x00",
    "ELLC": "0",
    "Filter": "na",
    "ExtSel": "0",
    "Deprecated": "0",
    "FILTER_VALUE": "0",
    "CounterType": "PGMABLE"
  },
  {
    "Unit": "IIO",
    "EventCode": "0x83",
    "UMask": "0x01",
    "PortMask": "0x08",
    "FCMask": "0x07",
    "UMaskExt": "0x00",
    "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3",
    "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
    "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3",
    "Counter": "0,1",
    "MSRValue": "0x00",
    "ELLC": "0",
    "Filter": "na",
    "ExtSel": "0",
    "Deprecated": "0",
    "FILTER_VALUE": "0",
    "CounterType": "PGMABLE"
  },
  {
    "Unit": "IIO",
    "EventCode": "0x83",
    "UMask": "0x04",
    "PortMask": "0x01",
    "FCMask": "0x07",
    "UMaskExt": "0x00",
    "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0",
    "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
    "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
    "Counter": "0,1",
    "MSRValue": "0x00",
    "ELLC": "0",
    "Filter": "na",
    "ExtSel": "0",
    "Deprecated": "0",
    "FILTER_VALUE": "0",
    "CounterType": "PGMABLE"
  },
  {
    "Unit": "IIO",
    "EventCode": "0x83",
    "UMask": "0x04",
    "PortMask": "0x02",
    "FCMask": "0x07",
    "UMaskExt": "0x00",
    "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1",
    "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
    "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1",
    "Counter": "0,1",
    "MSRValue": "0x00",
    "ELLC": "0",
    "Filter": "na",
    "ExtSel": "0",
    "Deprecated": "0",
    "FILTER_VALUE": "0",
    "CounterType": "PGMABLE"
  },
  {
    "Unit": "IIO",
    "EventCode": "0x83",
    "UMask": "0x04",
    "PortMask": "0x04",
    "FCMask": "0x07",
    "UMaskExt": "0x00",
    "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2",
    "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
    "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
    "Counter": "0,1",
    "MSRValue": "0x00",
    "ELLC": "0",
    "Filter": "na",
    "ExtSel": "0",
    "Deprecated": "0",
    "FILTER_VALUE": "0",
    "CounterType": "PGMABLE"
  },
  {
    "Unit": "IIO",
    "EventCode": "0x83",
    "UMask": "0x04",
    "PortMask": "0x08",
    "FCMask": "0x07",
    "UMaskExt": "0x00",
    "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3",
    "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
    "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3",
    "Counter": "0,1",
    "MSRValue": "0x00",
    "ELLC": "0",
    "Filter": "na",
    "ExtSel": "0",
    "Deprecated": "0",
    "FILTER_VALUE": "0",
    "CounterType": "PGMABLE"
  },
  {
    "Unit": "IIO",
    "EventCode": "0x83",
    "UMask": "0x01",
    "PortMask": "0x10",
    "FCMask": "0x07",
    "UMaskExt": "0x00",
    "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART4",
    "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
    "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
    "Counter": "0,1",
    "MSRValue": "0x00",
    "ELLC": "0",
    "Filter": "na",
    "ExtSel": "0",
    "Deprecated": "0",
    "FILTER_VALUE": "0",
    "CounterType": "PGMABLE"
  },
  {
    "Unit": "IIO",
    "EventCode": "0x83",
    "UMask": "0x01",
    "PortMask": "0x20",
    "FCMask": "0x07",
    "UMaskExt": "0x00",
    "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART5",
    "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
    "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5",
    "Counter": "0,1",
    "MSRValue": "0x00",
    "ELLC": "0",
    "Filter": "na",
    "ExtSel": "0",
    "Deprecated": "0",
    "FILTER_VALUE": "0",
    "CounterType": "PGMABLE"
  },
  {
    "Unit": "IIO",
    "EventCode": "0x83",
    "UMask": "0x01",
    "PortMask": "0x40",
    "FCMask": "0x07",
    "UMaskExt": "0x00",
    "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART6",
    "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
    "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
    "Counter": "0,1",
    "MSRValue": "0x00",
    "ELLC": "0",
    "Filter": "na",
    "ExtSel": "0",
    "Deprecated": "0",
    "FILTER_VALUE": "0",
    "CounterType": "PGMABLE"
  },
  {
    "Unit": "IIO",
    "EventCode": "0x83",
    "UMask": "0x01",
    "PortMask": "0x80",
    "FCMask": "0x07",
    "UMaskExt": "0x00",
    "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART7",
    "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
    "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7",
    "Counter": "0,1",
    "MSRValue": "0x00",
    "ELLC": "0",
    "Filter": "na",
    "ExtSel": "0",
    "Deprecated": "0",
    "FILTER_VALUE": "0",
    "CounterType": "PGMABLE"
  },
  {
    "Unit": "IIO",
    "EventCode": "0x83",
    "UMask": "0x04",
    "PortMask": "0x10",
    "FCMask": "0x07",
    "UMaskExt": "0x00",
    "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART4",
    "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
    "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
    "Counter": "0,1",
    "MSRValue": "0x00",
    "ELLC": "0",
    "Filter": "na",
    "ExtSel": "0",
    "Deprecated": "0",
    "FILTER_VALUE": "0",
    "CounterType": "PGMABLE"
  },
  {
    "Unit": "IIO",
    "EventCode": "0x83",
    "UMask": "0x04",
    "PortMask": "0x20",
    "FCMask": "0x07",
    "UMaskExt": "0x00",
    "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART5",
    "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
    "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5",
    "Counter": "0,1",
    "MSRValue": "0x00",
    "ELLC": "0",
    "Filter": "na",
    "ExtSel": "0",
    "Deprecated": "0",
    "FILTER_VALUE": "0",
    "CounterType": "PGMABLE"
  },
  {
    "Unit": "IIO",
    "EventCode": "0x83",
    "UMask": "0x04",
    "PortMask": "0x40",
    "FCMask": "0x07",
    "UMaskExt": "0x00",
    "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART6",
    "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
    "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
    "Counter": "0,1",
    "MSRValue": "0x00",
    "ELLC": "0",
    "Filter": "na",
    "ExtSel": "0",
    "Deprecated": "0",
    "FILTER_VALUE": "0",
    "CounterType": "PGMABLE"
  },
  {
    "Unit": "IIO",
    "EventCode": "0x83",
    "UMask": "0x04",
    "PortMask": "0x80",
    "FCMask": "0x07",
    "UMaskExt": "0x00",
    "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART7",
    "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
    "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7",
    "Counter": "0,1",
    "MSRValue": "0x00",
    "ELLC": "0",
    "Filter": "na",
    "ExtSel": "0",
    "Deprecated": "0",
    "FILTER_VALUE": "0",
    "CounterType": "PGMABLE"
  },
  {
    "Unit": "IRP",
    "EventCode": "0x01",
    "UMask": "0x00",
    "PortMask": "0x00",
    "FCMask": "0x00",
    "UMaskExt": "0x00",
    "EventName": "UNC_I_CLOCKTICKS",
    "BriefDescription": "Clockticks of the IO coherency tracker (IRP)",
    "PublicDescription": "Clockticks of the IO coherency tracker (IRP)",
    "Counter": "0,1",
    "MSRValue": "0x00",
    "ELLC": "0",
    "Filter": "na",
    "ExtSel": "0",
    "Deprecated": "0",
    "FILTER_VALUE": "0",
    "CounterType": "PGMABLE"
  },
  {
    "Unit": "iMC",
    "EventCode": "0x02",
    "UMask": "0x04",
    "PortMask": "0x00",
    "FCMask": "0x00",
    "UMaskExt": "0x00",
    "EventName": "UNC_M_PRE_COUNT.RD",
    "BriefDescription": "DRAM Precharge commands. : Precharge due to read",
    "PublicDescription": "DRAM Precharge commands. : Precharge due to read : Counts the number of DRAM Precharge commands sent on this channel. : Precharge from read bank scheduler",
    "Counter": "0,1,2,3",
    "MSRValue": "0x00",
    "ELLC": "0",
    "Filter": "na",
    "ExtSel": "0",
    "Deprecated": "0",
    "FILTER_VALUE": "0",
    "CounterType": "PGMABLE"
  },
  {
    "Unit": "iMC",
    "EventCode": "0x02",
    "UMask": "0x08",
    "PortMask": "0x00",
    "FCMask": "0x00",
    "UMaskExt": "0x00",
    "EventName": "UNC_M_PRE_COUNT.WR",
    "BriefDescription": "DRAM Precharge commands. : Precharge due to write",
    "PublicDescription": "DRAM Precharge commands. : Precharge due to write : Counts the number of DRAM Precharge commands sent on this channel. : Precharge from write bank scheduler",
    "Counter": "0,1,2,3",
    "MSRValue": "0x00",
    "ELLC": "0",
    "Filter": "na",
    "ExtSel": "0",
    "Deprecated": "0",
    "FILTER_VALUE": "0",
    "CounterType": "PGMABLE"
  },
  {
    "Unit": "iMC",
    "EventCode": "0x04",
    "UMask": "0x0f",
    "PortMask": "0x00",
    "FCMask": "0x00",
    "UMaskExt": "0x00",
    "EventName": "UNC_M_CAS_COUNT.RD",
    "BriefDescription": "All DRAM read CAS commands issued (including underfills)",
    "PublicDescription": "Counts the total number of DRAM Read CAS commands, w/ and w/o auto-pre, issued on this channel.  This includes underfills.",
    "Counter": "0,1,2,3",
    "MSRValue": "0x00",
    "ELLC": "0",
    "Filter": "na",
    "ExtSel": "0",
    "Deprecated": "0",
    "FILTER_VALUE": "0",
    "CounterType": "PGMABLE"
  },
  {
    "Unit": "iMC",
    "EventCode": "0x04",
    "UMask": "0x30",
    "PortMask": "0x00",
    "FCMask": "0x00",
    "UMaskExt": "0x00",
    "EventName": "UNC_M_CAS_COUNT.WR",
    "BriefDescription": "All DRAM write CAS commands issued",
    "PublicDescription": "Counts the total number of DRAM Write CAS commands issued, w/ and w/o auto-pre, on this channel.",
    "Counter": "0,1,2,3",
    "MSRValue": "0x00",
    "ELLC": "0",
    "Filter": "na",
    "ExtSel": "0",
    "Deprecated": "0",
    "FILTER_VALUE": "0",
    "CounterType": "PGMABLE"
  },
  {
    "Unit": "iMC",
    "EventCode": "0x02",
    "UMask": "0x10",
    "PortMask": "0x00",
    "FCMask": "0x00",
    "UMaskExt": "0x00",
    "EventName": "UNC_M_PRE_COUNT.PGT",
    "BriefDescription": "DRAM Precharge commands. : Precharge due to page table",
    "PublicDescription": "DRAM Precharge commands. : Precharge due to page table : Counts the number of DRAM Precharge commands sent on this channel. : Prechages from Page Table",
    "Counter": "0,1,2,3",
    "MSRValue": "0x00",
    "ELLC": "0",
    "Filter": "na",
    "ExtSel": "0",
    "Deprecated": "0",
    "FILTER_VALUE": "0",
    "CounterType": "PGMABLE"
  },
  {
    "Unit": "iMC",
    "EventCode": "0x00",
    "UMask": "0x00",
    "PortMask": "0x00",
    "FCMask": "0x00",
    "UMaskExt": "0x00",
    "EventName": "UNC_M_CLOCKTICKS",
    "BriefDescription": "DRAM Clockticks",
    "PublicDescription": "Clockticks of the integrated memory controller (IMC)",
    "Counter": "0,1,2,3",
    "MSRValue": "0x00",
    "ELLC": "0",
    "Filter": "na",
    "ExtSel": "0",
    "Deprecated": "0",
    "FILTER_VALUE": "0",
    "CounterType": "PGMABLE"
  },
  {
    "Unit": "iMC",
    "EventCode": "0x02",
    "UMask": "0x1C",
    "PortMask": "0x00",
    "FCMask": "0x00",
    "UMaskExt": "0x00",
    "EventName": "UNC_M_PRE_COUNT.ALL",
    "BriefDescription": "DRAM Precharge commands.",
    "PublicDescription": "DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel.",
    "Counter": "0,1,2,3",
    "MSRValue": "0x00",
    "ELLC": "0",
    "Filter": "na",
    "ExtSel": "0",
    "Deprecated": "0",
    "FILTER_VALUE": "0",
    "CounterType": "PGMABLE"
  },
  {
    "Unit": "M2M",
    "EventCode": "0x00",
    "UMask": "0x00",
    "PortMask": "0x00",
    "FCMask": "0x00",
    "UMaskExt": "0x00",
    "EventName": "UNC_M2M_CLOCKTICKS",
    "BriefDescription": "Clockticks of the mesh to memory (M2M)",
    "PublicDescription": "Clockticks of the mesh to memory (M2M)",
    "Counter": "0,1,2,3",
    "MSRValue": "0x00",
    "ELLC": "0",
    "Filter": "na",
    "ExtSel": "0",
    "Deprecated": "0",
    "FILTER_VALUE": "0",
    "CounterType": "PGMABLE"
  },
  {
    "Unit": "M2PCIe",
    "EventCode": "0x01",
    "UMask": "0x00",
    "PortMask": "0x00",
    "FCMask": "0x00",
    "UMaskExt": "0x00",
    "EventName": "UNC_M2P_CLOCKTICKS",
    "BriefDescription": "Clockticks of the mesh to PCI (M2P)",
    "PublicDescription": "Clockticks of the mesh to PCI (M2P)",
    "Counter": "0,1,2,3",
    "MSRValue": "0x00",
    "ELLC": "0",
    "Filter": "na",
    "ExtSel": "0",
    "Deprecated": "0",
    "FILTER_VALUE": "0",
    "CounterType": "PGMABLE"
  },
  {
    "Unit": "UBOX",
    "EventCode": "0x00",
    "UMask": "0x01",
    "PortMask": "0x00",
    "FCMask": "0x00",
    "UMaskExt": "0x00",
    "EventName": "UNC_U_CLOCKTICKS",
    "BriefDescription": "Clockticks in the UBOX using a dedicated 48-bit Fixed Counter",
    "PublicDescription": "Clockticks in the UBOX using a dedicated 48-bit Fixed Counter",
    "Counter": "FIXED",
    "MSRValue": "0x00",
    "ELLC": "0",
    "Filter": "na",
    "ExtSel": "0",
    "Deprecated": "0",
    "FILTER_VALUE": "0",
    "CounterType": "FIXED"
  },
  {
    "Unit": "PCU",
    "EventCode": "0x00",
    "UMask": "0x00",
    "PortMask": "0x00",
    "FCMask": "0x00",
    "UMaskExt": "0x00",
    "EventName": "UNC_P_CLOCKTICKS",
    "BriefDescription": "Clockticks of the power control unit (PCU)",
    "PublicDescription": "Clockticks of the power control unit (PCU)",
    "Counter": "0,1,2,3",
    "MSRValue": "0x00",
    "ELLC": "0",
    "Filter": "na",
    "ExtSel": "0",
    "Deprecated": "0",
    "FILTER_VALUE": "0",
    "CounterType": "PGMABLE"
  }
]