Searched refs:gpio_mmio_base (Results 1 – 2 of 2) sorted by relevance
69 I915_WRITE(dev_priv->gpio_mmio_base + GMBUS0, 0); in intel_i2c_reset()209 bus->gpio_reg = dev_priv->gpio_mmio_base + gmbus_ports[pin - 1].reg; in intel_gpio_setup()240 int reg_offset = dev_priv->gpio_mmio_base; in gmbus_wait_hw_status()271 int reg_offset = dev_priv->gpio_mmio_base; in gmbus_wait_idle()296 int reg_offset = dev_priv->gpio_mmio_base; in gmbus_xfer_read()328 int reg_offset = dev_priv->gpio_mmio_base; in gmbus_xfer_write()378 int reg_offset = dev_priv->gpio_mmio_base; in gmbus_xfer_index_read()422 reg_offset = dev_priv->gpio_mmio_base; in gmbus_xfer()539 dev_priv->gpio_mmio_base = PCH_GPIOA - GPIOA; in intel_setup_gmbus()541 dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE; in intel_setup_gmbus()[all …]
1036 uint32_t gpio_mmio_base; member