Searched refs:dram (Results 1 – 8 of 8) sorted by relevance
337 engine=serd.cpu.intel.nb.fbd.ch@dram-channel;339 prop fault.memory.intel.fbd.ch@dram-channel (1)->340 ereport.cpu.intel.nb.fbd.ch@dram-channel;342 prop fault.memory.intel.fbd.ch@dram-channel (0)->348 engine=serd.cpu.intel.nb.fbd_otf@dram-channel;351 ereport.cpu.intel.nb.fbd.otf@dram-channel;364 memory-controller/dram-channel {within(12s)};458 chip/memory-controller/dram-channel/dimm/rank530 chip/memory-controller/dram-channel;573 chip/memory-controller/dram-channel/dimm;[all …]
47 * hc:///motherboard/chip/memory-controller/dram-channel/chip-select77 #define CSPATH chip/memory-controller/dram-channel/chip-select107 * | includes a chip/memory-controller/dram-channel/chip-select |
364 * a bit indicating which dram controller channel (A or B) experienced369 event fault.cpu.amd.dramchannel@chip/memory-controller/dram-channel, response=0;371 prop fault.cpu.amd.dramchannel@chip/memory-controller/dram-channel[y] (0)->
46 int dram; member
97 dram 1|16 oz98 dr dram
1695 uint32_t dram, interleave; in imc_sad_read_dram_rules() local1698 dram = pci_config_get32(sad->isad_dram->istub_cfgspace, off); in imc_sad_read_dram_rules()1702 if (dram == PCI_EINVAL32 || interleave == PCI_EINVAL32) { in imc_sad_read_dram_rules()1707 imc_sad_fill_rule(imc, sad, rule, dram); in imc_sad_read_dram_rules()
7125 dram
7123 dram