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Searched refs:VLV_DISPLAY_BASE (Results 1 – 4 of 4) sorted by relevance

/gfx-drm/usr/src/uts/intel/io/i915/
H A Di915_reg.h477 #define DPIO_CTL (VLV_DISPLAY_BASE + 0x2110)
811 #define VLV_DISPLAY_BASE 0x180000 macro
820 #define VLV_IIR_RW (VLV_DISPLAY_BASE + 0x2084)
821 #define VLV_IER (VLV_DISPLAY_BASE + 0x20a0)
822 #define VLV_IIR (VLV_DISPLAY_BASE + 0x20a4)
823 #define VLV_IMR (VLV_DISPLAY_BASE + 0x20a8)
824 #define VLV_ISR (VLV_DISPLAY_BASE + 0x20ac)
825 #define VLV_PCBR (VLV_DISPLAY_BASE + 0x2120)
1458 #define MI_ARB_VLV (VLV_DISPLAY_BASE + 0x6504)
1870 #define VLV_ADPA (VLV_DISPLAY_BASE + ADPA)
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H A Dintel_i2c.c541 dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE; in intel_setup_gmbus()
H A Di915_drv.c265 .display_mmio_offset = VLV_DISPLAY_BASE,
273 .display_mmio_offset = VLV_DISPLAY_BASE,
H A Dintel_display.c9104 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED) in intel_setup_outputs()
9105 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C); in intel_setup_outputs()
9107 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) { in intel_setup_outputs()
9108 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB, in intel_setup_outputs()
9110 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED) in intel_setup_outputs()
9111 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B); in intel_setup_outputs()