147dc10d7SGordon Ross /*
247dc10d7SGordon Ross * Copyright (c) 2006, 2016, Oracle and/or its affiliates. All rights reserved.
347dc10d7SGordon Ross */
447dc10d7SGordon Ross
547dc10d7SGordon Ross /*
647dc10d7SGordon Ross * Copyright (c) 2006-2007, 2013, Intel Corporation
747dc10d7SGordon Ross *
847dc10d7SGordon Ross * Permission is hereby granted, free of charge, to any person obtaining a
947dc10d7SGordon Ross * copy of this software and associated documentation files (the "Software"),
1047dc10d7SGordon Ross * to deal in the Software without restriction, including without limitation
1147dc10d7SGordon Ross * the rights to use, copy, modify, merge, publish, distribute, sublicense,
1247dc10d7SGordon Ross * and/or sell copies of the Software, and to permit persons to whom the
1347dc10d7SGordon Ross * Software is furnished to do so, subject to the following conditions:
1447dc10d7SGordon Ross *
1547dc10d7SGordon Ross * The above copyright notice and this permission notice (including the next
1647dc10d7SGordon Ross * paragraph) shall be included in all copies or substantial portions of the
1747dc10d7SGordon Ross * Software.
1847dc10d7SGordon Ross *
1947dc10d7SGordon Ross * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
2047dc10d7SGordon Ross * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
2147dc10d7SGordon Ross * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
2247dc10d7SGordon Ross * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
2347dc10d7SGordon Ross * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
2447dc10d7SGordon Ross * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
2547dc10d7SGordon Ross * DEALINGS IN THE SOFTWARE.
2647dc10d7SGordon Ross *
2747dc10d7SGordon Ross * Authors:
2847dc10d7SGordon Ross * Eric Anholt <eric@anholt.net>
2947dc10d7SGordon Ross */
3047dc10d7SGordon Ross
3147dc10d7SGordon Ross #include "drm_edid.h"
3247dc10d7SGordon Ross #include "drmP.h"
3347dc10d7SGordon Ross #include "intel_drv.h"
3447dc10d7SGordon Ross #include "i915_drm.h"
3547dc10d7SGordon Ross #include "i915_drv.h"
3647dc10d7SGordon Ross #include "drm_dp_helper.h"
3747dc10d7SGordon Ross
3847dc10d7SGordon Ross #include "drm_crtc_helper.h"
3947dc10d7SGordon Ross
4047dc10d7SGordon Ross bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
4147dc10d7SGordon Ross static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
4247dc10d7SGordon Ross
4347dc10d7SGordon Ross typedef struct {
4447dc10d7SGordon Ross int min, max;
4547dc10d7SGordon Ross } intel_range_t;
4647dc10d7SGordon Ross
4747dc10d7SGordon Ross typedef struct {
4847dc10d7SGordon Ross int dot_limit;
4947dc10d7SGordon Ross int p2_slow, p2_fast;
5047dc10d7SGordon Ross } intel_p2_t;
5147dc10d7SGordon Ross
5247dc10d7SGordon Ross #define INTEL_P2_NUM 2
5347dc10d7SGordon Ross typedef struct intel_limit intel_limit_t;
5447dc10d7SGordon Ross struct intel_limit {
5547dc10d7SGordon Ross intel_range_t dot, vco, n, m, m1, m2, p, p1;
5647dc10d7SGordon Ross intel_p2_t p2;
5747dc10d7SGordon Ross };
5847dc10d7SGordon Ross
5947dc10d7SGordon Ross /* FDI */
6047dc10d7SGordon Ross #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
6147dc10d7SGordon Ross
6247dc10d7SGordon Ross int
intel_pch_rawclk(struct drm_device * dev)6347dc10d7SGordon Ross intel_pch_rawclk(struct drm_device *dev)
6447dc10d7SGordon Ross {
6547dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
6647dc10d7SGordon Ross
6747dc10d7SGordon Ross WARN_ON(!HAS_PCH_SPLIT(dev));
6847dc10d7SGordon Ross
6947dc10d7SGordon Ross return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
7047dc10d7SGordon Ross }
7147dc10d7SGordon Ross
7247dc10d7SGordon Ross static inline u32 /* units of 100MHz */
intel_fdi_link_freq(struct drm_device * dev)7347dc10d7SGordon Ross intel_fdi_link_freq(struct drm_device *dev)
7447dc10d7SGordon Ross {
7547dc10d7SGordon Ross if (IS_GEN5(dev)) {
7647dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
7747dc10d7SGordon Ross return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
7847dc10d7SGordon Ross } else
7947dc10d7SGordon Ross return 27;
8047dc10d7SGordon Ross }
8147dc10d7SGordon Ross
8247dc10d7SGordon Ross static const intel_limit_t intel_limits_i8xx_dvo = {
8347dc10d7SGordon Ross .dot = { .min = 25000, .max = 350000 },
8447dc10d7SGordon Ross .vco = { .min = 930000, .max = 1400000 },
8547dc10d7SGordon Ross .n = { .min = 3, .max = 16 },
8647dc10d7SGordon Ross .m = { .min = 96, .max = 140 },
8747dc10d7SGordon Ross .m1 = { .min = 18, .max = 26 },
8847dc10d7SGordon Ross .m2 = { .min = 6, .max = 16 },
8947dc10d7SGordon Ross .p = { .min = 4, .max = 128 },
9047dc10d7SGordon Ross .p1 = { .min = 2, .max = 33 },
9147dc10d7SGordon Ross .p2 = { .dot_limit = 165000,
9247dc10d7SGordon Ross .p2_slow = 4, .p2_fast = 2 },
9347dc10d7SGordon Ross };
9447dc10d7SGordon Ross
9547dc10d7SGordon Ross static const intel_limit_t intel_limits_i8xx_lvds = {
9647dc10d7SGordon Ross .dot = { .min = 25000, .max = 350000 },
9747dc10d7SGordon Ross .vco = { .min = 930000, .max = 1400000 },
9847dc10d7SGordon Ross .n = { .min = 3, .max = 16 },
9947dc10d7SGordon Ross .m = { .min = 96, .max = 140 },
10047dc10d7SGordon Ross .m1 = { .min = 18, .max = 26 },
10147dc10d7SGordon Ross .m2 = { .min = 6, .max = 16 },
10247dc10d7SGordon Ross .p = { .min = 4, .max = 128 },
10347dc10d7SGordon Ross .p1 = { .min = 1, .max = 6 },
10447dc10d7SGordon Ross .p2 = { .dot_limit = 165000,
10547dc10d7SGordon Ross .p2_slow = 14, .p2_fast = 7 },
10647dc10d7SGordon Ross };
10747dc10d7SGordon Ross
10847dc10d7SGordon Ross static const intel_limit_t intel_limits_i9xx_sdvo = {
10947dc10d7SGordon Ross .dot = { .min = 20000, .max = 400000 },
11047dc10d7SGordon Ross .vco = { .min = 1400000, .max = 2800000 },
11147dc10d7SGordon Ross .n = { .min = 1, .max = 6 },
11247dc10d7SGordon Ross .m = { .min = 70, .max = 120 },
11347dc10d7SGordon Ross .m1 = { .min = 8, .max = 18 },
11447dc10d7SGordon Ross .m2 = { .min = 3, .max = 7 },
11547dc10d7SGordon Ross .p = { .min = 5, .max = 80 },
11647dc10d7SGordon Ross .p1 = { .min = 1, .max = 8 },
11747dc10d7SGordon Ross .p2 = { .dot_limit = 200000,
11847dc10d7SGordon Ross .p2_slow = 10, .p2_fast = 5 },
11947dc10d7SGordon Ross };
12047dc10d7SGordon Ross
12147dc10d7SGordon Ross static const intel_limit_t intel_limits_i9xx_lvds = {
12247dc10d7SGordon Ross .dot = { .min = 20000, .max = 400000 },
12347dc10d7SGordon Ross .vco = { .min = 1400000, .max = 2800000 },
12447dc10d7SGordon Ross .n = { .min = 1, .max = 6 },
12547dc10d7SGordon Ross .m = { .min = 70, .max = 120 },
12647dc10d7SGordon Ross .m1 = { .min = 8, .max = 18 },
12747dc10d7SGordon Ross .m2 = { .min = 3, .max = 7 },
12847dc10d7SGordon Ross .p = { .min = 7, .max = 98 },
12947dc10d7SGordon Ross .p1 = { .min = 1, .max = 8 },
13047dc10d7SGordon Ross .p2 = { .dot_limit = 112000,
13147dc10d7SGordon Ross .p2_slow = 14, .p2_fast = 7 },
13247dc10d7SGordon Ross };
13347dc10d7SGordon Ross
13447dc10d7SGordon Ross
13547dc10d7SGordon Ross static const intel_limit_t intel_limits_g4x_sdvo = {
13647dc10d7SGordon Ross .dot = { .min = 25000, .max = 270000 },
13747dc10d7SGordon Ross .vco = { .min = 1750000, .max = 3500000},
13847dc10d7SGordon Ross .n = { .min = 1, .max = 4 },
13947dc10d7SGordon Ross .m = { .min = 104, .max = 138 },
14047dc10d7SGordon Ross .m1 = { .min = 17, .max = 23 },
14147dc10d7SGordon Ross .m2 = { .min = 5, .max = 11 },
14247dc10d7SGordon Ross .p = { .min = 10, .max = 30 },
14347dc10d7SGordon Ross .p1 = { .min = 1, .max = 3},
14447dc10d7SGordon Ross .p2 = { .dot_limit = 270000,
14547dc10d7SGordon Ross .p2_slow = 10,
14647dc10d7SGordon Ross .p2_fast = 10
14747dc10d7SGordon Ross },
14847dc10d7SGordon Ross };
14947dc10d7SGordon Ross
15047dc10d7SGordon Ross static const intel_limit_t intel_limits_g4x_hdmi = {
15147dc10d7SGordon Ross .dot = { .min = 22000, .max = 400000 },
15247dc10d7SGordon Ross .vco = { .min = 1750000, .max = 3500000},
15347dc10d7SGordon Ross /* n.min 1->2 fix high resolution issue */
15447dc10d7SGordon Ross .n = { .min = 2, .max = 4 },
15547dc10d7SGordon Ross .m = { .min = 104, .max = 138 },
15647dc10d7SGordon Ross .m1 = { .min = 16, .max = 23 },
15747dc10d7SGordon Ross .m2 = { .min = 5, .max = 11 },
15847dc10d7SGordon Ross .p = { .min = 5, .max = 80 },
15947dc10d7SGordon Ross .p1 = { .min = 1, .max = 8},
16047dc10d7SGordon Ross .p2 = { .dot_limit = 165000,
16147dc10d7SGordon Ross .p2_slow = 10, .p2_fast = 5 },
16247dc10d7SGordon Ross };
16347dc10d7SGordon Ross
16447dc10d7SGordon Ross static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
16547dc10d7SGordon Ross .dot = { .min = 20000, .max = 115000 },
16647dc10d7SGordon Ross .vco = { .min = 1750000, .max = 3500000 },
16747dc10d7SGordon Ross .n = { .min = 1, .max = 3 },
16847dc10d7SGordon Ross .m = { .min = 104, .max = 138 },
16947dc10d7SGordon Ross .m1 = { .min = 17, .max = 23 },
17047dc10d7SGordon Ross .m2 = { .min = 5, .max = 11 },
17147dc10d7SGordon Ross .p = { .min = 28, .max = 112 },
17247dc10d7SGordon Ross .p1 = { .min = 2, .max = 8 },
17347dc10d7SGordon Ross .p2 = { .dot_limit = 0,
17447dc10d7SGordon Ross .p2_slow = 14, .p2_fast = 14
17547dc10d7SGordon Ross },
17647dc10d7SGordon Ross };
17747dc10d7SGordon Ross
17847dc10d7SGordon Ross static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
17947dc10d7SGordon Ross .dot = { .min = 80000, .max = 224000 },
18047dc10d7SGordon Ross .vco = { .min = 1750000, .max = 3500000 },
18147dc10d7SGordon Ross .n = { .min = 1, .max = 3 },
18247dc10d7SGordon Ross .m = { .min = 104, .max = 138 },
18347dc10d7SGordon Ross .m1 = { .min = 17, .max = 23 },
18447dc10d7SGordon Ross .m2 = { .min = 5, .max = 11 },
18547dc10d7SGordon Ross .p = { .min = 14, .max = 42 },
18647dc10d7SGordon Ross .p1 = { .min = 2, .max = 6 },
18747dc10d7SGordon Ross .p2 = { .dot_limit = 0,
18847dc10d7SGordon Ross .p2_slow = 7, .p2_fast = 7
18947dc10d7SGordon Ross },
19047dc10d7SGordon Ross };
19147dc10d7SGordon Ross
19247dc10d7SGordon Ross static const intel_limit_t intel_limits_pineview_sdvo = {
19347dc10d7SGordon Ross .dot = { .min = 20000, .max = 400000},
19447dc10d7SGordon Ross .vco = { .min = 1700000, .max = 3500000 },
19547dc10d7SGordon Ross /* Pineview's Ncounter is a ring counter */
19647dc10d7SGordon Ross .n = { .min = 3, .max = 6 },
19747dc10d7SGordon Ross .m = { .min = 2, .max = 256 },
19847dc10d7SGordon Ross /* Pineview only has one combined m divider, which we treat as m2. */
19947dc10d7SGordon Ross .m1 = { .min = 0, .max = 0 },
20047dc10d7SGordon Ross .m2 = { .min = 0, .max = 254 },
20147dc10d7SGordon Ross .p = { .min = 5, .max = 80 },
20247dc10d7SGordon Ross .p1 = { .min = 1, .max = 8 },
20347dc10d7SGordon Ross .p2 = { .dot_limit = 200000,
20447dc10d7SGordon Ross .p2_slow = 10, .p2_fast = 5 },
20547dc10d7SGordon Ross };
20647dc10d7SGordon Ross
20747dc10d7SGordon Ross static const intel_limit_t intel_limits_pineview_lvds = {
20847dc10d7SGordon Ross .dot = { .min = 20000, .max = 400000 },
20947dc10d7SGordon Ross .vco = { .min = 1700000, .max = 3500000 },
21047dc10d7SGordon Ross .n = { .min = 3, .max = 6 },
21147dc10d7SGordon Ross .m = { .min = 2, .max = 256 },
21247dc10d7SGordon Ross .m1 = { .min = 0, .max = 0 },
21347dc10d7SGordon Ross .m2 = { .min = 0, .max = 254 },
21447dc10d7SGordon Ross .p = { .min = 7, .max = 112 },
21547dc10d7SGordon Ross .p1 = { .min = 1, .max = 8 },
21647dc10d7SGordon Ross .p2 = { .dot_limit = 112000,
21747dc10d7SGordon Ross .p2_slow = 14, .p2_fast = 14 },
21847dc10d7SGordon Ross };
21947dc10d7SGordon Ross
22047dc10d7SGordon Ross /* Ironlake / Sandybridge
22147dc10d7SGordon Ross *
22247dc10d7SGordon Ross * We calculate clock using (register_value + 2) for N/M1/M2, so here
22347dc10d7SGordon Ross * the range value for them is (actual_value - 2).
22447dc10d7SGordon Ross */
22547dc10d7SGordon Ross static const intel_limit_t intel_limits_ironlake_dac = {
22647dc10d7SGordon Ross .dot = { .min = 25000, .max = 350000 },
22747dc10d7SGordon Ross .vco = { .min = 1760000, .max = 3510000 },
22847dc10d7SGordon Ross /* n.min 1->2 fix high resolution issue */
22947dc10d7SGordon Ross .n = { .min = 2, .max = 5 },
23047dc10d7SGordon Ross .m = { .min = 79, .max = 127 },
23147dc10d7SGordon Ross .m1 = { .min = 12, .max = 22 },
23247dc10d7SGordon Ross .m2 = { .min = 5, .max = 9 },
23347dc10d7SGordon Ross .p = { .min = 5, .max = 80 },
23447dc10d7SGordon Ross .p1 = { .min = 1, .max = 8 },
23547dc10d7SGordon Ross .p2 = { .dot_limit = 225000,
23647dc10d7SGordon Ross .p2_slow = 10, .p2_fast = 5 },
23747dc10d7SGordon Ross };
23847dc10d7SGordon Ross
23947dc10d7SGordon Ross static const intel_limit_t intel_limits_ironlake_single_lvds = {
24047dc10d7SGordon Ross .dot = { .min = 25000, .max = 350000 },
24147dc10d7SGordon Ross .vco = { .min = 1760000, .max = 3510000 },
24247dc10d7SGordon Ross .n = { .min = 1, .max = 3 },
24347dc10d7SGordon Ross .m = { .min = 79, .max = 118 },
24447dc10d7SGordon Ross .m1 = { .min = 12, .max = 22 },
24547dc10d7SGordon Ross .m2 = { .min = 5, .max = 9 },
24647dc10d7SGordon Ross .p = { .min = 28, .max = 112 },
24747dc10d7SGordon Ross .p1 = { .min = 2, .max = 8 },
24847dc10d7SGordon Ross .p2 = { .dot_limit = 225000,
24947dc10d7SGordon Ross .p2_slow = 14, .p2_fast = 14 },
25047dc10d7SGordon Ross };
25147dc10d7SGordon Ross
25247dc10d7SGordon Ross static const intel_limit_t intel_limits_ironlake_dual_lvds = {
25347dc10d7SGordon Ross .dot = { .min = 25000, .max = 350000 },
25447dc10d7SGordon Ross .vco = { .min = 1760000, .max = 3510000 },
25547dc10d7SGordon Ross .n = { .min = 1, .max = 3 },
25647dc10d7SGordon Ross .m = { .min = 79, .max = 127 },
25747dc10d7SGordon Ross .m1 = { .min = 12, .max = 22 },
25847dc10d7SGordon Ross .m2 = { .min = 5, .max = 9 },
25947dc10d7SGordon Ross .p = { .min = 14, .max = 56 },
26047dc10d7SGordon Ross .p1 = { .min = 2, .max = 8 },
26147dc10d7SGordon Ross .p2 = { .dot_limit = 225000,
26247dc10d7SGordon Ross .p2_slow = 7, .p2_fast = 7 },
26347dc10d7SGordon Ross };
26447dc10d7SGordon Ross
26547dc10d7SGordon Ross /* LVDS 100mhz refclk limits. */
26647dc10d7SGordon Ross static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
26747dc10d7SGordon Ross .dot = { .min = 25000, .max = 350000 },
26847dc10d7SGordon Ross .vco = { .min = 1760000, .max = 3510000 },
26947dc10d7SGordon Ross .n = { .min = 1, .max = 2 },
27047dc10d7SGordon Ross .m = { .min = 79, .max = 126 },
27147dc10d7SGordon Ross .m1 = { .min = 12, .max = 22 },
27247dc10d7SGordon Ross .m2 = { .min = 5, .max = 9 },
27347dc10d7SGordon Ross .p = { .min = 28, .max = 112 },
27447dc10d7SGordon Ross .p1 = { .min = 2,.max = 8 },
27547dc10d7SGordon Ross .p2 = { .dot_limit = 225000,
27647dc10d7SGordon Ross .p2_slow = 14, .p2_fast = 14 },
27747dc10d7SGordon Ross };
27847dc10d7SGordon Ross
27947dc10d7SGordon Ross static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
28047dc10d7SGordon Ross .dot = { .min = 25000, .max = 350000 },
28147dc10d7SGordon Ross .vco = { .min = 1760000, .max = 3510000 },
28247dc10d7SGordon Ross .n = { .min = 1, .max = 3 },
28347dc10d7SGordon Ross .m = { .min = 79, .max = 126 },
28447dc10d7SGordon Ross .m1 = { .min = 12, .max = 22 },
28547dc10d7SGordon Ross .m2 = { .min = 5, .max = 9 },
28647dc10d7SGordon Ross .p = { .min = 14, .max = 42 },
28747dc10d7SGordon Ross .p1 = { .min = 2,.max = 6 },
28847dc10d7SGordon Ross .p2 = { .dot_limit = 225000,
28947dc10d7SGordon Ross .p2_slow = 7, .p2_fast = 7 },
29047dc10d7SGordon Ross };
29147dc10d7SGordon Ross
29247dc10d7SGordon Ross static const intel_limit_t intel_limits_vlv_dac = {
29347dc10d7SGordon Ross .dot = { .min = 25000, .max = 270000 },
29447dc10d7SGordon Ross .vco = { .min = 4000000, .max = 6000000 },
29547dc10d7SGordon Ross .n = { .min = 1, .max = 7 },
29647dc10d7SGordon Ross .m = { .min = 22, .max = 450 }, /* guess */
29747dc10d7SGordon Ross .m1 = { .min = 2, .max = 3 },
29847dc10d7SGordon Ross .m2 = { .min = 11, .max = 156 },
29947dc10d7SGordon Ross .p = { .min = 10, .max = 30 },
30047dc10d7SGordon Ross .p1 = { .min = 1, .max = 3 },
30147dc10d7SGordon Ross .p2 = { .dot_limit = 270000,
30247dc10d7SGordon Ross .p2_slow = 2, .p2_fast = 20 },
30347dc10d7SGordon Ross };
30447dc10d7SGordon Ross
30547dc10d7SGordon Ross static const intel_limit_t intel_limits_vlv_hdmi = {
30647dc10d7SGordon Ross .dot = { .min = 25000, .max = 270000 },
30747dc10d7SGordon Ross .vco = { .min = 4000000, .max = 6000000 },
30847dc10d7SGordon Ross .n = { .min = 1, .max = 7 },
30947dc10d7SGordon Ross .m = { .min = 60, .max = 300 }, /* guess */
31047dc10d7SGordon Ross .m1 = { .min = 2, .max = 3 },
31147dc10d7SGordon Ross .m2 = { .min = 11, .max = 156 },
31247dc10d7SGordon Ross .p = { .min = 10, .max = 30 },
31347dc10d7SGordon Ross .p1 = { .min = 2, .max = 3 },
31447dc10d7SGordon Ross .p2 = { .dot_limit = 270000,
31547dc10d7SGordon Ross .p2_slow = 2, .p2_fast = 20 },
31647dc10d7SGordon Ross };
31747dc10d7SGordon Ross
31847dc10d7SGordon Ross static const intel_limit_t intel_limits_vlv_dp = {
31947dc10d7SGordon Ross .dot = { .min = 25000, .max = 270000 },
32047dc10d7SGordon Ross .vco = { .min = 4000000, .max = 6000000 },
32147dc10d7SGordon Ross .n = { .min = 1, .max = 7 },
32247dc10d7SGordon Ross .m = { .min = 22, .max = 450 },
32347dc10d7SGordon Ross .m1 = { .min = 2, .max = 3 },
32447dc10d7SGordon Ross .m2 = { .min = 11, .max = 156 },
32547dc10d7SGordon Ross .p = { .min = 10, .max = 30 },
32647dc10d7SGordon Ross .p1 = { .min = 1, .max = 3 },
32747dc10d7SGordon Ross .p2 = { .dot_limit = 270000,
32847dc10d7SGordon Ross .p2_slow = 2, .p2_fast = 20 },
32947dc10d7SGordon Ross };
33047dc10d7SGordon Ross
intel_ironlake_limit(struct drm_crtc * crtc,int refclk)33147dc10d7SGordon Ross static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
33247dc10d7SGordon Ross int refclk)
33347dc10d7SGordon Ross {
33447dc10d7SGordon Ross struct drm_device *dev = crtc->dev;
33547dc10d7SGordon Ross const intel_limit_t *limit;
33647dc10d7SGordon Ross
33747dc10d7SGordon Ross if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
33847dc10d7SGordon Ross if (intel_is_dual_link_lvds(dev)) {
33947dc10d7SGordon Ross if (refclk == 100000)
34047dc10d7SGordon Ross limit = &intel_limits_ironlake_dual_lvds_100m;
34147dc10d7SGordon Ross else
34247dc10d7SGordon Ross limit = &intel_limits_ironlake_dual_lvds;
34347dc10d7SGordon Ross } else {
34447dc10d7SGordon Ross if (refclk == 100000)
34547dc10d7SGordon Ross limit = &intel_limits_ironlake_single_lvds_100m;
34647dc10d7SGordon Ross else
34747dc10d7SGordon Ross limit = &intel_limits_ironlake_single_lvds;
34847dc10d7SGordon Ross }
34947dc10d7SGordon Ross } else
35047dc10d7SGordon Ross limit = &intel_limits_ironlake_dac;
35147dc10d7SGordon Ross
35247dc10d7SGordon Ross return limit;
35347dc10d7SGordon Ross }
35447dc10d7SGordon Ross
intel_g4x_limit(struct drm_crtc * crtc)35547dc10d7SGordon Ross static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
35647dc10d7SGordon Ross {
35747dc10d7SGordon Ross struct drm_device *dev = crtc->dev;
35847dc10d7SGordon Ross const intel_limit_t *limit;
35947dc10d7SGordon Ross
36047dc10d7SGordon Ross if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
36147dc10d7SGordon Ross if (intel_is_dual_link_lvds(dev))
36247dc10d7SGordon Ross limit = &intel_limits_g4x_dual_channel_lvds;
36347dc10d7SGordon Ross else
36447dc10d7SGordon Ross limit = &intel_limits_g4x_single_channel_lvds;
36547dc10d7SGordon Ross } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
36647dc10d7SGordon Ross intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
36747dc10d7SGordon Ross limit = &intel_limits_g4x_hdmi;
36847dc10d7SGordon Ross } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
36947dc10d7SGordon Ross limit = &intel_limits_g4x_sdvo;
37047dc10d7SGordon Ross } else /* The option is for other outputs */
37147dc10d7SGordon Ross limit = &intel_limits_i9xx_sdvo;
37247dc10d7SGordon Ross
37347dc10d7SGordon Ross return limit;
37447dc10d7SGordon Ross }
37547dc10d7SGordon Ross
intel_limit(struct drm_crtc * crtc,int refclk)37647dc10d7SGordon Ross static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
37747dc10d7SGordon Ross {
37847dc10d7SGordon Ross struct drm_device *dev = crtc->dev;
37947dc10d7SGordon Ross const intel_limit_t *limit;
38047dc10d7SGordon Ross
38147dc10d7SGordon Ross if (HAS_PCH_SPLIT(dev))
38247dc10d7SGordon Ross limit = intel_ironlake_limit(crtc, refclk);
38347dc10d7SGordon Ross else if (IS_G4X(dev)) {
38447dc10d7SGordon Ross limit = intel_g4x_limit(crtc);
38547dc10d7SGordon Ross } else if (IS_PINEVIEW(dev)) {
38647dc10d7SGordon Ross if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
38747dc10d7SGordon Ross limit = &intel_limits_pineview_lvds;
38847dc10d7SGordon Ross else
38947dc10d7SGordon Ross limit = &intel_limits_pineview_sdvo;
39047dc10d7SGordon Ross } else if (IS_VALLEYVIEW(dev)) {
39147dc10d7SGordon Ross if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
39247dc10d7SGordon Ross limit = &intel_limits_vlv_dac;
39347dc10d7SGordon Ross else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
39447dc10d7SGordon Ross limit = &intel_limits_vlv_hdmi;
39547dc10d7SGordon Ross else
39647dc10d7SGordon Ross limit = &intel_limits_vlv_dp;
39747dc10d7SGordon Ross } else if (!IS_GEN2(dev)) {
39847dc10d7SGordon Ross if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
39947dc10d7SGordon Ross limit = &intel_limits_i9xx_lvds;
40047dc10d7SGordon Ross else
40147dc10d7SGordon Ross limit = &intel_limits_i9xx_sdvo;
40247dc10d7SGordon Ross } else {
40347dc10d7SGordon Ross if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
40447dc10d7SGordon Ross limit = &intel_limits_i8xx_lvds;
40547dc10d7SGordon Ross else
40647dc10d7SGordon Ross limit = &intel_limits_i8xx_dvo;
40747dc10d7SGordon Ross }
40847dc10d7SGordon Ross return limit;
40947dc10d7SGordon Ross }
41047dc10d7SGordon Ross
41147dc10d7SGordon Ross /* m1 is reserved as 0 in Pineview, n is a ring counter */
pineview_clock(int refclk,intel_clock_t * clock)41247dc10d7SGordon Ross static void pineview_clock(int refclk, intel_clock_t *clock)
41347dc10d7SGordon Ross {
41447dc10d7SGordon Ross clock->m = clock->m2 + 2;
41547dc10d7SGordon Ross clock->p = clock->p1 * clock->p2;
41647dc10d7SGordon Ross clock->vco = refclk * clock->m / clock->n;
41747dc10d7SGordon Ross clock->dot = clock->vco / clock->p;
41847dc10d7SGordon Ross }
41947dc10d7SGordon Ross
i9xx_dpll_compute_m(struct dpll * dpll)42047dc10d7SGordon Ross static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
42147dc10d7SGordon Ross {
42247dc10d7SGordon Ross return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
42347dc10d7SGordon Ross }
42447dc10d7SGordon Ross
i9xx_clock(int refclk,intel_clock_t * clock)42547dc10d7SGordon Ross static void i9xx_clock(int refclk, intel_clock_t *clock)
42647dc10d7SGordon Ross {
42747dc10d7SGordon Ross clock->m = i9xx_dpll_compute_m(clock);
42847dc10d7SGordon Ross clock->p = clock->p1 * clock->p2;
42947dc10d7SGordon Ross clock->vco = refclk * clock->m / (clock->n + 2);
43047dc10d7SGordon Ross clock->dot = clock->vco / clock->p;
43147dc10d7SGordon Ross }
43247dc10d7SGordon Ross
43347dc10d7SGordon Ross /**
43447dc10d7SGordon Ross * Returns whether any output on the specified pipe is of the specified type
43547dc10d7SGordon Ross */
intel_pipe_has_type(struct drm_crtc * crtc,int type)43647dc10d7SGordon Ross bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
43747dc10d7SGordon Ross {
43847dc10d7SGordon Ross struct drm_device *dev = crtc->dev;
43947dc10d7SGordon Ross struct intel_encoder *encoder;
44047dc10d7SGordon Ross
44147dc10d7SGordon Ross for_each_encoder_on_crtc(dev, crtc, encoder)
44247dc10d7SGordon Ross if (encoder->type == type)
44347dc10d7SGordon Ross return true;
44447dc10d7SGordon Ross
44547dc10d7SGordon Ross return false;
44647dc10d7SGordon Ross }
44747dc10d7SGordon Ross
44847dc10d7SGordon Ross #define INTELPllInvalid(s) { DRM_DEBUG_KMS(s); return false; }
44947dc10d7SGordon Ross /**
45047dc10d7SGordon Ross * Returns whether the given set of divisors are valid for a given refclk with
45147dc10d7SGordon Ross * the given connectors.
45247dc10d7SGordon Ross */
45347dc10d7SGordon Ross
intel_PLL_is_valid(struct drm_device * dev,const intel_limit_t * limit,const intel_clock_t * clock)45447dc10d7SGordon Ross static bool intel_PLL_is_valid(struct drm_device *dev,
45547dc10d7SGordon Ross const intel_limit_t *limit,
45647dc10d7SGordon Ross const intel_clock_t *clock)
45747dc10d7SGordon Ross {
45847dc10d7SGordon Ross if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
45947dc10d7SGordon Ross INTELPllInvalid ("p1 out of range\n");
46047dc10d7SGordon Ross if (clock->p < limit->p.min || limit->p.max < clock->p)
46147dc10d7SGordon Ross INTELPllInvalid ("p out of range\n");
46247dc10d7SGordon Ross if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
46347dc10d7SGordon Ross INTELPllInvalid ("m2 out of range\n");
46447dc10d7SGordon Ross if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
46547dc10d7SGordon Ross INTELPllInvalid ("m1 out of range\n");
46647dc10d7SGordon Ross if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
46747dc10d7SGordon Ross INTELPllInvalid ("m1 <= m2\n");
46847dc10d7SGordon Ross if (clock->m < limit->m.min || limit->m.max < clock->m)
46947dc10d7SGordon Ross INTELPllInvalid ("m out of range\n");
47047dc10d7SGordon Ross if (clock->n < limit->n.min || limit->n.max < clock->n)
47147dc10d7SGordon Ross INTELPllInvalid ("n out of range\n");
47247dc10d7SGordon Ross if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
47347dc10d7SGordon Ross INTELPllInvalid ("vco out of range\n");
47447dc10d7SGordon Ross /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
47547dc10d7SGordon Ross * connector, etc., rather than just a single range.
47647dc10d7SGordon Ross */
47747dc10d7SGordon Ross if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
47847dc10d7SGordon Ross INTELPllInvalid ("dot out of range\n");
47947dc10d7SGordon Ross
48047dc10d7SGordon Ross return true;
48147dc10d7SGordon Ross }
48247dc10d7SGordon Ross
48347dc10d7SGordon Ross static bool
i9xx_find_best_dpll(const intel_limit_t * limit,struct drm_crtc * crtc,int target,int refclk,intel_clock_t * match_clock,intel_clock_t * best_clock)48447dc10d7SGordon Ross i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
48547dc10d7SGordon Ross int target, int refclk, intel_clock_t *match_clock,
48647dc10d7SGordon Ross intel_clock_t *best_clock)
48747dc10d7SGordon Ross {
48847dc10d7SGordon Ross struct drm_device *dev = crtc->dev;
48947dc10d7SGordon Ross intel_clock_t clock;
49047dc10d7SGordon Ross int err = target;
49147dc10d7SGordon Ross
49247dc10d7SGordon Ross if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
49347dc10d7SGordon Ross /*
49447dc10d7SGordon Ross * For LVDS just rely on its current settings for dual-channel.
49547dc10d7SGordon Ross * We haven't figured out how to reliably set up different
49647dc10d7SGordon Ross * single/dual channel state, if we even can.
49747dc10d7SGordon Ross */
49847dc10d7SGordon Ross if (intel_is_dual_link_lvds(dev))
49947dc10d7SGordon Ross clock.p2 = limit->p2.p2_fast;
50047dc10d7SGordon Ross else
50147dc10d7SGordon Ross clock.p2 = limit->p2.p2_slow;
50247dc10d7SGordon Ross } else {
50347dc10d7SGordon Ross if (target < limit->p2.dot_limit)
50447dc10d7SGordon Ross clock.p2 = limit->p2.p2_slow;
50547dc10d7SGordon Ross else
50647dc10d7SGordon Ross clock.p2 = limit->p2.p2_fast;
50747dc10d7SGordon Ross }
50847dc10d7SGordon Ross
50947dc10d7SGordon Ross (void) memset (best_clock, 0, sizeof (*best_clock));
51047dc10d7SGordon Ross
51147dc10d7SGordon Ross for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
51247dc10d7SGordon Ross clock.m1++) {
51347dc10d7SGordon Ross for (clock.m2 = limit->m2.min;
51447dc10d7SGordon Ross clock.m2 <= limit->m2.max; clock.m2++) {
51547dc10d7SGordon Ross if (clock.m2 >= clock.m1)
51647dc10d7SGordon Ross break;
51747dc10d7SGordon Ross for (clock.n = limit->n.min;
51847dc10d7SGordon Ross clock.n <= limit->n.max; clock.n++) {
51947dc10d7SGordon Ross for (clock.p1 = limit->p1.min;
52047dc10d7SGordon Ross clock.p1 <= limit->p1.max; clock.p1++) {
52147dc10d7SGordon Ross int this_err;
52247dc10d7SGordon Ross
52347dc10d7SGordon Ross i9xx_clock(refclk, &clock);
52447dc10d7SGordon Ross if (!intel_PLL_is_valid(dev, limit,
52547dc10d7SGordon Ross &clock))
52647dc10d7SGordon Ross continue;
52747dc10d7SGordon Ross if (match_clock &&
52847dc10d7SGordon Ross clock.p != match_clock->p)
52947dc10d7SGordon Ross continue;
53047dc10d7SGordon Ross
53147dc10d7SGordon Ross this_err = abs(clock.dot - target);
53247dc10d7SGordon Ross if (this_err < err) {
53347dc10d7SGordon Ross *best_clock = clock;
53447dc10d7SGordon Ross err = this_err;
53547dc10d7SGordon Ross }
53647dc10d7SGordon Ross }
53747dc10d7SGordon Ross }
53847dc10d7SGordon Ross }
53947dc10d7SGordon Ross }
54047dc10d7SGordon Ross
54147dc10d7SGordon Ross return (err != target);
54247dc10d7SGordon Ross }
54347dc10d7SGordon Ross
54447dc10d7SGordon Ross static bool
pnv_find_best_dpll(const intel_limit_t * limit,struct drm_crtc * crtc,int target,int refclk,intel_clock_t * match_clock,intel_clock_t * best_clock)54547dc10d7SGordon Ross pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
54647dc10d7SGordon Ross int target, int refclk, intel_clock_t *match_clock,
54747dc10d7SGordon Ross intel_clock_t *best_clock)
54847dc10d7SGordon Ross {
54947dc10d7SGordon Ross struct drm_device *dev = crtc->dev;
55047dc10d7SGordon Ross intel_clock_t clock;
55147dc10d7SGordon Ross int err = target;
55247dc10d7SGordon Ross
55347dc10d7SGordon Ross if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
55447dc10d7SGordon Ross /*
55547dc10d7SGordon Ross * For LVDS just rely on its current settings for dual-channel.
55647dc10d7SGordon Ross * We haven't figured out how to reliably set up different
55747dc10d7SGordon Ross * single/dual channel state, if we even can.
55847dc10d7SGordon Ross */
55947dc10d7SGordon Ross if (intel_is_dual_link_lvds(dev))
56047dc10d7SGordon Ross clock.p2 = limit->p2.p2_fast;
56147dc10d7SGordon Ross else
56247dc10d7SGordon Ross clock.p2 = limit->p2.p2_slow;
56347dc10d7SGordon Ross } else {
56447dc10d7SGordon Ross if (target < limit->p2.dot_limit)
56547dc10d7SGordon Ross clock.p2 = limit->p2.p2_slow;
56647dc10d7SGordon Ross else
56747dc10d7SGordon Ross clock.p2 = limit->p2.p2_fast;
56847dc10d7SGordon Ross }
56947dc10d7SGordon Ross
57047dc10d7SGordon Ross (void) memset(best_clock, 0, sizeof(*best_clock));
57147dc10d7SGordon Ross
57247dc10d7SGordon Ross for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
57347dc10d7SGordon Ross clock.m1++) {
57447dc10d7SGordon Ross for (clock.m2 = limit->m2.min;
57547dc10d7SGordon Ross clock.m2 <= limit->m2.max; clock.m2++) {
57647dc10d7SGordon Ross for (clock.n = limit->n.min;
57747dc10d7SGordon Ross clock.n <= limit->n.max; clock.n++) {
57847dc10d7SGordon Ross for (clock.p1 = limit->p1.min;
57947dc10d7SGordon Ross clock.p1 <= limit->p1.max; clock.p1++) {
58047dc10d7SGordon Ross int this_err;
58147dc10d7SGordon Ross
58247dc10d7SGordon Ross pineview_clock(refclk, &clock);
58347dc10d7SGordon Ross if (!intel_PLL_is_valid(dev, limit,
58447dc10d7SGordon Ross &clock))
58547dc10d7SGordon Ross continue;
58647dc10d7SGordon Ross if (match_clock &&
58747dc10d7SGordon Ross clock.p != match_clock->p)
58847dc10d7SGordon Ross continue;
58947dc10d7SGordon Ross
59047dc10d7SGordon Ross this_err = abs(clock.dot - target);
59147dc10d7SGordon Ross if (this_err < err) {
59247dc10d7SGordon Ross *best_clock = clock;
59347dc10d7SGordon Ross err = this_err;
59447dc10d7SGordon Ross }
59547dc10d7SGordon Ross }
59647dc10d7SGordon Ross }
59747dc10d7SGordon Ross }
59847dc10d7SGordon Ross }
59947dc10d7SGordon Ross
60047dc10d7SGordon Ross return (err != target);
60147dc10d7SGordon Ross }
60247dc10d7SGordon Ross
60347dc10d7SGordon Ross static bool
g4x_find_best_dpll(const intel_limit_t * limit,struct drm_crtc * crtc,int target,int refclk,intel_clock_t * match_clock,intel_clock_t * best_clock)60447dc10d7SGordon Ross g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
60547dc10d7SGordon Ross int target, int refclk, intel_clock_t *match_clock,
60647dc10d7SGordon Ross intel_clock_t *best_clock)
60747dc10d7SGordon Ross {
60847dc10d7SGordon Ross struct drm_device *dev = crtc->dev;
60947dc10d7SGordon Ross intel_clock_t clock;
61047dc10d7SGordon Ross int max_n;
61147dc10d7SGordon Ross bool found;
61247dc10d7SGordon Ross /* approximately equals target * 0.00585 */
61347dc10d7SGordon Ross int err_most = (target >> 8) + (target >> 9);
61447dc10d7SGordon Ross found = false;
61547dc10d7SGordon Ross
61647dc10d7SGordon Ross if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
61747dc10d7SGordon Ross if (intel_is_dual_link_lvds(dev))
61847dc10d7SGordon Ross clock.p2 = limit->p2.p2_fast;
61947dc10d7SGordon Ross else
62047dc10d7SGordon Ross clock.p2 = limit->p2.p2_slow;
62147dc10d7SGordon Ross } else {
62247dc10d7SGordon Ross if (target < limit->p2.dot_limit)
62347dc10d7SGordon Ross clock.p2 = limit->p2.p2_slow;
62447dc10d7SGordon Ross else
62547dc10d7SGordon Ross clock.p2 = limit->p2.p2_fast;
62647dc10d7SGordon Ross }
62747dc10d7SGordon Ross
62847dc10d7SGordon Ross (void) memset(best_clock, 0, sizeof(*best_clock));
62947dc10d7SGordon Ross max_n = limit->n.max;
63047dc10d7SGordon Ross /* based on hardware requirement prefer smaller n to precision */
63147dc10d7SGordon Ross for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
63247dc10d7SGordon Ross /* based on hardware requirement prefer larger m1,m2 */
63347dc10d7SGordon Ross for (clock.m1 = limit->m1.max;
63447dc10d7SGordon Ross clock.m1 >= limit->m1.min; clock.m1--) {
63547dc10d7SGordon Ross for (clock.m2 = limit->m2.max;
63647dc10d7SGordon Ross clock.m2 >= limit->m2.min; clock.m2--) {
63747dc10d7SGordon Ross for (clock.p1 = limit->p1.max;
63847dc10d7SGordon Ross clock.p1 >= limit->p1.min; clock.p1--) {
63947dc10d7SGordon Ross int this_err;
64047dc10d7SGordon Ross
64147dc10d7SGordon Ross i9xx_clock(refclk, &clock);
64247dc10d7SGordon Ross if (!intel_PLL_is_valid(dev, limit,
64347dc10d7SGordon Ross &clock))
64447dc10d7SGordon Ross continue;
64547dc10d7SGordon Ross
64647dc10d7SGordon Ross this_err = abs(clock.dot - target) ;
64747dc10d7SGordon Ross if (this_err < err_most) {
64847dc10d7SGordon Ross *best_clock = clock;
64947dc10d7SGordon Ross err_most = this_err;
65047dc10d7SGordon Ross max_n = clock.n;
65147dc10d7SGordon Ross found = true;
65247dc10d7SGordon Ross }
65347dc10d7SGordon Ross }
65447dc10d7SGordon Ross }
65547dc10d7SGordon Ross }
65647dc10d7SGordon Ross }
65747dc10d7SGordon Ross return found;
65847dc10d7SGordon Ross }
65947dc10d7SGordon Ross
66047dc10d7SGordon Ross static bool
vlv_find_best_dpll(const intel_limit_t * limit,struct drm_crtc * crtc,int target,int refclk,intel_clock_t * match_clock,intel_clock_t * best_clock)66147dc10d7SGordon Ross vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
66247dc10d7SGordon Ross int target, int refclk, intel_clock_t *match_clock,
66347dc10d7SGordon Ross intel_clock_t *best_clock)
66447dc10d7SGordon Ross {
66547dc10d7SGordon Ross u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
66647dc10d7SGordon Ross u32 m, n, fastclk;
66747dc10d7SGordon Ross u32 updrate, minupdate, p;
66847dc10d7SGordon Ross unsigned long bestppm, ppm, absppm;
66947dc10d7SGordon Ross int dotclk, flag;
67047dc10d7SGordon Ross
67147dc10d7SGordon Ross flag = 0;
67247dc10d7SGordon Ross dotclk = target * 1000;
67347dc10d7SGordon Ross bestppm = 1000000;
67447dc10d7SGordon Ross ppm = absppm = 0;
67547dc10d7SGordon Ross fastclk = dotclk / (2*100);
67647dc10d7SGordon Ross updrate = 0;
67747dc10d7SGordon Ross minupdate = 19200;
67847dc10d7SGordon Ross n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
67947dc10d7SGordon Ross bestm1 = bestm2 = bestp1 = bestp2 = 0;
68047dc10d7SGordon Ross
68147dc10d7SGordon Ross /* based on hardware requirement, prefer smaller n to precision */
68247dc10d7SGordon Ross for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
68347dc10d7SGordon Ross updrate = refclk / n;
68447dc10d7SGordon Ross for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
68547dc10d7SGordon Ross for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
68647dc10d7SGordon Ross if (p2 > 10)
68747dc10d7SGordon Ross p2 = p2 - 1;
68847dc10d7SGordon Ross p = p1 * p2;
68947dc10d7SGordon Ross /* based on hardware requirement, prefer bigger m1,m2 values */
69047dc10d7SGordon Ross for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
69147dc10d7SGordon Ross m2 = (((2*(fastclk * p * n / m1 )) +
69247dc10d7SGordon Ross refclk) / (2*refclk));
69347dc10d7SGordon Ross m = m1 * m2;
69447dc10d7SGordon Ross vco = updrate * m;
69547dc10d7SGordon Ross if (vco >= limit->vco.min && vco < limit->vco.max) {
69647dc10d7SGordon Ross ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
69747dc10d7SGordon Ross absppm = (ppm > 0) ? ppm : (-ppm);
69847dc10d7SGordon Ross if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
69947dc10d7SGordon Ross bestppm = 0;
70047dc10d7SGordon Ross flag = 1;
70147dc10d7SGordon Ross }
70247dc10d7SGordon Ross if (absppm < bestppm - 10) {
70347dc10d7SGordon Ross bestppm = absppm;
70447dc10d7SGordon Ross flag = 1;
70547dc10d7SGordon Ross }
70647dc10d7SGordon Ross if (flag) {
70747dc10d7SGordon Ross bestn = n;
70847dc10d7SGordon Ross bestm1 = m1;
70947dc10d7SGordon Ross bestm2 = m2;
71047dc10d7SGordon Ross bestp1 = p1;
71147dc10d7SGordon Ross bestp2 = p2;
71247dc10d7SGordon Ross flag = 0;
71347dc10d7SGordon Ross }
71447dc10d7SGordon Ross }
71547dc10d7SGordon Ross }
71647dc10d7SGordon Ross }
71747dc10d7SGordon Ross }
71847dc10d7SGordon Ross }
71947dc10d7SGordon Ross best_clock->n = bestn;
72047dc10d7SGordon Ross best_clock->m1 = bestm1;
72147dc10d7SGordon Ross best_clock->m2 = bestm2;
72247dc10d7SGordon Ross best_clock->p1 = bestp1;
72347dc10d7SGordon Ross best_clock->p2 = bestp2;
72447dc10d7SGordon Ross
72547dc10d7SGordon Ross return true;
72647dc10d7SGordon Ross }
72747dc10d7SGordon Ross
intel_pipe_to_cpu_transcoder(struct drm_i915_private * dev_priv,enum pipe pipe)72847dc10d7SGordon Ross enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
72947dc10d7SGordon Ross enum pipe pipe)
73047dc10d7SGordon Ross {
73147dc10d7SGordon Ross struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
73247dc10d7SGordon Ross struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
73347dc10d7SGordon Ross
73447dc10d7SGordon Ross return intel_crtc->config.cpu_transcoder;
73547dc10d7SGordon Ross }
73647dc10d7SGordon Ross
ironlake_wait_for_vblank(struct drm_device * dev,int pipe)73747dc10d7SGordon Ross static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
73847dc10d7SGordon Ross {
73947dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
74047dc10d7SGordon Ross u32 frame, frame_reg = PIPEFRAME(pipe);
74147dc10d7SGordon Ross
74247dc10d7SGordon Ross frame = I915_READ(frame_reg);
74347dc10d7SGordon Ross
74447dc10d7SGordon Ross if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
74547dc10d7SGordon Ross DRM_DEBUG_KMS("vblank wait timed out\n");
74647dc10d7SGordon Ross }
74747dc10d7SGordon Ross
74847dc10d7SGordon Ross /**
74947dc10d7SGordon Ross * intel_wait_for_vblank - wait for vblank on a given pipe
75047dc10d7SGordon Ross * @dev: drm device
75147dc10d7SGordon Ross * @pipe: pipe to wait for
75247dc10d7SGordon Ross *
75347dc10d7SGordon Ross * Wait for vblank to occur on a given pipe. Needed for various bits of
75447dc10d7SGordon Ross * mode setting code.
75547dc10d7SGordon Ross */
intel_wait_for_vblank(struct drm_device * dev,int pipe)75647dc10d7SGordon Ross void intel_wait_for_vblank(struct drm_device *dev, int pipe)
75747dc10d7SGordon Ross {
75847dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
75947dc10d7SGordon Ross int pipestat_reg = PIPESTAT(pipe);
76047dc10d7SGordon Ross
76147dc10d7SGordon Ross if (INTEL_INFO(dev)->gen >= 5) {
76247dc10d7SGordon Ross ironlake_wait_for_vblank(dev, pipe);
76347dc10d7SGordon Ross return;
76447dc10d7SGordon Ross }
76547dc10d7SGordon Ross
76647dc10d7SGordon Ross /* Clear existing vblank status. Note this will clear any other
76747dc10d7SGordon Ross * sticky status fields as well.
76847dc10d7SGordon Ross *
76947dc10d7SGordon Ross * This races with i915_driver_irq_handler() with the result
77047dc10d7SGordon Ross * that either function could miss a vblank event. Here it is not
77147dc10d7SGordon Ross * fatal, as we will either wait upon the next vblank interrupt or
77247dc10d7SGordon Ross * timeout. Generally speaking intel_wait_for_vblank() is only
77347dc10d7SGordon Ross * called during modeset at which time the GPU should be idle and
77447dc10d7SGordon Ross * should *not* be performing page flips and thus not waiting on
77547dc10d7SGordon Ross * vblanks...
77647dc10d7SGordon Ross * Currently, the result of us stealing a vblank from the irq
77747dc10d7SGordon Ross * handler is that a single frame will be skipped during swapbuffers.
77847dc10d7SGordon Ross */
77947dc10d7SGordon Ross I915_WRITE(pipestat_reg,
78047dc10d7SGordon Ross I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
78147dc10d7SGordon Ross
78247dc10d7SGordon Ross /* Wait for vblank interrupt bit to set */
78347dc10d7SGordon Ross if (wait_for(I915_READ(pipestat_reg) &
78447dc10d7SGordon Ross PIPE_VBLANK_INTERRUPT_STATUS,
78547dc10d7SGordon Ross 50))
78647dc10d7SGordon Ross DRM_DEBUG_KMS("vblank wait timed out\n");
78747dc10d7SGordon Ross }
78847dc10d7SGordon Ross
78947dc10d7SGordon Ross /*
79047dc10d7SGordon Ross * intel_wait_for_pipe_off - wait for pipe to turn off
79147dc10d7SGordon Ross * @dev: drm device
79247dc10d7SGordon Ross * @pipe: pipe to wait for
79347dc10d7SGordon Ross *
79447dc10d7SGordon Ross * After disabling a pipe, we can't wait for vblank in the usual way,
79547dc10d7SGordon Ross * spinning on the vblank interrupt status bit, since we won't actually
79647dc10d7SGordon Ross * see an interrupt when the pipe is disabled.
79747dc10d7SGordon Ross *
79847dc10d7SGordon Ross * On Gen4 and above:
79947dc10d7SGordon Ross * wait for the pipe register state bit to turn off
80047dc10d7SGordon Ross *
80147dc10d7SGordon Ross * Otherwise:
80247dc10d7SGordon Ross * wait for the display line value to settle (it usually
80347dc10d7SGordon Ross * ends up stopping at the start of the next frame).
80447dc10d7SGordon Ross *
80547dc10d7SGordon Ross */
intel_wait_for_pipe_off(struct drm_device * dev,int pipe)80647dc10d7SGordon Ross void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
80747dc10d7SGordon Ross {
80847dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
80947dc10d7SGordon Ross enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
81047dc10d7SGordon Ross pipe);
81147dc10d7SGordon Ross
81247dc10d7SGordon Ross if (INTEL_INFO(dev)->gen >= 4) {
81347dc10d7SGordon Ross int reg = PIPECONF(cpu_transcoder);
81447dc10d7SGordon Ross
81547dc10d7SGordon Ross /* Wait for the Pipe State to go off */
81647dc10d7SGordon Ross if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
81747dc10d7SGordon Ross 100))
81847dc10d7SGordon Ross DRM_ERROR("pipe_off wait timed out\n");
81947dc10d7SGordon Ross } else {
82047dc10d7SGordon Ross u32 last_line, line_mask;
82147dc10d7SGordon Ross int reg = PIPEDSL(pipe);
82247dc10d7SGordon Ross unsigned long timeout = jiffies + msecs_to_jiffies(100);
82347dc10d7SGordon Ross
82447dc10d7SGordon Ross if (IS_GEN2(dev))
82547dc10d7SGordon Ross line_mask = DSL_LINEMASK_GEN2;
82647dc10d7SGordon Ross else
82747dc10d7SGordon Ross line_mask = DSL_LINEMASK_GEN3;
82847dc10d7SGordon Ross
82947dc10d7SGordon Ross /* Wait for the display line to settle */
83047dc10d7SGordon Ross do {
83147dc10d7SGordon Ross last_line = I915_READ(reg) & line_mask;
83247dc10d7SGordon Ross mdelay(5);
83347dc10d7SGordon Ross } while (((I915_READ(reg) & line_mask) != last_line) &&
83447dc10d7SGordon Ross time_after(timeout, jiffies));
83547dc10d7SGordon Ross if (time_after(jiffies, timeout))
83647dc10d7SGordon Ross DRM_ERROR("pipe_off wait timed out\n");
83747dc10d7SGordon Ross }
83847dc10d7SGordon Ross }
83947dc10d7SGordon Ross
84047dc10d7SGordon Ross /*
84147dc10d7SGordon Ross * ibx_digital_port_connected - is the specified port connected?
84247dc10d7SGordon Ross * @dev_priv: i915 private structure
84347dc10d7SGordon Ross * @port: the port to test
84447dc10d7SGordon Ross *
84547dc10d7SGordon Ross * Returns true if @port is connected, false otherwise.
84647dc10d7SGordon Ross */
ibx_digital_port_connected(struct drm_i915_private * dev_priv,struct intel_digital_port * port)84747dc10d7SGordon Ross bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
84847dc10d7SGordon Ross struct intel_digital_port *port)
84947dc10d7SGordon Ross {
85047dc10d7SGordon Ross u32 bit;
85147dc10d7SGordon Ross
85247dc10d7SGordon Ross if (HAS_PCH_IBX(dev_priv->dev)) {
85347dc10d7SGordon Ross switch(port->port) {
85447dc10d7SGordon Ross case PORT_B:
85547dc10d7SGordon Ross bit = SDE_PORTB_HOTPLUG;
85647dc10d7SGordon Ross break;
85747dc10d7SGordon Ross case PORT_C:
85847dc10d7SGordon Ross bit = SDE_PORTC_HOTPLUG;
85947dc10d7SGordon Ross break;
86047dc10d7SGordon Ross case PORT_D:
86147dc10d7SGordon Ross bit = SDE_PORTD_HOTPLUG;
86247dc10d7SGordon Ross break;
86347dc10d7SGordon Ross default:
86447dc10d7SGordon Ross return true;
86547dc10d7SGordon Ross }
86647dc10d7SGordon Ross } else {
86747dc10d7SGordon Ross switch(port->port) {
86847dc10d7SGordon Ross case PORT_B:
86947dc10d7SGordon Ross bit = SDE_PORTB_HOTPLUG_CPT;
87047dc10d7SGordon Ross break;
87147dc10d7SGordon Ross case PORT_C:
87247dc10d7SGordon Ross bit = SDE_PORTC_HOTPLUG_CPT;
87347dc10d7SGordon Ross break;
87447dc10d7SGordon Ross case PORT_D:
87547dc10d7SGordon Ross bit = SDE_PORTD_HOTPLUG_CPT;
87647dc10d7SGordon Ross break;
87747dc10d7SGordon Ross default:
87847dc10d7SGordon Ross return true;
87947dc10d7SGordon Ross }
88047dc10d7SGordon Ross }
88147dc10d7SGordon Ross
88247dc10d7SGordon Ross return I915_READ(SDEISR) & bit;
88347dc10d7SGordon Ross }
88447dc10d7SGordon Ross
state_string(bool enabled)88547dc10d7SGordon Ross static const char *state_string(bool enabled)
88647dc10d7SGordon Ross {
88747dc10d7SGordon Ross return enabled ? "on" : "off";
88847dc10d7SGordon Ross }
88947dc10d7SGordon Ross
89047dc10d7SGordon Ross /* Only for pre-ILK configs */
assert_pll(struct drm_i915_private * dev_priv,enum pipe pipe,bool state)89147dc10d7SGordon Ross static void assert_pll(struct drm_i915_private *dev_priv,
89247dc10d7SGordon Ross enum pipe pipe, bool state)
89347dc10d7SGordon Ross {
89447dc10d7SGordon Ross int reg;
89547dc10d7SGordon Ross u32 val;
89647dc10d7SGordon Ross bool cur_state;
89747dc10d7SGordon Ross
89847dc10d7SGordon Ross reg = DPLL(pipe);
89947dc10d7SGordon Ross val = I915_READ(reg);
90047dc10d7SGordon Ross cur_state = !!(val & DPLL_VCO_ENABLE);
90147dc10d7SGordon Ross if (cur_state != state)
90247dc10d7SGordon Ross DRM_ERROR("PLL state assertion failure (expected %s, current %s)",
90347dc10d7SGordon Ross state_string(state), state_string(cur_state));
90447dc10d7SGordon Ross }
90547dc10d7SGordon Ross #define assert_pll_enabled(d, p) assert_pll(d, p, true)
90647dc10d7SGordon Ross #define assert_pll_disabled(d, p) assert_pll(d, p, false)
90747dc10d7SGordon Ross
90847dc10d7SGordon Ross static struct intel_shared_dpll *
intel_crtc_to_shared_dpll(struct intel_crtc * crtc)90947dc10d7SGordon Ross intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
91047dc10d7SGordon Ross {
91147dc10d7SGordon Ross struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
91247dc10d7SGordon Ross
91347dc10d7SGordon Ross if (crtc->config.shared_dpll < 0)
91447dc10d7SGordon Ross return NULL;
91547dc10d7SGordon Ross
91647dc10d7SGordon Ross return &dev_priv->shared_dplls[crtc->config.shared_dpll];
91747dc10d7SGordon Ross }
91847dc10d7SGordon Ross
91947dc10d7SGordon Ross /* For ILK+ */
assert_shared_dpll(struct drm_i915_private * dev_priv,struct intel_shared_dpll * pll,bool state)92047dc10d7SGordon Ross static void assert_shared_dpll(struct drm_i915_private *dev_priv,
92147dc10d7SGordon Ross struct intel_shared_dpll *pll,
92247dc10d7SGordon Ross bool state)
92347dc10d7SGordon Ross {
92447dc10d7SGordon Ross bool cur_state;
92547dc10d7SGordon Ross struct intel_dpll_hw_state hw_state;
92647dc10d7SGordon Ross
92747dc10d7SGordon Ross if (HAS_PCH_LPT(dev_priv->dev)) {
92847dc10d7SGordon Ross DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
92947dc10d7SGordon Ross return;
93047dc10d7SGordon Ross }
93147dc10d7SGordon Ross
93247dc10d7SGordon Ross if (!pll) {
93347dc10d7SGordon Ross DRM_ERROR("asserting PCH PLL %s with no PLL\n", state_string(state));
93447dc10d7SGordon Ross return;
93547dc10d7SGordon Ross }
93647dc10d7SGordon Ross
93747dc10d7SGordon Ross cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
93847dc10d7SGordon Ross if (cur_state != state)
93947dc10d7SGordon Ross DRM_DEBUG_KMS("%s assertion failure (expected %s, current %s)",
94047dc10d7SGordon Ross pll->name, state_string(state), state_string(cur_state));
94147dc10d7SGordon Ross }
94247dc10d7SGordon Ross #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
94347dc10d7SGordon Ross #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
94447dc10d7SGordon Ross
assert_fdi_tx(struct drm_i915_private * dev_priv,enum pipe pipe,bool state)94547dc10d7SGordon Ross static void assert_fdi_tx(struct drm_i915_private *dev_priv,
94647dc10d7SGordon Ross enum pipe pipe, bool state)
94747dc10d7SGordon Ross {
94847dc10d7SGordon Ross int reg;
94947dc10d7SGordon Ross u32 val;
95047dc10d7SGordon Ross bool cur_state;
95147dc10d7SGordon Ross enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
95247dc10d7SGordon Ross pipe);
95347dc10d7SGordon Ross
95447dc10d7SGordon Ross if (HAS_DDI(dev_priv->dev)) {
95547dc10d7SGordon Ross /* On Haswell, DDI is used instead of FDI_TX_CTL */
95647dc10d7SGordon Ross reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
95747dc10d7SGordon Ross val = I915_READ(reg);
95847dc10d7SGordon Ross cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
95947dc10d7SGordon Ross } else {
96047dc10d7SGordon Ross reg = FDI_TX_CTL(pipe);
96147dc10d7SGordon Ross val = I915_READ(reg);
96247dc10d7SGordon Ross cur_state = !!(val & FDI_TX_ENABLE);
96347dc10d7SGordon Ross }
96447dc10d7SGordon Ross if(cur_state != state)
96547dc10d7SGordon Ross DRM_ERROR("FDI TX state assertion failure (expected %s, current %s)\n",
96647dc10d7SGordon Ross state_string(state), state_string(cur_state));
96747dc10d7SGordon Ross }
96847dc10d7SGordon Ross #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
96947dc10d7SGordon Ross #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
97047dc10d7SGordon Ross
assert_fdi_rx(struct drm_i915_private * dev_priv,enum pipe pipe,bool state)97147dc10d7SGordon Ross static void assert_fdi_rx(struct drm_i915_private *dev_priv,
97247dc10d7SGordon Ross enum pipe pipe, bool state)
97347dc10d7SGordon Ross {
97447dc10d7SGordon Ross int reg;
97547dc10d7SGordon Ross u32 val;
97647dc10d7SGordon Ross bool cur_state;
97747dc10d7SGordon Ross
97847dc10d7SGordon Ross reg = FDI_RX_CTL(pipe);
97947dc10d7SGordon Ross val = I915_READ(reg);
98047dc10d7SGordon Ross cur_state = !!(val & FDI_RX_ENABLE);
98147dc10d7SGordon Ross if(cur_state != state)
98247dc10d7SGordon Ross DRM_ERROR("FDI RX state assertion failure (expected %s, current %s)\n",
98347dc10d7SGordon Ross state_string(state), state_string(cur_state));
98447dc10d7SGordon Ross }
98547dc10d7SGordon Ross #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
98647dc10d7SGordon Ross #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
98747dc10d7SGordon Ross
assert_fdi_tx_pll_enabled(struct drm_i915_private * dev_priv,enum pipe pipe)98847dc10d7SGordon Ross static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
98947dc10d7SGordon Ross enum pipe pipe)
99047dc10d7SGordon Ross {
99147dc10d7SGordon Ross int reg;
99247dc10d7SGordon Ross u32 val;
99347dc10d7SGordon Ross
99447dc10d7SGordon Ross /* ILK FDI PLL is always enabled */
99547dc10d7SGordon Ross if (dev_priv->info->gen == 5)
99647dc10d7SGordon Ross return;
99747dc10d7SGordon Ross
99847dc10d7SGordon Ross /* On Haswell, DDI ports are responsible for the FDI PLL setup */
99947dc10d7SGordon Ross if (HAS_DDI(dev_priv->dev))
100047dc10d7SGordon Ross return;
100147dc10d7SGordon Ross
100247dc10d7SGordon Ross reg = FDI_TX_CTL(pipe);
100347dc10d7SGordon Ross val = I915_READ(reg);
100447dc10d7SGordon Ross if(!(val & FDI_TX_PLL_ENABLE))
100547dc10d7SGordon Ross DRM_ERROR("FDI TX PLL assertion failure, should be active but is disabled\n");
100647dc10d7SGordon Ross }
100747dc10d7SGordon Ross
assert_fdi_rx_pll_enabled(struct drm_i915_private * dev_priv,enum pipe pipe)100847dc10d7SGordon Ross static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
100947dc10d7SGordon Ross enum pipe pipe)
101047dc10d7SGordon Ross {
101147dc10d7SGordon Ross int reg;
101247dc10d7SGordon Ross u32 val;
101347dc10d7SGordon Ross
101447dc10d7SGordon Ross reg = FDI_RX_CTL(pipe);
101547dc10d7SGordon Ross val = I915_READ(reg);
101647dc10d7SGordon Ross if(!(val & FDI_RX_PLL_ENABLE))
101747dc10d7SGordon Ross DRM_ERROR("FDI RX PLL assertion failure, should be active but is disabled\n");
101847dc10d7SGordon Ross }
101947dc10d7SGordon Ross
assert_panel_unlocked(struct drm_i915_private * dev_priv,enum pipe pipe)102047dc10d7SGordon Ross static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
102147dc10d7SGordon Ross enum pipe pipe)
102247dc10d7SGordon Ross {
102347dc10d7SGordon Ross int pp_reg, lvds_reg;
102447dc10d7SGordon Ross u32 val;
102547dc10d7SGordon Ross enum pipe panel_pipe = PIPE_A;
102647dc10d7SGordon Ross bool locked = true;
102747dc10d7SGordon Ross
102847dc10d7SGordon Ross if (HAS_PCH_SPLIT(dev_priv->dev)) {
102947dc10d7SGordon Ross pp_reg = PCH_PP_CONTROL;
103047dc10d7SGordon Ross lvds_reg = PCH_LVDS;
103147dc10d7SGordon Ross } else {
103247dc10d7SGordon Ross pp_reg = PP_CONTROL;
103347dc10d7SGordon Ross lvds_reg = LVDS;
103447dc10d7SGordon Ross }
103547dc10d7SGordon Ross
103647dc10d7SGordon Ross val = I915_READ(pp_reg);
103747dc10d7SGordon Ross if (!(val & PANEL_POWER_ON) ||
103847dc10d7SGordon Ross ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
103947dc10d7SGordon Ross locked = false;
104047dc10d7SGordon Ross
104147dc10d7SGordon Ross if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
104247dc10d7SGordon Ross panel_pipe = PIPE_B;
104347dc10d7SGordon Ross
104447dc10d7SGordon Ross if(panel_pipe == pipe && locked)
104547dc10d7SGordon Ross DRM_ERROR("panel assertion failure, pipe %c regs locked\n",
104647dc10d7SGordon Ross pipe_name(pipe));
104747dc10d7SGordon Ross }
104847dc10d7SGordon Ross
assert_pipe(struct drm_i915_private * dev_priv,enum pipe pipe,bool state)104947dc10d7SGordon Ross void assert_pipe(struct drm_i915_private *dev_priv,
105047dc10d7SGordon Ross enum pipe pipe, bool state)
105147dc10d7SGordon Ross {
105247dc10d7SGordon Ross int reg;
105347dc10d7SGordon Ross u32 val;
105447dc10d7SGordon Ross bool cur_state;
105547dc10d7SGordon Ross enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
105647dc10d7SGordon Ross pipe);
105747dc10d7SGordon Ross
105847dc10d7SGordon Ross /* if we need the pipe A quirk it must be always on */
105947dc10d7SGordon Ross if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
106047dc10d7SGordon Ross state = true;
106147dc10d7SGordon Ross
106247dc10d7SGordon Ross if (!intel_display_power_enabled(dev_priv->dev,
106347dc10d7SGordon Ross POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
106447dc10d7SGordon Ross cur_state = false;
106547dc10d7SGordon Ross } else {
106647dc10d7SGordon Ross reg = PIPECONF(cpu_transcoder);
106747dc10d7SGordon Ross val = I915_READ(reg);
106847dc10d7SGordon Ross cur_state = !!(val & PIPECONF_ENABLE);
106947dc10d7SGordon Ross }
107047dc10d7SGordon Ross
107147dc10d7SGordon Ross if(cur_state != state)
107247dc10d7SGordon Ross DRM_ERROR("pipe %c assertion failure (expected %s, current %s)\n",
107347dc10d7SGordon Ross pipe_name(pipe), state_string(state), state_string(cur_state));
107447dc10d7SGordon Ross }
107547dc10d7SGordon Ross
assert_plane(struct drm_i915_private * dev_priv,enum plane plane,bool state)107647dc10d7SGordon Ross static void assert_plane(struct drm_i915_private *dev_priv,
107747dc10d7SGordon Ross enum plane plane, bool state)
107847dc10d7SGordon Ross {
107947dc10d7SGordon Ross int reg;
108047dc10d7SGordon Ross u32 val;
108147dc10d7SGordon Ross bool cur_state;
108247dc10d7SGordon Ross
108347dc10d7SGordon Ross reg = DSPCNTR(plane);
108447dc10d7SGordon Ross val = I915_READ(reg);
108547dc10d7SGordon Ross cur_state = !!(val & DISPLAY_PLANE_ENABLE);
108647dc10d7SGordon Ross if(cur_state != state)
108747dc10d7SGordon Ross DRM_ERROR("plane %c assertion failure, should be active but is disabled\n",
108847dc10d7SGordon Ross plane_name(plane));
108947dc10d7SGordon Ross }
109047dc10d7SGordon Ross
109147dc10d7SGordon Ross #define assert_plane_enabled(d, p) assert_plane(d, p, true)
109247dc10d7SGordon Ross #define assert_plane_disabled(d, p) assert_plane(d, p, false)
109347dc10d7SGordon Ross
assert_planes_disabled(struct drm_i915_private * dev_priv,enum pipe pipe)109447dc10d7SGordon Ross static void assert_planes_disabled(struct drm_i915_private *dev_priv,
109547dc10d7SGordon Ross enum pipe pipe)
109647dc10d7SGordon Ross {
109747dc10d7SGordon Ross struct drm_device *dev = dev_priv->dev;
109847dc10d7SGordon Ross int reg, i;
109947dc10d7SGordon Ross u32 val;
110047dc10d7SGordon Ross int cur_pipe;
110147dc10d7SGordon Ross
110247dc10d7SGordon Ross /* Planes are fixed to pipes on ILK+ */
110347dc10d7SGordon Ross if (INTEL_INFO(dev)->gen >= 4) {
110447dc10d7SGordon Ross reg = DSPCNTR(pipe);
110547dc10d7SGordon Ross val = I915_READ(reg);
110647dc10d7SGordon Ross if(val & DISPLAY_PLANE_ENABLE)
110747dc10d7SGordon Ross DRM_ERROR("plane %c assertion failure, should be disabled but not\n",
110847dc10d7SGordon Ross plane_name(pipe));
110947dc10d7SGordon Ross return;
111047dc10d7SGordon Ross }
111147dc10d7SGordon Ross
111247dc10d7SGordon Ross /* Need to check both planes against the pipe */
111347dc10d7SGordon Ross for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
111447dc10d7SGordon Ross reg = DSPCNTR(i);
111547dc10d7SGordon Ross val = I915_READ(reg);
111647dc10d7SGordon Ross cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
111747dc10d7SGordon Ross DISPPLANE_SEL_PIPE_SHIFT;
111847dc10d7SGordon Ross if((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe)
111947dc10d7SGordon Ross DRM_ERROR("plane %c assertion failure, should be off on pipe %c but is still active\n",
112047dc10d7SGordon Ross plane_name(i), pipe_name(pipe));
112147dc10d7SGordon Ross }
112247dc10d7SGordon Ross }
112347dc10d7SGordon Ross
assert_sprites_disabled(struct drm_i915_private * dev_priv,enum pipe pipe)112447dc10d7SGordon Ross static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
112547dc10d7SGordon Ross enum pipe pipe)
112647dc10d7SGordon Ross {
112747dc10d7SGordon Ross struct drm_device *dev = dev_priv->dev;
112847dc10d7SGordon Ross int reg, i;
112947dc10d7SGordon Ross u32 val;
113047dc10d7SGordon Ross
113147dc10d7SGordon Ross if (IS_VALLEYVIEW(dev)) {
113247dc10d7SGordon Ross for (i = 0; i < dev_priv->num_plane; i++) {
113347dc10d7SGordon Ross reg = SPCNTR(pipe, i);
113447dc10d7SGordon Ross val = I915_READ(reg);
113547dc10d7SGordon Ross if(val & SP_ENABLE)
113647dc10d7SGordon Ross DRM_ERROR("sprite %c assertion failure, should be off on pipe %c but is still active\n",
113747dc10d7SGordon Ross sprite_name(pipe, i), pipe_name(pipe));
113847dc10d7SGordon Ross }
113947dc10d7SGordon Ross } else if (INTEL_INFO(dev)->gen >= 7) {
114047dc10d7SGordon Ross reg = SPRCTL(pipe);
114147dc10d7SGordon Ross val = I915_READ(reg);
114247dc10d7SGordon Ross if(val & SPRITE_ENABLE)
114347dc10d7SGordon Ross DRM_ERROR("sprite %c assertion failure, should be off on pipe %c but is still active\n",
114447dc10d7SGordon Ross plane_name(pipe), pipe_name(pipe));
114547dc10d7SGordon Ross } else if (INTEL_INFO(dev)->gen >= 5) {
114647dc10d7SGordon Ross reg = DVSCNTR(pipe);
114747dc10d7SGordon Ross val = I915_READ(reg);
114847dc10d7SGordon Ross if(val & DVS_ENABLE)
114947dc10d7SGordon Ross DRM_ERROR("sprite %c assertion failure, should be off on pipe %c but is still active\n",
115047dc10d7SGordon Ross plane_name(pipe), pipe_name(pipe));
115147dc10d7SGordon Ross }
115247dc10d7SGordon Ross }
115347dc10d7SGordon Ross
assert_pch_refclk_enabled(struct drm_i915_private * dev_priv)115447dc10d7SGordon Ross static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
115547dc10d7SGordon Ross {
115647dc10d7SGordon Ross u32 val;
115747dc10d7SGordon Ross bool enabled;
115847dc10d7SGordon Ross
115947dc10d7SGordon Ross if (HAS_PCH_LPT(dev_priv->dev)) {
116047dc10d7SGordon Ross DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
116147dc10d7SGordon Ross return;
116247dc10d7SGordon Ross }
116347dc10d7SGordon Ross
116447dc10d7SGordon Ross val = I915_READ(PCH_DREF_CONTROL);
116547dc10d7SGordon Ross enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
116647dc10d7SGordon Ross DREF_SUPERSPREAD_SOURCE_MASK));
116747dc10d7SGordon Ross if(!enabled)
116847dc10d7SGordon Ross DRM_ERROR("PCH refclk assertion failure, should be active but is disabled\n");
116947dc10d7SGordon Ross }
117047dc10d7SGordon Ross
assert_pch_transcoder_disabled(struct drm_i915_private * dev_priv,enum pipe pipe)117147dc10d7SGordon Ross static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
117247dc10d7SGordon Ross enum pipe pipe)
117347dc10d7SGordon Ross {
117447dc10d7SGordon Ross int reg;
117547dc10d7SGordon Ross u32 val;
117647dc10d7SGordon Ross bool enabled;
117747dc10d7SGordon Ross
117847dc10d7SGordon Ross reg = PCH_TRANSCONF(pipe);
117947dc10d7SGordon Ross val = I915_READ(reg);
118047dc10d7SGordon Ross enabled = !!(val & TRANS_ENABLE);
118147dc10d7SGordon Ross if(enabled)
118247dc10d7SGordon Ross DRM_ERROR("transcoder assertion failed, should be off on pipe %c but is still active\n",
118347dc10d7SGordon Ross pipe_name(pipe));
118447dc10d7SGordon Ross }
118547dc10d7SGordon Ross
dp_pipe_enabled(struct drm_i915_private * dev_priv,enum pipe pipe,u32 port_sel,u32 val)118647dc10d7SGordon Ross static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
118747dc10d7SGordon Ross enum pipe pipe, u32 port_sel, u32 val)
118847dc10d7SGordon Ross {
118947dc10d7SGordon Ross if ((val & DP_PORT_EN) == 0)
119047dc10d7SGordon Ross return false;
119147dc10d7SGordon Ross
119247dc10d7SGordon Ross if (HAS_PCH_CPT(dev_priv->dev)) {
119347dc10d7SGordon Ross u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
119447dc10d7SGordon Ross u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
119547dc10d7SGordon Ross if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
119647dc10d7SGordon Ross return false;
119747dc10d7SGordon Ross } else {
119847dc10d7SGordon Ross if ((val & DP_PIPE_MASK) != (pipe << 30))
119947dc10d7SGordon Ross return false;
120047dc10d7SGordon Ross }
120147dc10d7SGordon Ross return true;
120247dc10d7SGordon Ross }
120347dc10d7SGordon Ross
hdmi_pipe_enabled(struct drm_i915_private * dev_priv,enum pipe pipe,u32 val)120447dc10d7SGordon Ross static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
120547dc10d7SGordon Ross enum pipe pipe, u32 val)
120647dc10d7SGordon Ross {
120747dc10d7SGordon Ross if ((val & SDVO_ENABLE) == 0)
120847dc10d7SGordon Ross return false;
120947dc10d7SGordon Ross
121047dc10d7SGordon Ross if (HAS_PCH_CPT(dev_priv->dev)) {
121147dc10d7SGordon Ross if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
121247dc10d7SGordon Ross return false;
121347dc10d7SGordon Ross } else {
121447dc10d7SGordon Ross if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
121547dc10d7SGordon Ross return false;
121647dc10d7SGordon Ross }
121747dc10d7SGordon Ross return true;
121847dc10d7SGordon Ross }
121947dc10d7SGordon Ross
lvds_pipe_enabled(struct drm_i915_private * dev_priv,enum pipe pipe,u32 val)122047dc10d7SGordon Ross static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
122147dc10d7SGordon Ross enum pipe pipe, u32 val)
122247dc10d7SGordon Ross {
122347dc10d7SGordon Ross if ((val & LVDS_PORT_EN) == 0)
122447dc10d7SGordon Ross return false;
122547dc10d7SGordon Ross
122647dc10d7SGordon Ross if (HAS_PCH_CPT(dev_priv->dev)) {
122747dc10d7SGordon Ross if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
122847dc10d7SGordon Ross return false;
122947dc10d7SGordon Ross } else {
123047dc10d7SGordon Ross if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
123147dc10d7SGordon Ross return false;
123247dc10d7SGordon Ross }
123347dc10d7SGordon Ross return true;
123447dc10d7SGordon Ross }
123547dc10d7SGordon Ross
adpa_pipe_enabled(struct drm_i915_private * dev_priv,enum pipe pipe,u32 val)123647dc10d7SGordon Ross static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
123747dc10d7SGordon Ross enum pipe pipe, u32 val)
123847dc10d7SGordon Ross {
123947dc10d7SGordon Ross if ((val & ADPA_DAC_ENABLE) == 0)
124047dc10d7SGordon Ross return false;
124147dc10d7SGordon Ross if (HAS_PCH_CPT(dev_priv->dev)) {
124247dc10d7SGordon Ross if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
124347dc10d7SGordon Ross return false;
124447dc10d7SGordon Ross } else {
124547dc10d7SGordon Ross if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
124647dc10d7SGordon Ross return false;
124747dc10d7SGordon Ross }
124847dc10d7SGordon Ross return true;
124947dc10d7SGordon Ross }
125047dc10d7SGordon Ross
assert_pch_dp_disabled(struct drm_i915_private * dev_priv,enum pipe pipe,int reg,u32 port_sel)125147dc10d7SGordon Ross static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
125247dc10d7SGordon Ross enum pipe pipe, int reg, u32 port_sel)
125347dc10d7SGordon Ross {
125447dc10d7SGordon Ross u32 val = I915_READ(reg);
125547dc10d7SGordon Ross if(dp_pipe_enabled(dev_priv, pipe, port_sel, val))
125647dc10d7SGordon Ross DRM_ERROR("PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
125747dc10d7SGordon Ross reg, pipe_name(pipe));
125847dc10d7SGordon Ross
125947dc10d7SGordon Ross if (HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
126047dc10d7SGordon Ross && (val & DP_PIPEB_SELECT))
126147dc10d7SGordon Ross DRM_ERROR("IBX PCH dp port still using transcoder B\n");
126247dc10d7SGordon Ross }
126347dc10d7SGordon Ross
assert_pch_hdmi_disabled(struct drm_i915_private * dev_priv,enum pipe pipe,int reg)126447dc10d7SGordon Ross static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
126547dc10d7SGordon Ross enum pipe pipe, int reg)
126647dc10d7SGordon Ross {
126747dc10d7SGordon Ross u32 val = I915_READ(reg);
126847dc10d7SGordon Ross if(hdmi_pipe_enabled(dev_priv, pipe, val))
126947dc10d7SGordon Ross DRM_ERROR("PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
127047dc10d7SGordon Ross reg, pipe_name(pipe));
127147dc10d7SGordon Ross
127247dc10d7SGordon Ross if (HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
127347dc10d7SGordon Ross && (val & SDVO_PIPE_B_SELECT))
127447dc10d7SGordon Ross DRM_ERROR("IBX PCH hdmi port still using transcoder B\n");
127547dc10d7SGordon Ross }
127647dc10d7SGordon Ross
assert_pch_ports_disabled(struct drm_i915_private * dev_priv,enum pipe pipe)127747dc10d7SGordon Ross static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
127847dc10d7SGordon Ross enum pipe pipe)
127947dc10d7SGordon Ross {
128047dc10d7SGordon Ross int reg;
128147dc10d7SGordon Ross u32 val;
128247dc10d7SGordon Ross
128347dc10d7SGordon Ross assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
128447dc10d7SGordon Ross assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
128547dc10d7SGordon Ross assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
128647dc10d7SGordon Ross
128747dc10d7SGordon Ross reg = PCH_ADPA;
128847dc10d7SGordon Ross val = I915_READ(reg);
128947dc10d7SGordon Ross if(adpa_pipe_enabled(dev_priv, pipe, val))
129047dc10d7SGordon Ross DRM_ERROR("PCH VGA enabled on transcoder %c, should be disabled\n",
129147dc10d7SGordon Ross pipe_name(pipe));
129247dc10d7SGordon Ross
129347dc10d7SGordon Ross reg = PCH_LVDS;
129447dc10d7SGordon Ross val = I915_READ(reg);
129547dc10d7SGordon Ross if(lvds_pipe_enabled(dev_priv, pipe, val))
129647dc10d7SGordon Ross DRM_ERROR("PCH LVDS enabled on transcoder %c, should be disabled\n",
129747dc10d7SGordon Ross pipe_name(pipe));
129847dc10d7SGordon Ross
129947dc10d7SGordon Ross assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
130047dc10d7SGordon Ross assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
130147dc10d7SGordon Ross assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
130247dc10d7SGordon Ross }
130347dc10d7SGordon Ross
130447dc10d7SGordon Ross /**
130547dc10d7SGordon Ross * intel_enable_pll - enable a PLL
130647dc10d7SGordon Ross * @dev_priv: i915 private structure
130747dc10d7SGordon Ross * @pipe: pipe PLL to enable
130847dc10d7SGordon Ross *
130947dc10d7SGordon Ross * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
131047dc10d7SGordon Ross * make sure the PLL reg is writable first though, since the panel write
131147dc10d7SGordon Ross * protect mechanism may be enabled.
131247dc10d7SGordon Ross *
131347dc10d7SGordon Ross * Note! This is for pre-ILK only.
131447dc10d7SGordon Ross *
131547dc10d7SGordon Ross * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
131647dc10d7SGordon Ross */
intel_enable_pll(struct drm_i915_private * dev_priv,enum pipe pipe)131747dc10d7SGordon Ross static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
131847dc10d7SGordon Ross {
131947dc10d7SGordon Ross int reg;
132047dc10d7SGordon Ross u32 val;
132147dc10d7SGordon Ross
132247dc10d7SGordon Ross assert_pipe_disabled(dev_priv, pipe);
132347dc10d7SGordon Ross
132447dc10d7SGordon Ross /* No really, not for ILK+ */
132547dc10d7SGordon Ross BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
132647dc10d7SGordon Ross
132747dc10d7SGordon Ross /* PLL is protected by panel, make sure we can write it */
132847dc10d7SGordon Ross if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
132947dc10d7SGordon Ross assert_panel_unlocked(dev_priv, pipe);
133047dc10d7SGordon Ross
133147dc10d7SGordon Ross reg = DPLL(pipe);
133247dc10d7SGordon Ross val = I915_READ(reg);
133347dc10d7SGordon Ross val |= DPLL_VCO_ENABLE;
133447dc10d7SGordon Ross
133547dc10d7SGordon Ross /* We do this three times for luck */
133647dc10d7SGordon Ross I915_WRITE(reg, val);
133747dc10d7SGordon Ross POSTING_READ(reg);
133847dc10d7SGordon Ross udelay(150); /* wait for warmup */
133947dc10d7SGordon Ross I915_WRITE(reg, val);
134047dc10d7SGordon Ross POSTING_READ(reg);
134147dc10d7SGordon Ross udelay(150); /* wait for warmup */
134247dc10d7SGordon Ross I915_WRITE(reg, val);
134347dc10d7SGordon Ross POSTING_READ(reg);
134447dc10d7SGordon Ross udelay(150); /* wait for warmup */
134547dc10d7SGordon Ross }
134647dc10d7SGordon Ross
134747dc10d7SGordon Ross /**
134847dc10d7SGordon Ross * intel_disable_pll - disable a PLL
134947dc10d7SGordon Ross * @dev_priv: i915 private structure
135047dc10d7SGordon Ross * @pipe: pipe PLL to disable
135147dc10d7SGordon Ross *
135247dc10d7SGordon Ross * Disable the PLL for @pipe, making sure the pipe is off first.
135347dc10d7SGordon Ross *
135447dc10d7SGordon Ross * Note! This is for pre-ILK only.
135547dc10d7SGordon Ross */
intel_disable_pll(struct drm_i915_private * dev_priv,enum pipe pipe)135647dc10d7SGordon Ross static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
135747dc10d7SGordon Ross {
135847dc10d7SGordon Ross int reg;
135947dc10d7SGordon Ross u32 val;
136047dc10d7SGordon Ross
136147dc10d7SGordon Ross /* Don't disable pipe A or pipe A PLLs if needed */
136247dc10d7SGordon Ross if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
136347dc10d7SGordon Ross return;
136447dc10d7SGordon Ross
136547dc10d7SGordon Ross /* Make sure the pipe isn't still relying on us */
136647dc10d7SGordon Ross assert_pipe_disabled(dev_priv, pipe);
136747dc10d7SGordon Ross
136847dc10d7SGordon Ross reg = DPLL(pipe);
136947dc10d7SGordon Ross val = I915_READ(reg);
137047dc10d7SGordon Ross val &= ~DPLL_VCO_ENABLE;
137147dc10d7SGordon Ross I915_WRITE(reg, val);
137247dc10d7SGordon Ross POSTING_READ(reg);
137347dc10d7SGordon Ross }
137447dc10d7SGordon Ross
vlv_wait_port_ready(struct drm_i915_private * dev_priv,int port)137547dc10d7SGordon Ross void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
137647dc10d7SGordon Ross {
137747dc10d7SGordon Ross u32 port_mask;
137847dc10d7SGordon Ross
137947dc10d7SGordon Ross if (!port)
138047dc10d7SGordon Ross port_mask = DPLL_PORTB_READY_MASK;
138147dc10d7SGordon Ross else
138247dc10d7SGordon Ross port_mask = DPLL_PORTC_READY_MASK;
138347dc10d7SGordon Ross
138447dc10d7SGordon Ross if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
138547dc10d7SGordon Ross DRM_ERROR("timed out waiting for port %c ready: 0x%08x\n",
138647dc10d7SGordon Ross 'B' + port, I915_READ(DPLL(0)));
138747dc10d7SGordon Ross }
138847dc10d7SGordon Ross
138947dc10d7SGordon Ross /**
139047dc10d7SGordon Ross * ironlake_enable_pch_pll - enable PCH PLL
139147dc10d7SGordon Ross * @dev_priv: i915 private structure
139247dc10d7SGordon Ross * @pipe: pipe PLL to enable
139347dc10d7SGordon Ross *
139447dc10d7SGordon Ross * The PCH PLL needs to be enabled before the PCH transcoder, since it
139547dc10d7SGordon Ross * drives the transcoder clock.
139647dc10d7SGordon Ross */
ironlake_enable_shared_dpll(struct intel_crtc * crtc)139747dc10d7SGordon Ross static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
139847dc10d7SGordon Ross {
139947dc10d7SGordon Ross struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
140047dc10d7SGordon Ross struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
140147dc10d7SGordon Ross
140247dc10d7SGordon Ross /* PCH PLLs only available on ILK, SNB and IVB */
140347dc10d7SGordon Ross BUG_ON(dev_priv->info->gen < 5);
140447dc10d7SGordon Ross if (pll == NULL) {
140547dc10d7SGordon Ross DRM_ERROR("pll is NULL");
140647dc10d7SGordon Ross return;
140747dc10d7SGordon Ross }
140847dc10d7SGordon Ross if (pll->refcount == 0) {
140947dc10d7SGordon Ross DRM_ERROR("pll refcount equal to 0");
141047dc10d7SGordon Ross return;
141147dc10d7SGordon Ross }
141247dc10d7SGordon Ross
141347dc10d7SGordon Ross DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
141447dc10d7SGordon Ross pll->name, pll->active, pll->on,
141547dc10d7SGordon Ross crtc->base.base.id);
141647dc10d7SGordon Ross
141747dc10d7SGordon Ross if (pll->active++) {
141847dc10d7SGordon Ross WARN_ON(!pll->on);
141947dc10d7SGordon Ross assert_shared_dpll_enabled(dev_priv, pll);
142047dc10d7SGordon Ross return;
142147dc10d7SGordon Ross }
142247dc10d7SGordon Ross WARN_ON(pll->on);
142347dc10d7SGordon Ross
142447dc10d7SGordon Ross DRM_DEBUG_KMS("enabling %s\n", pll->name);
142547dc10d7SGordon Ross pll->enable(dev_priv, pll);
142647dc10d7SGordon Ross pll->on = true;
142747dc10d7SGordon Ross }
142847dc10d7SGordon Ross
intel_disable_shared_dpll(struct intel_crtc * crtc)142947dc10d7SGordon Ross static void intel_disable_shared_dpll(struct intel_crtc *crtc)
143047dc10d7SGordon Ross {
143147dc10d7SGordon Ross struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
143247dc10d7SGordon Ross struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
143347dc10d7SGordon Ross
143447dc10d7SGordon Ross /* PCH only available on ILK+ */
143547dc10d7SGordon Ross BUG_ON(dev_priv->info->gen < 5);
143647dc10d7SGordon Ross if (pll == NULL) {
143747dc10d7SGordon Ross DRM_ERROR("pll is NULL");
143847dc10d7SGordon Ross return;
143947dc10d7SGordon Ross }
144047dc10d7SGordon Ross
144147dc10d7SGordon Ross if (pll->refcount == 0) {
144247dc10d7SGordon Ross DRM_ERROR("pll refcount equal to 0");
144347dc10d7SGordon Ross return;
144447dc10d7SGordon Ross }
144547dc10d7SGordon Ross
144647dc10d7SGordon Ross DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
144747dc10d7SGordon Ross pll->name, pll->active, pll->on,
144847dc10d7SGordon Ross crtc->base.base.id);
144947dc10d7SGordon Ross
145047dc10d7SGordon Ross if ((pll->active == 0)) {
145147dc10d7SGordon Ross assert_shared_dpll_disabled(dev_priv, pll);
145247dc10d7SGordon Ross return;
145347dc10d7SGordon Ross }
145447dc10d7SGordon Ross
145547dc10d7SGordon Ross assert_shared_dpll_enabled(dev_priv, pll);
145647dc10d7SGordon Ross WARN_ON(!pll->on);
145747dc10d7SGordon Ross if (--pll->active)
145847dc10d7SGordon Ross return;
145947dc10d7SGordon Ross
146047dc10d7SGordon Ross DRM_DEBUG_KMS("disabling %s\n", pll->name);
146147dc10d7SGordon Ross pll->disable(dev_priv, pll);
146247dc10d7SGordon Ross pll->on = false;
146347dc10d7SGordon Ross }
146447dc10d7SGordon Ross
ironlake_enable_pch_transcoder(struct drm_i915_private * dev_priv,enum pipe pipe)146547dc10d7SGordon Ross static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
146647dc10d7SGordon Ross enum pipe pipe)
146747dc10d7SGordon Ross {
146847dc10d7SGordon Ross struct drm_device *dev = dev_priv->dev;
146947dc10d7SGordon Ross struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
147047dc10d7SGordon Ross struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
147147dc10d7SGordon Ross uint32_t reg, val, pipeconf_val;
147247dc10d7SGordon Ross
147347dc10d7SGordon Ross /* PCH only available on ILK+ */
147447dc10d7SGordon Ross BUG_ON(dev_priv->info->gen < 5);
147547dc10d7SGordon Ross
147647dc10d7SGordon Ross /* Make sure PCH DPLL is enabled */
147747dc10d7SGordon Ross assert_shared_dpll_enabled(dev_priv,
147847dc10d7SGordon Ross intel_crtc_to_shared_dpll(intel_crtc));
147947dc10d7SGordon Ross
148047dc10d7SGordon Ross /* FDI must be feeding us bits for PCH ports */
148147dc10d7SGordon Ross assert_fdi_tx_enabled(dev_priv, pipe);
148247dc10d7SGordon Ross assert_fdi_rx_enabled(dev_priv, pipe);
148347dc10d7SGordon Ross
148447dc10d7SGordon Ross if (HAS_PCH_CPT(dev)) {
148547dc10d7SGordon Ross /* Workaround: Set the timing override bit before enabling the
148647dc10d7SGordon Ross * pch transcoder. */
148747dc10d7SGordon Ross reg = TRANS_CHICKEN2(pipe);
148847dc10d7SGordon Ross val = I915_READ(reg);
148947dc10d7SGordon Ross val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
149047dc10d7SGordon Ross I915_WRITE(reg, val);
149147dc10d7SGordon Ross }
149247dc10d7SGordon Ross
149347dc10d7SGordon Ross reg = PCH_TRANSCONF(pipe);
149447dc10d7SGordon Ross val = I915_READ(reg);
149547dc10d7SGordon Ross pipeconf_val = I915_READ(PIPECONF(pipe));
149647dc10d7SGordon Ross
149747dc10d7SGordon Ross if (HAS_PCH_IBX(dev_priv->dev)) {
149847dc10d7SGordon Ross /*
149947dc10d7SGordon Ross * make the BPC in transcoder be consistent with
150047dc10d7SGordon Ross * that in pipeconf reg.
150147dc10d7SGordon Ross */
150247dc10d7SGordon Ross val &= ~PIPECONF_BPC_MASK;
150347dc10d7SGordon Ross val |= pipeconf_val & PIPECONF_BPC_MASK;
150447dc10d7SGordon Ross }
150547dc10d7SGordon Ross
150647dc10d7SGordon Ross val &= ~TRANS_INTERLACE_MASK;
150747dc10d7SGordon Ross if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
150847dc10d7SGordon Ross if (HAS_PCH_IBX(dev_priv->dev) &&
150947dc10d7SGordon Ross intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
151047dc10d7SGordon Ross val |= TRANS_LEGACY_INTERLACED_ILK;
151147dc10d7SGordon Ross else
151247dc10d7SGordon Ross val |= TRANS_INTERLACED;
151347dc10d7SGordon Ross else
151447dc10d7SGordon Ross val |= TRANS_PROGRESSIVE;
151547dc10d7SGordon Ross
151647dc10d7SGordon Ross I915_WRITE(reg, val | TRANS_ENABLE);
151747dc10d7SGordon Ross if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
151847dc10d7SGordon Ross DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
151947dc10d7SGordon Ross }
152047dc10d7SGordon Ross
lpt_enable_pch_transcoder(struct drm_i915_private * dev_priv,enum transcoder cpu_transcoder)152147dc10d7SGordon Ross static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
152247dc10d7SGordon Ross enum transcoder cpu_transcoder)
152347dc10d7SGordon Ross {
152447dc10d7SGordon Ross u32 val, pipeconf_val;
152547dc10d7SGordon Ross
152647dc10d7SGordon Ross /* PCH only available on ILK+ */
152747dc10d7SGordon Ross BUG_ON(dev_priv->info->gen < 5);
152847dc10d7SGordon Ross
152947dc10d7SGordon Ross /* FDI must be feeding us bits for PCH ports */
153047dc10d7SGordon Ross assert_fdi_tx_enabled(dev_priv, (enum pipe)cpu_transcoder);
153147dc10d7SGordon Ross assert_fdi_rx_enabled(dev_priv, (enum pipe)TRANSCODER_A);
153247dc10d7SGordon Ross
153347dc10d7SGordon Ross /* Workaround: set timing override bit. */
153447dc10d7SGordon Ross val = I915_READ(_TRANSA_CHICKEN2);
153547dc10d7SGordon Ross val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
153647dc10d7SGordon Ross I915_WRITE(_TRANSA_CHICKEN2, val);
153747dc10d7SGordon Ross
153847dc10d7SGordon Ross val = TRANS_ENABLE;
153947dc10d7SGordon Ross pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
154047dc10d7SGordon Ross
154147dc10d7SGordon Ross if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
154247dc10d7SGordon Ross PIPECONF_INTERLACED_ILK)
154347dc10d7SGordon Ross val |= TRANS_INTERLACED;
154447dc10d7SGordon Ross else
154547dc10d7SGordon Ross val |= TRANS_PROGRESSIVE;
154647dc10d7SGordon Ross
154747dc10d7SGordon Ross I915_WRITE(LPT_TRANSCONF, val);
154847dc10d7SGordon Ross if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
154947dc10d7SGordon Ross DRM_ERROR("Failed to enable PCH transcoder\n");
155047dc10d7SGordon Ross }
155147dc10d7SGordon Ross
ironlake_disable_pch_transcoder(struct drm_i915_private * dev_priv,enum pipe pipe)155247dc10d7SGordon Ross static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
155347dc10d7SGordon Ross enum pipe pipe)
155447dc10d7SGordon Ross {
155547dc10d7SGordon Ross struct drm_device *dev = dev_priv->dev;
155647dc10d7SGordon Ross uint32_t reg, val;
155747dc10d7SGordon Ross
155847dc10d7SGordon Ross /* FDI relies on the transcoder */
155947dc10d7SGordon Ross assert_fdi_tx_disabled(dev_priv, pipe);
156047dc10d7SGordon Ross assert_fdi_rx_disabled(dev_priv, pipe);
156147dc10d7SGordon Ross
156247dc10d7SGordon Ross /* Ports must be off as well */
156347dc10d7SGordon Ross assert_pch_ports_disabled(dev_priv, pipe);
156447dc10d7SGordon Ross
156547dc10d7SGordon Ross reg = PCH_TRANSCONF(pipe);
156647dc10d7SGordon Ross val = I915_READ(reg);
156747dc10d7SGordon Ross val &= ~TRANS_ENABLE;
156847dc10d7SGordon Ross I915_WRITE(reg, val);
156947dc10d7SGordon Ross /* wait for PCH transcoder off, transcoder state */
157047dc10d7SGordon Ross if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
157147dc10d7SGordon Ross DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
157247dc10d7SGordon Ross
157347dc10d7SGordon Ross if (!HAS_PCH_IBX(dev)) {
157447dc10d7SGordon Ross /* Workaround: Clear the timing override chicken bit again. */
157547dc10d7SGordon Ross reg = TRANS_CHICKEN2(pipe);
157647dc10d7SGordon Ross val = I915_READ(reg);
157747dc10d7SGordon Ross val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
157847dc10d7SGordon Ross I915_WRITE(reg, val);
157947dc10d7SGordon Ross }
158047dc10d7SGordon Ross }
158147dc10d7SGordon Ross
lpt_disable_pch_transcoder(struct drm_i915_private * dev_priv)158247dc10d7SGordon Ross static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
158347dc10d7SGordon Ross {
158447dc10d7SGordon Ross u32 val;
158547dc10d7SGordon Ross
158647dc10d7SGordon Ross val = I915_READ(LPT_TRANSCONF);
158747dc10d7SGordon Ross val &= ~TRANS_ENABLE;
158847dc10d7SGordon Ross I915_WRITE(LPT_TRANSCONF, val);
158947dc10d7SGordon Ross /* wait for PCH transcoder off, transcoder state */
159047dc10d7SGordon Ross if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
159147dc10d7SGordon Ross DRM_ERROR("Failed to disable PCH transcoder\n");
159247dc10d7SGordon Ross
159347dc10d7SGordon Ross /* Workaround: clear timing override bit. */
159447dc10d7SGordon Ross val = I915_READ(_TRANSA_CHICKEN2);
159547dc10d7SGordon Ross val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
159647dc10d7SGordon Ross I915_WRITE(_TRANSA_CHICKEN2, val);
159747dc10d7SGordon Ross }
159847dc10d7SGordon Ross
159947dc10d7SGordon Ross /**
160047dc10d7SGordon Ross * intel_enable_pipe - enable a pipe, asserting requirements
160147dc10d7SGordon Ross * @dev_priv: i915 private structure
160247dc10d7SGordon Ross * @pipe: pipe to enable
160347dc10d7SGordon Ross * @pch_port: on ILK+, is this pipe driving a PCH port or not
160447dc10d7SGordon Ross *
160547dc10d7SGordon Ross * Enable @pipe, making sure that various hardware specific requirements
160647dc10d7SGordon Ross * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
160747dc10d7SGordon Ross *
160847dc10d7SGordon Ross * @pipe should be %PIPE_A or %PIPE_B.
160947dc10d7SGordon Ross *
161047dc10d7SGordon Ross * Will wait until the pipe is actually running (i.e. first vblank) before
161147dc10d7SGordon Ross * returning.
161247dc10d7SGordon Ross */
intel_enable_pipe(struct drm_i915_private * dev_priv,enum pipe pipe,bool pch_port)161347dc10d7SGordon Ross static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
161447dc10d7SGordon Ross bool pch_port)
161547dc10d7SGordon Ross {
161647dc10d7SGordon Ross enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
161747dc10d7SGordon Ross pipe);
161847dc10d7SGordon Ross enum pipe pch_transcoder;
161947dc10d7SGordon Ross int reg;
162047dc10d7SGordon Ross u32 val;
162147dc10d7SGordon Ross
162247dc10d7SGordon Ross assert_planes_disabled(dev_priv, pipe);
162347dc10d7SGordon Ross assert_sprites_disabled(dev_priv, pipe);
162447dc10d7SGordon Ross
162547dc10d7SGordon Ross if (HAS_PCH_LPT(dev_priv->dev))
162647dc10d7SGordon Ross pch_transcoder = (enum pipe)TRANSCODER_A;
162747dc10d7SGordon Ross else
162847dc10d7SGordon Ross pch_transcoder = pipe;
162947dc10d7SGordon Ross
163047dc10d7SGordon Ross /*
163147dc10d7SGordon Ross * A pipe without a PLL won't actually be able to drive bits from
163247dc10d7SGordon Ross * a plane. On ILK+ the pipe PLLs are integrated, so we don't
163347dc10d7SGordon Ross * need the check.
163447dc10d7SGordon Ross */
163547dc10d7SGordon Ross if (!HAS_PCH_SPLIT(dev_priv->dev))
163647dc10d7SGordon Ross assert_pll_enabled(dev_priv, pipe);
163747dc10d7SGordon Ross else {
163847dc10d7SGordon Ross if (pch_port) {
163947dc10d7SGordon Ross /* if driving the PCH, we need FDI enabled */
164047dc10d7SGordon Ross assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
164147dc10d7SGordon Ross assert_fdi_tx_pll_enabled(dev_priv,
164247dc10d7SGordon Ross (enum pipe) cpu_transcoder);
164347dc10d7SGordon Ross }
164447dc10d7SGordon Ross /* FIXME: assert CPU port conditions for SNB+ */
164547dc10d7SGordon Ross }
164647dc10d7SGordon Ross
164747dc10d7SGordon Ross reg = PIPECONF(cpu_transcoder);
164847dc10d7SGordon Ross val = I915_READ(reg);
164947dc10d7SGordon Ross if (val & PIPECONF_ENABLE)
165047dc10d7SGordon Ross return;
165147dc10d7SGordon Ross
165247dc10d7SGordon Ross I915_WRITE(reg, val | PIPECONF_ENABLE);
165347dc10d7SGordon Ross intel_wait_for_vblank(dev_priv->dev, pipe);
165447dc10d7SGordon Ross }
165547dc10d7SGordon Ross
165647dc10d7SGordon Ross /**
165747dc10d7SGordon Ross * intel_disable_pipe - disable a pipe, asserting requirements
165847dc10d7SGordon Ross * @dev_priv: i915 private structure
165947dc10d7SGordon Ross * @pipe: pipe to disable
166047dc10d7SGordon Ross *
166147dc10d7SGordon Ross * Disable @pipe, making sure that various hardware specific requirements
166247dc10d7SGordon Ross * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
166347dc10d7SGordon Ross *
166447dc10d7SGordon Ross * @pipe should be %PIPE_A or %PIPE_B.
166547dc10d7SGordon Ross *
166647dc10d7SGordon Ross * Will wait until the pipe has shut down before returning.
166747dc10d7SGordon Ross */
intel_disable_pipe(struct drm_i915_private * dev_priv,enum pipe pipe)166847dc10d7SGordon Ross static void intel_disable_pipe(struct drm_i915_private *dev_priv,
166947dc10d7SGordon Ross enum pipe pipe)
167047dc10d7SGordon Ross {
167147dc10d7SGordon Ross enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
167247dc10d7SGordon Ross pipe);
167347dc10d7SGordon Ross int reg;
167447dc10d7SGordon Ross u32 val;
167547dc10d7SGordon Ross
167647dc10d7SGordon Ross /*
167747dc10d7SGordon Ross * Make sure planes won't keep trying to pump pixels to us,
167847dc10d7SGordon Ross * or we might hang the display.
167947dc10d7SGordon Ross */
168047dc10d7SGordon Ross assert_planes_disabled(dev_priv, pipe);
168147dc10d7SGordon Ross assert_sprites_disabled(dev_priv, pipe);
168247dc10d7SGordon Ross
168347dc10d7SGordon Ross /* Don't disable pipe A or pipe A PLLs if needed */
168447dc10d7SGordon Ross if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
168547dc10d7SGordon Ross return;
168647dc10d7SGordon Ross
168747dc10d7SGordon Ross reg = PIPECONF(cpu_transcoder);
168847dc10d7SGordon Ross val = I915_READ(reg);
168947dc10d7SGordon Ross if ((val & PIPECONF_ENABLE) == 0)
169047dc10d7SGordon Ross return;
169147dc10d7SGordon Ross
169247dc10d7SGordon Ross I915_WRITE(reg, val & ~PIPECONF_ENABLE);
169347dc10d7SGordon Ross intel_wait_for_pipe_off(dev_priv->dev, pipe);
169447dc10d7SGordon Ross }
169547dc10d7SGordon Ross
169647dc10d7SGordon Ross /*
169747dc10d7SGordon Ross * Plane regs are double buffered, going from enabled->disabled needs a
169847dc10d7SGordon Ross * trigger in order to latch. The display address reg provides this.
169947dc10d7SGordon Ross */
intel_flush_display_plane(struct drm_i915_private * dev_priv,enum plane plane)170047dc10d7SGordon Ross void intel_flush_display_plane(struct drm_i915_private *dev_priv,
170147dc10d7SGordon Ross enum plane plane)
170247dc10d7SGordon Ross {
170347dc10d7SGordon Ross if (dev_priv->info->gen >= 4)
170447dc10d7SGordon Ross I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
170547dc10d7SGordon Ross else
170647dc10d7SGordon Ross I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
170747dc10d7SGordon Ross }
170847dc10d7SGordon Ross
170947dc10d7SGordon Ross /**
171047dc10d7SGordon Ross * intel_enable_plane - enable a display plane on a given pipe
171147dc10d7SGordon Ross * @dev_priv: i915 private structure
171247dc10d7SGordon Ross * @plane: plane to enable
171347dc10d7SGordon Ross * @pipe: pipe being fed
171447dc10d7SGordon Ross *
171547dc10d7SGordon Ross * Enable @plane on @pipe, making sure that @pipe is running first.
171647dc10d7SGordon Ross */
intel_enable_plane(struct drm_i915_private * dev_priv,enum plane plane,enum pipe pipe)171747dc10d7SGordon Ross static void intel_enable_plane(struct drm_i915_private *dev_priv,
171847dc10d7SGordon Ross enum plane plane, enum pipe pipe)
171947dc10d7SGordon Ross {
172047dc10d7SGordon Ross int reg;
172147dc10d7SGordon Ross u32 val;
172247dc10d7SGordon Ross
172347dc10d7SGordon Ross /* If the pipe isn't enabled, we can't pump pixels and may hang */
172447dc10d7SGordon Ross assert_pipe_enabled(dev_priv, pipe);
172547dc10d7SGordon Ross
172647dc10d7SGordon Ross reg = DSPCNTR(plane);
172747dc10d7SGordon Ross val = I915_READ(reg);
172847dc10d7SGordon Ross if (val & DISPLAY_PLANE_ENABLE)
172947dc10d7SGordon Ross return;
173047dc10d7SGordon Ross
173147dc10d7SGordon Ross I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
173247dc10d7SGordon Ross intel_flush_display_plane(dev_priv, plane);
173347dc10d7SGordon Ross intel_wait_for_vblank(dev_priv->dev, pipe);
173447dc10d7SGordon Ross }
173547dc10d7SGordon Ross
173647dc10d7SGordon Ross /**
173747dc10d7SGordon Ross * intel_disable_plane - disable a display plane
173847dc10d7SGordon Ross * @dev_priv: i915 private structure
173947dc10d7SGordon Ross * @plane: plane to disable
174047dc10d7SGordon Ross * @pipe: pipe consuming the data
174147dc10d7SGordon Ross *
174247dc10d7SGordon Ross * Disable @plane; should be an independent operation.
174347dc10d7SGordon Ross */
intel_disable_plane(struct drm_i915_private * dev_priv,enum plane plane,enum pipe pipe)174447dc10d7SGordon Ross static void intel_disable_plane(struct drm_i915_private *dev_priv,
174547dc10d7SGordon Ross enum plane plane, enum pipe pipe)
174647dc10d7SGordon Ross {
174747dc10d7SGordon Ross int reg;
174847dc10d7SGordon Ross u32 val;
174947dc10d7SGordon Ross
175047dc10d7SGordon Ross reg = DSPCNTR(plane);
175147dc10d7SGordon Ross val = I915_READ(reg);
175247dc10d7SGordon Ross if ((val & DISPLAY_PLANE_ENABLE) == 0)
175347dc10d7SGordon Ross return;
175447dc10d7SGordon Ross
175547dc10d7SGordon Ross I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
175647dc10d7SGordon Ross intel_flush_display_plane(dev_priv, plane);
175747dc10d7SGordon Ross intel_wait_for_vblank(dev_priv->dev, pipe);
175847dc10d7SGordon Ross }
175947dc10d7SGordon Ross
need_vtd_wa(struct drm_device * dev)176047dc10d7SGordon Ross static bool need_vtd_wa(struct drm_device *dev)
176147dc10d7SGordon Ross {
176247dc10d7SGordon Ross #ifdef CONFIG_INTEL_IOMMU
176347dc10d7SGordon Ross if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
176447dc10d7SGordon Ross return true;
176547dc10d7SGordon Ross #endif
176647dc10d7SGordon Ross return false;
176747dc10d7SGordon Ross }
176847dc10d7SGordon Ross
176947dc10d7SGordon Ross int
intel_pin_and_fence_fb_obj(struct drm_device * dev,struct drm_i915_gem_object * obj,struct intel_ring_buffer * pipelined)177047dc10d7SGordon Ross intel_pin_and_fence_fb_obj(struct drm_device *dev,
177147dc10d7SGordon Ross struct drm_i915_gem_object *obj,
177247dc10d7SGordon Ross struct intel_ring_buffer *pipelined)
177347dc10d7SGordon Ross {
177447dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
177547dc10d7SGordon Ross u32 alignment;
177647dc10d7SGordon Ross int ret;
177747dc10d7SGordon Ross
177847dc10d7SGordon Ross switch (obj->tiling_mode) {
177947dc10d7SGordon Ross case I915_TILING_NONE:
178047dc10d7SGordon Ross if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
178147dc10d7SGordon Ross alignment = 128 * 1024;
178247dc10d7SGordon Ross else if (INTEL_INFO(dev)->gen >= 4)
178347dc10d7SGordon Ross alignment = 4 * 1024;
178447dc10d7SGordon Ross else
178547dc10d7SGordon Ross alignment = 64 * 1024;
178647dc10d7SGordon Ross break;
178747dc10d7SGordon Ross case I915_TILING_X:
178847dc10d7SGordon Ross /* pin() will align the object as required by fence */
178947dc10d7SGordon Ross alignment = 0;
179047dc10d7SGordon Ross break;
179147dc10d7SGordon Ross case I915_TILING_Y:
179247dc10d7SGordon Ross /* Despite that we check this in framebuffer_init userspace can
179347dc10d7SGordon Ross * screw us over and change the tiling after the fact. Only
179447dc10d7SGordon Ross * pinned buffers can't change their tiling. */
179547dc10d7SGordon Ross DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
179647dc10d7SGordon Ross return -EINVAL;
179747dc10d7SGordon Ross default:
179847dc10d7SGordon Ross BUG();
179947dc10d7SGordon Ross return -EINVAL;
180047dc10d7SGordon Ross }
180147dc10d7SGordon Ross
180247dc10d7SGordon Ross /* Note that the w/a also requires 64 PTE of padding following the
180347dc10d7SGordon Ross * bo. We currently fill all unused PTE with the shadow page and so
180447dc10d7SGordon Ross * we should always have valid PTE following the scanout preventing
180547dc10d7SGordon Ross * the VT-d warning.
180647dc10d7SGordon Ross */
180747dc10d7SGordon Ross if (need_vtd_wa(dev) && alignment < 256 * 1024)
180847dc10d7SGordon Ross alignment = 256 * 1024;
180947dc10d7SGordon Ross
181047dc10d7SGordon Ross dev_priv->mm.interruptible = false;
181147dc10d7SGordon Ross ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
181247dc10d7SGordon Ross if (ret)
181347dc10d7SGordon Ross goto err_interruptible;
181447dc10d7SGordon Ross
181547dc10d7SGordon Ross /* Install a fence for tiled scan-out. Pre-i965 always needs a
181647dc10d7SGordon Ross * fence, whereas 965+ only requires a fence if using
181747dc10d7SGordon Ross * framebuffer compression. For simplicity, we always install
181847dc10d7SGordon Ross * a fence as the cost is not that onerous.
181947dc10d7SGordon Ross */
182047dc10d7SGordon Ross ret = i915_gem_object_get_fence(obj);
182147dc10d7SGordon Ross if (ret)
182247dc10d7SGordon Ross goto err_unpin;
182347dc10d7SGordon Ross
182447dc10d7SGordon Ross i915_gem_object_pin_fence(obj);
182547dc10d7SGordon Ross
182647dc10d7SGordon Ross dev_priv->mm.interruptible = true;
182747dc10d7SGordon Ross return 0;
182847dc10d7SGordon Ross
182947dc10d7SGordon Ross err_unpin:
183047dc10d7SGordon Ross i915_gem_object_unpin(obj);
183147dc10d7SGordon Ross err_interruptible:
183247dc10d7SGordon Ross dev_priv->mm.interruptible = true;
183347dc10d7SGordon Ross return ret;
183447dc10d7SGordon Ross }
183547dc10d7SGordon Ross
intel_unpin_fb_obj(struct drm_i915_gem_object * obj)183647dc10d7SGordon Ross void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
183747dc10d7SGordon Ross {
183847dc10d7SGordon Ross i915_gem_object_unpin_fence(obj);
183947dc10d7SGordon Ross i915_gem_object_unpin(obj);
184047dc10d7SGordon Ross }
184147dc10d7SGordon Ross
184247dc10d7SGordon Ross /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
184347dc10d7SGordon Ross * is assumed to be a power-of-two. */
intel_gen4_compute_page_offset(int * x,int * y,unsigned int tiling_mode,unsigned int cpp,unsigned int pitch)184447dc10d7SGordon Ross unsigned long intel_gen4_compute_page_offset(int *x, int *y,
184547dc10d7SGordon Ross unsigned int tiling_mode,
184647dc10d7SGordon Ross unsigned int cpp,
184747dc10d7SGordon Ross unsigned int pitch)
184847dc10d7SGordon Ross {
184947dc10d7SGordon Ross if (tiling_mode != I915_TILING_NONE) {
185047dc10d7SGordon Ross unsigned int tile_rows, tiles;
185147dc10d7SGordon Ross
185247dc10d7SGordon Ross tile_rows = *y / 8;
185347dc10d7SGordon Ross *y %= 8;
185447dc10d7SGordon Ross
185547dc10d7SGordon Ross tiles = *x / (512/cpp);
185647dc10d7SGordon Ross *x %= 512/cpp;
185747dc10d7SGordon Ross
185847dc10d7SGordon Ross return tile_rows * pitch * 8 + tiles * 4096;
185947dc10d7SGordon Ross } else {
186047dc10d7SGordon Ross unsigned int offset;
186147dc10d7SGordon Ross
186247dc10d7SGordon Ross offset = *y * pitch + *x * cpp;
186347dc10d7SGordon Ross *y = 0;
186447dc10d7SGordon Ross *x = (offset & 4095) / cpp;
186547dc10d7SGordon Ross return offset & -4096;
186647dc10d7SGordon Ross }
186747dc10d7SGordon Ross }
186847dc10d7SGordon Ross
i9xx_update_plane(struct drm_crtc * crtc,struct drm_framebuffer * fb,int x,int y)186947dc10d7SGordon Ross static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
187047dc10d7SGordon Ross int x, int y)
187147dc10d7SGordon Ross {
187247dc10d7SGordon Ross struct drm_device *dev = crtc->dev;
187347dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
187447dc10d7SGordon Ross struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
187547dc10d7SGordon Ross struct intel_framebuffer *intel_fb;
187647dc10d7SGordon Ross struct drm_i915_gem_object *obj;
187747dc10d7SGordon Ross int plane = intel_crtc->plane;
187847dc10d7SGordon Ross unsigned long linear_offset;
187947dc10d7SGordon Ross u32 dspcntr;
188047dc10d7SGordon Ross u32 reg;
188147dc10d7SGordon Ross
188247dc10d7SGordon Ross switch (plane) {
188347dc10d7SGordon Ross case 0:
188447dc10d7SGordon Ross case 1:
188547dc10d7SGordon Ross break;
188647dc10d7SGordon Ross default:
188747dc10d7SGordon Ross DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
188847dc10d7SGordon Ross return -EINVAL;
188947dc10d7SGordon Ross }
189047dc10d7SGordon Ross
189147dc10d7SGordon Ross intel_fb = to_intel_framebuffer(fb);
189247dc10d7SGordon Ross obj = intel_fb->obj;
189347dc10d7SGordon Ross
189447dc10d7SGordon Ross reg = DSPCNTR(plane);
189547dc10d7SGordon Ross dspcntr = I915_READ(reg);
189647dc10d7SGordon Ross /* Mask out pixel format bits in case we change it */
189747dc10d7SGordon Ross dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
189847dc10d7SGordon Ross switch (fb->pixel_format) {
189947dc10d7SGordon Ross case DRM_FORMAT_C8:
190047dc10d7SGordon Ross dspcntr |= DISPPLANE_8BPP;
190147dc10d7SGordon Ross break;
190247dc10d7SGordon Ross case DRM_FORMAT_XRGB1555:
190347dc10d7SGordon Ross case DRM_FORMAT_ARGB1555:
190447dc10d7SGordon Ross dspcntr |= DISPPLANE_BGRX555;
190547dc10d7SGordon Ross break;
190647dc10d7SGordon Ross case DRM_FORMAT_RGB565:
190747dc10d7SGordon Ross dspcntr |= DISPPLANE_BGRX565;
190847dc10d7SGordon Ross break;
190947dc10d7SGordon Ross case DRM_FORMAT_XRGB8888:
191047dc10d7SGordon Ross case DRM_FORMAT_ARGB8888:
191147dc10d7SGordon Ross dspcntr |= DISPPLANE_BGRX888;
191247dc10d7SGordon Ross break;
191347dc10d7SGordon Ross case DRM_FORMAT_XBGR8888:
191447dc10d7SGordon Ross case DRM_FORMAT_ABGR8888:
191547dc10d7SGordon Ross dspcntr |= DISPPLANE_RGBX888;
191647dc10d7SGordon Ross break;
191747dc10d7SGordon Ross case DRM_FORMAT_XRGB2101010:
191847dc10d7SGordon Ross case DRM_FORMAT_ARGB2101010:
191947dc10d7SGordon Ross dspcntr |= DISPPLANE_BGRX101010;
192047dc10d7SGordon Ross break;
192147dc10d7SGordon Ross case DRM_FORMAT_XBGR2101010:
192247dc10d7SGordon Ross case DRM_FORMAT_ABGR2101010:
192347dc10d7SGordon Ross dspcntr |= DISPPLANE_RGBX101010;
192447dc10d7SGordon Ross break;
192547dc10d7SGordon Ross default:
192647dc10d7SGordon Ross DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
192747dc10d7SGordon Ross return -EINVAL;
192847dc10d7SGordon Ross }
192947dc10d7SGordon Ross
193047dc10d7SGordon Ross if (INTEL_INFO(dev)->gen >= 4) {
193147dc10d7SGordon Ross if (obj->tiling_mode != I915_TILING_NONE)
193247dc10d7SGordon Ross dspcntr |= DISPPLANE_TILED;
193347dc10d7SGordon Ross else
193447dc10d7SGordon Ross dspcntr &= ~DISPPLANE_TILED;
193547dc10d7SGordon Ross }
193647dc10d7SGordon Ross
193747dc10d7SGordon Ross if (IS_G4X(dev))
193847dc10d7SGordon Ross dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
193947dc10d7SGordon Ross
194047dc10d7SGordon Ross I915_WRITE(reg, dspcntr);
194147dc10d7SGordon Ross
194247dc10d7SGordon Ross linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
194347dc10d7SGordon Ross
194447dc10d7SGordon Ross if (INTEL_INFO(dev)->gen >= 4) {
194547dc10d7SGordon Ross intel_crtc->dspaddr_offset =
194647dc10d7SGordon Ross intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
194747dc10d7SGordon Ross fb->bits_per_pixel / 8,
194847dc10d7SGordon Ross fb->pitches[0]);
194947dc10d7SGordon Ross linear_offset -= intel_crtc->dspaddr_offset;
195047dc10d7SGordon Ross } else {
195147dc10d7SGordon Ross intel_crtc->dspaddr_offset = linear_offset;
195247dc10d7SGordon Ross }
195347dc10d7SGordon Ross
195447dc10d7SGordon Ross DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
195547dc10d7SGordon Ross obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
195647dc10d7SGordon Ross I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
195747dc10d7SGordon Ross if (INTEL_INFO(dev)->gen >= 4) {
195847dc10d7SGordon Ross I915_MODIFY_DISPBASE(DSPSURF(plane),
195947dc10d7SGordon Ross obj->gtt_offset + intel_crtc->dspaddr_offset);
196047dc10d7SGordon Ross I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
196147dc10d7SGordon Ross I915_WRITE(DSPLINOFF(plane), linear_offset);
196247dc10d7SGordon Ross } else
196347dc10d7SGordon Ross I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
196447dc10d7SGordon Ross POSTING_READ(reg);
196547dc10d7SGordon Ross
196647dc10d7SGordon Ross return 0;
196747dc10d7SGordon Ross }
196847dc10d7SGordon Ross
ironlake_update_plane(struct drm_crtc * crtc,struct drm_framebuffer * fb,int x,int y)196947dc10d7SGordon Ross static int ironlake_update_plane(struct drm_crtc *crtc,
197047dc10d7SGordon Ross struct drm_framebuffer *fb, int x, int y)
197147dc10d7SGordon Ross {
197247dc10d7SGordon Ross struct drm_device *dev = crtc->dev;
197347dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
197447dc10d7SGordon Ross struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
197547dc10d7SGordon Ross struct intel_framebuffer *intel_fb;
197647dc10d7SGordon Ross struct drm_i915_gem_object *obj;
197747dc10d7SGordon Ross int plane = intel_crtc->plane;
197847dc10d7SGordon Ross unsigned long linear_offset;
197947dc10d7SGordon Ross u32 dspcntr;
198047dc10d7SGordon Ross u32 reg;
198147dc10d7SGordon Ross
198247dc10d7SGordon Ross switch (plane) {
198347dc10d7SGordon Ross case 0:
198447dc10d7SGordon Ross case 1:
198547dc10d7SGordon Ross case 2:
198647dc10d7SGordon Ross break;
198747dc10d7SGordon Ross default:
198847dc10d7SGordon Ross DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
198947dc10d7SGordon Ross return -EINVAL;
199047dc10d7SGordon Ross }
199147dc10d7SGordon Ross
199247dc10d7SGordon Ross intel_fb = to_intel_framebuffer(fb);
199347dc10d7SGordon Ross obj = intel_fb->obj;
199447dc10d7SGordon Ross
199547dc10d7SGordon Ross reg = DSPCNTR(plane);
199647dc10d7SGordon Ross dspcntr = I915_READ(reg);
199747dc10d7SGordon Ross /* Mask out pixel format bits in case we change it */
199847dc10d7SGordon Ross dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
199947dc10d7SGordon Ross switch (fb->pixel_format) {
200047dc10d7SGordon Ross case DRM_FORMAT_C8:
200147dc10d7SGordon Ross dspcntr |= DISPPLANE_8BPP;
200247dc10d7SGordon Ross break;
200347dc10d7SGordon Ross case DRM_FORMAT_RGB565:
200447dc10d7SGordon Ross dspcntr |= DISPPLANE_BGRX565;
200547dc10d7SGordon Ross break;
200647dc10d7SGordon Ross case DRM_FORMAT_XRGB8888:
200747dc10d7SGordon Ross case DRM_FORMAT_ARGB8888:
200847dc10d7SGordon Ross dspcntr |= DISPPLANE_BGRX888;
200947dc10d7SGordon Ross break;
201047dc10d7SGordon Ross case DRM_FORMAT_XBGR8888:
201147dc10d7SGordon Ross case DRM_FORMAT_ABGR8888:
201247dc10d7SGordon Ross dspcntr |= DISPPLANE_RGBX888;
201347dc10d7SGordon Ross break;
201447dc10d7SGordon Ross case DRM_FORMAT_XRGB2101010:
201547dc10d7SGordon Ross case DRM_FORMAT_ARGB2101010:
201647dc10d7SGordon Ross dspcntr |= DISPPLANE_BGRX101010;
201747dc10d7SGordon Ross break;
201847dc10d7SGordon Ross case DRM_FORMAT_XBGR2101010:
201947dc10d7SGordon Ross case DRM_FORMAT_ABGR2101010:
202047dc10d7SGordon Ross dspcntr |= DISPPLANE_RGBX101010;
202147dc10d7SGordon Ross break;
202247dc10d7SGordon Ross default:
202347dc10d7SGordon Ross DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
202447dc10d7SGordon Ross return -EINVAL;
202547dc10d7SGordon Ross }
202647dc10d7SGordon Ross
202747dc10d7SGordon Ross if (obj->tiling_mode != I915_TILING_NONE)
202847dc10d7SGordon Ross dspcntr |= DISPPLANE_TILED;
202947dc10d7SGordon Ross else
203047dc10d7SGordon Ross dspcntr &= ~DISPPLANE_TILED;
203147dc10d7SGordon Ross
203247dc10d7SGordon Ross /* must disable */
203347dc10d7SGordon Ross dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
203447dc10d7SGordon Ross
203547dc10d7SGordon Ross I915_WRITE(reg, dspcntr);
203647dc10d7SGordon Ross
203747dc10d7SGordon Ross linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
203847dc10d7SGordon Ross intel_crtc->dspaddr_offset =
203947dc10d7SGordon Ross intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
204047dc10d7SGordon Ross fb->bits_per_pixel / 8,
204147dc10d7SGordon Ross fb->pitches[0]);
204247dc10d7SGordon Ross linear_offset -= intel_crtc->dspaddr_offset;
204347dc10d7SGordon Ross
204447dc10d7SGordon Ross DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
204547dc10d7SGordon Ross obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
204647dc10d7SGordon Ross I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
204747dc10d7SGordon Ross I915_MODIFY_DISPBASE(DSPSURF(plane),
204847dc10d7SGordon Ross obj->gtt_offset + intel_crtc->dspaddr_offset);
204947dc10d7SGordon Ross if (IS_HASWELL(dev)) {
205047dc10d7SGordon Ross I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
205147dc10d7SGordon Ross } else {
205247dc10d7SGordon Ross I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
205347dc10d7SGordon Ross I915_WRITE(DSPLINOFF(plane), linear_offset);
205447dc10d7SGordon Ross }
205547dc10d7SGordon Ross POSTING_READ(reg);
205647dc10d7SGordon Ross
205747dc10d7SGordon Ross return 0;
205847dc10d7SGordon Ross }
205947dc10d7SGordon Ross
206047dc10d7SGordon Ross /* Assume fb object is pinned & idle & fenced and just update base pointers */
206147dc10d7SGordon Ross static int
intel_pipe_set_base_atomic(struct drm_crtc * crtc,struct drm_framebuffer * fb,int x,int y,enum mode_set_atomic state)206247dc10d7SGordon Ross intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
206347dc10d7SGordon Ross int x, int y, enum mode_set_atomic state)
206447dc10d7SGordon Ross {
206547dc10d7SGordon Ross struct drm_device *dev = crtc->dev;
206647dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
206747dc10d7SGordon Ross
206847dc10d7SGordon Ross if (dev_priv->display.disable_fbc)
206947dc10d7SGordon Ross dev_priv->display.disable_fbc(dev);
207047dc10d7SGordon Ross intel_increase_pllclock(crtc);
207147dc10d7SGordon Ross
207247dc10d7SGordon Ross return dev_priv->display.update_plane(crtc, fb, x, y);
207347dc10d7SGordon Ross }
207447dc10d7SGordon Ross
intel_display_handle_reset(struct drm_device * dev)207547dc10d7SGordon Ross void intel_display_handle_reset(struct drm_device *dev)
207647dc10d7SGordon Ross {
207747dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
207847dc10d7SGordon Ross struct drm_crtc *crtc;
207947dc10d7SGordon Ross
208047dc10d7SGordon Ross /*
208147dc10d7SGordon Ross * Flips in the rings have been nuked by the reset,
208247dc10d7SGordon Ross * so complete all pending flips so that user space
208347dc10d7SGordon Ross * will get its events and not get stuck.
208447dc10d7SGordon Ross *
208547dc10d7SGordon Ross * Also update the base address of all primary
208647dc10d7SGordon Ross * planes to the the last fb to make sure we're
208747dc10d7SGordon Ross * showing the correct fb after a reset.
208847dc10d7SGordon Ross *
208947dc10d7SGordon Ross * Need to make two loops over the crtcs so that we
209047dc10d7SGordon Ross * don't try to grab a crtc mutex before the
209147dc10d7SGordon Ross * pending_flip_queue really got woken up.
209247dc10d7SGordon Ross */
209347dc10d7SGordon Ross
209447dc10d7SGordon Ross list_for_each_entry(crtc, struct drm_crtc, &dev->mode_config.crtc_list, head) {
209547dc10d7SGordon Ross struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
209647dc10d7SGordon Ross enum plane plane = intel_crtc->plane;
209747dc10d7SGordon Ross
209847dc10d7SGordon Ross intel_prepare_page_flip(dev, plane);
209947dc10d7SGordon Ross intel_finish_page_flip_plane(dev, plane);
210047dc10d7SGordon Ross }
210147dc10d7SGordon Ross
210247dc10d7SGordon Ross list_for_each_entry(crtc, struct drm_crtc, &dev->mode_config.crtc_list, head) {
210347dc10d7SGordon Ross struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
210447dc10d7SGordon Ross
210547dc10d7SGordon Ross mutex_lock(&crtc->mutex);
210647dc10d7SGordon Ross if (intel_crtc->active)
210747dc10d7SGordon Ross dev_priv->display.update_plane(crtc, crtc->fb,
210847dc10d7SGordon Ross crtc->x, crtc->y);
210947dc10d7SGordon Ross mutex_unlock(&crtc->mutex);
211047dc10d7SGordon Ross }
211147dc10d7SGordon Ross }
211247dc10d7SGordon Ross
211347dc10d7SGordon Ross static int
intel_finish_fb(struct drm_framebuffer * old_fb)211447dc10d7SGordon Ross intel_finish_fb(struct drm_framebuffer *old_fb)
211547dc10d7SGordon Ross {
211647dc10d7SGordon Ross struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
211747dc10d7SGordon Ross struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
211847dc10d7SGordon Ross bool was_interruptible = dev_priv->mm.interruptible;
211947dc10d7SGordon Ross int ret;
212047dc10d7SGordon Ross
212147dc10d7SGordon Ross /* Big Hammer, we also need to ensure that any pending
212247dc10d7SGordon Ross * MI_WAIT_FOR_EVENT inside a user batch buffer on the
212347dc10d7SGordon Ross * current scanout is retired before unpinning the old
212447dc10d7SGordon Ross * framebuffer.
212547dc10d7SGordon Ross *
212647dc10d7SGordon Ross * This should only fail upon a hung GPU, in which case we
212747dc10d7SGordon Ross * can safely continue.
212847dc10d7SGordon Ross */
212947dc10d7SGordon Ross dev_priv->mm.interruptible = false;
213047dc10d7SGordon Ross ret = i915_gem_object_finish_gpu(obj);
213147dc10d7SGordon Ross dev_priv->mm.interruptible = was_interruptible;
213247dc10d7SGordon Ross
213347dc10d7SGordon Ross return ret;
213447dc10d7SGordon Ross }
213547dc10d7SGordon Ross
intel_crtc_update_sarea_pos(struct drm_crtc * crtc,int x,int y)213647dc10d7SGordon Ross static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
213747dc10d7SGordon Ross {
213847dc10d7SGordon Ross struct drm_device *dev = crtc->dev;
213947dc10d7SGordon Ross struct drm_i915_master_private *master_priv;
214047dc10d7SGordon Ross struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
214147dc10d7SGordon Ross
214247dc10d7SGordon Ross if (!dev->primary->master)
214347dc10d7SGordon Ross return;
214447dc10d7SGordon Ross
214547dc10d7SGordon Ross master_priv = dev->primary->master->driver_priv;
214647dc10d7SGordon Ross if (!master_priv->sarea_priv)
214747dc10d7SGordon Ross return;
214847dc10d7SGordon Ross
214947dc10d7SGordon Ross switch (intel_crtc->pipe) {
215047dc10d7SGordon Ross case 0:
215147dc10d7SGordon Ross master_priv->sarea_priv->pipeA_x = x;
215247dc10d7SGordon Ross master_priv->sarea_priv->pipeA_y = y;
215347dc10d7SGordon Ross break;
215447dc10d7SGordon Ross case 1:
215547dc10d7SGordon Ross master_priv->sarea_priv->pipeB_x = x;
215647dc10d7SGordon Ross master_priv->sarea_priv->pipeB_y = y;
215747dc10d7SGordon Ross break;
215847dc10d7SGordon Ross default:
215947dc10d7SGordon Ross break;
216047dc10d7SGordon Ross }
216147dc10d7SGordon Ross }
216247dc10d7SGordon Ross
216347dc10d7SGordon Ross static int
intel_pipe_set_base(struct drm_crtc * crtc,int x,int y,struct drm_framebuffer * fb)216447dc10d7SGordon Ross intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
216547dc10d7SGordon Ross struct drm_framebuffer *fb)
216647dc10d7SGordon Ross {
216747dc10d7SGordon Ross struct drm_device *dev = crtc->dev;
216847dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
216947dc10d7SGordon Ross struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
217047dc10d7SGordon Ross struct drm_framebuffer *old_fb;
217147dc10d7SGordon Ross int ret;
217247dc10d7SGordon Ross
217347dc10d7SGordon Ross /* no fb bound */
217447dc10d7SGordon Ross if (!fb) {
217547dc10d7SGordon Ross DRM_ERROR("No FB bound\n");
217647dc10d7SGordon Ross return 0;
217747dc10d7SGordon Ross }
217847dc10d7SGordon Ross
217947dc10d7SGordon Ross if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
218047dc10d7SGordon Ross DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
218147dc10d7SGordon Ross plane_name(intel_crtc->plane),
218247dc10d7SGordon Ross INTEL_INFO(dev)->num_pipes);
218347dc10d7SGordon Ross return -EINVAL;
218447dc10d7SGordon Ross }
218547dc10d7SGordon Ross
218647dc10d7SGordon Ross mutex_lock(&dev->struct_mutex);
218747dc10d7SGordon Ross ret = intel_pin_and_fence_fb_obj(dev,
218847dc10d7SGordon Ross to_intel_framebuffer(fb)->obj,
218947dc10d7SGordon Ross NULL);
219047dc10d7SGordon Ross if (ret != 0) {
219147dc10d7SGordon Ross mutex_unlock(&dev->struct_mutex);
219247dc10d7SGordon Ross DRM_ERROR("pin & fence failed\n");
219347dc10d7SGordon Ross return ret;
219447dc10d7SGordon Ross }
219547dc10d7SGordon Ross
219647dc10d7SGordon Ross ret = dev_priv->display.update_plane(crtc, fb, x, y);
219747dc10d7SGordon Ross if (ret) {
219847dc10d7SGordon Ross intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
219947dc10d7SGordon Ross mutex_unlock(&dev->struct_mutex);
220047dc10d7SGordon Ross DRM_ERROR("failed to update base address\n");
220147dc10d7SGordon Ross return ret;
220247dc10d7SGordon Ross }
220347dc10d7SGordon Ross
220447dc10d7SGordon Ross old_fb = crtc->fb;
220547dc10d7SGordon Ross crtc->fb = fb;
220647dc10d7SGordon Ross crtc->x = x;
220747dc10d7SGordon Ross crtc->y = y;
220847dc10d7SGordon Ross
220947dc10d7SGordon Ross if (old_fb) {
221047dc10d7SGordon Ross if (intel_crtc->active && old_fb != fb)
221147dc10d7SGordon Ross intel_wait_for_vblank(dev, intel_crtc->pipe);
221247dc10d7SGordon Ross intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
221347dc10d7SGordon Ross }
221447dc10d7SGordon Ross
221547dc10d7SGordon Ross intel_update_fbc(dev);
221647dc10d7SGordon Ross mutex_unlock(&dev->struct_mutex);
221747dc10d7SGordon Ross
221847dc10d7SGordon Ross intel_crtc_update_sarea_pos(crtc, x, y);
221947dc10d7SGordon Ross
222047dc10d7SGordon Ross return 0;
222147dc10d7SGordon Ross }
222247dc10d7SGordon Ross
intel_fdi_normal_train(struct drm_crtc * crtc)222347dc10d7SGordon Ross static void intel_fdi_normal_train(struct drm_crtc *crtc)
222447dc10d7SGordon Ross {
222547dc10d7SGordon Ross struct drm_device *dev = crtc->dev;
222647dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
222747dc10d7SGordon Ross struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
222847dc10d7SGordon Ross int pipe = intel_crtc->pipe;
222947dc10d7SGordon Ross u32 reg, temp;
223047dc10d7SGordon Ross
223147dc10d7SGordon Ross /* enable normal train */
223247dc10d7SGordon Ross reg = FDI_TX_CTL(pipe);
223347dc10d7SGordon Ross temp = I915_READ(reg);
223447dc10d7SGordon Ross if (IS_IVYBRIDGE(dev)) {
223547dc10d7SGordon Ross temp &= ~FDI_LINK_TRAIN_NONE_IVB;
223647dc10d7SGordon Ross temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
223747dc10d7SGordon Ross } else {
223847dc10d7SGordon Ross temp &= ~FDI_LINK_TRAIN_NONE;
223947dc10d7SGordon Ross temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
224047dc10d7SGordon Ross }
224147dc10d7SGordon Ross I915_WRITE(reg, temp);
224247dc10d7SGordon Ross
224347dc10d7SGordon Ross reg = FDI_RX_CTL(pipe);
224447dc10d7SGordon Ross temp = I915_READ(reg);
224547dc10d7SGordon Ross if (HAS_PCH_CPT(dev)) {
224647dc10d7SGordon Ross temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
224747dc10d7SGordon Ross temp |= FDI_LINK_TRAIN_NORMAL_CPT;
224847dc10d7SGordon Ross } else {
224947dc10d7SGordon Ross temp &= ~FDI_LINK_TRAIN_NONE;
225047dc10d7SGordon Ross temp |= FDI_LINK_TRAIN_NONE;
225147dc10d7SGordon Ross }
225247dc10d7SGordon Ross I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
225347dc10d7SGordon Ross
225447dc10d7SGordon Ross /* wait one idle pattern time */
225547dc10d7SGordon Ross POSTING_READ(reg);
225647dc10d7SGordon Ross udelay(1000);
225747dc10d7SGordon Ross
225847dc10d7SGordon Ross /* IVB wants error correction enabled */
225947dc10d7SGordon Ross if (IS_IVYBRIDGE(dev))
226047dc10d7SGordon Ross I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
226147dc10d7SGordon Ross FDI_FE_ERRC_ENABLE);
226247dc10d7SGordon Ross }
226347dc10d7SGordon Ross
pipe_has_enabled_pch(struct intel_crtc * intel_crtc)226447dc10d7SGordon Ross static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
226547dc10d7SGordon Ross {
226647dc10d7SGordon Ross return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
226747dc10d7SGordon Ross }
226847dc10d7SGordon Ross
ivb_modeset_global_resources(struct drm_device * dev)226947dc10d7SGordon Ross static void ivb_modeset_global_resources(struct drm_device *dev)
227047dc10d7SGordon Ross {
227147dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
227247dc10d7SGordon Ross struct intel_crtc *pipe_B_crtc =
227347dc10d7SGordon Ross to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
227447dc10d7SGordon Ross struct intel_crtc *pipe_C_crtc =
227547dc10d7SGordon Ross to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
227647dc10d7SGordon Ross uint32_t temp;
227747dc10d7SGordon Ross
227847dc10d7SGordon Ross /*
227947dc10d7SGordon Ross * When everything is off disable fdi C so that we could enable fdi B
228047dc10d7SGordon Ross * with all lanes. Note that we don't care about enabled pipes without
228147dc10d7SGordon Ross * an enabled pch encoder.
228247dc10d7SGordon Ross */
228347dc10d7SGordon Ross if (!pipe_has_enabled_pch(pipe_B_crtc) &&
228447dc10d7SGordon Ross !pipe_has_enabled_pch(pipe_C_crtc)) {
228547dc10d7SGordon Ross WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
228647dc10d7SGordon Ross WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
228747dc10d7SGordon Ross
228847dc10d7SGordon Ross temp = I915_READ(SOUTH_CHICKEN1);
228947dc10d7SGordon Ross temp &= ~FDI_BC_BIFURCATION_SELECT;
229047dc10d7SGordon Ross DRM_DEBUG_KMS("disabling fdi C rx\n");
229147dc10d7SGordon Ross I915_WRITE(SOUTH_CHICKEN1, temp);
229247dc10d7SGordon Ross }
229347dc10d7SGordon Ross }
229447dc10d7SGordon Ross
229547dc10d7SGordon Ross /* The FDI link training functions for ILK/Ibexpeak. */
ironlake_fdi_link_train(struct drm_crtc * crtc)229647dc10d7SGordon Ross static void ironlake_fdi_link_train(struct drm_crtc *crtc)
229747dc10d7SGordon Ross {
229847dc10d7SGordon Ross struct drm_device *dev = crtc->dev;
229947dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
230047dc10d7SGordon Ross struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
230147dc10d7SGordon Ross int pipe = intel_crtc->pipe;
230247dc10d7SGordon Ross int plane = intel_crtc->plane;
230347dc10d7SGordon Ross u32 reg, temp, tries;
230447dc10d7SGordon Ross
230547dc10d7SGordon Ross /* FDI needs bits from pipe & plane first */
230647dc10d7SGordon Ross assert_pipe_enabled(dev_priv, pipe);
230747dc10d7SGordon Ross assert_plane_enabled(dev_priv, plane);
230847dc10d7SGordon Ross
230947dc10d7SGordon Ross /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
231047dc10d7SGordon Ross for train result */
231147dc10d7SGordon Ross reg = FDI_RX_IMR(pipe);
231247dc10d7SGordon Ross temp = I915_READ(reg);
231347dc10d7SGordon Ross temp &= ~FDI_RX_SYMBOL_LOCK;
231447dc10d7SGordon Ross temp &= ~FDI_RX_BIT_LOCK;
231547dc10d7SGordon Ross I915_WRITE(reg, temp);
231647dc10d7SGordon Ross POSTING_READ(reg);
231747dc10d7SGordon Ross udelay(150);
231847dc10d7SGordon Ross
231947dc10d7SGordon Ross /* enable CPU FDI TX and PCH FDI RX */
232047dc10d7SGordon Ross reg = FDI_TX_CTL(pipe);
232147dc10d7SGordon Ross temp = I915_READ(reg);
232247dc10d7SGordon Ross temp &= ~FDI_DP_PORT_WIDTH_MASK;
232347dc10d7SGordon Ross temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
232447dc10d7SGordon Ross temp &= ~FDI_LINK_TRAIN_NONE;
232547dc10d7SGordon Ross temp |= FDI_LINK_TRAIN_PATTERN_1;
232647dc10d7SGordon Ross I915_WRITE(reg, temp | FDI_TX_ENABLE);
232747dc10d7SGordon Ross
232847dc10d7SGordon Ross reg = FDI_RX_CTL(pipe);
232947dc10d7SGordon Ross temp = I915_READ(reg);
233047dc10d7SGordon Ross temp &= ~FDI_LINK_TRAIN_NONE;
233147dc10d7SGordon Ross temp |= FDI_LINK_TRAIN_PATTERN_1;
233247dc10d7SGordon Ross I915_WRITE(reg, temp | FDI_RX_ENABLE);
233347dc10d7SGordon Ross
233447dc10d7SGordon Ross POSTING_READ(reg);
233547dc10d7SGordon Ross udelay(150);
233647dc10d7SGordon Ross
233747dc10d7SGordon Ross /* Ironlake workaround, enable clock pointer after FDI enable*/
233847dc10d7SGordon Ross I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
233947dc10d7SGordon Ross I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
234047dc10d7SGordon Ross FDI_RX_PHASE_SYNC_POINTER_EN);
234147dc10d7SGordon Ross
234247dc10d7SGordon Ross reg = FDI_RX_IIR(pipe);
234347dc10d7SGordon Ross for (tries = 0; tries < 5; tries++) {
234447dc10d7SGordon Ross temp = I915_READ(reg);
234547dc10d7SGordon Ross DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
234647dc10d7SGordon Ross
234747dc10d7SGordon Ross if ((temp & FDI_RX_BIT_LOCK)) {
234847dc10d7SGordon Ross DRM_DEBUG_KMS("FDI train 1 done.\n");
234947dc10d7SGordon Ross I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
235047dc10d7SGordon Ross break;
235147dc10d7SGordon Ross }
235247dc10d7SGordon Ross }
235347dc10d7SGordon Ross if (tries == 5)
235447dc10d7SGordon Ross DRM_ERROR("FDI train 1 fail!\n");
235547dc10d7SGordon Ross
235647dc10d7SGordon Ross /* Train 2 */
235747dc10d7SGordon Ross reg = FDI_TX_CTL(pipe);
235847dc10d7SGordon Ross temp = I915_READ(reg);
235947dc10d7SGordon Ross temp &= ~FDI_LINK_TRAIN_NONE;
236047dc10d7SGordon Ross temp |= FDI_LINK_TRAIN_PATTERN_2;
236147dc10d7SGordon Ross I915_WRITE(reg, temp);
236247dc10d7SGordon Ross
236347dc10d7SGordon Ross reg = FDI_RX_CTL(pipe);
236447dc10d7SGordon Ross temp = I915_READ(reg);
236547dc10d7SGordon Ross temp &= ~FDI_LINK_TRAIN_NONE;
236647dc10d7SGordon Ross temp |= FDI_LINK_TRAIN_PATTERN_2;
236747dc10d7SGordon Ross I915_WRITE(reg, temp);
236847dc10d7SGordon Ross
236947dc10d7SGordon Ross POSTING_READ(reg);
237047dc10d7SGordon Ross udelay(150);
237147dc10d7SGordon Ross
237247dc10d7SGordon Ross reg = FDI_RX_IIR(pipe);
237347dc10d7SGordon Ross for (tries = 0; tries < 5; tries++) {
237447dc10d7SGordon Ross temp = I915_READ(reg);
237547dc10d7SGordon Ross DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
237647dc10d7SGordon Ross
237747dc10d7SGordon Ross if (temp & FDI_RX_SYMBOL_LOCK) {
237847dc10d7SGordon Ross I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
237947dc10d7SGordon Ross DRM_DEBUG_KMS("FDI train 2 done.\n");
238047dc10d7SGordon Ross break;
238147dc10d7SGordon Ross }
238247dc10d7SGordon Ross }
238347dc10d7SGordon Ross if (tries == 5)
238447dc10d7SGordon Ross DRM_ERROR("FDI train 2 fail!\n");
238547dc10d7SGordon Ross
238647dc10d7SGordon Ross DRM_DEBUG_KMS("FDI train done\n");
238747dc10d7SGordon Ross
238847dc10d7SGordon Ross }
238947dc10d7SGordon Ross
239047dc10d7SGordon Ross static const int snb_b_fdi_train_param [] = {
239147dc10d7SGordon Ross FDI_LINK_TRAIN_400MV_0DB_SNB_B,
239247dc10d7SGordon Ross FDI_LINK_TRAIN_400MV_6DB_SNB_B,
239347dc10d7SGordon Ross FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
239447dc10d7SGordon Ross FDI_LINK_TRAIN_800MV_0DB_SNB_B,
239547dc10d7SGordon Ross };
239647dc10d7SGordon Ross
239747dc10d7SGordon Ross /* The FDI link training functions for SNB/Cougarpoint. */
gen6_fdi_link_train(struct drm_crtc * crtc)239847dc10d7SGordon Ross static void gen6_fdi_link_train(struct drm_crtc *crtc)
239947dc10d7SGordon Ross {
240047dc10d7SGordon Ross struct drm_device *dev = crtc->dev;
240147dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
240247dc10d7SGordon Ross struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
240347dc10d7SGordon Ross int pipe = intel_crtc->pipe;
240447dc10d7SGordon Ross u32 reg, temp, i, retry;
240547dc10d7SGordon Ross
240647dc10d7SGordon Ross /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
240747dc10d7SGordon Ross for train result */
240847dc10d7SGordon Ross reg = FDI_RX_IMR(pipe);
240947dc10d7SGordon Ross temp = I915_READ(reg);
241047dc10d7SGordon Ross temp &= ~FDI_RX_SYMBOL_LOCK;
241147dc10d7SGordon Ross temp &= ~FDI_RX_BIT_LOCK;
241247dc10d7SGordon Ross I915_WRITE(reg, temp);
241347dc10d7SGordon Ross
241447dc10d7SGordon Ross POSTING_READ(reg);
241547dc10d7SGordon Ross udelay(150);
241647dc10d7SGordon Ross
241747dc10d7SGordon Ross /* enable CPU FDI TX and PCH FDI RX */
241847dc10d7SGordon Ross reg = FDI_TX_CTL(pipe);
241947dc10d7SGordon Ross temp = I915_READ(reg);
242047dc10d7SGordon Ross temp &= ~FDI_DP_PORT_WIDTH_MASK;
242147dc10d7SGordon Ross temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
242247dc10d7SGordon Ross temp &= ~FDI_LINK_TRAIN_NONE;
242347dc10d7SGordon Ross temp |= FDI_LINK_TRAIN_PATTERN_1;
242447dc10d7SGordon Ross temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
242547dc10d7SGordon Ross /* SNB-B */
242647dc10d7SGordon Ross temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
242747dc10d7SGordon Ross I915_WRITE(reg, temp | FDI_TX_ENABLE);
242847dc10d7SGordon Ross
242947dc10d7SGordon Ross I915_WRITE(FDI_RX_MISC(pipe),
243047dc10d7SGordon Ross FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
243147dc10d7SGordon Ross
243247dc10d7SGordon Ross reg = FDI_RX_CTL(pipe);
243347dc10d7SGordon Ross temp = I915_READ(reg);
243447dc10d7SGordon Ross if (HAS_PCH_CPT(dev)) {
243547dc10d7SGordon Ross temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
243647dc10d7SGordon Ross temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
243747dc10d7SGordon Ross } else {
243847dc10d7SGordon Ross temp &= ~FDI_LINK_TRAIN_NONE;
243947dc10d7SGordon Ross temp |= FDI_LINK_TRAIN_PATTERN_1;
244047dc10d7SGordon Ross }
244147dc10d7SGordon Ross I915_WRITE(reg, temp | FDI_RX_ENABLE);
244247dc10d7SGordon Ross
244347dc10d7SGordon Ross POSTING_READ(reg);
244447dc10d7SGordon Ross udelay(150);
244547dc10d7SGordon Ross
244647dc10d7SGordon Ross for (i = 0; i < 4; i++ ) {
244747dc10d7SGordon Ross reg = FDI_TX_CTL(pipe);
244847dc10d7SGordon Ross temp = I915_READ(reg);
244947dc10d7SGordon Ross temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
245047dc10d7SGordon Ross temp |= snb_b_fdi_train_param[i];
245147dc10d7SGordon Ross I915_WRITE(reg, temp);
245247dc10d7SGordon Ross
245347dc10d7SGordon Ross POSTING_READ(reg);
245447dc10d7SGordon Ross udelay(500);
245547dc10d7SGordon Ross
245647dc10d7SGordon Ross for (retry = 0; retry < 5; retry++) {
245747dc10d7SGordon Ross reg = FDI_RX_IIR(pipe);
245847dc10d7SGordon Ross temp = I915_READ(reg);
245947dc10d7SGordon Ross DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
246047dc10d7SGordon Ross if (temp & FDI_RX_BIT_LOCK) {
246147dc10d7SGordon Ross I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
246247dc10d7SGordon Ross DRM_DEBUG_KMS("FDI train 1 done.\n");
246347dc10d7SGordon Ross break;
246447dc10d7SGordon Ross }
246547dc10d7SGordon Ross udelay(50);
246647dc10d7SGordon Ross }
246747dc10d7SGordon Ross if (retry < 5)
246847dc10d7SGordon Ross break;
246947dc10d7SGordon Ross }
247047dc10d7SGordon Ross if (i == 4)
247147dc10d7SGordon Ross DRM_ERROR("FDI train 1 fail!\n");
247247dc10d7SGordon Ross
247347dc10d7SGordon Ross /* Train 2 */
247447dc10d7SGordon Ross reg = FDI_TX_CTL(pipe);
247547dc10d7SGordon Ross temp = I915_READ(reg);
247647dc10d7SGordon Ross temp &= ~FDI_LINK_TRAIN_NONE;
247747dc10d7SGordon Ross temp |= FDI_LINK_TRAIN_PATTERN_2;
247847dc10d7SGordon Ross if (IS_GEN6(dev)) {
247947dc10d7SGordon Ross temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
248047dc10d7SGordon Ross /* SNB-B */
248147dc10d7SGordon Ross temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
248247dc10d7SGordon Ross }
248347dc10d7SGordon Ross I915_WRITE(reg, temp);
248447dc10d7SGordon Ross
248547dc10d7SGordon Ross reg = FDI_RX_CTL(pipe);
248647dc10d7SGordon Ross temp = I915_READ(reg);
248747dc10d7SGordon Ross if (HAS_PCH_CPT(dev)) {
248847dc10d7SGordon Ross temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
248947dc10d7SGordon Ross temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
249047dc10d7SGordon Ross } else {
249147dc10d7SGordon Ross temp &= ~FDI_LINK_TRAIN_NONE;
249247dc10d7SGordon Ross temp |= FDI_LINK_TRAIN_PATTERN_2;
249347dc10d7SGordon Ross }
249447dc10d7SGordon Ross I915_WRITE(reg, temp);
249547dc10d7SGordon Ross
249647dc10d7SGordon Ross POSTING_READ(reg);
249747dc10d7SGordon Ross udelay(150);
249847dc10d7SGordon Ross
249947dc10d7SGordon Ross for (i = 0; i < 4; i++ ) {
250047dc10d7SGordon Ross reg = FDI_TX_CTL(pipe);
250147dc10d7SGordon Ross temp = I915_READ(reg);
250247dc10d7SGordon Ross temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
250347dc10d7SGordon Ross temp |= snb_b_fdi_train_param[i];
250447dc10d7SGordon Ross I915_WRITE(reg, temp);
250547dc10d7SGordon Ross
250647dc10d7SGordon Ross POSTING_READ(reg);
250747dc10d7SGordon Ross udelay(500);
250847dc10d7SGordon Ross
250947dc10d7SGordon Ross for (retry = 0; retry < 5; retry++) {
251047dc10d7SGordon Ross reg = FDI_RX_IIR(pipe);
251147dc10d7SGordon Ross temp = I915_READ(reg);
251247dc10d7SGordon Ross DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
251347dc10d7SGordon Ross if (temp & FDI_RX_SYMBOL_LOCK) {
251447dc10d7SGordon Ross I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
251547dc10d7SGordon Ross DRM_DEBUG_KMS("FDI train 2 done.\n");
251647dc10d7SGordon Ross break;
251747dc10d7SGordon Ross }
251847dc10d7SGordon Ross udelay(50);
251947dc10d7SGordon Ross }
252047dc10d7SGordon Ross if (retry < 5)
252147dc10d7SGordon Ross break;
252247dc10d7SGordon Ross }
252347dc10d7SGordon Ross if (i == 4)
252447dc10d7SGordon Ross DRM_ERROR("FDI train 2 fail!\n");
252547dc10d7SGordon Ross
252647dc10d7SGordon Ross DRM_DEBUG_KMS("FDI train done.\n");
252747dc10d7SGordon Ross }
252847dc10d7SGordon Ross
252947dc10d7SGordon Ross /* Manual link training for Ivy Bridge A0 parts */
ivb_manual_fdi_link_train(struct drm_crtc * crtc)253047dc10d7SGordon Ross static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
253147dc10d7SGordon Ross {
253247dc10d7SGordon Ross struct drm_device *dev = crtc->dev;
253347dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
253447dc10d7SGordon Ross struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
253547dc10d7SGordon Ross int pipe = intel_crtc->pipe;
253647dc10d7SGordon Ross u32 reg, temp, i;
253747dc10d7SGordon Ross
253847dc10d7SGordon Ross /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
253947dc10d7SGordon Ross for train result */
254047dc10d7SGordon Ross reg = FDI_RX_IMR(pipe);
254147dc10d7SGordon Ross temp = I915_READ(reg);
254247dc10d7SGordon Ross temp &= ~FDI_RX_SYMBOL_LOCK;
254347dc10d7SGordon Ross temp &= ~FDI_RX_BIT_LOCK;
254447dc10d7SGordon Ross I915_WRITE(reg, temp);
254547dc10d7SGordon Ross
254647dc10d7SGordon Ross POSTING_READ(reg);
254747dc10d7SGordon Ross udelay(150);
254847dc10d7SGordon Ross
254947dc10d7SGordon Ross DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
255047dc10d7SGordon Ross I915_READ(FDI_RX_IIR(pipe)));
255147dc10d7SGordon Ross
255247dc10d7SGordon Ross /* enable CPU FDI TX and PCH FDI RX */
255347dc10d7SGordon Ross reg = FDI_TX_CTL(pipe);
255447dc10d7SGordon Ross temp = I915_READ(reg);
255547dc10d7SGordon Ross temp &= ~FDI_DP_PORT_WIDTH_MASK;
255647dc10d7SGordon Ross temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
255747dc10d7SGordon Ross temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
255847dc10d7SGordon Ross temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
255947dc10d7SGordon Ross temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
256047dc10d7SGordon Ross temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
256147dc10d7SGordon Ross temp |= FDI_COMPOSITE_SYNC;
256247dc10d7SGordon Ross I915_WRITE(reg, temp | FDI_TX_ENABLE);
256347dc10d7SGordon Ross
256447dc10d7SGordon Ross I915_WRITE(FDI_RX_MISC(pipe),
256547dc10d7SGordon Ross FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
256647dc10d7SGordon Ross
256747dc10d7SGordon Ross reg = FDI_RX_CTL(pipe);
256847dc10d7SGordon Ross temp = I915_READ(reg);
256947dc10d7SGordon Ross temp &= ~FDI_LINK_TRAIN_AUTO;
257047dc10d7SGordon Ross temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
257147dc10d7SGordon Ross temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
257247dc10d7SGordon Ross temp |= FDI_COMPOSITE_SYNC;
257347dc10d7SGordon Ross I915_WRITE(reg, temp | FDI_RX_ENABLE);
257447dc10d7SGordon Ross
257547dc10d7SGordon Ross POSTING_READ(reg);
257647dc10d7SGordon Ross udelay(150);
257747dc10d7SGordon Ross
257847dc10d7SGordon Ross for (i = 0; i < 4; i++ ) {
257947dc10d7SGordon Ross reg = FDI_TX_CTL(pipe);
258047dc10d7SGordon Ross temp = I915_READ(reg);
258147dc10d7SGordon Ross temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
258247dc10d7SGordon Ross temp |= snb_b_fdi_train_param[i];
258347dc10d7SGordon Ross I915_WRITE(reg, temp);
258447dc10d7SGordon Ross
258547dc10d7SGordon Ross POSTING_READ(reg);
258647dc10d7SGordon Ross udelay(500);
258747dc10d7SGordon Ross
258847dc10d7SGordon Ross reg = FDI_RX_IIR(pipe);
258947dc10d7SGordon Ross temp = I915_READ(reg);
259047dc10d7SGordon Ross DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
259147dc10d7SGordon Ross
259247dc10d7SGordon Ross if (temp & FDI_RX_BIT_LOCK ||
259347dc10d7SGordon Ross (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
259447dc10d7SGordon Ross I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
259547dc10d7SGordon Ross DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
259647dc10d7SGordon Ross break;
259747dc10d7SGordon Ross }
259847dc10d7SGordon Ross }
259947dc10d7SGordon Ross if (i == 4)
260047dc10d7SGordon Ross DRM_ERROR("FDI train 1 fail!\n");
260147dc10d7SGordon Ross
260247dc10d7SGordon Ross /* Train 2 */
260347dc10d7SGordon Ross reg = FDI_TX_CTL(pipe);
260447dc10d7SGordon Ross temp = I915_READ(reg);
260547dc10d7SGordon Ross temp &= ~FDI_LINK_TRAIN_NONE_IVB;
260647dc10d7SGordon Ross temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
260747dc10d7SGordon Ross temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
260847dc10d7SGordon Ross temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
260947dc10d7SGordon Ross I915_WRITE(reg, temp);
261047dc10d7SGordon Ross
261147dc10d7SGordon Ross reg = FDI_RX_CTL(pipe);
261247dc10d7SGordon Ross temp = I915_READ(reg);
261347dc10d7SGordon Ross temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
261447dc10d7SGordon Ross temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
261547dc10d7SGordon Ross I915_WRITE(reg, temp);
261647dc10d7SGordon Ross
261747dc10d7SGordon Ross POSTING_READ(reg);
261847dc10d7SGordon Ross udelay(150);
261947dc10d7SGordon Ross
262047dc10d7SGordon Ross for (i = 0; i < 4; i++ ) {
262147dc10d7SGordon Ross reg = FDI_TX_CTL(pipe);
262247dc10d7SGordon Ross temp = I915_READ(reg);
262347dc10d7SGordon Ross temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
262447dc10d7SGordon Ross temp |= snb_b_fdi_train_param[i];
262547dc10d7SGordon Ross I915_WRITE(reg, temp);
262647dc10d7SGordon Ross
262747dc10d7SGordon Ross POSTING_READ(reg);
262847dc10d7SGordon Ross udelay(500);
262947dc10d7SGordon Ross
263047dc10d7SGordon Ross reg = FDI_RX_IIR(pipe);
263147dc10d7SGordon Ross temp = I915_READ(reg);
263247dc10d7SGordon Ross DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
263347dc10d7SGordon Ross
263447dc10d7SGordon Ross if (temp & FDI_RX_SYMBOL_LOCK) {
263547dc10d7SGordon Ross I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
263647dc10d7SGordon Ross DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
263747dc10d7SGordon Ross break;
263847dc10d7SGordon Ross }
263947dc10d7SGordon Ross }
264047dc10d7SGordon Ross if (i == 4)
264147dc10d7SGordon Ross DRM_ERROR("FDI train 2 fail!\n");
264247dc10d7SGordon Ross
264347dc10d7SGordon Ross DRM_DEBUG_KMS("FDI train done.\n");
264447dc10d7SGordon Ross }
264547dc10d7SGordon Ross
ironlake_fdi_pll_enable(struct intel_crtc * intel_crtc)264647dc10d7SGordon Ross static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
264747dc10d7SGordon Ross {
264847dc10d7SGordon Ross struct drm_device *dev = intel_crtc->base.dev;
264947dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
265047dc10d7SGordon Ross int pipe = intel_crtc->pipe;
265147dc10d7SGordon Ross u32 reg, temp;
265247dc10d7SGordon Ross
265347dc10d7SGordon Ross
265447dc10d7SGordon Ross /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
265547dc10d7SGordon Ross reg = FDI_RX_CTL(pipe);
265647dc10d7SGordon Ross temp = I915_READ(reg);
265747dc10d7SGordon Ross temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
265847dc10d7SGordon Ross temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
265947dc10d7SGordon Ross temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
266047dc10d7SGordon Ross I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
266147dc10d7SGordon Ross
266247dc10d7SGordon Ross POSTING_READ(reg);
266347dc10d7SGordon Ross udelay(200);
266447dc10d7SGordon Ross
266547dc10d7SGordon Ross /* Switch from Rawclk to PCDclk */
266647dc10d7SGordon Ross temp = I915_READ(reg);
266747dc10d7SGordon Ross I915_WRITE(reg, temp | FDI_PCDCLK);
266847dc10d7SGordon Ross
266947dc10d7SGordon Ross POSTING_READ(reg);
267047dc10d7SGordon Ross udelay(200);
267147dc10d7SGordon Ross
267247dc10d7SGordon Ross /* Enable CPU FDI TX PLL, always on for Ironlake */
267347dc10d7SGordon Ross reg = FDI_TX_CTL(pipe);
267447dc10d7SGordon Ross temp = I915_READ(reg);
267547dc10d7SGordon Ross if ((temp & FDI_TX_PLL_ENABLE) == 0) {
267647dc10d7SGordon Ross I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
267747dc10d7SGordon Ross
267847dc10d7SGordon Ross POSTING_READ(reg);
267947dc10d7SGordon Ross udelay(100);
268047dc10d7SGordon Ross }
268147dc10d7SGordon Ross }
268247dc10d7SGordon Ross
ironlake_fdi_pll_disable(struct intel_crtc * intel_crtc)268347dc10d7SGordon Ross static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
268447dc10d7SGordon Ross {
268547dc10d7SGordon Ross struct drm_device *dev = intel_crtc->base.dev;
268647dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
268747dc10d7SGordon Ross int pipe = intel_crtc->pipe;
268847dc10d7SGordon Ross u32 reg, temp;
268947dc10d7SGordon Ross
269047dc10d7SGordon Ross /* Switch from PCDclk to Rawclk */
269147dc10d7SGordon Ross reg = FDI_RX_CTL(pipe);
269247dc10d7SGordon Ross temp = I915_READ(reg);
269347dc10d7SGordon Ross I915_WRITE(reg, temp & ~FDI_PCDCLK);
269447dc10d7SGordon Ross
269547dc10d7SGordon Ross /* Disable CPU FDI TX PLL */
269647dc10d7SGordon Ross reg = FDI_TX_CTL(pipe);
269747dc10d7SGordon Ross temp = I915_READ(reg);
269847dc10d7SGordon Ross I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
269947dc10d7SGordon Ross
270047dc10d7SGordon Ross POSTING_READ(reg);
270147dc10d7SGordon Ross udelay(100);
270247dc10d7SGordon Ross
270347dc10d7SGordon Ross reg = FDI_RX_CTL(pipe);
270447dc10d7SGordon Ross temp = I915_READ(reg);
270547dc10d7SGordon Ross I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
270647dc10d7SGordon Ross
270747dc10d7SGordon Ross /* Wait for the clocks to turn off. */
270847dc10d7SGordon Ross POSTING_READ(reg);
270947dc10d7SGordon Ross udelay(100);
271047dc10d7SGordon Ross }
271147dc10d7SGordon Ross
ironlake_fdi_disable(struct drm_crtc * crtc)271247dc10d7SGordon Ross static void ironlake_fdi_disable(struct drm_crtc *crtc)
271347dc10d7SGordon Ross {
271447dc10d7SGordon Ross struct drm_device *dev = crtc->dev;
271547dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
271647dc10d7SGordon Ross struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
271747dc10d7SGordon Ross int pipe = intel_crtc->pipe;
271847dc10d7SGordon Ross u32 reg, temp;
271947dc10d7SGordon Ross
272047dc10d7SGordon Ross /* disable CPU FDI tx and PCH FDI rx */
272147dc10d7SGordon Ross reg = FDI_TX_CTL(pipe);
272247dc10d7SGordon Ross temp = I915_READ(reg);
272347dc10d7SGordon Ross I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
272447dc10d7SGordon Ross POSTING_READ(reg);
272547dc10d7SGordon Ross
272647dc10d7SGordon Ross reg = FDI_RX_CTL(pipe);
272747dc10d7SGordon Ross temp = I915_READ(reg);
272847dc10d7SGordon Ross temp &= ~(0x7 << 16);
272947dc10d7SGordon Ross temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
273047dc10d7SGordon Ross I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
273147dc10d7SGordon Ross
273247dc10d7SGordon Ross POSTING_READ(reg);
273347dc10d7SGordon Ross udelay(100);
273447dc10d7SGordon Ross
273547dc10d7SGordon Ross /* Ironlake workaround, disable clock pointer after downing FDI */
273647dc10d7SGordon Ross if (HAS_PCH_IBX(dev)) {
273747dc10d7SGordon Ross I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
273847dc10d7SGordon Ross }
273947dc10d7SGordon Ross
274047dc10d7SGordon Ross /* still set train pattern 1 */
274147dc10d7SGordon Ross reg = FDI_TX_CTL(pipe);
274247dc10d7SGordon Ross temp = I915_READ(reg);
274347dc10d7SGordon Ross temp &= ~FDI_LINK_TRAIN_NONE;
274447dc10d7SGordon Ross temp |= FDI_LINK_TRAIN_PATTERN_1;
274547dc10d7SGordon Ross I915_WRITE(reg, temp);
274647dc10d7SGordon Ross
274747dc10d7SGordon Ross reg = FDI_RX_CTL(pipe);
274847dc10d7SGordon Ross temp = I915_READ(reg);
274947dc10d7SGordon Ross if (HAS_PCH_CPT(dev)) {
275047dc10d7SGordon Ross temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
275147dc10d7SGordon Ross temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
275247dc10d7SGordon Ross } else {
275347dc10d7SGordon Ross temp &= ~FDI_LINK_TRAIN_NONE;
275447dc10d7SGordon Ross temp |= FDI_LINK_TRAIN_PATTERN_1;
275547dc10d7SGordon Ross }
275647dc10d7SGordon Ross /* BPC in FDI rx is consistent with that in PIPECONF */
275747dc10d7SGordon Ross temp &= ~(0x07 << 16);
275847dc10d7SGordon Ross temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
275947dc10d7SGordon Ross I915_WRITE(reg, temp);
276047dc10d7SGordon Ross
276147dc10d7SGordon Ross POSTING_READ(reg);
276247dc10d7SGordon Ross udelay(100);
276347dc10d7SGordon Ross }
276447dc10d7SGordon Ross
intel_crtc_has_pending_flip(struct drm_crtc * crtc)276547dc10d7SGordon Ross static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
276647dc10d7SGordon Ross {
276747dc10d7SGordon Ross struct drm_device *dev = crtc->dev;
276847dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
276947dc10d7SGordon Ross struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
277047dc10d7SGordon Ross unsigned long flags;
277147dc10d7SGordon Ross bool pending;
277247dc10d7SGordon Ross
277347dc10d7SGordon Ross if (i915_reset_in_progress(&dev_priv->gpu_error) ||
277447dc10d7SGordon Ross intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
277547dc10d7SGordon Ross return false;
277647dc10d7SGordon Ross
277747dc10d7SGordon Ross spin_lock_irqsave(&dev->event_lock, flags);
277847dc10d7SGordon Ross pending = to_intel_crtc(crtc)->unpin_work != NULL;
277947dc10d7SGordon Ross spin_unlock_irqrestore(&dev->event_lock, flags);
278047dc10d7SGordon Ross
278147dc10d7SGordon Ross return pending;
278247dc10d7SGordon Ross }
278347dc10d7SGordon Ross
intel_crtc_wait_for_pending_flips(struct drm_crtc * crtc)278447dc10d7SGordon Ross static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
278547dc10d7SGordon Ross {
278647dc10d7SGordon Ross /* LINTED */
278747dc10d7SGordon Ross int ret;
278847dc10d7SGordon Ross
278947dc10d7SGordon Ross struct drm_device *dev = crtc->dev;
279047dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
279147dc10d7SGordon Ross
279247dc10d7SGordon Ross if (crtc->fb == NULL)
279347dc10d7SGordon Ross return;
279447dc10d7SGordon Ross
279547dc10d7SGordon Ross WARN_ON(mutex_is_locked(&dev_priv->pending_flip_queue.lock));
279647dc10d7SGordon Ross
279747dc10d7SGordon Ross DRM_WAIT(ret, &dev_priv->pending_flip_queue,
279847dc10d7SGordon Ross !intel_crtc_has_pending_flip(crtc));
279947dc10d7SGordon Ross
280047dc10d7SGordon Ross mutex_lock(&dev->struct_mutex);
280147dc10d7SGordon Ross intel_finish_fb(crtc->fb);
280247dc10d7SGordon Ross mutex_unlock(&dev->struct_mutex);
280347dc10d7SGordon Ross }
280447dc10d7SGordon Ross
280547dc10d7SGordon Ross /* Program iCLKIP clock to the desired frequency */
lpt_program_iclkip(struct drm_crtc * crtc)280647dc10d7SGordon Ross static void lpt_program_iclkip(struct drm_crtc *crtc)
280747dc10d7SGordon Ross {
280847dc10d7SGordon Ross struct drm_device *dev = crtc->dev;
280947dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
281047dc10d7SGordon Ross u32 divsel, phaseinc, auxdiv, phasedir = 0;
281147dc10d7SGordon Ross u32 temp;
281247dc10d7SGordon Ross
281347dc10d7SGordon Ross mutex_lock(&dev_priv->dpio_lock);
281447dc10d7SGordon Ross
281547dc10d7SGordon Ross /* It is necessary to ungate the pixclk gate prior to programming
281647dc10d7SGordon Ross * the divisors, and gate it back when it is done.
281747dc10d7SGordon Ross */
281847dc10d7SGordon Ross I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
281947dc10d7SGordon Ross
282047dc10d7SGordon Ross /* Disable SSCCTL */
282147dc10d7SGordon Ross intel_sbi_write(dev_priv, SBI_SSCCTL6,
282247dc10d7SGordon Ross intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
282347dc10d7SGordon Ross SBI_SSCCTL_DISABLE,
282447dc10d7SGordon Ross SBI_ICLK);
282547dc10d7SGordon Ross
282647dc10d7SGordon Ross /* 20MHz is a corner case which is out of range for the 7-bit divisor */
282747dc10d7SGordon Ross if (crtc->mode.clock == 20000) {
282847dc10d7SGordon Ross auxdiv = 1;
282947dc10d7SGordon Ross divsel = 0x41;
283047dc10d7SGordon Ross phaseinc = 0x20;
283147dc10d7SGordon Ross } else {
283247dc10d7SGordon Ross /* The iCLK virtual clock root frequency is in MHz,
283347dc10d7SGordon Ross * but the crtc->mode.clock in in KHz. To get the divisors,
283447dc10d7SGordon Ross * it is necessary to divide one by another, so we
283547dc10d7SGordon Ross * convert the virtual clock precision to KHz here for higher
283647dc10d7SGordon Ross * precision.
283747dc10d7SGordon Ross */
283847dc10d7SGordon Ross u32 iclk_virtual_root_freq = 172800 * 1000;
283947dc10d7SGordon Ross u32 iclk_pi_range = 64;
284047dc10d7SGordon Ross u32 desired_divisor, msb_divisor_value, pi_value;
284147dc10d7SGordon Ross
284247dc10d7SGordon Ross desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
284347dc10d7SGordon Ross msb_divisor_value = desired_divisor / iclk_pi_range;
284447dc10d7SGordon Ross pi_value = desired_divisor % iclk_pi_range;
284547dc10d7SGordon Ross
284647dc10d7SGordon Ross auxdiv = 0;
284747dc10d7SGordon Ross divsel = msb_divisor_value - 2;
284847dc10d7SGordon Ross phaseinc = pi_value;
284947dc10d7SGordon Ross }
285047dc10d7SGordon Ross
285147dc10d7SGordon Ross /* This should not happen with any sane values */
285247dc10d7SGordon Ross WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
285347dc10d7SGordon Ross ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
285447dc10d7SGordon Ross WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
285547dc10d7SGordon Ross ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
285647dc10d7SGordon Ross
285747dc10d7SGordon Ross DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
285847dc10d7SGordon Ross crtc->mode.clock,
285947dc10d7SGordon Ross auxdiv,
286047dc10d7SGordon Ross divsel,
286147dc10d7SGordon Ross phasedir,
286247dc10d7SGordon Ross phaseinc);
286347dc10d7SGordon Ross
286447dc10d7SGordon Ross /* Program SSCDIVINTPHASE6 */
286547dc10d7SGordon Ross temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
286647dc10d7SGordon Ross temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
286747dc10d7SGordon Ross temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
286847dc10d7SGordon Ross temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
286947dc10d7SGordon Ross temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
287047dc10d7SGordon Ross temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
287147dc10d7SGordon Ross temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
287247dc10d7SGordon Ross intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
287347dc10d7SGordon Ross
287447dc10d7SGordon Ross /* Program SSCAUXDIV */
287547dc10d7SGordon Ross temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
287647dc10d7SGordon Ross temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
287747dc10d7SGordon Ross temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
287847dc10d7SGordon Ross intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
287947dc10d7SGordon Ross
288047dc10d7SGordon Ross /* Enable modulator and associated divider */
288147dc10d7SGordon Ross temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
288247dc10d7SGordon Ross temp &= ~SBI_SSCCTL_DISABLE;
288347dc10d7SGordon Ross intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
288447dc10d7SGordon Ross
288547dc10d7SGordon Ross /* Wait for initialization time */
288647dc10d7SGordon Ross udelay(24);
288747dc10d7SGordon Ross
288847dc10d7SGordon Ross I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
288947dc10d7SGordon Ross
289047dc10d7SGordon Ross mutex_unlock(&dev_priv->dpio_lock);
289147dc10d7SGordon Ross }
289247dc10d7SGordon Ross
ironlake_pch_transcoder_set_timings(struct intel_crtc * crtc,enum pipe pch_transcoder)289347dc10d7SGordon Ross static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
289447dc10d7SGordon Ross enum pipe pch_transcoder)
289547dc10d7SGordon Ross {
289647dc10d7SGordon Ross struct drm_device *dev = crtc->base.dev;
289747dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
289847dc10d7SGordon Ross enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
289947dc10d7SGordon Ross
290047dc10d7SGordon Ross I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
290147dc10d7SGordon Ross I915_READ(HTOTAL(cpu_transcoder)));
290247dc10d7SGordon Ross I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
290347dc10d7SGordon Ross I915_READ(HBLANK(cpu_transcoder)));
290447dc10d7SGordon Ross I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
290547dc10d7SGordon Ross I915_READ(HSYNC(cpu_transcoder)));
290647dc10d7SGordon Ross
290747dc10d7SGordon Ross I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
290847dc10d7SGordon Ross I915_READ(VTOTAL(cpu_transcoder)));
290947dc10d7SGordon Ross I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
291047dc10d7SGordon Ross I915_READ(VBLANK(cpu_transcoder)));
291147dc10d7SGordon Ross I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
291247dc10d7SGordon Ross I915_READ(VSYNC(cpu_transcoder)));
291347dc10d7SGordon Ross I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
291447dc10d7SGordon Ross I915_READ(VSYNCSHIFT(cpu_transcoder)));
291547dc10d7SGordon Ross }
291647dc10d7SGordon Ross
291747dc10d7SGordon Ross /*
291847dc10d7SGordon Ross * Enable PCH resources required for PCH ports:
291947dc10d7SGordon Ross * - PCH PLLs
292047dc10d7SGordon Ross * - FDI training & RX/TX
292147dc10d7SGordon Ross * - update transcoder timings
292247dc10d7SGordon Ross * - DP transcoding bits
292347dc10d7SGordon Ross * - transcoder
292447dc10d7SGordon Ross */
ironlake_pch_enable(struct drm_crtc * crtc)292547dc10d7SGordon Ross static void ironlake_pch_enable(struct drm_crtc *crtc)
292647dc10d7SGordon Ross {
292747dc10d7SGordon Ross struct drm_device *dev = crtc->dev;
292847dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
292947dc10d7SGordon Ross struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
293047dc10d7SGordon Ross int pipe = intel_crtc->pipe;
293147dc10d7SGordon Ross u32 reg, temp;
293247dc10d7SGordon Ross
293347dc10d7SGordon Ross assert_pch_transcoder_disabled(dev_priv, pipe);
293447dc10d7SGordon Ross
293547dc10d7SGordon Ross /* Write the TU size bits before fdi link training, so that error
293647dc10d7SGordon Ross * detection works. */
293747dc10d7SGordon Ross I915_WRITE(FDI_RX_TUSIZE1(pipe),
293847dc10d7SGordon Ross I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
293947dc10d7SGordon Ross
294047dc10d7SGordon Ross /* For PCH output, training FDI link */
294147dc10d7SGordon Ross dev_priv->display.fdi_link_train(crtc);
294247dc10d7SGordon Ross
294347dc10d7SGordon Ross /* XXX: pch pll's can be enabled any time before we enable the PCH
294447dc10d7SGordon Ross * transcoder, and we actually should do this to not upset any PCH
294547dc10d7SGordon Ross * transcoder that already use the clock when we share it.
294647dc10d7SGordon Ross *
294747dc10d7SGordon Ross * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
294847dc10d7SGordon Ross * unconditionally resets the pll - we need that to have the right LVDS
294947dc10d7SGordon Ross * enable sequence. */
295047dc10d7SGordon Ross ironlake_enable_shared_dpll(intel_crtc);
295147dc10d7SGordon Ross
295247dc10d7SGordon Ross if (HAS_PCH_CPT(dev)) {
295347dc10d7SGordon Ross u32 sel;
295447dc10d7SGordon Ross
295547dc10d7SGordon Ross temp = I915_READ(PCH_DPLL_SEL);
295647dc10d7SGordon Ross temp |= TRANS_DPLL_ENABLE(pipe);
295747dc10d7SGordon Ross sel = TRANS_DPLLB_SEL(pipe);
295847dc10d7SGordon Ross if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
295947dc10d7SGordon Ross temp |= sel;
296047dc10d7SGordon Ross else
296147dc10d7SGordon Ross temp &= ~sel;
296247dc10d7SGordon Ross I915_WRITE(PCH_DPLL_SEL, temp);
296347dc10d7SGordon Ross }
296447dc10d7SGordon Ross
296547dc10d7SGordon Ross /* set transcoder timing */
296647dc10d7SGordon Ross assert_panel_unlocked(dev_priv, pipe);
296747dc10d7SGordon Ross ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
296847dc10d7SGordon Ross
296947dc10d7SGordon Ross intel_fdi_normal_train(crtc);
297047dc10d7SGordon Ross
297147dc10d7SGordon Ross /* For PCH DP, enable TRANS_DP_CTL */
297247dc10d7SGordon Ross if (HAS_PCH_CPT(dev) &&
297347dc10d7SGordon Ross (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
297447dc10d7SGordon Ross intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
297547dc10d7SGordon Ross u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
297647dc10d7SGordon Ross reg = TRANS_DP_CTL(pipe);
297747dc10d7SGordon Ross temp = I915_READ(reg);
297847dc10d7SGordon Ross temp &= ~(TRANS_DP_PORT_SEL_MASK |
297947dc10d7SGordon Ross TRANS_DP_SYNC_MASK |
298047dc10d7SGordon Ross TRANS_DP_BPC_MASK);
298147dc10d7SGordon Ross temp |= (TRANS_DP_OUTPUT_ENABLE |
298247dc10d7SGordon Ross TRANS_DP_ENH_FRAMING);
298347dc10d7SGordon Ross temp |= bpc << 9; /* same format but at 11:9 */
298447dc10d7SGordon Ross
298547dc10d7SGordon Ross if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
298647dc10d7SGordon Ross temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
298747dc10d7SGordon Ross if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
298847dc10d7SGordon Ross temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
298947dc10d7SGordon Ross
299047dc10d7SGordon Ross switch (intel_trans_dp_port_sel(crtc)) {
299147dc10d7SGordon Ross case PCH_DP_B:
299247dc10d7SGordon Ross temp |= TRANS_DP_PORT_SEL_B;
299347dc10d7SGordon Ross break;
299447dc10d7SGordon Ross case PCH_DP_C:
299547dc10d7SGordon Ross temp |= TRANS_DP_PORT_SEL_C;
299647dc10d7SGordon Ross break;
299747dc10d7SGordon Ross case PCH_DP_D:
299847dc10d7SGordon Ross temp |= TRANS_DP_PORT_SEL_D;
299947dc10d7SGordon Ross break;
300047dc10d7SGordon Ross default:
300147dc10d7SGordon Ross BUG();
300247dc10d7SGordon Ross }
300347dc10d7SGordon Ross
300447dc10d7SGordon Ross I915_WRITE(reg, temp);
300547dc10d7SGordon Ross }
300647dc10d7SGordon Ross
300747dc10d7SGordon Ross ironlake_enable_pch_transcoder(dev_priv, pipe);
300847dc10d7SGordon Ross }
300947dc10d7SGordon Ross
lpt_pch_enable(struct drm_crtc * crtc)301047dc10d7SGordon Ross static void lpt_pch_enable(struct drm_crtc *crtc)
301147dc10d7SGordon Ross {
301247dc10d7SGordon Ross struct drm_device *dev = crtc->dev;
301347dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
301447dc10d7SGordon Ross struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
301547dc10d7SGordon Ross enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
301647dc10d7SGordon Ross
301747dc10d7SGordon Ross assert_pch_transcoder_disabled(dev_priv, (enum pipe) TRANSCODER_A);
301847dc10d7SGordon Ross
301947dc10d7SGordon Ross lpt_program_iclkip(crtc);
302047dc10d7SGordon Ross
302147dc10d7SGordon Ross /* Set transcoder timing. */
302247dc10d7SGordon Ross ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
302347dc10d7SGordon Ross
302447dc10d7SGordon Ross lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
302547dc10d7SGordon Ross }
302647dc10d7SGordon Ross
intel_put_shared_dpll(struct intel_crtc * crtc)302747dc10d7SGordon Ross static void intel_put_shared_dpll(struct intel_crtc *crtc)
302847dc10d7SGordon Ross {
302947dc10d7SGordon Ross struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
303047dc10d7SGordon Ross
303147dc10d7SGordon Ross if (pll == NULL)
303247dc10d7SGordon Ross return;
303347dc10d7SGordon Ross
303447dc10d7SGordon Ross if (pll->refcount == 0) {
303547dc10d7SGordon Ross DRM_ERROR("bad PCH PLL refcount\n");
303647dc10d7SGordon Ross return;
303747dc10d7SGordon Ross }
303847dc10d7SGordon Ross
303947dc10d7SGordon Ross if (--pll->refcount == 0) {
304047dc10d7SGordon Ross WARN_ON(pll->on);
304147dc10d7SGordon Ross WARN_ON(pll->active);
304247dc10d7SGordon Ross if (pll->on || pll->active)
304347dc10d7SGordon Ross DRM_ERROR("PCH PLL refcount is 0, but it's still active");
304447dc10d7SGordon Ross }
304547dc10d7SGordon Ross
304647dc10d7SGordon Ross crtc->config.shared_dpll = DPLL_ID_PRIVATE;
304747dc10d7SGordon Ross }
304847dc10d7SGordon Ross
intel_get_shared_dpll(struct intel_crtc * crtc,u32 dpll,u32 fp)304947dc10d7SGordon Ross static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc, u32 dpll, u32 fp)
305047dc10d7SGordon Ross {
305147dc10d7SGordon Ross struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
305247dc10d7SGordon Ross struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
305347dc10d7SGordon Ross enum intel_dpll_id i;
305447dc10d7SGordon Ross
305547dc10d7SGordon Ross if (pll) {
305647dc10d7SGordon Ross DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
305747dc10d7SGordon Ross crtc->base.base.id, pll->name);
305847dc10d7SGordon Ross intel_put_shared_dpll(crtc);
305947dc10d7SGordon Ross }
306047dc10d7SGordon Ross
306147dc10d7SGordon Ross if (HAS_PCH_IBX(dev_priv->dev)) {
306247dc10d7SGordon Ross /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
306347dc10d7SGordon Ross i = (enum intel_dpll_id)crtc->pipe;
306447dc10d7SGordon Ross pll = &dev_priv->shared_dplls[i];
306547dc10d7SGordon Ross
306647dc10d7SGordon Ross DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
306747dc10d7SGordon Ross crtc->base.base.id, pll->name);
306847dc10d7SGordon Ross
306947dc10d7SGordon Ross goto found;
307047dc10d7SGordon Ross }
307147dc10d7SGordon Ross
307247dc10d7SGordon Ross for (i = 0; i < dev_priv->num_shared_dpll; i++) {
307347dc10d7SGordon Ross pll = &dev_priv->shared_dplls[i];
307447dc10d7SGordon Ross
307547dc10d7SGordon Ross /* Only want to check enabled timings first */
307647dc10d7SGordon Ross if (pll->refcount == 0)
307747dc10d7SGordon Ross continue;
307847dc10d7SGordon Ross
307947dc10d7SGordon Ross if ((dpll & 0x7fffffff) == (I915_READ(PCH_DPLL(pll->id)) & 0x7fffffff) &&
308047dc10d7SGordon Ross fp == I915_READ(PCH_FP0(pll->id))) {
308147dc10d7SGordon Ross DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
308247dc10d7SGordon Ross crtc->base.base.id,
308347dc10d7SGordon Ross pll->name, pll->refcount, pll->active);
308447dc10d7SGordon Ross
308547dc10d7SGordon Ross goto found;
308647dc10d7SGordon Ross }
308747dc10d7SGordon Ross }
308847dc10d7SGordon Ross
308947dc10d7SGordon Ross /* Ok no matching timings, maybe there's a free one? */
309047dc10d7SGordon Ross for (i = 0; i < dev_priv->num_shared_dpll; i++) {
309147dc10d7SGordon Ross pll = &dev_priv->shared_dplls[i];
309247dc10d7SGordon Ross if (pll->refcount == 0) {
309347dc10d7SGordon Ross DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
309447dc10d7SGordon Ross crtc->base.base.id, pll->name);
309547dc10d7SGordon Ross goto found;
309647dc10d7SGordon Ross }
309747dc10d7SGordon Ross }
309847dc10d7SGordon Ross
309947dc10d7SGordon Ross return NULL;
310047dc10d7SGordon Ross
310147dc10d7SGordon Ross found:
310247dc10d7SGordon Ross crtc->config.shared_dpll = i;
310347dc10d7SGordon Ross DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
310447dc10d7SGordon Ross pipe_name(crtc->pipe));
310547dc10d7SGordon Ross
310647dc10d7SGordon Ross if (pll->active == 0) {
310747dc10d7SGordon Ross memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
310847dc10d7SGordon Ross sizeof(pll->hw_state));
310947dc10d7SGordon Ross
311047dc10d7SGordon Ross DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
311147dc10d7SGordon Ross WARN_ON(pll->on);
311247dc10d7SGordon Ross assert_shared_dpll_disabled(dev_priv, pll);
311347dc10d7SGordon Ross
311447dc10d7SGordon Ross /* Wait for the clocks to stabilize before rewriting the regs */
311547dc10d7SGordon Ross I915_WRITE(PCH_DPLL(pll->id), dpll & ~DPLL_VCO_ENABLE);
311647dc10d7SGordon Ross POSTING_READ(PCH_DPLL(pll->id));
311747dc10d7SGordon Ross udelay(150);
311847dc10d7SGordon Ross
311947dc10d7SGordon Ross I915_WRITE(PCH_FP0(pll->id), fp);
312047dc10d7SGordon Ross I915_WRITE(PCH_DPLL(pll->id), dpll & ~DPLL_VCO_ENABLE);
312147dc10d7SGordon Ross }
312247dc10d7SGordon Ross pll->refcount++;
312347dc10d7SGordon Ross
312447dc10d7SGordon Ross return pll;
312547dc10d7SGordon Ross }
312647dc10d7SGordon Ross
cpt_verify_modeset(struct drm_device * dev,int pipe)312747dc10d7SGordon Ross static void cpt_verify_modeset(struct drm_device *dev, int pipe)
312847dc10d7SGordon Ross {
312947dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
313047dc10d7SGordon Ross int dslreg = PIPEDSL(pipe);
313147dc10d7SGordon Ross u32 temp;
313247dc10d7SGordon Ross
313347dc10d7SGordon Ross temp = I915_READ(dslreg);
313447dc10d7SGordon Ross udelay(500);
313547dc10d7SGordon Ross if (wait_for(I915_READ(dslreg) != temp, 5)) {
313647dc10d7SGordon Ross if (wait_for(I915_READ(dslreg) != temp, 5))
313747dc10d7SGordon Ross DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
313847dc10d7SGordon Ross }
313947dc10d7SGordon Ross }
314047dc10d7SGordon Ross
ironlake_pfit_enable(struct intel_crtc * crtc)314147dc10d7SGordon Ross static void ironlake_pfit_enable(struct intel_crtc *crtc)
314247dc10d7SGordon Ross {
314347dc10d7SGordon Ross struct drm_device *dev = crtc->base.dev;
314447dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
314547dc10d7SGordon Ross int pipe = crtc->pipe;
314647dc10d7SGordon Ross
314747dc10d7SGordon Ross if (crtc->config.pch_pfit.size) {
314847dc10d7SGordon Ross /* Force use of hard-coded filter coefficients
314947dc10d7SGordon Ross * as some pre-programmed values are broken,
315047dc10d7SGordon Ross * e.g. x201.
315147dc10d7SGordon Ross */
315247dc10d7SGordon Ross if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
315347dc10d7SGordon Ross I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
315447dc10d7SGordon Ross PF_PIPE_SEL_IVB(pipe));
315547dc10d7SGordon Ross else
315647dc10d7SGordon Ross I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
315747dc10d7SGordon Ross I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
315847dc10d7SGordon Ross I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
315947dc10d7SGordon Ross }
316047dc10d7SGordon Ross }
316147dc10d7SGordon Ross
intel_enable_planes(struct drm_crtc * crtc)316247dc10d7SGordon Ross static void intel_enable_planes(struct drm_crtc *crtc)
316347dc10d7SGordon Ross {
316447dc10d7SGordon Ross struct drm_device *dev = crtc->dev;
316547dc10d7SGordon Ross enum pipe pipe = to_intel_crtc(crtc)->pipe;
316647dc10d7SGordon Ross struct intel_plane *intel_plane;
316747dc10d7SGordon Ross
316847dc10d7SGordon Ross list_for_each_entry(intel_plane, struct intel_plane, &dev->mode_config.plane_list, base.head)
316947dc10d7SGordon Ross if (intel_plane->pipe == pipe)
317047dc10d7SGordon Ross intel_plane_restore(&intel_plane->base);
317147dc10d7SGordon Ross }
317247dc10d7SGordon Ross
intel_disable_planes(struct drm_crtc * crtc)317347dc10d7SGordon Ross static void intel_disable_planes(struct drm_crtc *crtc)
317447dc10d7SGordon Ross {
317547dc10d7SGordon Ross struct drm_device *dev = crtc->dev;
317647dc10d7SGordon Ross enum pipe pipe = to_intel_crtc(crtc)->pipe;
317747dc10d7SGordon Ross struct intel_plane *intel_plane;
317847dc10d7SGordon Ross
317947dc10d7SGordon Ross list_for_each_entry(intel_plane, struct intel_plane, &dev->mode_config.plane_list, base.head)
318047dc10d7SGordon Ross if (intel_plane->pipe == pipe)
318147dc10d7SGordon Ross intel_plane_disable(&intel_plane->base);
318247dc10d7SGordon Ross }
318347dc10d7SGordon Ross
ironlake_crtc_enable(struct drm_crtc * crtc)318447dc10d7SGordon Ross static void ironlake_crtc_enable(struct drm_crtc *crtc)
318547dc10d7SGordon Ross {
318647dc10d7SGordon Ross struct drm_device *dev = crtc->dev;
318747dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
318847dc10d7SGordon Ross struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
318947dc10d7SGordon Ross struct intel_encoder *encoder;
319047dc10d7SGordon Ross int pipe = intel_crtc->pipe;
319147dc10d7SGordon Ross int plane = intel_crtc->plane;
319247dc10d7SGordon Ross u32 temp;
319347dc10d7SGordon Ross
319447dc10d7SGordon Ross WARN_ON(!crtc->enabled);
319547dc10d7SGordon Ross
319647dc10d7SGordon Ross if (intel_crtc->active)
319747dc10d7SGordon Ross return;
319847dc10d7SGordon Ross
319947dc10d7SGordon Ross intel_crtc->active = true;
320047dc10d7SGordon Ross
320147dc10d7SGordon Ross intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
320247dc10d7SGordon Ross intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
320347dc10d7SGordon Ross
320447dc10d7SGordon Ross intel_update_watermarks(dev);
320547dc10d7SGordon Ross
320647dc10d7SGordon Ross if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
320747dc10d7SGordon Ross temp = I915_READ(PCH_LVDS);
320847dc10d7SGordon Ross if ((temp & LVDS_PORT_EN) == 0)
320947dc10d7SGordon Ross I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
321047dc10d7SGordon Ross }
321147dc10d7SGordon Ross
321247dc10d7SGordon Ross
321347dc10d7SGordon Ross if (intel_crtc->config.has_pch_encoder) {
321447dc10d7SGordon Ross /* Note: FDI PLL enabling _must_ be done before we enable the
321547dc10d7SGordon Ross * cpu pipes, hence this is separate from all the other fdi/pch
321647dc10d7SGordon Ross * enabling. */
321747dc10d7SGordon Ross ironlake_fdi_pll_enable(intel_crtc);
321847dc10d7SGordon Ross } else {
321947dc10d7SGordon Ross assert_fdi_tx_disabled(dev_priv, pipe);
322047dc10d7SGordon Ross assert_fdi_rx_disabled(dev_priv, pipe);
322147dc10d7SGordon Ross }
322247dc10d7SGordon Ross
322347dc10d7SGordon Ross for_each_encoder_on_crtc(dev, crtc, encoder)
322447dc10d7SGordon Ross if (encoder->pre_enable)
322547dc10d7SGordon Ross encoder->pre_enable(encoder);
322647dc10d7SGordon Ross
322747dc10d7SGordon Ross ironlake_pfit_enable(intel_crtc);
322847dc10d7SGordon Ross
322947dc10d7SGordon Ross /*
323047dc10d7SGordon Ross * On ILK+ LUT must be loaded before the pipe is running but with
323147dc10d7SGordon Ross * clocks enabled
323247dc10d7SGordon Ross */
323347dc10d7SGordon Ross intel_crtc_load_lut(crtc);
323447dc10d7SGordon Ross
323547dc10d7SGordon Ross intel_enable_pipe(dev_priv, pipe,
323647dc10d7SGordon Ross intel_crtc->config.has_pch_encoder);
323747dc10d7SGordon Ross intel_enable_plane(dev_priv, plane, pipe);
323847dc10d7SGordon Ross intel_enable_planes(crtc);
323947dc10d7SGordon Ross intel_crtc_update_cursor(crtc, true);
324047dc10d7SGordon Ross
324147dc10d7SGordon Ross if (intel_crtc->config.has_pch_encoder)
324247dc10d7SGordon Ross ironlake_pch_enable(crtc);
324347dc10d7SGordon Ross
324447dc10d7SGordon Ross mutex_lock(&dev->struct_mutex);
324547dc10d7SGordon Ross intel_update_fbc(dev);
324647dc10d7SGordon Ross mutex_unlock(&dev->struct_mutex);
324747dc10d7SGordon Ross
324847dc10d7SGordon Ross for_each_encoder_on_crtc(dev, crtc, encoder)
324947dc10d7SGordon Ross encoder->enable(encoder);
325047dc10d7SGordon Ross
325147dc10d7SGordon Ross if (HAS_PCH_CPT(dev))
325247dc10d7SGordon Ross cpt_verify_modeset(dev, intel_crtc->pipe);
325347dc10d7SGordon Ross
325447dc10d7SGordon Ross /*
325547dc10d7SGordon Ross * There seems to be a race in PCH platform hw (at least on some
325647dc10d7SGordon Ross * outputs) where an enabled pipe still completes any pageflip right
325747dc10d7SGordon Ross * away (as if the pipe is off) instead of waiting for vblank. As soon
325847dc10d7SGordon Ross * as the first vblank happend, everything works as expected. Hence just
325947dc10d7SGordon Ross * wait for one vblank before returning to avoid strange things
326047dc10d7SGordon Ross * happening.
326147dc10d7SGordon Ross */
326247dc10d7SGordon Ross intel_wait_for_vblank(dev, intel_crtc->pipe);
326347dc10d7SGordon Ross }
326447dc10d7SGordon Ross
326547dc10d7SGordon Ross /* IPS only exists on ULT machines and is tied to pipe A. */
hsw_crtc_supports_ips(struct intel_crtc * crtc)326647dc10d7SGordon Ross static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
326747dc10d7SGordon Ross {
326847dc10d7SGordon Ross return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
326947dc10d7SGordon Ross }
327047dc10d7SGordon Ross
hsw_enable_ips(struct intel_crtc * crtc)327147dc10d7SGordon Ross static void hsw_enable_ips(struct intel_crtc *crtc)
327247dc10d7SGordon Ross {
327347dc10d7SGordon Ross struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
327447dc10d7SGordon Ross
327547dc10d7SGordon Ross if (!crtc->config.ips_enabled)
327647dc10d7SGordon Ross return;
327747dc10d7SGordon Ross
327847dc10d7SGordon Ross /* We can only enable IPS after we enable a plane and wait for a vblank.
327947dc10d7SGordon Ross * We guarantee that the plane is enabled by calling intel_enable_ips
328047dc10d7SGordon Ross * only after intel_enable_plane. And intel_enable_plane already waits
328147dc10d7SGordon Ross * for a vblank, so all we need to do here is to enable the IPS bit. */
328247dc10d7SGordon Ross assert_plane_enabled(dev_priv, crtc->plane);
328347dc10d7SGordon Ross I915_WRITE(IPS_CTL, IPS_ENABLE);
328447dc10d7SGordon Ross }
328547dc10d7SGordon Ross
hsw_disable_ips(struct intel_crtc * crtc)328647dc10d7SGordon Ross static void hsw_disable_ips(struct intel_crtc *crtc)
328747dc10d7SGordon Ross {
328847dc10d7SGordon Ross struct drm_device *dev = crtc->base.dev;
328947dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
329047dc10d7SGordon Ross
329147dc10d7SGordon Ross if (!crtc->config.ips_enabled)
329247dc10d7SGordon Ross return;
329347dc10d7SGordon Ross
329447dc10d7SGordon Ross assert_plane_enabled(dev_priv, crtc->plane);
329547dc10d7SGordon Ross I915_WRITE(IPS_CTL, 0);
329647dc10d7SGordon Ross
329747dc10d7SGordon Ross /* We need to wait for a vblank before we can disable the plane. */
329847dc10d7SGordon Ross intel_wait_for_vblank(dev, crtc->pipe);
329947dc10d7SGordon Ross }
330047dc10d7SGordon Ross
haswell_crtc_enable(struct drm_crtc * crtc)330147dc10d7SGordon Ross static void haswell_crtc_enable(struct drm_crtc *crtc)
330247dc10d7SGordon Ross {
330347dc10d7SGordon Ross struct drm_device *dev = crtc->dev;
330447dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
330547dc10d7SGordon Ross struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
330647dc10d7SGordon Ross struct intel_encoder *encoder;
330747dc10d7SGordon Ross int pipe = intel_crtc->pipe;
330847dc10d7SGordon Ross int plane = intel_crtc->plane;
330947dc10d7SGordon Ross
331047dc10d7SGordon Ross WARN_ON(!crtc->enabled);
331147dc10d7SGordon Ross
331247dc10d7SGordon Ross if (intel_crtc->active)
331347dc10d7SGordon Ross return;
331447dc10d7SGordon Ross
331547dc10d7SGordon Ross intel_crtc->active = true;
331647dc10d7SGordon Ross
331747dc10d7SGordon Ross intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
331847dc10d7SGordon Ross if (intel_crtc->config.has_pch_encoder)
331947dc10d7SGordon Ross intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
332047dc10d7SGordon Ross
332147dc10d7SGordon Ross intel_update_watermarks(dev);
332247dc10d7SGordon Ross
332347dc10d7SGordon Ross if (intel_crtc->config.has_pch_encoder)
332447dc10d7SGordon Ross dev_priv->display.fdi_link_train(crtc);
332547dc10d7SGordon Ross
332647dc10d7SGordon Ross for_each_encoder_on_crtc(dev, crtc, encoder)
332747dc10d7SGordon Ross if (encoder->pre_enable)
332847dc10d7SGordon Ross encoder->pre_enable(encoder);
332947dc10d7SGordon Ross
333047dc10d7SGordon Ross intel_ddi_enable_pipe_clock(intel_crtc);
333147dc10d7SGordon Ross
333247dc10d7SGordon Ross ironlake_pfit_enable(intel_crtc);
333347dc10d7SGordon Ross
333447dc10d7SGordon Ross /*
333547dc10d7SGordon Ross * On ILK+ LUT must be loaded before the pipe is running but with
333647dc10d7SGordon Ross * clocks enabled
333747dc10d7SGordon Ross */
333847dc10d7SGordon Ross intel_crtc_load_lut(crtc);
333947dc10d7SGordon Ross
334047dc10d7SGordon Ross intel_ddi_set_pipe_settings(crtc);
334147dc10d7SGordon Ross intel_ddi_enable_transcoder_func(crtc);
334247dc10d7SGordon Ross
334347dc10d7SGordon Ross intel_enable_pipe(dev_priv, pipe,
334447dc10d7SGordon Ross intel_crtc->config.has_pch_encoder);
334547dc10d7SGordon Ross intel_enable_plane(dev_priv, plane, pipe);
334647dc10d7SGordon Ross intel_enable_planes(crtc);
334747dc10d7SGordon Ross intel_crtc_update_cursor(crtc, true);
334847dc10d7SGordon Ross
334947dc10d7SGordon Ross hsw_enable_ips(intel_crtc);
335047dc10d7SGordon Ross
335147dc10d7SGordon Ross if (intel_crtc->config.has_pch_encoder)
335247dc10d7SGordon Ross lpt_pch_enable(crtc);
335347dc10d7SGordon Ross
335447dc10d7SGordon Ross mutex_lock(&dev->struct_mutex);
335547dc10d7SGordon Ross intel_update_fbc(dev);
335647dc10d7SGordon Ross mutex_unlock(&dev->struct_mutex);
335747dc10d7SGordon Ross
335847dc10d7SGordon Ross for_each_encoder_on_crtc(dev, crtc, encoder)
335947dc10d7SGordon Ross encoder->enable(encoder);
336047dc10d7SGordon Ross
336147dc10d7SGordon Ross /*
336247dc10d7SGordon Ross * There seems to be a race in PCH platform hw (at least on some
336347dc10d7SGordon Ross * outputs) where an enabled pipe still completes any pageflip right
336447dc10d7SGordon Ross * away (as if the pipe is off) instead of waiting for vblank. As soon
336547dc10d7SGordon Ross * as the first vblank happend, everything works as expected. Hence just
336647dc10d7SGordon Ross * wait for one vblank before returning to avoid strange things
336747dc10d7SGordon Ross * happening.
336847dc10d7SGordon Ross */
336947dc10d7SGordon Ross intel_wait_for_vblank(dev, intel_crtc->pipe);
337047dc10d7SGordon Ross }
337147dc10d7SGordon Ross
ironlake_pfit_disable(struct intel_crtc * crtc)337247dc10d7SGordon Ross static void ironlake_pfit_disable(struct intel_crtc *crtc)
337347dc10d7SGordon Ross {
337447dc10d7SGordon Ross struct drm_device *dev = crtc->base.dev;
337547dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
337647dc10d7SGordon Ross int pipe = crtc->pipe;
337747dc10d7SGordon Ross
337847dc10d7SGordon Ross /* To avoid upsetting the power well on haswell only disable the pfit if
337947dc10d7SGordon Ross * it's in use. The hw state code will make sure we get this right. */
338047dc10d7SGordon Ross if (crtc->config.pch_pfit.size) {
338147dc10d7SGordon Ross I915_WRITE(PF_CTL(pipe), 0);
338247dc10d7SGordon Ross I915_WRITE(PF_WIN_POS(pipe), 0);
338347dc10d7SGordon Ross I915_WRITE(PF_WIN_SZ(pipe), 0);
338447dc10d7SGordon Ross }
338547dc10d7SGordon Ross }
338647dc10d7SGordon Ross
ironlake_crtc_disable(struct drm_crtc * crtc)338747dc10d7SGordon Ross static void ironlake_crtc_disable(struct drm_crtc *crtc)
338847dc10d7SGordon Ross {
338947dc10d7SGordon Ross struct drm_device *dev = crtc->dev;
339047dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
339147dc10d7SGordon Ross struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
339247dc10d7SGordon Ross struct intel_encoder *encoder;
339347dc10d7SGordon Ross int pipe = intel_crtc->pipe;
339447dc10d7SGordon Ross int plane = intel_crtc->plane;
339547dc10d7SGordon Ross u32 reg, temp;
339647dc10d7SGordon Ross
339747dc10d7SGordon Ross
339847dc10d7SGordon Ross if (!intel_crtc->active)
339947dc10d7SGordon Ross return;
340047dc10d7SGordon Ross
340147dc10d7SGordon Ross for_each_encoder_on_crtc(dev, crtc, encoder)
340247dc10d7SGordon Ross encoder->disable(encoder);
340347dc10d7SGordon Ross
340447dc10d7SGordon Ross intel_crtc_wait_for_pending_flips(crtc);
340547dc10d7SGordon Ross drm_vblank_off(dev, pipe);
340647dc10d7SGordon Ross
340747dc10d7SGordon Ross if (dev_priv->cfb_plane == plane)
340847dc10d7SGordon Ross intel_disable_fbc(dev);
340947dc10d7SGordon Ross
341047dc10d7SGordon Ross intel_crtc_update_cursor(crtc, false);
341147dc10d7SGordon Ross intel_disable_planes(crtc);
341247dc10d7SGordon Ross intel_disable_plane(dev_priv, plane, pipe);
341347dc10d7SGordon Ross
341447dc10d7SGordon Ross if (intel_crtc->config.has_pch_encoder)
341547dc10d7SGordon Ross intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
341647dc10d7SGordon Ross
341747dc10d7SGordon Ross intel_disable_pipe(dev_priv, pipe);
341847dc10d7SGordon Ross
341947dc10d7SGordon Ross ironlake_pfit_disable(intel_crtc);
342047dc10d7SGordon Ross
342147dc10d7SGordon Ross for_each_encoder_on_crtc(dev, crtc, encoder)
342247dc10d7SGordon Ross if (encoder->post_disable)
342347dc10d7SGordon Ross encoder->post_disable(encoder);
342447dc10d7SGordon Ross
342547dc10d7SGordon Ross if (intel_crtc->config.has_pch_encoder) {
342647dc10d7SGordon Ross ironlake_fdi_disable(crtc);
342747dc10d7SGordon Ross
342847dc10d7SGordon Ross ironlake_disable_pch_transcoder(dev_priv, pipe);
342947dc10d7SGordon Ross intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
343047dc10d7SGordon Ross
343147dc10d7SGordon Ross if (HAS_PCH_CPT(dev)) {
343247dc10d7SGordon Ross /* disable TRANS_DP_CTL */
343347dc10d7SGordon Ross reg = TRANS_DP_CTL(pipe);
343447dc10d7SGordon Ross temp = I915_READ(reg);
343547dc10d7SGordon Ross temp &= ~(TRANS_DP_OUTPUT_ENABLE |
343647dc10d7SGordon Ross TRANS_DP_PORT_SEL_MASK);
343747dc10d7SGordon Ross temp |= TRANS_DP_PORT_SEL_NONE;
343847dc10d7SGordon Ross I915_WRITE(reg, temp);
343947dc10d7SGordon Ross
344047dc10d7SGordon Ross /* disable DPLL_SEL */
344147dc10d7SGordon Ross temp = I915_READ(PCH_DPLL_SEL);
344247dc10d7SGordon Ross temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
344347dc10d7SGordon Ross I915_WRITE(PCH_DPLL_SEL, temp);
344447dc10d7SGordon Ross }
344547dc10d7SGordon Ross
344647dc10d7SGordon Ross /* disable PCH DPLL */
344747dc10d7SGordon Ross intel_disable_shared_dpll(intel_crtc);
344847dc10d7SGordon Ross
344947dc10d7SGordon Ross ironlake_fdi_pll_disable(intel_crtc);
345047dc10d7SGordon Ross }
345147dc10d7SGordon Ross
345247dc10d7SGordon Ross intel_crtc->active = false;
345347dc10d7SGordon Ross intel_update_watermarks(dev);
345447dc10d7SGordon Ross
345547dc10d7SGordon Ross mutex_lock(&dev->struct_mutex);
345647dc10d7SGordon Ross intel_update_fbc(dev);
345747dc10d7SGordon Ross mutex_unlock(&dev->struct_mutex);
345847dc10d7SGordon Ross }
345947dc10d7SGordon Ross
haswell_crtc_disable(struct drm_crtc * crtc)346047dc10d7SGordon Ross static void haswell_crtc_disable(struct drm_crtc *crtc)
346147dc10d7SGordon Ross {
346247dc10d7SGordon Ross struct drm_device *dev = crtc->dev;
346347dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
346447dc10d7SGordon Ross struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
346547dc10d7SGordon Ross struct intel_encoder *encoder;
346647dc10d7SGordon Ross int pipe = intel_crtc->pipe;
346747dc10d7SGordon Ross int plane = intel_crtc->plane;
346847dc10d7SGordon Ross enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
346947dc10d7SGordon Ross
347047dc10d7SGordon Ross if (!intel_crtc->active)
347147dc10d7SGordon Ross return;
347247dc10d7SGordon Ross
347347dc10d7SGordon Ross for_each_encoder_on_crtc(dev, crtc, encoder)
347447dc10d7SGordon Ross encoder->disable(encoder);
347547dc10d7SGordon Ross
347647dc10d7SGordon Ross intel_crtc_wait_for_pending_flips(crtc);
347747dc10d7SGordon Ross drm_vblank_off(dev, pipe);
347847dc10d7SGordon Ross
347947dc10d7SGordon Ross /* FBC must be disabled before disabling the plane on HSW. */
348047dc10d7SGordon Ross if (dev_priv->cfb_plane == plane)
348147dc10d7SGordon Ross intel_disable_fbc(dev);
348247dc10d7SGordon Ross
348347dc10d7SGordon Ross hsw_disable_ips(intel_crtc);
348447dc10d7SGordon Ross
348547dc10d7SGordon Ross intel_crtc_update_cursor(crtc, false);
348647dc10d7SGordon Ross intel_disable_planes(crtc);
348747dc10d7SGordon Ross intel_disable_plane(dev_priv, plane, pipe);
348847dc10d7SGordon Ross
348947dc10d7SGordon Ross if (intel_crtc->config.has_pch_encoder)
349047dc10d7SGordon Ross intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
349147dc10d7SGordon Ross intel_disable_pipe(dev_priv, pipe);
349247dc10d7SGordon Ross
349347dc10d7SGordon Ross intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
349447dc10d7SGordon Ross
349547dc10d7SGordon Ross ironlake_pfit_disable(intel_crtc);
349647dc10d7SGordon Ross
349747dc10d7SGordon Ross intel_ddi_disable_pipe_clock(intel_crtc);
349847dc10d7SGordon Ross
349947dc10d7SGordon Ross for_each_encoder_on_crtc(dev, crtc, encoder)
350047dc10d7SGordon Ross if (encoder->post_disable)
350147dc10d7SGordon Ross encoder->post_disable(encoder);
350247dc10d7SGordon Ross
350347dc10d7SGordon Ross if (intel_crtc->config.has_pch_encoder) {
350447dc10d7SGordon Ross lpt_disable_pch_transcoder(dev_priv);
350547dc10d7SGordon Ross intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
350647dc10d7SGordon Ross intel_ddi_fdi_disable(crtc);
350747dc10d7SGordon Ross }
350847dc10d7SGordon Ross
350947dc10d7SGordon Ross intel_crtc->active = false;
351047dc10d7SGordon Ross intel_update_watermarks(dev);
351147dc10d7SGordon Ross
351247dc10d7SGordon Ross mutex_lock(&dev->struct_mutex);
351347dc10d7SGordon Ross intel_update_fbc(dev);
351447dc10d7SGordon Ross mutex_unlock(&dev->struct_mutex);
351547dc10d7SGordon Ross }
351647dc10d7SGordon Ross
ironlake_crtc_off(struct drm_crtc * crtc)351747dc10d7SGordon Ross static void ironlake_crtc_off(struct drm_crtc *crtc)
351847dc10d7SGordon Ross {
351947dc10d7SGordon Ross struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
352047dc10d7SGordon Ross intel_put_shared_dpll(intel_crtc);
352147dc10d7SGordon Ross }
352247dc10d7SGordon Ross
haswell_crtc_off(struct drm_crtc * crtc)352347dc10d7SGordon Ross static void haswell_crtc_off(struct drm_crtc *crtc)
352447dc10d7SGordon Ross {
352547dc10d7SGordon Ross intel_ddi_put_crtc_pll(crtc);
352647dc10d7SGordon Ross }
352747dc10d7SGordon Ross
intel_crtc_dpms_overlay(struct intel_crtc * intel_crtc,bool enable)352847dc10d7SGordon Ross static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
352947dc10d7SGordon Ross {
353047dc10d7SGordon Ross if (!enable && intel_crtc->overlay) {
353147dc10d7SGordon Ross struct drm_device *dev = intel_crtc->base.dev;
353247dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
353347dc10d7SGordon Ross
353447dc10d7SGordon Ross mutex_lock(&dev->struct_mutex);
353547dc10d7SGordon Ross dev_priv->mm.interruptible = false;
353647dc10d7SGordon Ross (void) intel_overlay_switch_off(intel_crtc->overlay);
353747dc10d7SGordon Ross dev_priv->mm.interruptible = true;
353847dc10d7SGordon Ross mutex_unlock(&dev->struct_mutex);
353947dc10d7SGordon Ross }
354047dc10d7SGordon Ross
354147dc10d7SGordon Ross /* Let userspace switch the overlay on again. In most cases userspace
354247dc10d7SGordon Ross * has to recompute where to put it anyway.
354347dc10d7SGordon Ross */
354447dc10d7SGordon Ross }
354547dc10d7SGordon Ross
354647dc10d7SGordon Ross /**
354747dc10d7SGordon Ross * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
354847dc10d7SGordon Ross * cursor plane briefly if not already running after enabling the display
354947dc10d7SGordon Ross * plane.
355047dc10d7SGordon Ross * This workaround avoids occasional blank screens when self refresh is
355147dc10d7SGordon Ross * enabled.
355247dc10d7SGordon Ross */
355347dc10d7SGordon Ross static void
g4x_fixup_plane(struct drm_i915_private * dev_priv,enum pipe pipe)355447dc10d7SGordon Ross g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
355547dc10d7SGordon Ross {
355647dc10d7SGordon Ross u32 cntl = I915_READ(CURCNTR(pipe));
355747dc10d7SGordon Ross
355847dc10d7SGordon Ross if ((cntl & CURSOR_MODE) == 0) {
355947dc10d7SGordon Ross u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
356047dc10d7SGordon Ross
356147dc10d7SGordon Ross I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
356247dc10d7SGordon Ross I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
356347dc10d7SGordon Ross intel_wait_for_vblank(dev_priv->dev, pipe);
356447dc10d7SGordon Ross I915_WRITE(CURCNTR(pipe), cntl);
356547dc10d7SGordon Ross I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
356647dc10d7SGordon Ross I915_WRITE(FW_BLC_SELF, fw_bcl_self);
356747dc10d7SGordon Ross }
356847dc10d7SGordon Ross }
356947dc10d7SGordon Ross
i9xx_pfit_enable(struct intel_crtc * crtc)357047dc10d7SGordon Ross static void i9xx_pfit_enable(struct intel_crtc *crtc)
357147dc10d7SGordon Ross {
357247dc10d7SGordon Ross struct drm_device *dev = crtc->base.dev;
357347dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
357447dc10d7SGordon Ross struct intel_crtc_config *pipe_config = &crtc->config;
357547dc10d7SGordon Ross
357647dc10d7SGordon Ross if (!crtc->config.gmch_pfit.control)
357747dc10d7SGordon Ross return;
357847dc10d7SGordon Ross
357947dc10d7SGordon Ross /*
358047dc10d7SGordon Ross * The panel fitter should only be adjusted whilst the pipe is disabled,
358147dc10d7SGordon Ross * according to register description and PRM.
358247dc10d7SGordon Ross */
358347dc10d7SGordon Ross WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
358447dc10d7SGordon Ross assert_pipe_disabled(dev_priv, crtc->pipe);
358547dc10d7SGordon Ross
358647dc10d7SGordon Ross I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
358747dc10d7SGordon Ross I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
358847dc10d7SGordon Ross
358947dc10d7SGordon Ross /* Border color in case we don't scale up to the full screen. Black by
359047dc10d7SGordon Ross * default, change to something else for debugging. */
359147dc10d7SGordon Ross I915_WRITE(BCLRPAT(crtc->pipe), 0);
359247dc10d7SGordon Ross }
359347dc10d7SGordon Ross
valleyview_crtc_enable(struct drm_crtc * crtc)359447dc10d7SGordon Ross static void valleyview_crtc_enable(struct drm_crtc *crtc)
359547dc10d7SGordon Ross {
359647dc10d7SGordon Ross struct drm_device *dev = crtc->dev;
359747dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
359847dc10d7SGordon Ross struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
359947dc10d7SGordon Ross struct intel_encoder *encoder;
360047dc10d7SGordon Ross int pipe = intel_crtc->pipe;
360147dc10d7SGordon Ross int plane = intel_crtc->plane;
360247dc10d7SGordon Ross
360347dc10d7SGordon Ross WARN_ON(!crtc->enabled);
360447dc10d7SGordon Ross
360547dc10d7SGordon Ross if (intel_crtc->active)
360647dc10d7SGordon Ross return;
360747dc10d7SGordon Ross
360847dc10d7SGordon Ross intel_crtc->active = true;
360947dc10d7SGordon Ross intel_update_watermarks(dev);
361047dc10d7SGordon Ross
361147dc10d7SGordon Ross mutex_lock(&dev_priv->dpio_lock);
361247dc10d7SGordon Ross
361347dc10d7SGordon Ross for_each_encoder_on_crtc(dev, crtc, encoder)
361447dc10d7SGordon Ross if (encoder->pre_pll_enable)
361547dc10d7SGordon Ross encoder->pre_pll_enable(encoder);
361647dc10d7SGordon Ross
361747dc10d7SGordon Ross intel_enable_pll(dev_priv, pipe);
361847dc10d7SGordon Ross
361947dc10d7SGordon Ross for_each_encoder_on_crtc(dev, crtc, encoder)
362047dc10d7SGordon Ross if (encoder->pre_enable)
362147dc10d7SGordon Ross encoder->pre_enable(encoder);
362247dc10d7SGordon Ross
362347dc10d7SGordon Ross /* VLV wants encoder enabling _before_ the pipe is up. */
362447dc10d7SGordon Ross for_each_encoder_on_crtc(dev, crtc, encoder)
362547dc10d7SGordon Ross encoder->enable(encoder);
362647dc10d7SGordon Ross
362747dc10d7SGordon Ross i9xx_pfit_enable(intel_crtc);
362847dc10d7SGordon Ross
362947dc10d7SGordon Ross intel_crtc_load_lut(crtc);
363047dc10d7SGordon Ross
363147dc10d7SGordon Ross intel_enable_pipe(dev_priv, pipe, false);
363247dc10d7SGordon Ross intel_enable_plane(dev_priv, plane, pipe);
363347dc10d7SGordon Ross intel_enable_planes(crtc);
363447dc10d7SGordon Ross intel_crtc_update_cursor(crtc, true);
363547dc10d7SGordon Ross
363647dc10d7SGordon Ross intel_update_fbc(dev);
363747dc10d7SGordon Ross
363847dc10d7SGordon Ross mutex_unlock(&dev_priv->dpio_lock);
363947dc10d7SGordon Ross }
364047dc10d7SGordon Ross
i9xx_crtc_enable(struct drm_crtc * crtc)364147dc10d7SGordon Ross static void i9xx_crtc_enable(struct drm_crtc *crtc)
364247dc10d7SGordon Ross {
364347dc10d7SGordon Ross struct drm_device *dev = crtc->dev;
364447dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
364547dc10d7SGordon Ross struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
364647dc10d7SGordon Ross struct intel_encoder *encoder;
364747dc10d7SGordon Ross int pipe = intel_crtc->pipe;
364847dc10d7SGordon Ross int plane = intel_crtc->plane;
364947dc10d7SGordon Ross
365047dc10d7SGordon Ross WARN_ON(!crtc->enabled);
365147dc10d7SGordon Ross
365247dc10d7SGordon Ross if (intel_crtc->active)
365347dc10d7SGordon Ross return;
365447dc10d7SGordon Ross
365547dc10d7SGordon Ross intel_crtc->active = true;
365647dc10d7SGordon Ross intel_update_watermarks(dev);
365747dc10d7SGordon Ross
365847dc10d7SGordon Ross intel_enable_pll(dev_priv, pipe);
365947dc10d7SGordon Ross
366047dc10d7SGordon Ross for_each_encoder_on_crtc(dev, crtc, encoder)
366147dc10d7SGordon Ross if (encoder->pre_enable)
366247dc10d7SGordon Ross encoder->pre_enable(encoder);
366347dc10d7SGordon Ross
366447dc10d7SGordon Ross i9xx_pfit_enable(intel_crtc);
366547dc10d7SGordon Ross
366647dc10d7SGordon Ross intel_crtc_load_lut(crtc);
366747dc10d7SGordon Ross
366847dc10d7SGordon Ross intel_enable_pipe(dev_priv, pipe, false);
366947dc10d7SGordon Ross intel_enable_plane(dev_priv, plane, pipe);
367047dc10d7SGordon Ross intel_enable_planes(crtc);
367147dc10d7SGordon Ross /* The fixup needs to happen before cursor is enabled */
367247dc10d7SGordon Ross if (IS_G4X(dev))
367347dc10d7SGordon Ross g4x_fixup_plane(dev_priv, pipe);
367447dc10d7SGordon Ross intel_crtc_update_cursor(crtc, true);
367547dc10d7SGordon Ross
367647dc10d7SGordon Ross /* Give the overlay scaler a chance to enable if it's on this pipe */
367747dc10d7SGordon Ross intel_crtc_dpms_overlay(intel_crtc, true);
367847dc10d7SGordon Ross
367947dc10d7SGordon Ross intel_update_fbc(dev);
368047dc10d7SGordon Ross
368147dc10d7SGordon Ross for_each_encoder_on_crtc(dev, crtc, encoder)
368247dc10d7SGordon Ross encoder->enable(encoder);
368347dc10d7SGordon Ross }
368447dc10d7SGordon Ross
i9xx_pfit_disable(struct intel_crtc * crtc)368547dc10d7SGordon Ross static void i9xx_pfit_disable(struct intel_crtc *crtc)
368647dc10d7SGordon Ross {
368747dc10d7SGordon Ross struct drm_device *dev = crtc->base.dev;
368847dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
368947dc10d7SGordon Ross
369047dc10d7SGordon Ross if (!crtc->config.gmch_pfit.control)
369147dc10d7SGordon Ross return;
369247dc10d7SGordon Ross
369347dc10d7SGordon Ross assert_pipe_disabled(dev_priv, crtc->pipe);
369447dc10d7SGordon Ross
369547dc10d7SGordon Ross DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
369647dc10d7SGordon Ross I915_READ(PFIT_CONTROL));
369747dc10d7SGordon Ross I915_WRITE(PFIT_CONTROL, 0);
369847dc10d7SGordon Ross }
369947dc10d7SGordon Ross
i9xx_crtc_disable(struct drm_crtc * crtc)370047dc10d7SGordon Ross static void i9xx_crtc_disable(struct drm_crtc *crtc)
370147dc10d7SGordon Ross {
370247dc10d7SGordon Ross struct drm_device *dev = crtc->dev;
370347dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
370447dc10d7SGordon Ross struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
370547dc10d7SGordon Ross struct intel_encoder *encoder;
370647dc10d7SGordon Ross int pipe = intel_crtc->pipe;
370747dc10d7SGordon Ross int plane = intel_crtc->plane;
370847dc10d7SGordon Ross
370947dc10d7SGordon Ross if (!intel_crtc->active)
371047dc10d7SGordon Ross return;
371147dc10d7SGordon Ross
371247dc10d7SGordon Ross for_each_encoder_on_crtc(dev, crtc, encoder)
371347dc10d7SGordon Ross encoder->disable(encoder);
371447dc10d7SGordon Ross
371547dc10d7SGordon Ross /* Give the overlay scaler a chance to disable if it's on this pipe */
371647dc10d7SGordon Ross intel_crtc_wait_for_pending_flips(crtc);
371747dc10d7SGordon Ross drm_vblank_off(dev, pipe);
371847dc10d7SGordon Ross
371947dc10d7SGordon Ross if (dev_priv->cfb_plane == plane)
372047dc10d7SGordon Ross intel_disable_fbc(dev);
372147dc10d7SGordon Ross
372247dc10d7SGordon Ross intel_crtc_dpms_overlay(intel_crtc, false);
372347dc10d7SGordon Ross intel_crtc_update_cursor(crtc, false);
372447dc10d7SGordon Ross intel_disable_planes(crtc);
372547dc10d7SGordon Ross intel_disable_plane(dev_priv, plane, pipe);
372647dc10d7SGordon Ross
372747dc10d7SGordon Ross intel_disable_pipe(dev_priv, pipe);
372847dc10d7SGordon Ross
372947dc10d7SGordon Ross i9xx_pfit_disable(intel_crtc);
373047dc10d7SGordon Ross
373147dc10d7SGordon Ross for_each_encoder_on_crtc(dev, crtc, encoder)
373247dc10d7SGordon Ross if (encoder->post_disable)
373347dc10d7SGordon Ross encoder->post_disable(encoder);
373447dc10d7SGordon Ross
373547dc10d7SGordon Ross intel_disable_pll(dev_priv, pipe);
373647dc10d7SGordon Ross
373747dc10d7SGordon Ross intel_crtc->active = false;
373847dc10d7SGordon Ross intel_update_fbc(dev);
373947dc10d7SGordon Ross intel_update_watermarks(dev);
374047dc10d7SGordon Ross }
374147dc10d7SGordon Ross
i9xx_crtc_off(struct drm_crtc * crtc)374247dc10d7SGordon Ross static void i9xx_crtc_off(struct drm_crtc *crtc)
374347dc10d7SGordon Ross {
374447dc10d7SGordon Ross }
374547dc10d7SGordon Ross
intel_crtc_update_sarea(struct drm_crtc * crtc,bool enabled)374647dc10d7SGordon Ross static void intel_crtc_update_sarea(struct drm_crtc *crtc,
374747dc10d7SGordon Ross bool enabled)
374847dc10d7SGordon Ross {
374947dc10d7SGordon Ross struct drm_device *dev = crtc->dev;
375047dc10d7SGordon Ross struct drm_i915_master_private *master_priv;
375147dc10d7SGordon Ross struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
375247dc10d7SGordon Ross int pipe = intel_crtc->pipe;
375347dc10d7SGordon Ross
375447dc10d7SGordon Ross if (!dev->primary->master)
375547dc10d7SGordon Ross return;
375647dc10d7SGordon Ross
375747dc10d7SGordon Ross master_priv = dev->primary->master->driver_priv;
375847dc10d7SGordon Ross if (!master_priv->sarea_priv)
375947dc10d7SGordon Ross return;
376047dc10d7SGordon Ross
376147dc10d7SGordon Ross switch (pipe) {
376247dc10d7SGordon Ross case 0:
376347dc10d7SGordon Ross master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
376447dc10d7SGordon Ross master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
376547dc10d7SGordon Ross break;
376647dc10d7SGordon Ross case 1:
376747dc10d7SGordon Ross master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
376847dc10d7SGordon Ross master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
376947dc10d7SGordon Ross break;
377047dc10d7SGordon Ross default:
377147dc10d7SGordon Ross DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
377247dc10d7SGordon Ross break;
377347dc10d7SGordon Ross }
377447dc10d7SGordon Ross }
377547dc10d7SGordon Ross
377647dc10d7SGordon Ross /**
377747dc10d7SGordon Ross * Sets the power management mode of the pipe and plane.
377847dc10d7SGordon Ross */
intel_crtc_update_dpms(struct drm_crtc * crtc)377947dc10d7SGordon Ross void intel_crtc_update_dpms(struct drm_crtc *crtc)
378047dc10d7SGordon Ross {
378147dc10d7SGordon Ross struct drm_device *dev = crtc->dev;
378247dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
378347dc10d7SGordon Ross struct intel_encoder *intel_encoder;
378447dc10d7SGordon Ross bool enable = false;
378547dc10d7SGordon Ross
378647dc10d7SGordon Ross for_each_encoder_on_crtc(dev, crtc, intel_encoder)
378747dc10d7SGordon Ross enable |= intel_encoder->connectors_active;
378847dc10d7SGordon Ross
378947dc10d7SGordon Ross if (enable)
379047dc10d7SGordon Ross dev_priv->display.crtc_enable(crtc);
379147dc10d7SGordon Ross else
379247dc10d7SGordon Ross dev_priv->display.crtc_disable(crtc);
379347dc10d7SGordon Ross
379447dc10d7SGordon Ross intel_crtc_update_sarea(crtc, enable);
379547dc10d7SGordon Ross }
379647dc10d7SGordon Ross
intel_crtc_disable(struct drm_crtc * crtc)379747dc10d7SGordon Ross static void intel_crtc_disable(struct drm_crtc *crtc)
379847dc10d7SGordon Ross {
379947dc10d7SGordon Ross struct drm_device *dev = crtc->dev;
380047dc10d7SGordon Ross struct drm_connector *connector;
380147dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
380247dc10d7SGordon Ross struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
380347dc10d7SGordon Ross
380447dc10d7SGordon Ross /* crtc should still be enabled when we disable it. */
380547dc10d7SGordon Ross WARN_ON(!crtc->enabled);
380647dc10d7SGordon Ross
380747dc10d7SGordon Ross dev_priv->display.crtc_disable(crtc);
380847dc10d7SGordon Ross intel_crtc->eld_vld = false;
380947dc10d7SGordon Ross intel_crtc_update_sarea(crtc, false);
381047dc10d7SGordon Ross dev_priv->display.off(crtc);
381147dc10d7SGordon Ross
381247dc10d7SGordon Ross assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
381347dc10d7SGordon Ross assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
381447dc10d7SGordon Ross
381547dc10d7SGordon Ross if (crtc->fb) {
381647dc10d7SGordon Ross mutex_lock(&dev->struct_mutex);
381747dc10d7SGordon Ross intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
381847dc10d7SGordon Ross mutex_unlock(&dev->struct_mutex);
381947dc10d7SGordon Ross crtc->fb = NULL;
382047dc10d7SGordon Ross }
382147dc10d7SGordon Ross
382247dc10d7SGordon Ross /* Update computed state. */
382347dc10d7SGordon Ross list_for_each_entry(connector, struct drm_connector, &dev->mode_config.connector_list, head) {
382447dc10d7SGordon Ross if (!connector->encoder || !connector->encoder->crtc)
382547dc10d7SGordon Ross continue;
382647dc10d7SGordon Ross
382747dc10d7SGordon Ross if (connector->encoder->crtc != crtc)
382847dc10d7SGordon Ross continue;
382947dc10d7SGordon Ross
383047dc10d7SGordon Ross connector->dpms = DRM_MODE_DPMS_OFF;
383147dc10d7SGordon Ross to_intel_encoder(connector->encoder)->connectors_active = false;
383247dc10d7SGordon Ross }
383347dc10d7SGordon Ross }
383447dc10d7SGordon Ross
intel_modeset_disable(struct drm_device * dev)383547dc10d7SGordon Ross void intel_modeset_disable(struct drm_device *dev)
383647dc10d7SGordon Ross {
383747dc10d7SGordon Ross struct drm_crtc *crtc;
383847dc10d7SGordon Ross
383947dc10d7SGordon Ross list_for_each_entry(crtc, struct drm_crtc, &dev->mode_config.crtc_list, head) {
384047dc10d7SGordon Ross if (crtc->enabled)
384147dc10d7SGordon Ross intel_crtc_disable(crtc);
384247dc10d7SGordon Ross }
384347dc10d7SGordon Ross }
384447dc10d7SGordon Ross
intel_encoder_destroy(struct drm_encoder * encoder)384547dc10d7SGordon Ross void intel_encoder_destroy(struct drm_encoder *encoder)
384647dc10d7SGordon Ross {
384747dc10d7SGordon Ross struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
384847dc10d7SGordon Ross
384947dc10d7SGordon Ross drm_encoder_cleanup(encoder);
385047dc10d7SGordon Ross kfree(intel_encoder, intel_encoder->type_size);
385147dc10d7SGordon Ross }
385247dc10d7SGordon Ross
385347dc10d7SGordon Ross /* Simple dpms helper for encodres with just one connector, no cloning and only
385447dc10d7SGordon Ross * one kind of off state. It clamps all !ON modes to fully OFF and changes the
385547dc10d7SGordon Ross * state of the entire output pipe. */
intel_encoder_dpms(struct intel_encoder * encoder,int mode)385647dc10d7SGordon Ross void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
385747dc10d7SGordon Ross {
385847dc10d7SGordon Ross if (mode == DRM_MODE_DPMS_ON) {
385947dc10d7SGordon Ross encoder->connectors_active = true;
386047dc10d7SGordon Ross
386147dc10d7SGordon Ross intel_crtc_update_dpms(encoder->base.crtc);
386247dc10d7SGordon Ross } else {
386347dc10d7SGordon Ross encoder->connectors_active = false;
386447dc10d7SGordon Ross
386547dc10d7SGordon Ross intel_crtc_update_dpms(encoder->base.crtc);
386647dc10d7SGordon Ross }
386747dc10d7SGordon Ross }
386847dc10d7SGordon Ross
386947dc10d7SGordon Ross /* Cross check the actual hw state with our own modeset state tracking (and it's
387047dc10d7SGordon Ross * internal consistency). */
intel_connector_check_state(struct intel_connector * connector)387147dc10d7SGordon Ross static void intel_connector_check_state(struct intel_connector *connector)
387247dc10d7SGordon Ross {
387347dc10d7SGordon Ross if (connector->get_hw_state(connector)) {
387447dc10d7SGordon Ross struct intel_encoder *encoder = connector->encoder;
387547dc10d7SGordon Ross struct drm_crtc *crtc;
387647dc10d7SGordon Ross bool encoder_enabled;
387747dc10d7SGordon Ross enum pipe pipe;
387847dc10d7SGordon Ross
387947dc10d7SGordon Ross DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
388047dc10d7SGordon Ross connector->base.base.id,
388147dc10d7SGordon Ross drm_get_connector_name(&connector->base));
388247dc10d7SGordon Ross
388347dc10d7SGordon Ross if (connector->base.dpms == DRM_MODE_DPMS_OFF)
388447dc10d7SGordon Ross DRM_ERROR("wrong connector dpms state\n");
388547dc10d7SGordon Ross if (connector->base.encoder != &encoder->base)
388647dc10d7SGordon Ross DRM_ERROR("active connector not linked to encoder\n");
388747dc10d7SGordon Ross if (!encoder->connectors_active)
388847dc10d7SGordon Ross DRM_ERROR("encoder->connectors_active not set\n");
388947dc10d7SGordon Ross
389047dc10d7SGordon Ross encoder_enabled = encoder->get_hw_state(encoder, &pipe);
389147dc10d7SGordon Ross if (!encoder_enabled)
389247dc10d7SGordon Ross DRM_ERROR("encoder not enabled\n");
389347dc10d7SGordon Ross if (!encoder->base.crtc) {
389447dc10d7SGordon Ross DRM_ERROR("crtc is NULL");
389547dc10d7SGordon Ross return;
389647dc10d7SGordon Ross }
389747dc10d7SGordon Ross
389847dc10d7SGordon Ross crtc = encoder->base.crtc;
389947dc10d7SGordon Ross
390047dc10d7SGordon Ross if (!crtc->enabled)
390147dc10d7SGordon Ross DRM_ERROR("crtc not enabled\n");
390247dc10d7SGordon Ross if (!to_intel_crtc(crtc)->active)
390347dc10d7SGordon Ross DRM_ERROR("crtc not active\n");
390447dc10d7SGordon Ross if (pipe != to_intel_crtc(crtc)->pipe)
390547dc10d7SGordon Ross DRM_ERROR("encoder active on the wrong pipe\n");
390647dc10d7SGordon Ross }
390747dc10d7SGordon Ross }
390847dc10d7SGordon Ross
390947dc10d7SGordon Ross /* Even simpler default implementation, if there's really no special case to
391047dc10d7SGordon Ross * consider. */
intel_connector_dpms(struct drm_connector * connector,int mode)391147dc10d7SGordon Ross void intel_connector_dpms(struct drm_connector *connector, int mode)
391247dc10d7SGordon Ross {
391347dc10d7SGordon Ross struct intel_encoder *encoder = intel_attached_encoder(connector);
391447dc10d7SGordon Ross
391547dc10d7SGordon Ross /* All the simple cases only support two dpms states. */
391647dc10d7SGordon Ross if (mode != DRM_MODE_DPMS_ON)
391747dc10d7SGordon Ross mode = DRM_MODE_DPMS_OFF;
391847dc10d7SGordon Ross
391947dc10d7SGordon Ross if (mode == connector->dpms)
392047dc10d7SGordon Ross return;
392147dc10d7SGordon Ross
392247dc10d7SGordon Ross connector->dpms = mode;
392347dc10d7SGordon Ross
392447dc10d7SGordon Ross /* Only need to change hw state when actually enabled */
392547dc10d7SGordon Ross if (encoder->base.crtc)
392647dc10d7SGordon Ross intel_encoder_dpms(encoder, mode);
392747dc10d7SGordon Ross /* LINTED */
392847dc10d7SGordon Ross else
392947dc10d7SGordon Ross WARN_ON(encoder->connectors_active != false);
393047dc10d7SGordon Ross
393147dc10d7SGordon Ross intel_modeset_check_state(connector->dev);
393247dc10d7SGordon Ross }
393347dc10d7SGordon Ross
393447dc10d7SGordon Ross /* Simple connector->get_hw_state implementation for encoders that support only
393547dc10d7SGordon Ross * one connector and no cloning and hence the encoder state determines the state
393647dc10d7SGordon Ross * of the connector. */
intel_connector_get_hw_state(struct intel_connector * connector)393747dc10d7SGordon Ross bool intel_connector_get_hw_state(struct intel_connector *connector)
393847dc10d7SGordon Ross {
393947dc10d7SGordon Ross enum pipe pipe = 0;
394047dc10d7SGordon Ross struct intel_encoder *encoder = connector->encoder;
394147dc10d7SGordon Ross
394247dc10d7SGordon Ross return encoder->get_hw_state(encoder, &pipe);
394347dc10d7SGordon Ross }
394447dc10d7SGordon Ross
ironlake_check_fdi_lanes(struct drm_device * dev,enum pipe pipe,struct intel_crtc_config * pipe_config)394547dc10d7SGordon Ross static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
394647dc10d7SGordon Ross struct intel_crtc_config *pipe_config)
394747dc10d7SGordon Ross {
394847dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
394947dc10d7SGordon Ross struct intel_crtc *pipe_B_crtc =
395047dc10d7SGordon Ross to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
395147dc10d7SGordon Ross
395247dc10d7SGordon Ross DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
395347dc10d7SGordon Ross pipe_name(pipe), pipe_config->fdi_lanes);
395447dc10d7SGordon Ross if (pipe_config->fdi_lanes > 4) {
395547dc10d7SGordon Ross DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
395647dc10d7SGordon Ross pipe_name(pipe), pipe_config->fdi_lanes);
395747dc10d7SGordon Ross return false;
395847dc10d7SGordon Ross }
395947dc10d7SGordon Ross
396047dc10d7SGordon Ross if (IS_HASWELL(dev)) {
396147dc10d7SGordon Ross if (pipe_config->fdi_lanes > 2) {
396247dc10d7SGordon Ross DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
396347dc10d7SGordon Ross pipe_config->fdi_lanes);
396447dc10d7SGordon Ross return false;
396547dc10d7SGordon Ross } else {
396647dc10d7SGordon Ross return true;
396747dc10d7SGordon Ross }
396847dc10d7SGordon Ross }
396947dc10d7SGordon Ross
397047dc10d7SGordon Ross if (INTEL_INFO(dev)->num_pipes == 2)
397147dc10d7SGordon Ross return true;
397247dc10d7SGordon Ross
397347dc10d7SGordon Ross /* Ivybridge 3 pipe is really complicated */
397447dc10d7SGordon Ross switch (pipe) {
397547dc10d7SGordon Ross case PIPE_A:
397647dc10d7SGordon Ross return true;
397747dc10d7SGordon Ross case PIPE_B:
397847dc10d7SGordon Ross if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
397947dc10d7SGordon Ross pipe_config->fdi_lanes > 2) {
398047dc10d7SGordon Ross DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
398147dc10d7SGordon Ross pipe_name(pipe), pipe_config->fdi_lanes);
398247dc10d7SGordon Ross return false;
398347dc10d7SGordon Ross }
398447dc10d7SGordon Ross return true;
398547dc10d7SGordon Ross case PIPE_C:
398647dc10d7SGordon Ross if (!pipe_has_enabled_pch(pipe_B_crtc) ||
398747dc10d7SGordon Ross pipe_B_crtc->config.fdi_lanes <= 2) {
398847dc10d7SGordon Ross if (pipe_config->fdi_lanes > 2) {
398947dc10d7SGordon Ross DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
399047dc10d7SGordon Ross pipe_name(pipe), pipe_config->fdi_lanes);
399147dc10d7SGordon Ross return false;
399247dc10d7SGordon Ross }
399347dc10d7SGordon Ross } else {
399447dc10d7SGordon Ross DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
399547dc10d7SGordon Ross return false;
399647dc10d7SGordon Ross }
399747dc10d7SGordon Ross return true;
399847dc10d7SGordon Ross default:
399947dc10d7SGordon Ross BUG();
400047dc10d7SGordon Ross }
400147dc10d7SGordon Ross return false;
400247dc10d7SGordon Ross }
400347dc10d7SGordon Ross
400447dc10d7SGordon Ross int i915_lane_workaround = 0;
400547dc10d7SGordon Ross int i915_default_lanes = 4;
400647dc10d7SGordon Ross
400747dc10d7SGordon Ross #define RETRY 1
ironlake_fdi_compute_config(struct intel_crtc * intel_crtc,struct intel_crtc_config * pipe_config)400847dc10d7SGordon Ross static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
400947dc10d7SGordon Ross struct intel_crtc_config *pipe_config)
401047dc10d7SGordon Ross {
401147dc10d7SGordon Ross struct drm_device *dev = intel_crtc->base.dev;
401247dc10d7SGordon Ross struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
401347dc10d7SGordon Ross int lane, link_bw, fdi_dotclock;
401447dc10d7SGordon Ross bool setup_ok, needs_recompute = false;
401547dc10d7SGordon Ross
401647dc10d7SGordon Ross retry:
401747dc10d7SGordon Ross /* FDI is a binary signal running at ~2.7GHz, encoding
401847dc10d7SGordon Ross * each output octet as 10 bits. The actual frequency
401947dc10d7SGordon Ross * is stored as a divider into a 100MHz clock, and the
402047dc10d7SGordon Ross * mode pixel clock is stored in units of 1KHz.
402147dc10d7SGordon Ross * Hence the bw of each lane in terms of the mode signal
402247dc10d7SGordon Ross * is:
402347dc10d7SGordon Ross */
402447dc10d7SGordon Ross link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
402547dc10d7SGordon Ross
402647dc10d7SGordon Ross fdi_dotclock = adjusted_mode->clock;
402747dc10d7SGordon Ross fdi_dotclock /= pipe_config->pixel_multiplier;
402847dc10d7SGordon Ross
402947dc10d7SGordon Ross if (i915_lane_workaround)
403047dc10d7SGordon Ross lane = i915_default_lanes;
403147dc10d7SGordon Ross else
403247dc10d7SGordon Ross lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
403347dc10d7SGordon Ross pipe_config->pipe_bpp);
403447dc10d7SGordon Ross
403547dc10d7SGordon Ross pipe_config->fdi_lanes = lane;
403647dc10d7SGordon Ross
403747dc10d7SGordon Ross intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
403847dc10d7SGordon Ross link_bw, &pipe_config->fdi_m_n);
403947dc10d7SGordon Ross
404047dc10d7SGordon Ross setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
404147dc10d7SGordon Ross intel_crtc->pipe, pipe_config);
404247dc10d7SGordon Ross if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
404347dc10d7SGordon Ross pipe_config->pipe_bpp -= 2*3;
404447dc10d7SGordon Ross DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
404547dc10d7SGordon Ross pipe_config->pipe_bpp);
404647dc10d7SGordon Ross needs_recompute = true;
404747dc10d7SGordon Ross pipe_config->bw_constrained = true;
404847dc10d7SGordon Ross
404947dc10d7SGordon Ross goto retry;
405047dc10d7SGordon Ross }
405147dc10d7SGordon Ross
405247dc10d7SGordon Ross if (needs_recompute)
405347dc10d7SGordon Ross return RETRY;
405447dc10d7SGordon Ross
405547dc10d7SGordon Ross return setup_ok ? 0 : -EINVAL;
405647dc10d7SGordon Ross }
405747dc10d7SGordon Ross
hsw_compute_ips_config(struct intel_crtc * crtc,struct intel_crtc_config * pipe_config)405847dc10d7SGordon Ross static void hsw_compute_ips_config(struct intel_crtc *crtc,
405947dc10d7SGordon Ross struct intel_crtc_config *pipe_config)
406047dc10d7SGordon Ross {
406147dc10d7SGordon Ross pipe_config->ips_enabled = i915_enable_ips &&
406247dc10d7SGordon Ross hsw_crtc_supports_ips(crtc) &&
406347dc10d7SGordon Ross pipe_config->pipe_bpp == 24;
406447dc10d7SGordon Ross }
406547dc10d7SGordon Ross
intel_crtc_compute_config(struct intel_crtc * crtc,struct intel_crtc_config * pipe_config)406647dc10d7SGordon Ross static int intel_crtc_compute_config(struct intel_crtc *crtc,
406747dc10d7SGordon Ross struct intel_crtc_config *pipe_config)
406847dc10d7SGordon Ross {
406947dc10d7SGordon Ross struct drm_device *dev = crtc->base.dev;
407047dc10d7SGordon Ross struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
407147dc10d7SGordon Ross
407247dc10d7SGordon Ross if (HAS_PCH_SPLIT(dev)) {
407347dc10d7SGordon Ross /* FDI link clock is fixed at 2.7G */
407447dc10d7SGordon Ross if (pipe_config->requested_mode.clock * 3
407547dc10d7SGordon Ross > IRONLAKE_FDI_FREQ * 4)
407647dc10d7SGordon Ross return -EINVAL;
407747dc10d7SGordon Ross }
407847dc10d7SGordon Ross
407947dc10d7SGordon Ross /* All interlaced capable intel hw wants timings in frames. Note though
408047dc10d7SGordon Ross * that intel_lvds_mode_fixup does some funny tricks with the crtc
408147dc10d7SGordon Ross * timings, so we need to be careful not to clobber these.*/
408247dc10d7SGordon Ross if (!pipe_config->timings_set)
408347dc10d7SGordon Ross drm_mode_set_crtcinfo(adjusted_mode, 0);
408447dc10d7SGordon Ross
408547dc10d7SGordon Ross /* Cantiga+ cannot handle modes with a hsync front porch of 0.
408647dc10d7SGordon Ross * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
408747dc10d7SGordon Ross */
408847dc10d7SGordon Ross if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
408947dc10d7SGordon Ross adjusted_mode->hsync_start == adjusted_mode->hdisplay)
409047dc10d7SGordon Ross return -EINVAL;
409147dc10d7SGordon Ross
409247dc10d7SGordon Ross if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
409347dc10d7SGordon Ross pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
409447dc10d7SGordon Ross } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
409547dc10d7SGordon Ross /* only a 8bpc pipe, with 6bpc dither through the panel fitter
409647dc10d7SGordon Ross * for lvds. */
409747dc10d7SGordon Ross pipe_config->pipe_bpp = 8*3;
409847dc10d7SGordon Ross }
409947dc10d7SGordon Ross
410047dc10d7SGordon Ross if (HAS_IPS(dev))
410147dc10d7SGordon Ross hsw_compute_ips_config(crtc, pipe_config);
410247dc10d7SGordon Ross
410347dc10d7SGordon Ross /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
410447dc10d7SGordon Ross * clock survives for now. */
410547dc10d7SGordon Ross if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
410647dc10d7SGordon Ross pipe_config->shared_dpll = crtc->config.shared_dpll;
410747dc10d7SGordon Ross
410847dc10d7SGordon Ross if (pipe_config->has_pch_encoder)
410947dc10d7SGordon Ross return ironlake_fdi_compute_config(crtc, pipe_config);
411047dc10d7SGordon Ross
411147dc10d7SGordon Ross return 0;
411247dc10d7SGordon Ross }
411347dc10d7SGordon Ross
valleyview_get_display_clock_speed(struct drm_device * dev)411447dc10d7SGordon Ross static int valleyview_get_display_clock_speed(struct drm_device *dev)
411547dc10d7SGordon Ross {
411647dc10d7SGordon Ross return 400000; /* FIXME */
411747dc10d7SGordon Ross }
411847dc10d7SGordon Ross
411947dc10d7SGordon Ross /* LINTED */
i945_get_display_clock_speed(struct drm_device * dev)412047dc10d7SGordon Ross static int i945_get_display_clock_speed(struct drm_device *dev)
412147dc10d7SGordon Ross {
412247dc10d7SGordon Ross return 400000;
412347dc10d7SGordon Ross }
412447dc10d7SGordon Ross
412547dc10d7SGordon Ross /* LINTED */
i915_get_display_clock_speed(struct drm_device * dev)412647dc10d7SGordon Ross static int i915_get_display_clock_speed(struct drm_device *dev)
412747dc10d7SGordon Ross {
412847dc10d7SGordon Ross return 333000;
412947dc10d7SGordon Ross }
413047dc10d7SGordon Ross
413147dc10d7SGordon Ross /* LINTED */
i9xx_misc_get_display_clock_speed(struct drm_device * dev)413247dc10d7SGordon Ross static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
413347dc10d7SGordon Ross {
413447dc10d7SGordon Ross return 200000;
413547dc10d7SGordon Ross }
413647dc10d7SGordon Ross
i915gm_get_display_clock_speed(struct drm_device * dev)413747dc10d7SGordon Ross static int i915gm_get_display_clock_speed(struct drm_device *dev)
413847dc10d7SGordon Ross {
413947dc10d7SGordon Ross u16 gcfgc = 0;
414047dc10d7SGordon Ross
414147dc10d7SGordon Ross (void) pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
414247dc10d7SGordon Ross
414347dc10d7SGordon Ross if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
414447dc10d7SGordon Ross return 133000;
414547dc10d7SGordon Ross else {
414647dc10d7SGordon Ross switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
414747dc10d7SGordon Ross case GC_DISPLAY_CLOCK_333_MHZ:
414847dc10d7SGordon Ross return 333000;
414947dc10d7SGordon Ross default:
415047dc10d7SGordon Ross case GC_DISPLAY_CLOCK_190_200_MHZ:
415147dc10d7SGordon Ross return 190000;
415247dc10d7SGordon Ross }
415347dc10d7SGordon Ross }
415447dc10d7SGordon Ross }
415547dc10d7SGordon Ross
415647dc10d7SGordon Ross /* LINTED */
i865_get_display_clock_speed(struct drm_device * dev)415747dc10d7SGordon Ross static int i865_get_display_clock_speed(struct drm_device *dev)
415847dc10d7SGordon Ross {
415947dc10d7SGordon Ross return 266000;
416047dc10d7SGordon Ross }
416147dc10d7SGordon Ross
416247dc10d7SGordon Ross /* LINTED */
i855_get_display_clock_speed(struct drm_device * dev)416347dc10d7SGordon Ross static int i855_get_display_clock_speed(struct drm_device *dev)
416447dc10d7SGordon Ross {
416547dc10d7SGordon Ross u16 hpllcc = 0;
416647dc10d7SGordon Ross /* Assume that the hardware is in the high speed state. This
416747dc10d7SGordon Ross * should be the default.
416847dc10d7SGordon Ross */
416947dc10d7SGordon Ross switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
417047dc10d7SGordon Ross case GC_CLOCK_133_200:
417147dc10d7SGordon Ross case GC_CLOCK_100_200:
417247dc10d7SGordon Ross return 200000;
417347dc10d7SGordon Ross case GC_CLOCK_166_250:
417447dc10d7SGordon Ross return 250000;
417547dc10d7SGordon Ross case GC_CLOCK_100_133:
417647dc10d7SGordon Ross return 133000;
417747dc10d7SGordon Ross }
417847dc10d7SGordon Ross
417947dc10d7SGordon Ross /* Shouldn't happen */
418047dc10d7SGordon Ross return 0;
418147dc10d7SGordon Ross }
418247dc10d7SGordon Ross
418347dc10d7SGordon Ross /* LINTED */
i830_get_display_clock_speed(struct drm_device * dev)418447dc10d7SGordon Ross static int i830_get_display_clock_speed(struct drm_device *dev)
418547dc10d7SGordon Ross {
418647dc10d7SGordon Ross return 133000;
418747dc10d7SGordon Ross }
418847dc10d7SGordon Ross
418947dc10d7SGordon Ross static void
intel_reduce_m_n_ratio(uint32_t * num,uint32_t * den)419047dc10d7SGordon Ross intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
419147dc10d7SGordon Ross {
419247dc10d7SGordon Ross while (*num > DATA_LINK_M_N_MASK ||
419347dc10d7SGordon Ross *den > DATA_LINK_M_N_MASK) {
419447dc10d7SGordon Ross *num >>= 1;
419547dc10d7SGordon Ross *den >>= 1;
419647dc10d7SGordon Ross }
419747dc10d7SGordon Ross }
419847dc10d7SGordon Ross
419947dc10d7SGordon Ross static unsigned int
roundup_pow_of_two(unsigned int n)420047dc10d7SGordon Ross roundup_pow_of_two(unsigned int n)
420147dc10d7SGordon Ross {
420247dc10d7SGordon Ross unsigned int ret_val = 0;
420347dc10d7SGordon Ross unsigned int temp = n;
420447dc10d7SGordon Ross
420547dc10d7SGordon Ross if (n == 0)
420647dc10d7SGordon Ross return 0;
420747dc10d7SGordon Ross
420847dc10d7SGordon Ross while (temp != 1) {
420947dc10d7SGordon Ross ret_val++;
421047dc10d7SGordon Ross temp = temp >> 1;
421147dc10d7SGordon Ross }
421247dc10d7SGordon Ross
421347dc10d7SGordon Ross if ((1 << ret_val) ^ n)
421447dc10d7SGordon Ross ret_val++;
421547dc10d7SGordon Ross
421647dc10d7SGordon Ross return (1 << ret_val);
421747dc10d7SGordon Ross }
421847dc10d7SGordon Ross
compute_m_n(unsigned int m,unsigned int n,uint32_t * ret_m,uint32_t * ret_n)421947dc10d7SGordon Ross static void compute_m_n(unsigned int m, unsigned int n,
422047dc10d7SGordon Ross uint32_t *ret_m, uint32_t *ret_n)
422147dc10d7SGordon Ross {
422247dc10d7SGordon Ross *ret_n = min(roundup_pow_of_two(n), DATA_LINK_N_MAX);
422347dc10d7SGordon Ross *ret_m = div_u64((uint64_t) m * *ret_n, n);
422447dc10d7SGordon Ross intel_reduce_m_n_ratio(ret_m, ret_n);
422547dc10d7SGordon Ross }
422647dc10d7SGordon Ross
422747dc10d7SGordon Ross void
intel_link_compute_m_n(int bits_per_pixel,int nlanes,int pixel_clock,int link_clock,struct intel_link_m_n * m_n)422847dc10d7SGordon Ross intel_link_compute_m_n(int bits_per_pixel, int nlanes,
422947dc10d7SGordon Ross int pixel_clock, int link_clock,
423047dc10d7SGordon Ross struct intel_link_m_n *m_n)
423147dc10d7SGordon Ross {
423247dc10d7SGordon Ross m_n->tu = 64;
423347dc10d7SGordon Ross compute_m_n(bits_per_pixel * pixel_clock,
423447dc10d7SGordon Ross link_clock * nlanes * 8,
423547dc10d7SGordon Ross &m_n->gmch_m, &m_n->gmch_n);
423647dc10d7SGordon Ross
423747dc10d7SGordon Ross compute_m_n(pixel_clock, link_clock,
423847dc10d7SGordon Ross &m_n->link_m, &m_n->link_n);
423947dc10d7SGordon Ross }
424047dc10d7SGordon Ross
intel_panel_use_ssc(struct drm_i915_private * dev_priv)424147dc10d7SGordon Ross static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
424247dc10d7SGordon Ross {
424347dc10d7SGordon Ross if (i915_panel_use_ssc >= 0)
424447dc10d7SGordon Ross return i915_panel_use_ssc != 0;
424547dc10d7SGordon Ross return dev_priv->vbt.lvds_use_ssc
424647dc10d7SGordon Ross && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
424747dc10d7SGordon Ross }
424847dc10d7SGordon Ross
424947dc10d7SGordon Ross /* LINTED */
vlv_get_refclk(struct drm_crtc * crtc)425047dc10d7SGordon Ross static int vlv_get_refclk(struct drm_crtc *crtc)
425147dc10d7SGordon Ross {
425247dc10d7SGordon Ross #if 0
425347dc10d7SGordon Ross struct drm_device *dev = crtc->dev;
425447dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
425547dc10d7SGordon Ross int refclk = 27000; /* for DP & HDMI */
425647dc10d7SGordon Ross #endif
425747dc10d7SGordon Ross return 100000; /* only one validated so far */
425847dc10d7SGordon Ross /*
425947dc10d7SGordon Ross if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
426047dc10d7SGordon Ross refclk = 96000;
426147dc10d7SGordon Ross } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
426247dc10d7SGordon Ross if (intel_panel_use_ssc(dev_priv))
426347dc10d7SGordon Ross refclk = 100000;
426447dc10d7SGordon Ross else
426547dc10d7SGordon Ross refclk = 96000;
426647dc10d7SGordon Ross } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
426747dc10d7SGordon Ross refclk = 100000;
426847dc10d7SGordon Ross }
426947dc10d7SGordon Ross return refclk;
427047dc10d7SGordon Ross */
427147dc10d7SGordon Ross }
427247dc10d7SGordon Ross
i9xx_get_refclk(struct drm_crtc * crtc,int num_connectors)427347dc10d7SGordon Ross static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
427447dc10d7SGordon Ross {
427547dc10d7SGordon Ross struct drm_device *dev = crtc->dev;
427647dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
427747dc10d7SGordon Ross int refclk;
427847dc10d7SGordon Ross
427947dc10d7SGordon Ross if (IS_VALLEYVIEW(dev)) {
428047dc10d7SGordon Ross refclk = vlv_get_refclk(crtc);
428147dc10d7SGordon Ross } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
428247dc10d7SGordon Ross intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
428347dc10d7SGordon Ross refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
428447dc10d7SGordon Ross DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
428547dc10d7SGordon Ross refclk / 1000);
428647dc10d7SGordon Ross } else if (!IS_GEN2(dev)) {
428747dc10d7SGordon Ross refclk = 96000;
428847dc10d7SGordon Ross } else {
428947dc10d7SGordon Ross refclk = 48000;
429047dc10d7SGordon Ross }
429147dc10d7SGordon Ross
429247dc10d7SGordon Ross return refclk;
429347dc10d7SGordon Ross }
429447dc10d7SGordon Ross
pnv_dpll_compute_fp(struct dpll * dpll)429547dc10d7SGordon Ross static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
429647dc10d7SGordon Ross {
429747dc10d7SGordon Ross return (1 << dpll->n) << 16 | dpll->m2;
429847dc10d7SGordon Ross }
429947dc10d7SGordon Ross
i9xx_dpll_compute_fp(struct dpll * dpll)430047dc10d7SGordon Ross static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
430147dc10d7SGordon Ross {
430247dc10d7SGordon Ross return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
430347dc10d7SGordon Ross }
430447dc10d7SGordon Ross
i9xx_update_pll_dividers(struct intel_crtc * crtc,intel_clock_t * reduced_clock)430547dc10d7SGordon Ross static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
430647dc10d7SGordon Ross intel_clock_t *reduced_clock)
430747dc10d7SGordon Ross {
430847dc10d7SGordon Ross struct drm_device *dev = crtc->base.dev;
430947dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
431047dc10d7SGordon Ross int pipe = crtc->pipe;
431147dc10d7SGordon Ross u32 fp, fp2 = 0;
431247dc10d7SGordon Ross
431347dc10d7SGordon Ross if (IS_PINEVIEW(dev)) {
431447dc10d7SGordon Ross fp = pnv_dpll_compute_fp(&crtc->config.dpll);
431547dc10d7SGordon Ross if (reduced_clock)
431647dc10d7SGordon Ross fp2 = pnv_dpll_compute_fp(reduced_clock);
431747dc10d7SGordon Ross } else {
431847dc10d7SGordon Ross fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
431947dc10d7SGordon Ross if (reduced_clock)
432047dc10d7SGordon Ross fp2 = i9xx_dpll_compute_fp(reduced_clock);
432147dc10d7SGordon Ross }
432247dc10d7SGordon Ross
432347dc10d7SGordon Ross I915_WRITE(FP0(pipe), fp);
432447dc10d7SGordon Ross
432547dc10d7SGordon Ross crtc->lowfreq_avail = false;
432647dc10d7SGordon Ross if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
432747dc10d7SGordon Ross reduced_clock && i915_powersave) {
432847dc10d7SGordon Ross I915_WRITE(FP1(pipe), fp2);
432947dc10d7SGordon Ross crtc->lowfreq_avail = true;
433047dc10d7SGordon Ross } else {
433147dc10d7SGordon Ross I915_WRITE(FP1(pipe), fp);
433247dc10d7SGordon Ross }
433347dc10d7SGordon Ross }
433447dc10d7SGordon Ross
vlv_pllb_recal_opamp(struct drm_i915_private * dev_priv)433547dc10d7SGordon Ross static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
433647dc10d7SGordon Ross {
433747dc10d7SGordon Ross u32 reg_val;
433847dc10d7SGordon Ross
433947dc10d7SGordon Ross /*
434047dc10d7SGordon Ross * PLLB opamp always calibrates to max value of 0x3f, force enable it
434147dc10d7SGordon Ross * and set it to a reasonable value instead.
434247dc10d7SGordon Ross */
434347dc10d7SGordon Ross reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
434447dc10d7SGordon Ross reg_val &= 0xffffff00;
434547dc10d7SGordon Ross reg_val |= 0x00000030;
434647dc10d7SGordon Ross vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
434747dc10d7SGordon Ross
434847dc10d7SGordon Ross reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
434947dc10d7SGordon Ross reg_val &= 0x8cffffff;
435047dc10d7SGordon Ross reg_val = 0x8c000000;
435147dc10d7SGordon Ross vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
435247dc10d7SGordon Ross
435347dc10d7SGordon Ross reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
435447dc10d7SGordon Ross reg_val &= 0xffffff00;
435547dc10d7SGordon Ross vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
435647dc10d7SGordon Ross
435747dc10d7SGordon Ross reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
435847dc10d7SGordon Ross reg_val &= 0x00ffffff;
435947dc10d7SGordon Ross reg_val |= 0xb0000000;
436047dc10d7SGordon Ross vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
436147dc10d7SGordon Ross }
436247dc10d7SGordon Ross
intel_pch_transcoder_set_m_n(struct intel_crtc * crtc,struct intel_link_m_n * m_n)436347dc10d7SGordon Ross static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
436447dc10d7SGordon Ross struct intel_link_m_n *m_n)
436547dc10d7SGordon Ross {
436647dc10d7SGordon Ross struct drm_device *dev = crtc->base.dev;
436747dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
436847dc10d7SGordon Ross int pipe = crtc->pipe;
436947dc10d7SGordon Ross
437047dc10d7SGordon Ross I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
437147dc10d7SGordon Ross I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
437247dc10d7SGordon Ross I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
437347dc10d7SGordon Ross I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
437447dc10d7SGordon Ross }
437547dc10d7SGordon Ross
intel_cpu_transcoder_set_m_n(struct intel_crtc * crtc,struct intel_link_m_n * m_n)437647dc10d7SGordon Ross static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
437747dc10d7SGordon Ross struct intel_link_m_n *m_n)
437847dc10d7SGordon Ross {
437947dc10d7SGordon Ross struct drm_device *dev = crtc->base.dev;
438047dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
438147dc10d7SGordon Ross int pipe = crtc->pipe;
438247dc10d7SGordon Ross enum transcoder transcoder = crtc->config.cpu_transcoder;
438347dc10d7SGordon Ross
438447dc10d7SGordon Ross if (INTEL_INFO(dev)->gen >= 5) {
438547dc10d7SGordon Ross I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
438647dc10d7SGordon Ross I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
438747dc10d7SGordon Ross I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
438847dc10d7SGordon Ross I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
438947dc10d7SGordon Ross } else {
439047dc10d7SGordon Ross I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
439147dc10d7SGordon Ross I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
439247dc10d7SGordon Ross I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
439347dc10d7SGordon Ross I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
439447dc10d7SGordon Ross }
439547dc10d7SGordon Ross }
439647dc10d7SGordon Ross
intel_dp_set_m_n(struct intel_crtc * crtc)439747dc10d7SGordon Ross static void intel_dp_set_m_n(struct intel_crtc *crtc)
439847dc10d7SGordon Ross {
439947dc10d7SGordon Ross if (crtc->config.has_pch_encoder)
440047dc10d7SGordon Ross intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
440147dc10d7SGordon Ross else
440247dc10d7SGordon Ross intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
440347dc10d7SGordon Ross }
440447dc10d7SGordon Ross
vlv_update_pll(struct intel_crtc * crtc)440547dc10d7SGordon Ross static void vlv_update_pll(struct intel_crtc *crtc)
440647dc10d7SGordon Ross {
440747dc10d7SGordon Ross struct drm_device *dev = crtc->base.dev;
440847dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
440947dc10d7SGordon Ross struct intel_encoder *encoder;
441047dc10d7SGordon Ross int pipe = crtc->pipe;
441147dc10d7SGordon Ross u32 dpll, mdiv;
441247dc10d7SGordon Ross u32 bestn, bestm1, bestm2, bestp1, bestp2;
441347dc10d7SGordon Ross u32 coreclk, reg_val, dpll_md;
441447dc10d7SGordon Ross
441547dc10d7SGordon Ross mutex_lock(&dev_priv->dpio_lock);
441647dc10d7SGordon Ross
441747dc10d7SGordon Ross bestn = crtc->config.dpll.n;
441847dc10d7SGordon Ross bestm1 = crtc->config.dpll.m1;
441947dc10d7SGordon Ross bestm2 = crtc->config.dpll.m2;
442047dc10d7SGordon Ross bestp1 = crtc->config.dpll.p1;
442147dc10d7SGordon Ross bestp2 = crtc->config.dpll.p2;
442247dc10d7SGordon Ross
442347dc10d7SGordon Ross /* See eDP HDMI DPIO driver vbios notes doc */
442447dc10d7SGordon Ross
442547dc10d7SGordon Ross /* PLL B needs special handling */
442647dc10d7SGordon Ross if (pipe)
442747dc10d7SGordon Ross vlv_pllb_recal_opamp(dev_priv);
442847dc10d7SGordon Ross
442947dc10d7SGordon Ross /* Set up Tx target for periodic Rcomp update */
443047dc10d7SGordon Ross vlv_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
443147dc10d7SGordon Ross
443247dc10d7SGordon Ross /* Disable target IRef on PLL */
443347dc10d7SGordon Ross reg_val = vlv_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
443447dc10d7SGordon Ross reg_val &= 0x00ffffff;
443547dc10d7SGordon Ross vlv_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
443647dc10d7SGordon Ross
443747dc10d7SGordon Ross /* Disable fast lock */
443847dc10d7SGordon Ross vlv_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
443947dc10d7SGordon Ross
444047dc10d7SGordon Ross /* Set idtafcrecal before PLL is enabled */
444147dc10d7SGordon Ross mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
444247dc10d7SGordon Ross mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
444347dc10d7SGordon Ross mdiv |= ((bestn << DPIO_N_SHIFT));
444447dc10d7SGordon Ross mdiv |= (1 << DPIO_K_SHIFT);
444547dc10d7SGordon Ross
444647dc10d7SGordon Ross /*
444747dc10d7SGordon Ross * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
444847dc10d7SGordon Ross * but we don't support that).
444947dc10d7SGordon Ross * Note: don't use the DAC post divider as it seems unstable.
445047dc10d7SGordon Ross */
445147dc10d7SGordon Ross mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
445247dc10d7SGordon Ross vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
445347dc10d7SGordon Ross
445447dc10d7SGordon Ross mdiv |= DPIO_ENABLE_CALIBRATION;
445547dc10d7SGordon Ross vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
445647dc10d7SGordon Ross
445747dc10d7SGordon Ross /* Set HBR and RBR LPF coefficients */
445847dc10d7SGordon Ross if (crtc->config.port_clock == 162000 ||
445947dc10d7SGordon Ross intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
446047dc10d7SGordon Ross intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
446147dc10d7SGordon Ross vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
446247dc10d7SGordon Ross 0x005f0021);
446347dc10d7SGordon Ross else
446447dc10d7SGordon Ross vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
446547dc10d7SGordon Ross 0x00d0000f);
446647dc10d7SGordon Ross
446747dc10d7SGordon Ross if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
446847dc10d7SGordon Ross intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
446947dc10d7SGordon Ross /* Use SSC source */
447047dc10d7SGordon Ross if (!pipe)
447147dc10d7SGordon Ross vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
447247dc10d7SGordon Ross 0x0df40000);
447347dc10d7SGordon Ross else
447447dc10d7SGordon Ross vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
447547dc10d7SGordon Ross 0x0df70000);
447647dc10d7SGordon Ross } else { /* HDMI or VGA */
447747dc10d7SGordon Ross /* Use bend source */
447847dc10d7SGordon Ross if (!pipe)
447947dc10d7SGordon Ross vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
448047dc10d7SGordon Ross 0x0df70000);
448147dc10d7SGordon Ross else
448247dc10d7SGordon Ross vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
448347dc10d7SGordon Ross 0x0df40000);
448447dc10d7SGordon Ross }
448547dc10d7SGordon Ross
448647dc10d7SGordon Ross coreclk = vlv_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
448747dc10d7SGordon Ross coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
448847dc10d7SGordon Ross if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
448947dc10d7SGordon Ross intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
449047dc10d7SGordon Ross coreclk |= 0x01000000;
449147dc10d7SGordon Ross vlv_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
449247dc10d7SGordon Ross
449347dc10d7SGordon Ross vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
449447dc10d7SGordon Ross
449547dc10d7SGordon Ross for_each_encoder_on_crtc(dev, &crtc->base, encoder)
449647dc10d7SGordon Ross if (encoder->pre_pll_enable)
449747dc10d7SGordon Ross encoder->pre_pll_enable(encoder);
449847dc10d7SGordon Ross
449947dc10d7SGordon Ross /* Enable DPIO clock input */
450047dc10d7SGordon Ross dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
450147dc10d7SGordon Ross DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
450247dc10d7SGordon Ross if (pipe)
450347dc10d7SGordon Ross dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
450447dc10d7SGordon Ross
450547dc10d7SGordon Ross dpll |= DPLL_VCO_ENABLE;
450647dc10d7SGordon Ross I915_WRITE(DPLL(pipe), dpll);
450747dc10d7SGordon Ross POSTING_READ(DPLL(pipe));
450847dc10d7SGordon Ross udelay(150);
450947dc10d7SGordon Ross
451047dc10d7SGordon Ross if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
451147dc10d7SGordon Ross DRM_ERROR("DPLL %d failed to lock\n", pipe);
451247dc10d7SGordon Ross
451347dc10d7SGordon Ross dpll_md = (crtc->config.pixel_multiplier - 1)
451447dc10d7SGordon Ross << DPLL_MD_UDI_MULTIPLIER_SHIFT;
451547dc10d7SGordon Ross I915_WRITE(DPLL_MD(pipe), dpll_md);
451647dc10d7SGordon Ross POSTING_READ(DPLL_MD(pipe));
451747dc10d7SGordon Ross
451847dc10d7SGordon Ross if (crtc->config.has_dp_encoder)
451947dc10d7SGordon Ross intel_dp_set_m_n(crtc);
452047dc10d7SGordon Ross
452147dc10d7SGordon Ross mutex_unlock(&dev_priv->dpio_lock);
452247dc10d7SGordon Ross }
452347dc10d7SGordon Ross
i9xx_update_pll(struct intel_crtc * crtc,intel_clock_t * reduced_clock,int num_connectors)452447dc10d7SGordon Ross static void i9xx_update_pll(struct intel_crtc *crtc,
452547dc10d7SGordon Ross intel_clock_t *reduced_clock,
452647dc10d7SGordon Ross int num_connectors)
452747dc10d7SGordon Ross {
452847dc10d7SGordon Ross struct drm_device *dev = crtc->base.dev;
452947dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
453047dc10d7SGordon Ross struct intel_encoder *encoder;
453147dc10d7SGordon Ross int pipe = crtc->pipe;
453247dc10d7SGordon Ross u32 dpll;
453347dc10d7SGordon Ross bool is_sdvo;
453447dc10d7SGordon Ross struct dpll *clock = &crtc->config.dpll;
453547dc10d7SGordon Ross
453647dc10d7SGordon Ross i9xx_update_pll_dividers(crtc, reduced_clock);
453747dc10d7SGordon Ross
453847dc10d7SGordon Ross is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
453947dc10d7SGordon Ross intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
454047dc10d7SGordon Ross
454147dc10d7SGordon Ross dpll = DPLL_VGA_MODE_DIS;
454247dc10d7SGordon Ross
454347dc10d7SGordon Ross if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
454447dc10d7SGordon Ross dpll |= DPLLB_MODE_LVDS;
454547dc10d7SGordon Ross else
454647dc10d7SGordon Ross dpll |= DPLLB_MODE_DAC_SERIAL;
454747dc10d7SGordon Ross
454847dc10d7SGordon Ross if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
454947dc10d7SGordon Ross dpll |= (crtc->config.pixel_multiplier - 1)
455047dc10d7SGordon Ross << SDVO_MULTIPLIER_SHIFT_HIRES;
455147dc10d7SGordon Ross }
455247dc10d7SGordon Ross
455347dc10d7SGordon Ross if (is_sdvo)
455447dc10d7SGordon Ross dpll |= DPLL_DVO_HIGH_SPEED;
455547dc10d7SGordon Ross
455647dc10d7SGordon Ross if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
455747dc10d7SGordon Ross dpll |= DPLL_DVO_HIGH_SPEED;
455847dc10d7SGordon Ross
455947dc10d7SGordon Ross /* compute bitmask from p1 value */
456047dc10d7SGordon Ross if (IS_PINEVIEW(dev))
456147dc10d7SGordon Ross dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
456247dc10d7SGordon Ross else {
456347dc10d7SGordon Ross dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
456447dc10d7SGordon Ross if (IS_G4X(dev) && reduced_clock)
456547dc10d7SGordon Ross dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
456647dc10d7SGordon Ross }
456747dc10d7SGordon Ross switch (clock->p2) {
456847dc10d7SGordon Ross case 5:
456947dc10d7SGordon Ross dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
457047dc10d7SGordon Ross break;
457147dc10d7SGordon Ross case 7:
457247dc10d7SGordon Ross dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
457347dc10d7SGordon Ross break;
457447dc10d7SGordon Ross case 10:
457547dc10d7SGordon Ross dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
457647dc10d7SGordon Ross break;
457747dc10d7SGordon Ross case 14:
457847dc10d7SGordon Ross dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
457947dc10d7SGordon Ross break;
458047dc10d7SGordon Ross }
458147dc10d7SGordon Ross if (INTEL_INFO(dev)->gen >= 4)
458247dc10d7SGordon Ross dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
458347dc10d7SGordon Ross
458447dc10d7SGordon Ross if (crtc->config.sdvo_tv_clock)
458547dc10d7SGordon Ross dpll |= PLL_REF_INPUT_TVCLKINBC;
458647dc10d7SGordon Ross else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
458747dc10d7SGordon Ross intel_panel_use_ssc(dev_priv) && num_connectors < 2)
458847dc10d7SGordon Ross dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
458947dc10d7SGordon Ross else
459047dc10d7SGordon Ross dpll |= PLL_REF_INPUT_DREFCLK;
459147dc10d7SGordon Ross
459247dc10d7SGordon Ross dpll |= DPLL_VCO_ENABLE;
459347dc10d7SGordon Ross I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
459447dc10d7SGordon Ross POSTING_READ(DPLL(pipe));
459547dc10d7SGordon Ross udelay(150);
459647dc10d7SGordon Ross
459747dc10d7SGordon Ross for_each_encoder_on_crtc(dev, &crtc->base, encoder)
459847dc10d7SGordon Ross if (encoder->pre_pll_enable)
459947dc10d7SGordon Ross encoder->pre_pll_enable(encoder);
460047dc10d7SGordon Ross
460147dc10d7SGordon Ross if (crtc->config.has_dp_encoder)
460247dc10d7SGordon Ross intel_dp_set_m_n(crtc);
460347dc10d7SGordon Ross
460447dc10d7SGordon Ross I915_WRITE(DPLL(pipe), dpll);
460547dc10d7SGordon Ross
460647dc10d7SGordon Ross /* Wait for the clocks to stabilize. */
460747dc10d7SGordon Ross POSTING_READ(DPLL(pipe));
460847dc10d7SGordon Ross udelay(150);
460947dc10d7SGordon Ross
461047dc10d7SGordon Ross if (INTEL_INFO(dev)->gen >= 4) {
461147dc10d7SGordon Ross u32 dpll_md = (crtc->config.pixel_multiplier - 1)
461247dc10d7SGordon Ross << DPLL_MD_UDI_MULTIPLIER_SHIFT;
461347dc10d7SGordon Ross I915_WRITE(DPLL_MD(pipe), dpll_md);
461447dc10d7SGordon Ross } else {
461547dc10d7SGordon Ross /* The pixel multiplier can only be updated once the
461647dc10d7SGordon Ross * DPLL is enabled and the clocks are stable.
461747dc10d7SGordon Ross *
461847dc10d7SGordon Ross * So write it again.
461947dc10d7SGordon Ross */
462047dc10d7SGordon Ross I915_WRITE(DPLL(pipe), dpll);
462147dc10d7SGordon Ross }
462247dc10d7SGordon Ross }
462347dc10d7SGordon Ross
i8xx_update_pll(struct intel_crtc * crtc,intel_clock_t * reduced_clock,int num_connectors)462447dc10d7SGordon Ross static void i8xx_update_pll(struct intel_crtc *crtc,
462547dc10d7SGordon Ross intel_clock_t *reduced_clock,
462647dc10d7SGordon Ross int num_connectors)
462747dc10d7SGordon Ross {
462847dc10d7SGordon Ross struct drm_device *dev = crtc->base.dev;
462947dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
463047dc10d7SGordon Ross struct intel_encoder *encoder;
463147dc10d7SGordon Ross int pipe = crtc->pipe;
463247dc10d7SGordon Ross u32 dpll;
463347dc10d7SGordon Ross struct dpll *clock = &crtc->config.dpll;
463447dc10d7SGordon Ross
463547dc10d7SGordon Ross i9xx_update_pll_dividers(crtc, reduced_clock);
463647dc10d7SGordon Ross
463747dc10d7SGordon Ross dpll = DPLL_VGA_MODE_DIS;
463847dc10d7SGordon Ross
463947dc10d7SGordon Ross if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
464047dc10d7SGordon Ross dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
464147dc10d7SGordon Ross } else {
464247dc10d7SGordon Ross if (clock->p1 == 2)
464347dc10d7SGordon Ross dpll |= PLL_P1_DIVIDE_BY_TWO;
464447dc10d7SGordon Ross else
464547dc10d7SGordon Ross dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
464647dc10d7SGordon Ross if (clock->p2 == 4)
464747dc10d7SGordon Ross dpll |= PLL_P2_DIVIDE_BY_4;
464847dc10d7SGordon Ross }
464947dc10d7SGordon Ross
465047dc10d7SGordon Ross if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
465147dc10d7SGordon Ross intel_panel_use_ssc(dev_priv) && num_connectors < 2)
465247dc10d7SGordon Ross dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
465347dc10d7SGordon Ross else
465447dc10d7SGordon Ross dpll |= PLL_REF_INPUT_DREFCLK;
465547dc10d7SGordon Ross
465647dc10d7SGordon Ross dpll |= DPLL_VCO_ENABLE;
465747dc10d7SGordon Ross I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
465847dc10d7SGordon Ross POSTING_READ(DPLL(pipe));
465947dc10d7SGordon Ross udelay(150);
466047dc10d7SGordon Ross
466147dc10d7SGordon Ross for_each_encoder_on_crtc(dev, &crtc->base, encoder)
466247dc10d7SGordon Ross if (encoder->pre_pll_enable)
466347dc10d7SGordon Ross encoder->pre_pll_enable(encoder);
466447dc10d7SGordon Ross
466547dc10d7SGordon Ross I915_WRITE(DPLL(pipe), dpll);
466647dc10d7SGordon Ross
466747dc10d7SGordon Ross /* Wait for the clocks to stabilize. */
466847dc10d7SGordon Ross POSTING_READ(DPLL(pipe));
466947dc10d7SGordon Ross udelay(150);
467047dc10d7SGordon Ross
467147dc10d7SGordon Ross /* The pixel multiplier can only be updated once the
467247dc10d7SGordon Ross * DPLL is enabled and the clocks are stable.
467347dc10d7SGordon Ross *
467447dc10d7SGordon Ross * So write it again.
467547dc10d7SGordon Ross */
467647dc10d7SGordon Ross I915_WRITE(DPLL(pipe), dpll);
467747dc10d7SGordon Ross }
467847dc10d7SGordon Ross
intel_set_pipe_timings(struct intel_crtc * intel_crtc)467947dc10d7SGordon Ross static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
468047dc10d7SGordon Ross {
468147dc10d7SGordon Ross struct drm_device *dev = intel_crtc->base.dev;
468247dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
468347dc10d7SGordon Ross enum pipe pipe = intel_crtc->pipe;
468447dc10d7SGordon Ross enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
468547dc10d7SGordon Ross struct drm_display_mode *adjusted_mode =
468647dc10d7SGordon Ross &intel_crtc->config.adjusted_mode;
468747dc10d7SGordon Ross struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
468847dc10d7SGordon Ross uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
468947dc10d7SGordon Ross
469047dc10d7SGordon Ross /* We need to be careful not to changed the adjusted mode, for otherwise
469147dc10d7SGordon Ross * the hw state checker will get angry at the mismatch. */
469247dc10d7SGordon Ross crtc_vtotal = adjusted_mode->crtc_vtotal;
469347dc10d7SGordon Ross crtc_vblank_end = adjusted_mode->crtc_vblank_end;
469447dc10d7SGordon Ross
469547dc10d7SGordon Ross if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
469647dc10d7SGordon Ross /* the chip adds 2 halflines automatically */
469747dc10d7SGordon Ross crtc_vtotal -= 1;
469847dc10d7SGordon Ross crtc_vblank_end -= 1;
469947dc10d7SGordon Ross vsyncshift = adjusted_mode->crtc_hsync_start
470047dc10d7SGordon Ross - adjusted_mode->crtc_htotal / 2;
470147dc10d7SGordon Ross } else {
470247dc10d7SGordon Ross vsyncshift = 0;
470347dc10d7SGordon Ross }
470447dc10d7SGordon Ross
470547dc10d7SGordon Ross if (INTEL_INFO(dev)->gen > 3)
470647dc10d7SGordon Ross I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
470747dc10d7SGordon Ross
470847dc10d7SGordon Ross I915_WRITE(HTOTAL(cpu_transcoder),
470947dc10d7SGordon Ross (adjusted_mode->crtc_hdisplay - 1) |
471047dc10d7SGordon Ross ((adjusted_mode->crtc_htotal - 1) << 16));
471147dc10d7SGordon Ross I915_WRITE(HBLANK(cpu_transcoder),
471247dc10d7SGordon Ross (adjusted_mode->crtc_hblank_start - 1) |
471347dc10d7SGordon Ross ((adjusted_mode->crtc_hblank_end - 1) << 16));
471447dc10d7SGordon Ross I915_WRITE(HSYNC(cpu_transcoder),
471547dc10d7SGordon Ross (adjusted_mode->crtc_hsync_start - 1) |
471647dc10d7SGordon Ross ((adjusted_mode->crtc_hsync_end - 1) << 16));
471747dc10d7SGordon Ross
471847dc10d7SGordon Ross I915_WRITE(VTOTAL(cpu_transcoder),
471947dc10d7SGordon Ross (adjusted_mode->crtc_vdisplay - 1) |
472047dc10d7SGordon Ross ((crtc_vtotal - 1) << 16));
472147dc10d7SGordon Ross I915_WRITE(VBLANK(cpu_transcoder),
472247dc10d7SGordon Ross (adjusted_mode->crtc_vblank_start - 1) |
472347dc10d7SGordon Ross ((crtc_vblank_end - 1) << 16));
472447dc10d7SGordon Ross I915_WRITE(VSYNC(cpu_transcoder),
472547dc10d7SGordon Ross (adjusted_mode->crtc_vsync_start - 1) |
472647dc10d7SGordon Ross ((adjusted_mode->crtc_vsync_end - 1) << 16));
472747dc10d7SGordon Ross
472847dc10d7SGordon Ross /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
472947dc10d7SGordon Ross * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
473047dc10d7SGordon Ross * documented on the DDI_FUNC_CTL register description, EDP Input Select
473147dc10d7SGordon Ross * bits. */
473247dc10d7SGordon Ross if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
473347dc10d7SGordon Ross (pipe == PIPE_B || pipe == PIPE_C))
473447dc10d7SGordon Ross I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
473547dc10d7SGordon Ross
473647dc10d7SGordon Ross /* pipesrc controls the size that is scaled from, which should
473747dc10d7SGordon Ross * always be the user's requested size.
473847dc10d7SGordon Ross */
473947dc10d7SGordon Ross I915_WRITE(PIPESRC(pipe),
474047dc10d7SGordon Ross ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
474147dc10d7SGordon Ross }
474247dc10d7SGordon Ross
intel_get_pipe_timings(struct intel_crtc * crtc,struct intel_crtc_config * pipe_config)474347dc10d7SGordon Ross static void intel_get_pipe_timings(struct intel_crtc *crtc,
474447dc10d7SGordon Ross struct intel_crtc_config *pipe_config)
474547dc10d7SGordon Ross {
474647dc10d7SGordon Ross struct drm_device *dev = crtc->base.dev;
474747dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
474847dc10d7SGordon Ross enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
474947dc10d7SGordon Ross uint32_t tmp;
475047dc10d7SGordon Ross
475147dc10d7SGordon Ross tmp = I915_READ(HTOTAL(cpu_transcoder));
475247dc10d7SGordon Ross pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
475347dc10d7SGordon Ross pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
475447dc10d7SGordon Ross tmp = I915_READ(HBLANK(cpu_transcoder));
475547dc10d7SGordon Ross pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
475647dc10d7SGordon Ross pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
475747dc10d7SGordon Ross tmp = I915_READ(HSYNC(cpu_transcoder));
475847dc10d7SGordon Ross pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
475947dc10d7SGordon Ross pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
476047dc10d7SGordon Ross
476147dc10d7SGordon Ross tmp = I915_READ(VTOTAL(cpu_transcoder));
476247dc10d7SGordon Ross pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
476347dc10d7SGordon Ross pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
476447dc10d7SGordon Ross tmp = I915_READ(VBLANK(cpu_transcoder));
476547dc10d7SGordon Ross pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
476647dc10d7SGordon Ross pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
476747dc10d7SGordon Ross tmp = I915_READ(VSYNC(cpu_transcoder));
476847dc10d7SGordon Ross pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
476947dc10d7SGordon Ross pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
477047dc10d7SGordon Ross
477147dc10d7SGordon Ross if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
477247dc10d7SGordon Ross pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
477347dc10d7SGordon Ross pipe_config->adjusted_mode.crtc_vtotal += 1;
477447dc10d7SGordon Ross pipe_config->adjusted_mode.crtc_vblank_end += 1;
477547dc10d7SGordon Ross }
477647dc10d7SGordon Ross
477747dc10d7SGordon Ross tmp = I915_READ(PIPESRC(crtc->pipe));
477847dc10d7SGordon Ross pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
477947dc10d7SGordon Ross pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
478047dc10d7SGordon Ross }
478147dc10d7SGordon Ross
i9xx_set_pipeconf(struct intel_crtc * intel_crtc)478247dc10d7SGordon Ross static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
478347dc10d7SGordon Ross {
478447dc10d7SGordon Ross struct drm_device *dev = intel_crtc->base.dev;
478547dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
478647dc10d7SGordon Ross uint32_t pipeconf;
478747dc10d7SGordon Ross
478847dc10d7SGordon Ross pipeconf = 0;
478947dc10d7SGordon Ross
479047dc10d7SGordon Ross if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
479147dc10d7SGordon Ross /* Enable pixel doubling when the dot clock is > 90% of the (display)
479247dc10d7SGordon Ross * core speed.
479347dc10d7SGordon Ross *
479447dc10d7SGordon Ross * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
479547dc10d7SGordon Ross * pipe == 0 check?
479647dc10d7SGordon Ross */
479747dc10d7SGordon Ross if (intel_crtc->config.requested_mode.clock >
479847dc10d7SGordon Ross dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
479947dc10d7SGordon Ross pipeconf |= PIPECONF_DOUBLE_WIDE;
480047dc10d7SGordon Ross }
480147dc10d7SGordon Ross
480247dc10d7SGordon Ross /* only g4x and later have fancy bpc/dither controls */
480347dc10d7SGordon Ross if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
480447dc10d7SGordon Ross /* Bspec claims that we can't use dithering for 30bpp pipes. */
480547dc10d7SGordon Ross if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
480647dc10d7SGordon Ross pipeconf |= PIPECONF_DITHER_EN |
480747dc10d7SGordon Ross PIPECONF_DITHER_TYPE_SP;
480847dc10d7SGordon Ross
480947dc10d7SGordon Ross switch (intel_crtc->config.pipe_bpp) {
481047dc10d7SGordon Ross case 18:
481147dc10d7SGordon Ross pipeconf |= PIPECONF_6BPC;
481247dc10d7SGordon Ross break;
481347dc10d7SGordon Ross case 24:
481447dc10d7SGordon Ross pipeconf |= PIPECONF_8BPC;
481547dc10d7SGordon Ross break;
481647dc10d7SGordon Ross case 30:
481747dc10d7SGordon Ross pipeconf |= PIPECONF_10BPC;
481847dc10d7SGordon Ross break;
481947dc10d7SGordon Ross default:
482047dc10d7SGordon Ross /* Case prevented by intel_choose_pipe_bpp_dither. */
482147dc10d7SGordon Ross BUG();
482247dc10d7SGordon Ross }
482347dc10d7SGordon Ross }
482447dc10d7SGordon Ross
482547dc10d7SGordon Ross if (HAS_PIPE_CXSR(dev)) {
482647dc10d7SGordon Ross if (intel_crtc->lowfreq_avail) {
482747dc10d7SGordon Ross DRM_DEBUG_KMS("enabling CxSR downclocking\n");
482847dc10d7SGordon Ross pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
482947dc10d7SGordon Ross } else {
483047dc10d7SGordon Ross DRM_DEBUG_KMS("disabling CxSR downclocking\n");
483147dc10d7SGordon Ross }
483247dc10d7SGordon Ross }
483347dc10d7SGordon Ross
483447dc10d7SGordon Ross if (!IS_GEN2(dev) &&
483547dc10d7SGordon Ross intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
483647dc10d7SGordon Ross pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
483747dc10d7SGordon Ross else
483847dc10d7SGordon Ross pipeconf |= PIPECONF_PROGRESSIVE;
483947dc10d7SGordon Ross
484047dc10d7SGordon Ross if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
484147dc10d7SGordon Ross pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
484247dc10d7SGordon Ross
484347dc10d7SGordon Ross I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
484447dc10d7SGordon Ross POSTING_READ(PIPECONF(intel_crtc->pipe));
484547dc10d7SGordon Ross }
484647dc10d7SGordon Ross
i9xx_crtc_mode_set(struct drm_crtc * crtc,int x,int y,struct drm_framebuffer * fb)484747dc10d7SGordon Ross static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
484847dc10d7SGordon Ross int x, int y,
484947dc10d7SGordon Ross struct drm_framebuffer *fb)
485047dc10d7SGordon Ross {
485147dc10d7SGordon Ross struct drm_device *dev = crtc->dev;
485247dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
485347dc10d7SGordon Ross struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
485447dc10d7SGordon Ross struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
485547dc10d7SGordon Ross int pipe = intel_crtc->pipe;
485647dc10d7SGordon Ross int plane = intel_crtc->plane;
485747dc10d7SGordon Ross int refclk, num_connectors = 0;
485847dc10d7SGordon Ross intel_clock_t clock, reduced_clock;
485947dc10d7SGordon Ross u32 dspcntr;
486047dc10d7SGordon Ross bool ok, has_reduced_clock = false;
486147dc10d7SGordon Ross bool is_lvds = false;
486247dc10d7SGordon Ross struct intel_encoder *encoder;
486347dc10d7SGordon Ross const intel_limit_t *limit;
486447dc10d7SGordon Ross int ret;
486547dc10d7SGordon Ross
486647dc10d7SGordon Ross for_each_encoder_on_crtc(dev, crtc, encoder) {
486747dc10d7SGordon Ross switch (encoder->type) {
486847dc10d7SGordon Ross case INTEL_OUTPUT_LVDS:
486947dc10d7SGordon Ross is_lvds = true;
487047dc10d7SGordon Ross break;
487147dc10d7SGordon Ross }
487247dc10d7SGordon Ross
487347dc10d7SGordon Ross num_connectors++;
487447dc10d7SGordon Ross }
487547dc10d7SGordon Ross
487647dc10d7SGordon Ross refclk = i9xx_get_refclk(crtc, num_connectors);
487747dc10d7SGordon Ross
487847dc10d7SGordon Ross /*
487947dc10d7SGordon Ross * Returns a set of divisors for the desired target clock with the given
488047dc10d7SGordon Ross * refclk, or FALSE. The returned values represent the clock equation:
488147dc10d7SGordon Ross * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
488247dc10d7SGordon Ross */
488347dc10d7SGordon Ross limit = intel_limit(crtc, refclk);
488447dc10d7SGordon Ross ok = dev_priv->display.find_dpll(limit, crtc,
488547dc10d7SGordon Ross intel_crtc->config.port_clock,
488647dc10d7SGordon Ross refclk, NULL, &clock);
488747dc10d7SGordon Ross if (!ok && !intel_crtc->config.clock_set) {
488847dc10d7SGordon Ross DRM_ERROR("Couldn't find PLL settings for mode!\n");
488947dc10d7SGordon Ross return -EINVAL;
489047dc10d7SGordon Ross }
489147dc10d7SGordon Ross
489247dc10d7SGordon Ross /* Ensure that the cursor is valid for the new mode before changing... */
489347dc10d7SGordon Ross intel_crtc_update_cursor(crtc, true);
489447dc10d7SGordon Ross
489547dc10d7SGordon Ross if (is_lvds && dev_priv->lvds_downclock_avail) {
489647dc10d7SGordon Ross /*
489747dc10d7SGordon Ross * Ensure we match the reduced clock's P to the target clock.
489847dc10d7SGordon Ross * If the clocks don't match, we can't switch the display clock
489947dc10d7SGordon Ross * by using the FP0/FP1. In such case we will disable the LVDS
490047dc10d7SGordon Ross * downclock feature.
490147dc10d7SGordon Ross */
490247dc10d7SGordon Ross has_reduced_clock =
490347dc10d7SGordon Ross dev_priv->display.find_dpll(limit, crtc,
490447dc10d7SGordon Ross dev_priv->lvds_downclock,
490547dc10d7SGordon Ross refclk, &clock,
490647dc10d7SGordon Ross &reduced_clock);
490747dc10d7SGordon Ross }
490847dc10d7SGordon Ross /* Compat-code for transition, will disappear. */
490947dc10d7SGordon Ross if (!intel_crtc->config.clock_set) {
491047dc10d7SGordon Ross intel_crtc->config.dpll.n = clock.n;
491147dc10d7SGordon Ross intel_crtc->config.dpll.m1 = clock.m1;
491247dc10d7SGordon Ross intel_crtc->config.dpll.m2 = clock.m2;
491347dc10d7SGordon Ross intel_crtc->config.dpll.p1 = clock.p1;
491447dc10d7SGordon Ross intel_crtc->config.dpll.p2 = clock.p2;
491547dc10d7SGordon Ross }
491647dc10d7SGordon Ross
491747dc10d7SGordon Ross if (IS_GEN2(dev))
491847dc10d7SGordon Ross i8xx_update_pll(intel_crtc,
491947dc10d7SGordon Ross has_reduced_clock ? &reduced_clock : NULL,
492047dc10d7SGordon Ross num_connectors);
492147dc10d7SGordon Ross else if (IS_VALLEYVIEW(dev))
492247dc10d7SGordon Ross vlv_update_pll(intel_crtc);
492347dc10d7SGordon Ross else
492447dc10d7SGordon Ross i9xx_update_pll(intel_crtc,
492547dc10d7SGordon Ross has_reduced_clock ? &reduced_clock : NULL,
492647dc10d7SGordon Ross num_connectors);
492747dc10d7SGordon Ross
492847dc10d7SGordon Ross /* Set up the display plane register */
492947dc10d7SGordon Ross dspcntr = DISPPLANE_GAMMA_ENABLE;
493047dc10d7SGordon Ross
493147dc10d7SGordon Ross if (!IS_VALLEYVIEW(dev)) {
493247dc10d7SGordon Ross if (pipe == 0)
493347dc10d7SGordon Ross dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
493447dc10d7SGordon Ross else
493547dc10d7SGordon Ross dspcntr |= DISPPLANE_SEL_PIPE_B;
493647dc10d7SGordon Ross }
493747dc10d7SGordon Ross
493847dc10d7SGordon Ross intel_set_pipe_timings(intel_crtc);
493947dc10d7SGordon Ross
494047dc10d7SGordon Ross /* pipesrc and dspsize control the size that is scaled from,
494147dc10d7SGordon Ross * which should always be the user's requested size.
494247dc10d7SGordon Ross */
494347dc10d7SGordon Ross I915_WRITE(DSPSIZE(plane),
494447dc10d7SGordon Ross ((mode->vdisplay - 1) << 16) |
494547dc10d7SGordon Ross (mode->hdisplay - 1));
494647dc10d7SGordon Ross I915_WRITE(DSPPOS(plane), 0);
494747dc10d7SGordon Ross
494847dc10d7SGordon Ross i9xx_set_pipeconf(intel_crtc);
494947dc10d7SGordon Ross
495047dc10d7SGordon Ross I915_WRITE(DSPCNTR(plane), dspcntr);
495147dc10d7SGordon Ross POSTING_READ(DSPCNTR(plane));
495247dc10d7SGordon Ross
495347dc10d7SGordon Ross ret = intel_pipe_set_base(crtc, x, y, fb);
495447dc10d7SGordon Ross
495547dc10d7SGordon Ross intel_update_watermarks(dev);
495647dc10d7SGordon Ross
495747dc10d7SGordon Ross return ret;
495847dc10d7SGordon Ross }
495947dc10d7SGordon Ross
i9xx_get_pfit_config(struct intel_crtc * crtc,struct intel_crtc_config * pipe_config)496047dc10d7SGordon Ross static void i9xx_get_pfit_config(struct intel_crtc *crtc,
496147dc10d7SGordon Ross struct intel_crtc_config *pipe_config)
496247dc10d7SGordon Ross {
496347dc10d7SGordon Ross struct drm_device *dev = crtc->base.dev;
496447dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
496547dc10d7SGordon Ross uint32_t tmp;
496647dc10d7SGordon Ross
496747dc10d7SGordon Ross tmp = I915_READ(PFIT_CONTROL);
496847dc10d7SGordon Ross if (!(tmp & PFIT_ENABLE))
496947dc10d7SGordon Ross return;
497047dc10d7SGordon Ross
497147dc10d7SGordon Ross /* Check whether the pfit is attached to our pipe. */
497247dc10d7SGordon Ross if (INTEL_INFO(dev)->gen < 4) {
497347dc10d7SGordon Ross if (crtc->pipe != PIPE_B)
497447dc10d7SGordon Ross return;
497547dc10d7SGordon Ross } else {
497647dc10d7SGordon Ross if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
497747dc10d7SGordon Ross return;
497847dc10d7SGordon Ross }
497947dc10d7SGordon Ross
498047dc10d7SGordon Ross pipe_config->gmch_pfit.control = tmp;
498147dc10d7SGordon Ross pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
498247dc10d7SGordon Ross if (INTEL_INFO(dev)->gen < 5)
498347dc10d7SGordon Ross pipe_config->gmch_pfit.lvds_border_bits =
498447dc10d7SGordon Ross I915_READ(LVDS) & LVDS_BORDER_ENABLE;
498547dc10d7SGordon Ross }
498647dc10d7SGordon Ross
i9xx_get_pipe_config(struct intel_crtc * crtc,struct intel_crtc_config * pipe_config)498747dc10d7SGordon Ross static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
498847dc10d7SGordon Ross struct intel_crtc_config *pipe_config)
498947dc10d7SGordon Ross {
499047dc10d7SGordon Ross struct drm_device *dev = crtc->base.dev;
499147dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
499247dc10d7SGordon Ross uint32_t tmp;
499347dc10d7SGordon Ross
499447dc10d7SGordon Ross pipe_config->cpu_transcoder = (enum transcoder)crtc->pipe;
499547dc10d7SGordon Ross pipe_config->shared_dpll = DPLL_ID_PRIVATE;
499647dc10d7SGordon Ross
499747dc10d7SGordon Ross tmp = I915_READ(PIPECONF(crtc->pipe));
499847dc10d7SGordon Ross if (!(tmp & PIPECONF_ENABLE))
499947dc10d7SGordon Ross return false;
500047dc10d7SGordon Ross
500147dc10d7SGordon Ross intel_get_pipe_timings(crtc, pipe_config);
500247dc10d7SGordon Ross
500347dc10d7SGordon Ross i9xx_get_pfit_config(crtc, pipe_config);
500447dc10d7SGordon Ross
500547dc10d7SGordon Ross if (INTEL_INFO(dev)->gen >= 4) {
500647dc10d7SGordon Ross tmp = I915_READ(DPLL_MD(crtc->pipe));
500747dc10d7SGordon Ross pipe_config->pixel_multiplier =
500847dc10d7SGordon Ross ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
500947dc10d7SGordon Ross >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
501047dc10d7SGordon Ross } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
501147dc10d7SGordon Ross tmp = I915_READ(DPLL(crtc->pipe));
501247dc10d7SGordon Ross pipe_config->pixel_multiplier =
501347dc10d7SGordon Ross ((tmp & SDVO_MULTIPLIER_MASK)
501447dc10d7SGordon Ross >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
501547dc10d7SGordon Ross } else {
501647dc10d7SGordon Ross /* Note that on i915G/GM the pixel multiplier is in the sdvo
501747dc10d7SGordon Ross * port and will be fixed up in the encoder->get_config
501847dc10d7SGordon Ross * function. */
501947dc10d7SGordon Ross pipe_config->pixel_multiplier = 1;
502047dc10d7SGordon Ross }
502147dc10d7SGordon Ross
502247dc10d7SGordon Ross return true;
502347dc10d7SGordon Ross }
502447dc10d7SGordon Ross
ironlake_init_pch_refclk(struct drm_device * dev)502547dc10d7SGordon Ross static void ironlake_init_pch_refclk(struct drm_device *dev)
502647dc10d7SGordon Ross {
502747dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
502847dc10d7SGordon Ross struct drm_mode_config *mode_config = &dev->mode_config;
502947dc10d7SGordon Ross struct intel_encoder *encoder;
503047dc10d7SGordon Ross u32 val, final;
503147dc10d7SGordon Ross bool has_lvds = false;
503247dc10d7SGordon Ross bool has_cpu_edp = false;
503347dc10d7SGordon Ross bool has_panel = false;
503447dc10d7SGordon Ross bool has_ck505 = false;
503547dc10d7SGordon Ross bool can_ssc = false;
503647dc10d7SGordon Ross
503747dc10d7SGordon Ross /* We need to take the global config into account */
503847dc10d7SGordon Ross list_for_each_entry(encoder, struct intel_encoder, &mode_config->encoder_list,
503947dc10d7SGordon Ross base.head) {
504047dc10d7SGordon Ross switch (encoder->type) {
504147dc10d7SGordon Ross case INTEL_OUTPUT_LVDS:
504247dc10d7SGordon Ross has_panel = true;
504347dc10d7SGordon Ross has_lvds = true;
504447dc10d7SGordon Ross break;
504547dc10d7SGordon Ross case INTEL_OUTPUT_EDP:
504647dc10d7SGordon Ross has_panel = true;
504747dc10d7SGordon Ross if (enc_to_dig_port(&encoder->base)->port == PORT_A)
504847dc10d7SGordon Ross has_cpu_edp = true;
504947dc10d7SGordon Ross break;
505047dc10d7SGordon Ross }
505147dc10d7SGordon Ross }
505247dc10d7SGordon Ross
505347dc10d7SGordon Ross if (HAS_PCH_IBX(dev)) {
505447dc10d7SGordon Ross has_ck505 = dev_priv->vbt.display_clock_mode;
505547dc10d7SGordon Ross can_ssc = has_ck505;
505647dc10d7SGordon Ross } else {
505747dc10d7SGordon Ross has_ck505 = false;
505847dc10d7SGordon Ross can_ssc = true;
505947dc10d7SGordon Ross }
506047dc10d7SGordon Ross
506147dc10d7SGordon Ross DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
506247dc10d7SGordon Ross has_panel, has_lvds, has_ck505);
506347dc10d7SGordon Ross
506447dc10d7SGordon Ross /* Ironlake: try to setup display ref clock before DPLL
506547dc10d7SGordon Ross * enabling. This is only under driver's control after
506647dc10d7SGordon Ross * PCH B stepping, previous chipset stepping should be
506747dc10d7SGordon Ross * ignoring this setting.
506847dc10d7SGordon Ross */
506947dc10d7SGordon Ross val = I915_READ(PCH_DREF_CONTROL);
507047dc10d7SGordon Ross
507147dc10d7SGordon Ross /* As we must carefully and slowly disable/enable each source in turn,
507247dc10d7SGordon Ross * compute the final state we want first and check if we need to
507347dc10d7SGordon Ross * make any changes at all.
507447dc10d7SGordon Ross */
507547dc10d7SGordon Ross final = val;
507647dc10d7SGordon Ross final &= ~DREF_NONSPREAD_SOURCE_MASK;
507747dc10d7SGordon Ross if (has_ck505)
507847dc10d7SGordon Ross final |= DREF_NONSPREAD_CK505_ENABLE;
507947dc10d7SGordon Ross else
508047dc10d7SGordon Ross final |= DREF_NONSPREAD_SOURCE_ENABLE;
508147dc10d7SGordon Ross
508247dc10d7SGordon Ross final &= ~DREF_SSC_SOURCE_MASK;
508347dc10d7SGordon Ross final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
508447dc10d7SGordon Ross final &= ~DREF_SSC1_ENABLE;
508547dc10d7SGordon Ross
508647dc10d7SGordon Ross if (has_panel) {
508747dc10d7SGordon Ross final |= DREF_SSC_SOURCE_ENABLE;
508847dc10d7SGordon Ross
508947dc10d7SGordon Ross if (intel_panel_use_ssc(dev_priv) && can_ssc)
509047dc10d7SGordon Ross final |= DREF_SSC1_ENABLE;
509147dc10d7SGordon Ross
509247dc10d7SGordon Ross if (has_cpu_edp) {
509347dc10d7SGordon Ross if (intel_panel_use_ssc(dev_priv) && can_ssc)
509447dc10d7SGordon Ross final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
509547dc10d7SGordon Ross else
509647dc10d7SGordon Ross final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
509747dc10d7SGordon Ross } else
509847dc10d7SGordon Ross final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
509947dc10d7SGordon Ross } else {
510047dc10d7SGordon Ross final |= DREF_SSC_SOURCE_DISABLE;
510147dc10d7SGordon Ross final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
510247dc10d7SGordon Ross }
510347dc10d7SGordon Ross
510447dc10d7SGordon Ross if (final == val)
510547dc10d7SGordon Ross return;
510647dc10d7SGordon Ross
510747dc10d7SGordon Ross /* Always enable nonspread source */
510847dc10d7SGordon Ross val &= ~DREF_NONSPREAD_SOURCE_MASK;
510947dc10d7SGordon Ross
511047dc10d7SGordon Ross if (has_ck505)
511147dc10d7SGordon Ross val |= DREF_NONSPREAD_CK505_ENABLE;
511247dc10d7SGordon Ross else
511347dc10d7SGordon Ross val |= DREF_NONSPREAD_SOURCE_ENABLE;
511447dc10d7SGordon Ross
511547dc10d7SGordon Ross if (has_panel) {
511647dc10d7SGordon Ross val &= ~DREF_SSC_SOURCE_MASK;
511747dc10d7SGordon Ross val |= DREF_SSC_SOURCE_ENABLE;
511847dc10d7SGordon Ross
511947dc10d7SGordon Ross /* SSC must be turned on before enabling the CPU output */
512047dc10d7SGordon Ross if (intel_panel_use_ssc(dev_priv) && can_ssc) {
512147dc10d7SGordon Ross DRM_DEBUG_KMS("Using SSC on panel\n");
512247dc10d7SGordon Ross val |= DREF_SSC1_ENABLE;
512347dc10d7SGordon Ross } else
512447dc10d7SGordon Ross val &= ~DREF_SSC1_ENABLE;
512547dc10d7SGordon Ross
512647dc10d7SGordon Ross /* Get SSC going before enabling the outputs */
512747dc10d7SGordon Ross I915_WRITE(PCH_DREF_CONTROL, val);
512847dc10d7SGordon Ross POSTING_READ(PCH_DREF_CONTROL);
512947dc10d7SGordon Ross udelay(200);
513047dc10d7SGordon Ross
513147dc10d7SGordon Ross val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
513247dc10d7SGordon Ross
513347dc10d7SGordon Ross /* Enable CPU source on CPU attached eDP */
513447dc10d7SGordon Ross if (has_cpu_edp) {
513547dc10d7SGordon Ross if (intel_panel_use_ssc(dev_priv) && can_ssc) {
513647dc10d7SGordon Ross DRM_DEBUG_KMS("Using SSC on eDP\n");
513747dc10d7SGordon Ross val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
513847dc10d7SGordon Ross }
513947dc10d7SGordon Ross else
514047dc10d7SGordon Ross val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
514147dc10d7SGordon Ross } else
514247dc10d7SGordon Ross val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
514347dc10d7SGordon Ross
514447dc10d7SGordon Ross I915_WRITE(PCH_DREF_CONTROL, val);
514547dc10d7SGordon Ross POSTING_READ(PCH_DREF_CONTROL);
514647dc10d7SGordon Ross udelay(200);
514747dc10d7SGordon Ross } else {
514847dc10d7SGordon Ross DRM_DEBUG_KMS("Disabling SSC entirely\n");
514947dc10d7SGordon Ross
515047dc10d7SGordon Ross val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
515147dc10d7SGordon Ross
515247dc10d7SGordon Ross /* Turn off CPU output */
515347dc10d7SGordon Ross val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
515447dc10d7SGordon Ross
515547dc10d7SGordon Ross I915_WRITE(PCH_DREF_CONTROL, val);
515647dc10d7SGordon Ross POSTING_READ(PCH_DREF_CONTROL);
515747dc10d7SGordon Ross udelay(200);
515847dc10d7SGordon Ross
515947dc10d7SGordon Ross /* Turn off the SSC source */
516047dc10d7SGordon Ross val &= ~DREF_SSC_SOURCE_MASK;
516147dc10d7SGordon Ross val |= DREF_SSC_SOURCE_DISABLE;
516247dc10d7SGordon Ross
516347dc10d7SGordon Ross /* Turn off SSC1 */
516447dc10d7SGordon Ross val &= ~DREF_SSC1_ENABLE;
516547dc10d7SGordon Ross
516647dc10d7SGordon Ross I915_WRITE(PCH_DREF_CONTROL, val);
516747dc10d7SGordon Ross POSTING_READ(PCH_DREF_CONTROL);
516847dc10d7SGordon Ross udelay(200);
516947dc10d7SGordon Ross }
517047dc10d7SGordon Ross
517147dc10d7SGordon Ross BUG_ON(val != final);
517247dc10d7SGordon Ross }
517347dc10d7SGordon Ross
517447dc10d7SGordon Ross /* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
lpt_init_pch_refclk(struct drm_device * dev)517547dc10d7SGordon Ross static void lpt_init_pch_refclk(struct drm_device *dev)
517647dc10d7SGordon Ross {
517747dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
517847dc10d7SGordon Ross struct drm_mode_config *mode_config = &dev->mode_config;
517947dc10d7SGordon Ross struct intel_encoder *encoder;
518047dc10d7SGordon Ross bool has_vga = false;
518147dc10d7SGordon Ross bool is_sdv = false;
518247dc10d7SGordon Ross u32 tmp;
518347dc10d7SGordon Ross
518447dc10d7SGordon Ross list_for_each_entry(encoder, struct intel_encoder, &mode_config->encoder_list, base.head) {
518547dc10d7SGordon Ross switch (encoder->type) {
518647dc10d7SGordon Ross case INTEL_OUTPUT_ANALOG:
518747dc10d7SGordon Ross has_vga = true;
518847dc10d7SGordon Ross break;
518947dc10d7SGordon Ross }
519047dc10d7SGordon Ross }
519147dc10d7SGordon Ross
519247dc10d7SGordon Ross if (!has_vga)
519347dc10d7SGordon Ross return;
519447dc10d7SGordon Ross
519547dc10d7SGordon Ross mutex_lock(&dev_priv->dpio_lock);
519647dc10d7SGordon Ross
519747dc10d7SGordon Ross /* XXX: Rip out SDV support once Haswell ships for real. */
519847dc10d7SGordon Ross if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
519947dc10d7SGordon Ross is_sdv = true;
520047dc10d7SGordon Ross
520147dc10d7SGordon Ross tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
520247dc10d7SGordon Ross tmp &= ~SBI_SSCCTL_DISABLE;
520347dc10d7SGordon Ross tmp |= SBI_SSCCTL_PATHALT;
520447dc10d7SGordon Ross intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
520547dc10d7SGordon Ross
520647dc10d7SGordon Ross udelay(24);
520747dc10d7SGordon Ross
520847dc10d7SGordon Ross tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
520947dc10d7SGordon Ross tmp &= ~SBI_SSCCTL_PATHALT;
521047dc10d7SGordon Ross intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
521147dc10d7SGordon Ross
521247dc10d7SGordon Ross if (!is_sdv) {
521347dc10d7SGordon Ross tmp = I915_READ(SOUTH_CHICKEN2);
521447dc10d7SGordon Ross tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
521547dc10d7SGordon Ross I915_WRITE(SOUTH_CHICKEN2, tmp);
521647dc10d7SGordon Ross
521747dc10d7SGordon Ross if (wait_for_atomic(I915_READ(SOUTH_CHICKEN2) &
521847dc10d7SGordon Ross FDI_MPHY_IOSFSB_RESET_STATUS, 1))
521947dc10d7SGordon Ross DRM_ERROR("FDI mPHY reset assert timeout\n");
522047dc10d7SGordon Ross
522147dc10d7SGordon Ross tmp = I915_READ(SOUTH_CHICKEN2);
522247dc10d7SGordon Ross tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
522347dc10d7SGordon Ross I915_WRITE(SOUTH_CHICKEN2, tmp);
522447dc10d7SGordon Ross
522547dc10d7SGordon Ross if (wait_for_atomic((I915_READ(SOUTH_CHICKEN2) &
522647dc10d7SGordon Ross FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
522747dc10d7SGordon Ross 1))
522847dc10d7SGordon Ross DRM_ERROR("FDI mPHY reset de-assert timeout\n");
522947dc10d7SGordon Ross }
523047dc10d7SGordon Ross
523147dc10d7SGordon Ross tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
523247dc10d7SGordon Ross tmp &= ~(0xFFUL << 24);
523347dc10d7SGordon Ross tmp |= (0x12 << 24);
523447dc10d7SGordon Ross intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
523547dc10d7SGordon Ross
523647dc10d7SGordon Ross if (is_sdv) {
523747dc10d7SGordon Ross tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
523847dc10d7SGordon Ross tmp |= 0x7FFF;
523947dc10d7SGordon Ross intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
524047dc10d7SGordon Ross }
524147dc10d7SGordon Ross
524247dc10d7SGordon Ross tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
524347dc10d7SGordon Ross tmp |= (1 << 11);
524447dc10d7SGordon Ross intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
524547dc10d7SGordon Ross
524647dc10d7SGordon Ross tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
524747dc10d7SGordon Ross tmp |= (1 << 11);
524847dc10d7SGordon Ross intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
524947dc10d7SGordon Ross
525047dc10d7SGordon Ross if (is_sdv) {
525147dc10d7SGordon Ross tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
525247dc10d7SGordon Ross tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
525347dc10d7SGordon Ross intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
525447dc10d7SGordon Ross
525547dc10d7SGordon Ross tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
525647dc10d7SGordon Ross tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
525747dc10d7SGordon Ross intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
525847dc10d7SGordon Ross
525947dc10d7SGordon Ross tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
526047dc10d7SGordon Ross tmp |= (0x3F << 8);
526147dc10d7SGordon Ross intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
526247dc10d7SGordon Ross
526347dc10d7SGordon Ross tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
526447dc10d7SGordon Ross tmp |= (0x3F << 8);
526547dc10d7SGordon Ross intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
526647dc10d7SGordon Ross }
526747dc10d7SGordon Ross
526847dc10d7SGordon Ross tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
526947dc10d7SGordon Ross tmp |= (1 << 24) | (1 << 21) | (1 << 18);
527047dc10d7SGordon Ross intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
527147dc10d7SGordon Ross
527247dc10d7SGordon Ross tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
527347dc10d7SGordon Ross tmp |= (1 << 24) | (1 << 21) | (1 << 18);
527447dc10d7SGordon Ross intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
527547dc10d7SGordon Ross
527647dc10d7SGordon Ross if (!is_sdv) {
527747dc10d7SGordon Ross tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
527847dc10d7SGordon Ross tmp &= ~(7 << 13);
527947dc10d7SGordon Ross tmp |= (5 << 13);
528047dc10d7SGordon Ross intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
528147dc10d7SGordon Ross
528247dc10d7SGordon Ross tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
528347dc10d7SGordon Ross tmp &= ~(7 << 13);
528447dc10d7SGordon Ross tmp |= (5 << 13);
528547dc10d7SGordon Ross intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
528647dc10d7SGordon Ross }
528747dc10d7SGordon Ross
528847dc10d7SGordon Ross tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
528947dc10d7SGordon Ross tmp &= ~0xFF;
529047dc10d7SGordon Ross tmp |= 0x1C;
529147dc10d7SGordon Ross intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
529247dc10d7SGordon Ross
529347dc10d7SGordon Ross tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
529447dc10d7SGordon Ross tmp &= ~0xFF;
529547dc10d7SGordon Ross tmp |= 0x1C;
529647dc10d7SGordon Ross intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
529747dc10d7SGordon Ross
529847dc10d7SGordon Ross tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
529947dc10d7SGordon Ross tmp &= ~(0xFF << 16);
530047dc10d7SGordon Ross tmp |= (0x1C << 16);
530147dc10d7SGordon Ross intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
530247dc10d7SGordon Ross
530347dc10d7SGordon Ross tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
530447dc10d7SGordon Ross tmp &= ~(0xFF << 16);
530547dc10d7SGordon Ross tmp |= (0x1C << 16);
530647dc10d7SGordon Ross intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
530747dc10d7SGordon Ross
530847dc10d7SGordon Ross if (!is_sdv) {
530947dc10d7SGordon Ross tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
531047dc10d7SGordon Ross tmp |= (1 << 27);
531147dc10d7SGordon Ross intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
531247dc10d7SGordon Ross
531347dc10d7SGordon Ross tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
531447dc10d7SGordon Ross tmp |= (1 << 27);
531547dc10d7SGordon Ross intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
531647dc10d7SGordon Ross
531747dc10d7SGordon Ross tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
531847dc10d7SGordon Ross tmp &= ~(0xFUL << 28);
531947dc10d7SGordon Ross tmp |= (4 << 28);
532047dc10d7SGordon Ross intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
532147dc10d7SGordon Ross
532247dc10d7SGordon Ross tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
532347dc10d7SGordon Ross tmp &= ~(0xFUL << 28);
532447dc10d7SGordon Ross tmp |= (4 << 28);
532547dc10d7SGordon Ross intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
532647dc10d7SGordon Ross }
532747dc10d7SGordon Ross
532847dc10d7SGordon Ross /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
532947dc10d7SGordon Ross tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
533047dc10d7SGordon Ross tmp |= SBI_DBUFF0_ENABLE;
533147dc10d7SGordon Ross intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
533247dc10d7SGordon Ross
533347dc10d7SGordon Ross mutex_unlock(&dev_priv->dpio_lock);
533447dc10d7SGordon Ross }
533547dc10d7SGordon Ross
533647dc10d7SGordon Ross /*
533747dc10d7SGordon Ross * Initialize reference clocks when the driver loads
533847dc10d7SGordon Ross */
intel_init_pch_refclk(struct drm_device * dev)533947dc10d7SGordon Ross void intel_init_pch_refclk(struct drm_device *dev)
534047dc10d7SGordon Ross {
534147dc10d7SGordon Ross if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
534247dc10d7SGordon Ross ironlake_init_pch_refclk(dev);
534347dc10d7SGordon Ross else if (HAS_PCH_LPT(dev))
534447dc10d7SGordon Ross lpt_init_pch_refclk(dev);
534547dc10d7SGordon Ross }
534647dc10d7SGordon Ross
ironlake_get_refclk(struct drm_crtc * crtc)534747dc10d7SGordon Ross static int ironlake_get_refclk(struct drm_crtc *crtc)
534847dc10d7SGordon Ross {
534947dc10d7SGordon Ross struct drm_device *dev = crtc->dev;
535047dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
535147dc10d7SGordon Ross struct intel_encoder *encoder;
535247dc10d7SGordon Ross int num_connectors = 0;
535347dc10d7SGordon Ross bool is_lvds = false;
535447dc10d7SGordon Ross
535547dc10d7SGordon Ross for_each_encoder_on_crtc(dev, crtc, encoder) {
535647dc10d7SGordon Ross switch (encoder->type) {
535747dc10d7SGordon Ross case INTEL_OUTPUT_LVDS:
535847dc10d7SGordon Ross is_lvds = true;
535947dc10d7SGordon Ross break;
536047dc10d7SGordon Ross }
536147dc10d7SGordon Ross num_connectors++;
536247dc10d7SGordon Ross }
536347dc10d7SGordon Ross
536447dc10d7SGordon Ross if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
536547dc10d7SGordon Ross DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
536647dc10d7SGordon Ross dev_priv->vbt.lvds_ssc_freq);
536747dc10d7SGordon Ross return dev_priv->vbt.lvds_ssc_freq * 1000;
536847dc10d7SGordon Ross }
536947dc10d7SGordon Ross
537047dc10d7SGordon Ross return 120000;
537147dc10d7SGordon Ross }
537247dc10d7SGordon Ross
ironlake_set_pipeconf(struct drm_crtc * crtc)537347dc10d7SGordon Ross static void ironlake_set_pipeconf(struct drm_crtc *crtc)
537447dc10d7SGordon Ross {
537547dc10d7SGordon Ross struct drm_i915_private *dev_priv = crtc->dev->dev_private;
537647dc10d7SGordon Ross struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
537747dc10d7SGordon Ross int pipe = intel_crtc->pipe;
537847dc10d7SGordon Ross uint32_t val;
537947dc10d7SGordon Ross
538047dc10d7SGordon Ross val = 0;
538147dc10d7SGordon Ross
538247dc10d7SGordon Ross switch (intel_crtc->config.pipe_bpp) {
538347dc10d7SGordon Ross case 18:
538447dc10d7SGordon Ross val |= PIPECONF_6BPC;
538547dc10d7SGordon Ross break;
538647dc10d7SGordon Ross case 24:
538747dc10d7SGordon Ross val |= PIPECONF_8BPC;
538847dc10d7SGordon Ross break;
538947dc10d7SGordon Ross case 30:
539047dc10d7SGordon Ross val |= PIPECONF_10BPC;
539147dc10d7SGordon Ross break;
539247dc10d7SGordon Ross case 36:
539347dc10d7SGordon Ross val |= PIPECONF_12BPC;
539447dc10d7SGordon Ross break;
539547dc10d7SGordon Ross default:
539647dc10d7SGordon Ross /* Case prevented by intel_choose_pipe_bpp_dither. */
539747dc10d7SGordon Ross BUG();
539847dc10d7SGordon Ross }
539947dc10d7SGordon Ross
540047dc10d7SGordon Ross if (intel_crtc->config.dither)
540147dc10d7SGordon Ross val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
540247dc10d7SGordon Ross
540347dc10d7SGordon Ross if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
540447dc10d7SGordon Ross val |= PIPECONF_INTERLACED_ILK;
540547dc10d7SGordon Ross else
540647dc10d7SGordon Ross val |= PIPECONF_PROGRESSIVE;
540747dc10d7SGordon Ross
540847dc10d7SGordon Ross if (intel_crtc->config.limited_color_range)
540947dc10d7SGordon Ross val |= PIPECONF_COLOR_RANGE_SELECT;
541047dc10d7SGordon Ross
541147dc10d7SGordon Ross I915_WRITE(PIPECONF(pipe), val);
541247dc10d7SGordon Ross POSTING_READ(PIPECONF(pipe));
541347dc10d7SGordon Ross }
541447dc10d7SGordon Ross
541547dc10d7SGordon Ross /*
541647dc10d7SGordon Ross * Set up the pipe CSC unit.
541747dc10d7SGordon Ross *
541847dc10d7SGordon Ross * Currently only full range RGB to limited range RGB conversion
541947dc10d7SGordon Ross * is supported, but eventually this should handle various
542047dc10d7SGordon Ross * RGB<->YCbCr scenarios as well.
542147dc10d7SGordon Ross */
intel_set_pipe_csc(struct drm_crtc * crtc)542247dc10d7SGordon Ross static void intel_set_pipe_csc(struct drm_crtc *crtc)
542347dc10d7SGordon Ross {
542447dc10d7SGordon Ross struct drm_device *dev = crtc->dev;
542547dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
542647dc10d7SGordon Ross struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
542747dc10d7SGordon Ross int pipe = intel_crtc->pipe;
542847dc10d7SGordon Ross uint16_t coeff = 0x7800; /* 1.0 */
542947dc10d7SGordon Ross
543047dc10d7SGordon Ross /*
543147dc10d7SGordon Ross * TODO: Check what kind of values actually come out of the pipe
543247dc10d7SGordon Ross * with these coeff/postoff values and adjust to get the best
543347dc10d7SGordon Ross * accuracy. Perhaps we even need to take the bpc value into
543447dc10d7SGordon Ross * consideration.
543547dc10d7SGordon Ross */
543647dc10d7SGordon Ross
543747dc10d7SGordon Ross if (intel_crtc->config.limited_color_range)
543847dc10d7SGordon Ross coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
543947dc10d7SGordon Ross
544047dc10d7SGordon Ross /*
544147dc10d7SGordon Ross * GY/GU and RY/RU should be the other way around according
544247dc10d7SGordon Ross * to BSpec, but reality doesn't agree. Just set them up in
544347dc10d7SGordon Ross * a way that results in the correct picture.
544447dc10d7SGordon Ross */
544547dc10d7SGordon Ross I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
544647dc10d7SGordon Ross I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
544747dc10d7SGordon Ross
544847dc10d7SGordon Ross I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
544947dc10d7SGordon Ross I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
545047dc10d7SGordon Ross
545147dc10d7SGordon Ross I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
545247dc10d7SGordon Ross I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
545347dc10d7SGordon Ross
545447dc10d7SGordon Ross I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
545547dc10d7SGordon Ross I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
545647dc10d7SGordon Ross I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
545747dc10d7SGordon Ross
545847dc10d7SGordon Ross if (INTEL_INFO(dev)->gen > 6) {
545947dc10d7SGordon Ross uint16_t postoff = 0;
546047dc10d7SGordon Ross
546147dc10d7SGordon Ross if (intel_crtc->config.limited_color_range)
546247dc10d7SGordon Ross postoff = (16 * (1 << 13) / 255) & 0x1fff;
546347dc10d7SGordon Ross
546447dc10d7SGordon Ross I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
546547dc10d7SGordon Ross I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
546647dc10d7SGordon Ross I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
546747dc10d7SGordon Ross
546847dc10d7SGordon Ross I915_WRITE(PIPE_CSC_MODE(pipe), 0);
546947dc10d7SGordon Ross } else {
547047dc10d7SGordon Ross uint32_t mode = CSC_MODE_YUV_TO_RGB;
547147dc10d7SGordon Ross
547247dc10d7SGordon Ross if (intel_crtc->config.limited_color_range)
547347dc10d7SGordon Ross mode |= CSC_BLACK_SCREEN_OFFSET;
547447dc10d7SGordon Ross
547547dc10d7SGordon Ross I915_WRITE(PIPE_CSC_MODE(pipe), mode);
547647dc10d7SGordon Ross }
547747dc10d7SGordon Ross }
547847dc10d7SGordon Ross
haswell_set_pipeconf(struct drm_crtc * crtc)547947dc10d7SGordon Ross static void haswell_set_pipeconf(struct drm_crtc *crtc)
548047dc10d7SGordon Ross {
548147dc10d7SGordon Ross struct drm_i915_private *dev_priv = crtc->dev->dev_private;
548247dc10d7SGordon Ross struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
548347dc10d7SGordon Ross enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
548447dc10d7SGordon Ross uint32_t val;
548547dc10d7SGordon Ross
548647dc10d7SGordon Ross val = 0;
548747dc10d7SGordon Ross
548847dc10d7SGordon Ross if (intel_crtc->config.dither)
548947dc10d7SGordon Ross val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
549047dc10d7SGordon Ross
549147dc10d7SGordon Ross if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
549247dc10d7SGordon Ross val |= PIPECONF_INTERLACED_ILK;
549347dc10d7SGordon Ross else
549447dc10d7SGordon Ross val |= PIPECONF_PROGRESSIVE;
549547dc10d7SGordon Ross
549647dc10d7SGordon Ross I915_WRITE(PIPECONF(cpu_transcoder), val);
549747dc10d7SGordon Ross POSTING_READ(PIPECONF(cpu_transcoder));
549847dc10d7SGordon Ross
549947dc10d7SGordon Ross I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
550047dc10d7SGordon Ross POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
550147dc10d7SGordon Ross }
550247dc10d7SGordon Ross
ironlake_compute_clocks(struct drm_crtc * crtc,intel_clock_t * clock,bool * has_reduced_clock,intel_clock_t * reduced_clock)550347dc10d7SGordon Ross static bool ironlake_compute_clocks(struct drm_crtc *crtc,
550447dc10d7SGordon Ross intel_clock_t *clock,
550547dc10d7SGordon Ross bool *has_reduced_clock,
550647dc10d7SGordon Ross intel_clock_t *reduced_clock)
550747dc10d7SGordon Ross {
550847dc10d7SGordon Ross struct drm_device *dev = crtc->dev;
550947dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
551047dc10d7SGordon Ross struct intel_encoder *intel_encoder;
551147dc10d7SGordon Ross int refclk;
551247dc10d7SGordon Ross const intel_limit_t *limit;
551347dc10d7SGordon Ross bool ret, is_lvds = false;
551447dc10d7SGordon Ross
551547dc10d7SGordon Ross for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
551647dc10d7SGordon Ross switch (intel_encoder->type) {
551747dc10d7SGordon Ross case INTEL_OUTPUT_LVDS:
551847dc10d7SGordon Ross is_lvds = true;
551947dc10d7SGordon Ross break;
552047dc10d7SGordon Ross }
552147dc10d7SGordon Ross }
552247dc10d7SGordon Ross
552347dc10d7SGordon Ross refclk = ironlake_get_refclk(crtc);
552447dc10d7SGordon Ross
552547dc10d7SGordon Ross /*
552647dc10d7SGordon Ross * Returns a set of divisors for the desired target clock with the given
552747dc10d7SGordon Ross * refclk, or FALSE. The returned values represent the clock equation:
552847dc10d7SGordon Ross * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
552947dc10d7SGordon Ross */
553047dc10d7SGordon Ross limit = intel_limit(crtc, refclk);
553147dc10d7SGordon Ross ret = dev_priv->display.find_dpll(limit, crtc,
553247dc10d7SGordon Ross to_intel_crtc(crtc)->config.port_clock,
553347dc10d7SGordon Ross refclk, NULL, clock);
553447dc10d7SGordon Ross if (!ret)
553547dc10d7SGordon Ross return false;
553647dc10d7SGordon Ross
553747dc10d7SGordon Ross if (is_lvds && dev_priv->lvds_downclock_avail) {
553847dc10d7SGordon Ross /*
553947dc10d7SGordon Ross * Ensure we match the reduced clock's P to the target clock.
554047dc10d7SGordon Ross * If the clocks don't match, we can't switch the display clock
554147dc10d7SGordon Ross * by using the FP0/FP1. In such case we will disable the LVDS
554247dc10d7SGordon Ross * downclock feature.
554347dc10d7SGordon Ross */
554447dc10d7SGordon Ross *has_reduced_clock =
554547dc10d7SGordon Ross dev_priv->display.find_dpll(limit, crtc,
554647dc10d7SGordon Ross dev_priv->lvds_downclock,
554747dc10d7SGordon Ross refclk, clock,
554847dc10d7SGordon Ross reduced_clock);
554947dc10d7SGordon Ross }
555047dc10d7SGordon Ross
555147dc10d7SGordon Ross return true;
555247dc10d7SGordon Ross }
555347dc10d7SGordon Ross
cpt_enable_fdi_bc_bifurcation(struct drm_device * dev)555447dc10d7SGordon Ross static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
555547dc10d7SGordon Ross {
555647dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
555747dc10d7SGordon Ross uint32_t temp;
555847dc10d7SGordon Ross
555947dc10d7SGordon Ross temp = I915_READ(SOUTH_CHICKEN1);
556047dc10d7SGordon Ross if (temp & FDI_BC_BIFURCATION_SELECT)
556147dc10d7SGordon Ross return;
556247dc10d7SGordon Ross
556347dc10d7SGordon Ross WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
556447dc10d7SGordon Ross WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
556547dc10d7SGordon Ross
556647dc10d7SGordon Ross temp |= FDI_BC_BIFURCATION_SELECT;
556747dc10d7SGordon Ross DRM_DEBUG_KMS("enabling fdi C rx\n");
556847dc10d7SGordon Ross I915_WRITE(SOUTH_CHICKEN1, temp);
556947dc10d7SGordon Ross POSTING_READ(SOUTH_CHICKEN1);
557047dc10d7SGordon Ross }
557147dc10d7SGordon Ross
ivybridge_update_fdi_bc_bifurcation(struct intel_crtc * intel_crtc)557247dc10d7SGordon Ross static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
557347dc10d7SGordon Ross {
557447dc10d7SGordon Ross struct drm_device *dev = intel_crtc->base.dev;
557547dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
557647dc10d7SGordon Ross
557747dc10d7SGordon Ross switch (intel_crtc->pipe) {
557847dc10d7SGordon Ross case PIPE_A:
557947dc10d7SGordon Ross break;
558047dc10d7SGordon Ross case PIPE_B:
558147dc10d7SGordon Ross if (intel_crtc->config.fdi_lanes > 2) {
558247dc10d7SGordon Ross WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
558347dc10d7SGordon Ross DRM_DEBUG_KMS("bc_bifurcation select 0x%x", I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
558447dc10d7SGordon Ross } else
558547dc10d7SGordon Ross cpt_enable_fdi_bc_bifurcation(dev);
558647dc10d7SGordon Ross
558747dc10d7SGordon Ross break;
558847dc10d7SGordon Ross case PIPE_C:
558947dc10d7SGordon Ross cpt_enable_fdi_bc_bifurcation(dev);
559047dc10d7SGordon Ross
559147dc10d7SGordon Ross break;
559247dc10d7SGordon Ross default:
559347dc10d7SGordon Ross BUG();
559447dc10d7SGordon Ross }
559547dc10d7SGordon Ross }
559647dc10d7SGordon Ross
ironlake_get_lanes_required(int target_clock,int link_bw,int bpp)559747dc10d7SGordon Ross int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
559847dc10d7SGordon Ross {
559947dc10d7SGordon Ross /*
560047dc10d7SGordon Ross * Account for spread spectrum to avoid
560147dc10d7SGordon Ross * oversubscribing the link. Max center spread
560247dc10d7SGordon Ross * is 2.5%; use 5% for safety's sake.
560347dc10d7SGordon Ross */
560447dc10d7SGordon Ross u32 bps = target_clock * bpp * 21 / 20;
560547dc10d7SGordon Ross return bps / (link_bw * 8) + 1;
560647dc10d7SGordon Ross }
560747dc10d7SGordon Ross
ironlake_needs_fb_cb_tune(struct dpll * dpll,int factor)560847dc10d7SGordon Ross static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
560947dc10d7SGordon Ross {
561047dc10d7SGordon Ross return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
561147dc10d7SGordon Ross }
561247dc10d7SGordon Ross
ironlake_compute_dpll(struct intel_crtc * intel_crtc,u32 * fp,intel_clock_t * reduced_clock,u32 * fp2)561347dc10d7SGordon Ross static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
561447dc10d7SGordon Ross u32 *fp,
561547dc10d7SGordon Ross intel_clock_t *reduced_clock, u32 *fp2)
561647dc10d7SGordon Ross {
561747dc10d7SGordon Ross struct drm_crtc *crtc = &intel_crtc->base;
561847dc10d7SGordon Ross struct drm_device *dev = crtc->dev;
561947dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
562047dc10d7SGordon Ross struct intel_encoder *intel_encoder;
562147dc10d7SGordon Ross uint32_t dpll;
562247dc10d7SGordon Ross int factor, num_connectors = 0;
562347dc10d7SGordon Ross bool is_lvds = false, is_sdvo = false;
562447dc10d7SGordon Ross
562547dc10d7SGordon Ross for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
562647dc10d7SGordon Ross switch (intel_encoder->type) {
562747dc10d7SGordon Ross case INTEL_OUTPUT_LVDS:
562847dc10d7SGordon Ross is_lvds = true;
562947dc10d7SGordon Ross break;
563047dc10d7SGordon Ross case INTEL_OUTPUT_SDVO:
563147dc10d7SGordon Ross case INTEL_OUTPUT_HDMI:
563247dc10d7SGordon Ross is_sdvo = true;
563347dc10d7SGordon Ross break;
563447dc10d7SGordon Ross }
563547dc10d7SGordon Ross
563647dc10d7SGordon Ross num_connectors++;
563747dc10d7SGordon Ross }
563847dc10d7SGordon Ross
563947dc10d7SGordon Ross /* Enable autotuning of the PLL clock (if permissible) */
564047dc10d7SGordon Ross factor = 21;
564147dc10d7SGordon Ross if (is_lvds) {
564247dc10d7SGordon Ross if ((intel_panel_use_ssc(dev_priv) &&
564347dc10d7SGordon Ross dev_priv->vbt.lvds_ssc_freq == 100) ||
564447dc10d7SGordon Ross (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
564547dc10d7SGordon Ross factor = 25;
564647dc10d7SGordon Ross } else if (intel_crtc->config.sdvo_tv_clock)
564747dc10d7SGordon Ross factor = 20;
564847dc10d7SGordon Ross
564947dc10d7SGordon Ross if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
565047dc10d7SGordon Ross *fp |= FP_CB_TUNE;
565147dc10d7SGordon Ross
565247dc10d7SGordon Ross if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
565347dc10d7SGordon Ross *fp2 |= FP_CB_TUNE;
565447dc10d7SGordon Ross
565547dc10d7SGordon Ross dpll = 0;
565647dc10d7SGordon Ross
565747dc10d7SGordon Ross if (is_lvds)
565847dc10d7SGordon Ross dpll |= DPLLB_MODE_LVDS;
565947dc10d7SGordon Ross else
566047dc10d7SGordon Ross dpll |= DPLLB_MODE_DAC_SERIAL;
566147dc10d7SGordon Ross
566247dc10d7SGordon Ross dpll |= (intel_crtc->config.pixel_multiplier - 1)
566347dc10d7SGordon Ross << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
566447dc10d7SGordon Ross
566547dc10d7SGordon Ross if (is_sdvo)
566647dc10d7SGordon Ross dpll |= DPLL_DVO_HIGH_SPEED;
566747dc10d7SGordon Ross if (intel_crtc->config.has_dp_encoder)
566847dc10d7SGordon Ross dpll |= DPLL_DVO_HIGH_SPEED;
566947dc10d7SGordon Ross
567047dc10d7SGordon Ross /* compute bitmask from p1 value */
567147dc10d7SGordon Ross dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
567247dc10d7SGordon Ross /* also FPA1 */
567347dc10d7SGordon Ross dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
567447dc10d7SGordon Ross
567547dc10d7SGordon Ross switch (intel_crtc->config.dpll.p2) {
567647dc10d7SGordon Ross case 5:
567747dc10d7SGordon Ross dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
567847dc10d7SGordon Ross break;
567947dc10d7SGordon Ross case 7:
568047dc10d7SGordon Ross dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
568147dc10d7SGordon Ross break;
568247dc10d7SGordon Ross case 10:
568347dc10d7SGordon Ross dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
568447dc10d7SGordon Ross break;
568547dc10d7SGordon Ross case 14:
568647dc10d7SGordon Ross dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
568747dc10d7SGordon Ross break;
568847dc10d7SGordon Ross }
568947dc10d7SGordon Ross
569047dc10d7SGordon Ross if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
569147dc10d7SGordon Ross dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
569247dc10d7SGordon Ross else
569347dc10d7SGordon Ross dpll |= PLL_REF_INPUT_DREFCLK;
569447dc10d7SGordon Ross
569547dc10d7SGordon Ross return dpll | DPLL_VCO_ENABLE;
569647dc10d7SGordon Ross }
569747dc10d7SGordon Ross
ironlake_crtc_mode_set(struct drm_crtc * crtc,int x,int y,struct drm_framebuffer * fb)569847dc10d7SGordon Ross static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
569947dc10d7SGordon Ross int x, int y,
570047dc10d7SGordon Ross struct drm_framebuffer *fb)
570147dc10d7SGordon Ross {
570247dc10d7SGordon Ross struct drm_device *dev = crtc->dev;
570347dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
570447dc10d7SGordon Ross struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
570547dc10d7SGordon Ross int pipe = intel_crtc->pipe;
570647dc10d7SGordon Ross int plane = intel_crtc->plane;
570747dc10d7SGordon Ross int num_connectors = 0;
570847dc10d7SGordon Ross intel_clock_t clock, reduced_clock;
570947dc10d7SGordon Ross u32 dpll = 0, fp = 0, fp2 = 0;
571047dc10d7SGordon Ross bool ok, has_reduced_clock = false;
571147dc10d7SGordon Ross bool is_lvds = false;
571247dc10d7SGordon Ross struct intel_encoder *encoder;
571347dc10d7SGordon Ross struct intel_shared_dpll *pll;
571447dc10d7SGordon Ross int ret;
571547dc10d7SGordon Ross
571647dc10d7SGordon Ross for_each_encoder_on_crtc(dev, crtc, encoder) {
571747dc10d7SGordon Ross switch (encoder->type) {
571847dc10d7SGordon Ross case INTEL_OUTPUT_LVDS:
571947dc10d7SGordon Ross is_lvds = true;
572047dc10d7SGordon Ross break;
572147dc10d7SGordon Ross }
572247dc10d7SGordon Ross
572347dc10d7SGordon Ross num_connectors++;
572447dc10d7SGordon Ross }
572547dc10d7SGordon Ross
572647dc10d7SGordon Ross if(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)))
572747dc10d7SGordon Ross DRM_ERROR("Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
572847dc10d7SGordon Ross
572947dc10d7SGordon Ross ok = ironlake_compute_clocks(crtc, &clock,
573047dc10d7SGordon Ross &has_reduced_clock, &reduced_clock);
573147dc10d7SGordon Ross if (!ok && !intel_crtc->config.clock_set) {
573247dc10d7SGordon Ross DRM_ERROR("Couldn't find PLL settings for mode!\n");
573347dc10d7SGordon Ross return -EINVAL;
573447dc10d7SGordon Ross }
573547dc10d7SGordon Ross /* Compat-code for transition, will disappear. */
573647dc10d7SGordon Ross if (!intel_crtc->config.clock_set) {
573747dc10d7SGordon Ross intel_crtc->config.dpll.n = clock.n;
573847dc10d7SGordon Ross intel_crtc->config.dpll.m1 = clock.m1;
573947dc10d7SGordon Ross intel_crtc->config.dpll.m2 = clock.m2;
574047dc10d7SGordon Ross intel_crtc->config.dpll.p1 = clock.p1;
574147dc10d7SGordon Ross intel_crtc->config.dpll.p2 = clock.p2;
574247dc10d7SGordon Ross }
574347dc10d7SGordon Ross
574447dc10d7SGordon Ross /* Ensure that the cursor is valid for the new mode before changing... */
574547dc10d7SGordon Ross intel_crtc_update_cursor(crtc, true);
574647dc10d7SGordon Ross
574747dc10d7SGordon Ross /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
574847dc10d7SGordon Ross if (intel_crtc->config.has_pch_encoder) {
574947dc10d7SGordon Ross fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
575047dc10d7SGordon Ross if (has_reduced_clock)
575147dc10d7SGordon Ross fp2 = i9xx_dpll_compute_fp(&reduced_clock);
575247dc10d7SGordon Ross
575347dc10d7SGordon Ross dpll = ironlake_compute_dpll(intel_crtc,
575447dc10d7SGordon Ross &fp, &reduced_clock,
575547dc10d7SGordon Ross has_reduced_clock ? &fp2 : NULL);
575647dc10d7SGordon Ross
575747dc10d7SGordon Ross intel_crtc->config.dpll_hw_state.dpll = dpll;
575847dc10d7SGordon Ross intel_crtc->config.dpll_hw_state.fp0 = fp;
575947dc10d7SGordon Ross if (has_reduced_clock)
576047dc10d7SGordon Ross intel_crtc->config.dpll_hw_state.fp1 = fp2;
576147dc10d7SGordon Ross else
576247dc10d7SGordon Ross intel_crtc->config.dpll_hw_state.fp1 = fp;
576347dc10d7SGordon Ross
576447dc10d7SGordon Ross pll = intel_get_shared_dpll(intel_crtc, dpll, fp);
576547dc10d7SGordon Ross if (pll == NULL) {
576647dc10d7SGordon Ross DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
576747dc10d7SGordon Ross pipe_name(pipe));
576847dc10d7SGordon Ross return -EINVAL;
576947dc10d7SGordon Ross }
577047dc10d7SGordon Ross } else
577147dc10d7SGordon Ross intel_put_shared_dpll(intel_crtc);
577247dc10d7SGordon Ross
577347dc10d7SGordon Ross if (intel_crtc->config.has_dp_encoder)
577447dc10d7SGordon Ross intel_dp_set_m_n(intel_crtc);
577547dc10d7SGordon Ross
577647dc10d7SGordon Ross for_each_encoder_on_crtc(dev, crtc, encoder)
577747dc10d7SGordon Ross if (encoder->pre_pll_enable)
577847dc10d7SGordon Ross encoder->pre_pll_enable(encoder);
577947dc10d7SGordon Ross
578047dc10d7SGordon Ross if (is_lvds && has_reduced_clock && i915_powersave)
578147dc10d7SGordon Ross intel_crtc->lowfreq_avail = true;
578247dc10d7SGordon Ross else
578347dc10d7SGordon Ross intel_crtc->lowfreq_avail = false;
578447dc10d7SGordon Ross
578547dc10d7SGordon Ross if (intel_crtc->config.has_pch_encoder) {
578647dc10d7SGordon Ross pll = intel_crtc_to_shared_dpll(intel_crtc);
578747dc10d7SGordon Ross /*
578847dc10d7SGordon Ross * We previously verified the shared_dpll in the eDP case,
578947dc10d7SGordon Ross * so pll should not be NULL from above call.
579047dc10d7SGordon Ross */
579147dc10d7SGordon Ross BUG_ON(pll == NULL);
579247dc10d7SGordon Ross if (pll == NULL)
579347dc10d7SGordon Ross return -EINVAL;
579447dc10d7SGordon Ross
579547dc10d7SGordon Ross I915_WRITE(PCH_DPLL(pll->id), dpll);
579647dc10d7SGordon Ross
579747dc10d7SGordon Ross /* Wait for the clocks to stabilize. */
579847dc10d7SGordon Ross POSTING_READ(PCH_DPLL(pll->id));
579947dc10d7SGordon Ross udelay(150);
580047dc10d7SGordon Ross
580147dc10d7SGordon Ross /* The pixel multiplier can only be updated once the
580247dc10d7SGordon Ross * DPLL is enabled and the clocks are stable.
580347dc10d7SGordon Ross *
580447dc10d7SGordon Ross * So write it again.
580547dc10d7SGordon Ross */
580647dc10d7SGordon Ross I915_WRITE(PCH_DPLL(pll->id), dpll);
580747dc10d7SGordon Ross
580847dc10d7SGordon Ross if (has_reduced_clock)
580947dc10d7SGordon Ross I915_WRITE(PCH_FP1(pll->id), fp2);
581047dc10d7SGordon Ross else
581147dc10d7SGordon Ross I915_WRITE(PCH_FP1(pll->id), fp);
581247dc10d7SGordon Ross }
581347dc10d7SGordon Ross
581447dc10d7SGordon Ross intel_set_pipe_timings(intel_crtc);
581547dc10d7SGordon Ross
581647dc10d7SGordon Ross if (intel_crtc->config.has_pch_encoder) {
581747dc10d7SGordon Ross intel_cpu_transcoder_set_m_n(intel_crtc,
581847dc10d7SGordon Ross &intel_crtc->config.fdi_m_n);
581947dc10d7SGordon Ross }
582047dc10d7SGordon Ross
582147dc10d7SGordon Ross if (IS_IVYBRIDGE(dev))
582247dc10d7SGordon Ross ivybridge_update_fdi_bc_bifurcation(intel_crtc);
582347dc10d7SGordon Ross
582447dc10d7SGordon Ross ironlake_set_pipeconf(crtc);
582547dc10d7SGordon Ross
582647dc10d7SGordon Ross /* Set up the display plane register */
582747dc10d7SGordon Ross I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
582847dc10d7SGordon Ross POSTING_READ(DSPCNTR(plane));
582947dc10d7SGordon Ross
583047dc10d7SGordon Ross ret = intel_pipe_set_base(crtc, x, y, fb);
583147dc10d7SGordon Ross
583247dc10d7SGordon Ross intel_update_watermarks(dev);
583347dc10d7SGordon Ross
583447dc10d7SGordon Ross return ret;
583547dc10d7SGordon Ross }
583647dc10d7SGordon Ross
ironlake_get_fdi_m_n_config(struct intel_crtc * crtc,struct intel_crtc_config * pipe_config)583747dc10d7SGordon Ross static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
583847dc10d7SGordon Ross struct intel_crtc_config *pipe_config)
583947dc10d7SGordon Ross {
584047dc10d7SGordon Ross struct drm_device *dev = crtc->base.dev;
584147dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
584247dc10d7SGordon Ross enum transcoder transcoder = pipe_config->cpu_transcoder;
584347dc10d7SGordon Ross
584447dc10d7SGordon Ross pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
584547dc10d7SGordon Ross pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
584647dc10d7SGordon Ross pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
584747dc10d7SGordon Ross & ~TU_SIZE_MASK;
584847dc10d7SGordon Ross pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
584947dc10d7SGordon Ross pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
585047dc10d7SGordon Ross & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
585147dc10d7SGordon Ross }
585247dc10d7SGordon Ross
ironlake_get_pfit_config(struct intel_crtc * crtc,struct intel_crtc_config * pipe_config)585347dc10d7SGordon Ross static void ironlake_get_pfit_config(struct intel_crtc *crtc,
585447dc10d7SGordon Ross struct intel_crtc_config *pipe_config)
585547dc10d7SGordon Ross {
585647dc10d7SGordon Ross struct drm_device *dev = crtc->base.dev;
585747dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
585847dc10d7SGordon Ross uint32_t tmp;
585947dc10d7SGordon Ross
586047dc10d7SGordon Ross tmp = I915_READ(PF_CTL(crtc->pipe));
586147dc10d7SGordon Ross
586247dc10d7SGordon Ross if (tmp & PF_ENABLE) {
586347dc10d7SGordon Ross pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
586447dc10d7SGordon Ross pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
586547dc10d7SGordon Ross
586647dc10d7SGordon Ross /* We currently do not free assignements of panel fitters on
586747dc10d7SGordon Ross * ivb/hsw (since we don't use the higher upscaling modes which
586847dc10d7SGordon Ross * differentiates them) so just WARN about this case for now. */
586947dc10d7SGordon Ross if (IS_GEN7(dev)) {
587047dc10d7SGordon Ross WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
587147dc10d7SGordon Ross PF_PIPE_SEL_IVB(crtc->pipe));
587247dc10d7SGordon Ross DRM_DEBUG("PF_CTL(crtc->pipe) 0x%x", tmp);
587347dc10d7SGordon Ross }
587447dc10d7SGordon Ross }
587547dc10d7SGordon Ross }
587647dc10d7SGordon Ross
ironlake_get_pipe_config(struct intel_crtc * crtc,struct intel_crtc_config * pipe_config)587747dc10d7SGordon Ross static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
587847dc10d7SGordon Ross struct intel_crtc_config *pipe_config)
587947dc10d7SGordon Ross {
588047dc10d7SGordon Ross struct drm_device *dev = crtc->base.dev;
588147dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
588247dc10d7SGordon Ross uint32_t tmp;
588347dc10d7SGordon Ross
588447dc10d7SGordon Ross pipe_config->cpu_transcoder = (enum transcoder)crtc->pipe;
588547dc10d7SGordon Ross pipe_config->shared_dpll = DPLL_ID_PRIVATE;
588647dc10d7SGordon Ross
588747dc10d7SGordon Ross tmp = I915_READ(PIPECONF(crtc->pipe));
588847dc10d7SGordon Ross if (!(tmp & PIPECONF_ENABLE))
588947dc10d7SGordon Ross return false;
589047dc10d7SGordon Ross
589147dc10d7SGordon Ross if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
589247dc10d7SGordon Ross /* LINTED */
589347dc10d7SGordon Ross struct intel_shared_dpll *pll;
589447dc10d7SGordon Ross
589547dc10d7SGordon Ross pipe_config->has_pch_encoder = true;
589647dc10d7SGordon Ross
589747dc10d7SGordon Ross tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
589847dc10d7SGordon Ross pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
589947dc10d7SGordon Ross FDI_DP_PORT_WIDTH_SHIFT) + 1;
590047dc10d7SGordon Ross
590147dc10d7SGordon Ross ironlake_get_fdi_m_n_config(crtc, pipe_config);
590247dc10d7SGordon Ross
590347dc10d7SGordon Ross /* XXX: Can't properly read out the pch dpll pixel multiplier
590447dc10d7SGordon Ross * since we don't have state tracking for pch clocks yet. */
590547dc10d7SGordon Ross pipe_config->pixel_multiplier = 1;
590647dc10d7SGordon Ross
590747dc10d7SGordon Ross if (HAS_PCH_IBX(dev_priv->dev)) {
590847dc10d7SGordon Ross pipe_config->shared_dpll = (enum intel_dpll_id)crtc->pipe;
590947dc10d7SGordon Ross } else {
591047dc10d7SGordon Ross tmp = I915_READ(PCH_DPLL_SEL);
591147dc10d7SGordon Ross if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
591247dc10d7SGordon Ross pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
591347dc10d7SGordon Ross else
591447dc10d7SGordon Ross pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
591547dc10d7SGordon Ross }
591647dc10d7SGordon Ross
591747dc10d7SGordon Ross pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
591847dc10d7SGordon Ross
591947dc10d7SGordon Ross WARN_ON(!pll->get_hw_state(dev_priv, pll,
592047dc10d7SGordon Ross &pipe_config->dpll_hw_state));
592147dc10d7SGordon Ross } else {
592247dc10d7SGordon Ross pipe_config->pixel_multiplier = 1;
592347dc10d7SGordon Ross }
592447dc10d7SGordon Ross
592547dc10d7SGordon Ross intel_get_pipe_timings(crtc, pipe_config);
592647dc10d7SGordon Ross
592747dc10d7SGordon Ross ironlake_get_pfit_config(crtc, pipe_config);
592847dc10d7SGordon Ross
592947dc10d7SGordon Ross return true;
593047dc10d7SGordon Ross }
593147dc10d7SGordon Ross
haswell_modeset_global_resources(struct drm_device * dev)593247dc10d7SGordon Ross static void haswell_modeset_global_resources(struct drm_device *dev)
593347dc10d7SGordon Ross {
593447dc10d7SGordon Ross bool enable = false;
593547dc10d7SGordon Ross struct intel_crtc *crtc;
593647dc10d7SGordon Ross
593747dc10d7SGordon Ross list_for_each_entry(crtc, struct intel_crtc, &dev->mode_config.crtc_list, base.head) {
593847dc10d7SGordon Ross if (!crtc->base.enabled)
593947dc10d7SGordon Ross continue;
594047dc10d7SGordon Ross
594147dc10d7SGordon Ross if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.size ||
594247dc10d7SGordon Ross crtc->config.cpu_transcoder != TRANSCODER_EDP)
594347dc10d7SGordon Ross enable = true;
594447dc10d7SGordon Ross }
594547dc10d7SGordon Ross
594647dc10d7SGordon Ross intel_set_power_well(dev, enable);
594747dc10d7SGordon Ross }
594847dc10d7SGordon Ross
haswell_crtc_mode_set(struct drm_crtc * crtc,int x,int y,struct drm_framebuffer * fb)594947dc10d7SGordon Ross static int haswell_crtc_mode_set(struct drm_crtc *crtc,
595047dc10d7SGordon Ross int x, int y,
595147dc10d7SGordon Ross struct drm_framebuffer *fb)
595247dc10d7SGordon Ross {
595347dc10d7SGordon Ross struct drm_device *dev = crtc->dev;
595447dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
595547dc10d7SGordon Ross struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
595647dc10d7SGordon Ross int plane = intel_crtc->plane;
595747dc10d7SGordon Ross int ret;
595847dc10d7SGordon Ross
595947dc10d7SGordon Ross if (!intel_ddi_pll_mode_set(crtc))
596047dc10d7SGordon Ross return -EINVAL;
596147dc10d7SGordon Ross
596247dc10d7SGordon Ross /* Ensure that the cursor is valid for the new mode before changing... */
596347dc10d7SGordon Ross intel_crtc_update_cursor(crtc, true);
596447dc10d7SGordon Ross
596547dc10d7SGordon Ross if (intel_crtc->config.has_dp_encoder)
596647dc10d7SGordon Ross intel_dp_set_m_n(intel_crtc);
596747dc10d7SGordon Ross
596847dc10d7SGordon Ross intel_crtc->lowfreq_avail = false;
596947dc10d7SGordon Ross
597047dc10d7SGordon Ross intel_set_pipe_timings(intel_crtc);
597147dc10d7SGordon Ross
597247dc10d7SGordon Ross if (intel_crtc->config.has_pch_encoder) {
597347dc10d7SGordon Ross intel_cpu_transcoder_set_m_n(intel_crtc,
597447dc10d7SGordon Ross &intel_crtc->config.fdi_m_n);
597547dc10d7SGordon Ross }
597647dc10d7SGordon Ross
597747dc10d7SGordon Ross haswell_set_pipeconf(crtc);
597847dc10d7SGordon Ross
597947dc10d7SGordon Ross intel_set_pipe_csc(crtc);
598047dc10d7SGordon Ross
598147dc10d7SGordon Ross /* Set up the display plane register */
598247dc10d7SGordon Ross I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
598347dc10d7SGordon Ross POSTING_READ(DSPCNTR(plane));
598447dc10d7SGordon Ross
598547dc10d7SGordon Ross ret = intel_pipe_set_base(crtc, x, y, fb);
598647dc10d7SGordon Ross
598747dc10d7SGordon Ross intel_update_watermarks(dev);
598847dc10d7SGordon Ross
598947dc10d7SGordon Ross return ret;
599047dc10d7SGordon Ross }
599147dc10d7SGordon Ross
haswell_get_pipe_config(struct intel_crtc * crtc,struct intel_crtc_config * pipe_config)599247dc10d7SGordon Ross static bool haswell_get_pipe_config(struct intel_crtc *crtc,
599347dc10d7SGordon Ross struct intel_crtc_config *pipe_config)
599447dc10d7SGordon Ross {
599547dc10d7SGordon Ross struct drm_device *dev = crtc->base.dev;
599647dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
599747dc10d7SGordon Ross enum intel_display_power_domain pfit_domain;
599847dc10d7SGordon Ross uint32_t tmp;
599947dc10d7SGordon Ross
600047dc10d7SGordon Ross pipe_config->cpu_transcoder = (enum transcoder)crtc->pipe;
600147dc10d7SGordon Ross pipe_config->shared_dpll = DPLL_ID_PRIVATE;
600247dc10d7SGordon Ross
600347dc10d7SGordon Ross tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
600447dc10d7SGordon Ross if (tmp & TRANS_DDI_FUNC_ENABLE) {
600547dc10d7SGordon Ross enum pipe trans_edp_pipe;
600647dc10d7SGordon Ross switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
600747dc10d7SGordon Ross default:
600847dc10d7SGordon Ross DRM_ERROR("unknown pipe linked to edp transcoder\n");
6009*46b209bcSAurelien Larcher /* FALLTHROUGH */
601047dc10d7SGordon Ross case TRANS_DDI_EDP_INPUT_A_ONOFF:
601147dc10d7SGordon Ross case TRANS_DDI_EDP_INPUT_A_ON:
601247dc10d7SGordon Ross trans_edp_pipe = PIPE_A;
601347dc10d7SGordon Ross break;
601447dc10d7SGordon Ross case TRANS_DDI_EDP_INPUT_B_ONOFF:
601547dc10d7SGordon Ross trans_edp_pipe = PIPE_B;
601647dc10d7SGordon Ross break;
601747dc10d7SGordon Ross case TRANS_DDI_EDP_INPUT_C_ONOFF:
601847dc10d7SGordon Ross trans_edp_pipe = PIPE_C;
601947dc10d7SGordon Ross break;
602047dc10d7SGordon Ross }
602147dc10d7SGordon Ross
602247dc10d7SGordon Ross if (trans_edp_pipe == crtc->pipe)
602347dc10d7SGordon Ross pipe_config->cpu_transcoder = TRANSCODER_EDP;
602447dc10d7SGordon Ross }
602547dc10d7SGordon Ross
602647dc10d7SGordon Ross if (!intel_display_power_enabled(dev,
602747dc10d7SGordon Ross POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
602847dc10d7SGordon Ross return false;
602947dc10d7SGordon Ross
603047dc10d7SGordon Ross tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
603147dc10d7SGordon Ross if (!(tmp & PIPECONF_ENABLE))
603247dc10d7SGordon Ross return false;
603347dc10d7SGordon Ross
603447dc10d7SGordon Ross /*
603547dc10d7SGordon Ross * Haswell has only FDI/PCH transcoder A. It is which is connected to
603647dc10d7SGordon Ross * DDI E. So just check whether this pipe is wired to DDI E and whether
603747dc10d7SGordon Ross * the PCH transcoder is on.
603847dc10d7SGordon Ross */
603947dc10d7SGordon Ross tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
604047dc10d7SGordon Ross if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
604147dc10d7SGordon Ross I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
604247dc10d7SGordon Ross pipe_config->has_pch_encoder = true;
604347dc10d7SGordon Ross
604447dc10d7SGordon Ross tmp = I915_READ(FDI_RX_CTL(PIPE_A));
604547dc10d7SGordon Ross pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
604647dc10d7SGordon Ross FDI_DP_PORT_WIDTH_SHIFT) + 1;
604747dc10d7SGordon Ross
604847dc10d7SGordon Ross ironlake_get_fdi_m_n_config(crtc, pipe_config);
604947dc10d7SGordon Ross }
605047dc10d7SGordon Ross
605147dc10d7SGordon Ross intel_get_pipe_timings(crtc, pipe_config);
605247dc10d7SGordon Ross
605347dc10d7SGordon Ross pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
605447dc10d7SGordon Ross if (intel_display_power_enabled(dev, pfit_domain))
605547dc10d7SGordon Ross ironlake_get_pfit_config(crtc, pipe_config);
605647dc10d7SGordon Ross
605747dc10d7SGordon Ross pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
605847dc10d7SGordon Ross (I915_READ(IPS_CTL) & IPS_ENABLE);
605947dc10d7SGordon Ross
606047dc10d7SGordon Ross pipe_config->pixel_multiplier = 1;
606147dc10d7SGordon Ross
606247dc10d7SGordon Ross return true;
606347dc10d7SGordon Ross }
606447dc10d7SGordon Ross
intel_crtc_mode_set(struct drm_crtc * crtc,int x,int y,struct drm_framebuffer * fb)606547dc10d7SGordon Ross static int intel_crtc_mode_set(struct drm_crtc *crtc,
606647dc10d7SGordon Ross int x, int y,
606747dc10d7SGordon Ross struct drm_framebuffer *fb)
606847dc10d7SGordon Ross {
606947dc10d7SGordon Ross struct drm_device *dev = crtc->dev;
607047dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
607147dc10d7SGordon Ross struct drm_encoder_helper_funcs *encoder_funcs;
607247dc10d7SGordon Ross struct intel_encoder *encoder;
607347dc10d7SGordon Ross struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
607447dc10d7SGordon Ross struct drm_display_mode *adjusted_mode =
607547dc10d7SGordon Ross &intel_crtc->config.adjusted_mode;
607647dc10d7SGordon Ross struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
607747dc10d7SGordon Ross int pipe = intel_crtc->pipe;
607847dc10d7SGordon Ross int ret;
607947dc10d7SGordon Ross
608047dc10d7SGordon Ross drm_vblank_pre_modeset(dev, pipe);
608147dc10d7SGordon Ross
608247dc10d7SGordon Ross ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
608347dc10d7SGordon Ross
608447dc10d7SGordon Ross drm_vblank_post_modeset(dev, pipe);
608547dc10d7SGordon Ross
608647dc10d7SGordon Ross if (ret != 0)
608747dc10d7SGordon Ross return ret;
608847dc10d7SGordon Ross
608947dc10d7SGordon Ross for_each_encoder_on_crtc(dev, crtc, encoder) {
609047dc10d7SGordon Ross DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
609147dc10d7SGordon Ross encoder->base.base.id,
609247dc10d7SGordon Ross drm_get_encoder_name(&encoder->base),
609347dc10d7SGordon Ross mode->base.id, mode->name);
609447dc10d7SGordon Ross if (encoder->mode_set) {
609547dc10d7SGordon Ross encoder->mode_set(encoder);
609647dc10d7SGordon Ross } else {
609747dc10d7SGordon Ross encoder_funcs = encoder->base.helper_private;
609847dc10d7SGordon Ross encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
609947dc10d7SGordon Ross }
610047dc10d7SGordon Ross }
610147dc10d7SGordon Ross
610247dc10d7SGordon Ross return 0;
610347dc10d7SGordon Ross }
610447dc10d7SGordon Ross
intel_eld_uptodate(struct drm_connector * connector,int reg_eldv,uint32_t bits_eldv,int reg_elda,uint32_t bits_elda,int reg_edid)610547dc10d7SGordon Ross static bool intel_eld_uptodate(struct drm_connector *connector,
610647dc10d7SGordon Ross int reg_eldv, uint32_t bits_eldv,
610747dc10d7SGordon Ross int reg_elda, uint32_t bits_elda,
610847dc10d7SGordon Ross int reg_edid)
610947dc10d7SGordon Ross {
611047dc10d7SGordon Ross struct drm_i915_private *dev_priv = connector->dev->dev_private;
611147dc10d7SGordon Ross uint8_t *eld = connector->eld;
611247dc10d7SGordon Ross uint32_t i;
611347dc10d7SGordon Ross
611447dc10d7SGordon Ross i = I915_READ(reg_eldv);
611547dc10d7SGordon Ross i &= bits_eldv;
611647dc10d7SGordon Ross
611747dc10d7SGordon Ross if (!eld[0])
611847dc10d7SGordon Ross return !i;
611947dc10d7SGordon Ross
612047dc10d7SGordon Ross if (!i)
612147dc10d7SGordon Ross return false;
612247dc10d7SGordon Ross
612347dc10d7SGordon Ross i = I915_READ(reg_elda);
612447dc10d7SGordon Ross i &= ~bits_elda;
612547dc10d7SGordon Ross I915_WRITE(reg_elda, i);
612647dc10d7SGordon Ross
612747dc10d7SGordon Ross for (i = 0; i < eld[2]; i++)
612847dc10d7SGordon Ross if (I915_READ(reg_edid) != *((uint32_t *)(uintptr_t)eld + i))
612947dc10d7SGordon Ross return false;
613047dc10d7SGordon Ross
613147dc10d7SGordon Ross return true;
613247dc10d7SGordon Ross }
613347dc10d7SGordon Ross
g4x_write_eld(struct drm_connector * connector,struct drm_crtc * crtc)613447dc10d7SGordon Ross static void g4x_write_eld(struct drm_connector *connector,
613547dc10d7SGordon Ross struct drm_crtc *crtc)
613647dc10d7SGordon Ross {
613747dc10d7SGordon Ross struct drm_i915_private *dev_priv = connector->dev->dev_private;
613847dc10d7SGordon Ross uint8_t *eld = connector->eld;
613947dc10d7SGordon Ross uint32_t eldv;
614047dc10d7SGordon Ross uint32_t len;
614147dc10d7SGordon Ross uint32_t i;
614247dc10d7SGordon Ross
614347dc10d7SGordon Ross i = I915_READ(G4X_AUD_VID_DID);
614447dc10d7SGordon Ross
614547dc10d7SGordon Ross if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
614647dc10d7SGordon Ross eldv = G4X_ELDV_DEVCL_DEVBLC;
614747dc10d7SGordon Ross else
614847dc10d7SGordon Ross eldv = G4X_ELDV_DEVCTG;
614947dc10d7SGordon Ross
615047dc10d7SGordon Ross if (intel_eld_uptodate(connector,
615147dc10d7SGordon Ross G4X_AUD_CNTL_ST, eldv,
615247dc10d7SGordon Ross G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
615347dc10d7SGordon Ross G4X_HDMIW_HDMIEDID))
615447dc10d7SGordon Ross return;
615547dc10d7SGordon Ross
615647dc10d7SGordon Ross i = I915_READ(G4X_AUD_CNTL_ST);
615747dc10d7SGordon Ross i &= ~(eldv | G4X_ELD_ADDR);
615847dc10d7SGordon Ross len = (i >> 9) & 0x1f; /* ELD buffer size */
615947dc10d7SGordon Ross I915_WRITE(G4X_AUD_CNTL_ST, i);
616047dc10d7SGordon Ross
616147dc10d7SGordon Ross if (!eld[0])
616247dc10d7SGordon Ross return;
616347dc10d7SGordon Ross
616447dc10d7SGordon Ross len = min(eld[2], len);
616547dc10d7SGordon Ross DRM_DEBUG_DRIVER("ELD size %d\n", len);
616647dc10d7SGordon Ross for (i = 0; i < len; i++)
616747dc10d7SGordon Ross I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)(uintptr_t)eld + i));
616847dc10d7SGordon Ross
616947dc10d7SGordon Ross i = I915_READ(G4X_AUD_CNTL_ST);
617047dc10d7SGordon Ross i |= eldv;
617147dc10d7SGordon Ross I915_WRITE(G4X_AUD_CNTL_ST, i);
617247dc10d7SGordon Ross }
617347dc10d7SGordon Ross
haswell_write_eld(struct drm_connector * connector,struct drm_crtc * crtc)617447dc10d7SGordon Ross static void haswell_write_eld(struct drm_connector *connector,
617547dc10d7SGordon Ross struct drm_crtc *crtc)
617647dc10d7SGordon Ross {
617747dc10d7SGordon Ross struct drm_i915_private *dev_priv = connector->dev->dev_private;
617847dc10d7SGordon Ross uint8_t *eld = connector->eld;
617947dc10d7SGordon Ross struct drm_device *dev = crtc->dev;
618047dc10d7SGordon Ross struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
618147dc10d7SGordon Ross uint32_t eldv;
618247dc10d7SGordon Ross uint32_t i;
618347dc10d7SGordon Ross int len;
618447dc10d7SGordon Ross int pipe = to_intel_crtc(crtc)->pipe;
618547dc10d7SGordon Ross int tmp;
618647dc10d7SGordon Ross
618747dc10d7SGordon Ross int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
618847dc10d7SGordon Ross int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
618947dc10d7SGordon Ross int aud_config = HSW_AUD_CFG(pipe);
619047dc10d7SGordon Ross int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
619147dc10d7SGordon Ross
619247dc10d7SGordon Ross
619347dc10d7SGordon Ross DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
619447dc10d7SGordon Ross
619547dc10d7SGordon Ross /* Audio output enable */
619647dc10d7SGordon Ross DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
619747dc10d7SGordon Ross tmp = I915_READ(aud_cntrl_st2);
619847dc10d7SGordon Ross tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
619947dc10d7SGordon Ross I915_WRITE(aud_cntrl_st2, tmp);
620047dc10d7SGordon Ross
620147dc10d7SGordon Ross /* Wait for 1 vertical blank */
620247dc10d7SGordon Ross intel_wait_for_vblank(dev, pipe);
620347dc10d7SGordon Ross
620447dc10d7SGordon Ross /* Set ELD valid state */
620547dc10d7SGordon Ross tmp = I915_READ(aud_cntrl_st2);
620647dc10d7SGordon Ross DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
620747dc10d7SGordon Ross tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
620847dc10d7SGordon Ross I915_WRITE(aud_cntrl_st2, tmp);
620947dc10d7SGordon Ross tmp = I915_READ(aud_cntrl_st2);
621047dc10d7SGordon Ross DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
621147dc10d7SGordon Ross
621247dc10d7SGordon Ross /* Enable HDMI mode */
621347dc10d7SGordon Ross tmp = I915_READ(aud_config);
621447dc10d7SGordon Ross DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
621547dc10d7SGordon Ross /* clear N_programing_enable and N_value_index */
621647dc10d7SGordon Ross tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
621747dc10d7SGordon Ross I915_WRITE(aud_config, tmp);
621847dc10d7SGordon Ross
621947dc10d7SGordon Ross DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
622047dc10d7SGordon Ross
622147dc10d7SGordon Ross eldv = AUDIO_ELD_VALID_A << (pipe * 4);
622247dc10d7SGordon Ross intel_crtc->eld_vld = true;
622347dc10d7SGordon Ross
622447dc10d7SGordon Ross if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
622547dc10d7SGordon Ross DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
622647dc10d7SGordon Ross eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
622747dc10d7SGordon Ross I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
622847dc10d7SGordon Ross } else
622947dc10d7SGordon Ross I915_WRITE(aud_config, 0);
623047dc10d7SGordon Ross
623147dc10d7SGordon Ross if (intel_eld_uptodate(connector,
623247dc10d7SGordon Ross aud_cntrl_st2, eldv,
623347dc10d7SGordon Ross aud_cntl_st, IBX_ELD_ADDRESS,
623447dc10d7SGordon Ross hdmiw_hdmiedid))
623547dc10d7SGordon Ross return;
623647dc10d7SGordon Ross
623747dc10d7SGordon Ross i = I915_READ(aud_cntrl_st2);
623847dc10d7SGordon Ross i &= ~eldv;
623947dc10d7SGordon Ross I915_WRITE(aud_cntrl_st2, i);
624047dc10d7SGordon Ross
624147dc10d7SGordon Ross if (!eld[0])
624247dc10d7SGordon Ross return;
624347dc10d7SGordon Ross
624447dc10d7SGordon Ross i = I915_READ(aud_cntl_st);
624547dc10d7SGordon Ross i &= ~IBX_ELD_ADDRESS;
624647dc10d7SGordon Ross I915_WRITE(aud_cntl_st, i);
624747dc10d7SGordon Ross i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
624847dc10d7SGordon Ross DRM_DEBUG_DRIVER("port num:%d\n", i);
624947dc10d7SGordon Ross
625047dc10d7SGordon Ross len = min(eld[2], 21); /* 84 bytes of hw ELD buffer */
625147dc10d7SGordon Ross DRM_DEBUG_DRIVER("ELD size %d\n", len);
625247dc10d7SGordon Ross for (i = 0; i < len; i++)
625347dc10d7SGordon Ross I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)(uintptr_t)(eld + i)));
625447dc10d7SGordon Ross
625547dc10d7SGordon Ross i = I915_READ(aud_cntrl_st2);
625647dc10d7SGordon Ross i |= eldv;
625747dc10d7SGordon Ross I915_WRITE(aud_cntrl_st2, i);
625847dc10d7SGordon Ross
625947dc10d7SGordon Ross }
626047dc10d7SGordon Ross
ironlake_write_eld(struct drm_connector * connector,struct drm_crtc * crtc)626147dc10d7SGordon Ross static void ironlake_write_eld(struct drm_connector *connector,
626247dc10d7SGordon Ross struct drm_crtc *crtc)
626347dc10d7SGordon Ross {
626447dc10d7SGordon Ross struct drm_i915_private *dev_priv = connector->dev->dev_private;
626547dc10d7SGordon Ross uint8_t *eld = connector->eld;
626647dc10d7SGordon Ross uint32_t eldv;
626747dc10d7SGordon Ross uint32_t i;
626847dc10d7SGordon Ross int len;
626947dc10d7SGordon Ross int hdmiw_hdmiedid;
627047dc10d7SGordon Ross int aud_config;
627147dc10d7SGordon Ross int aud_cntl_st;
627247dc10d7SGordon Ross int aud_cntrl_st2;
627347dc10d7SGordon Ross int pipe = to_intel_crtc(crtc)->pipe;
627447dc10d7SGordon Ross
627547dc10d7SGordon Ross if (HAS_PCH_IBX(connector->dev)) {
627647dc10d7SGordon Ross hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
627747dc10d7SGordon Ross aud_config = IBX_AUD_CFG(pipe);
627847dc10d7SGordon Ross aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
627947dc10d7SGordon Ross aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
628047dc10d7SGordon Ross } else {
628147dc10d7SGordon Ross hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
628247dc10d7SGordon Ross aud_config = CPT_AUD_CFG(pipe);
628347dc10d7SGordon Ross aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
628447dc10d7SGordon Ross aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
628547dc10d7SGordon Ross }
628647dc10d7SGordon Ross
628747dc10d7SGordon Ross DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
628847dc10d7SGordon Ross
628947dc10d7SGordon Ross i = I915_READ(aud_cntl_st);
629047dc10d7SGordon Ross i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
629147dc10d7SGordon Ross if (!i) {
629247dc10d7SGordon Ross DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
629347dc10d7SGordon Ross /* operate blindly on all ports */
629447dc10d7SGordon Ross eldv = IBX_ELD_VALIDB;
629547dc10d7SGordon Ross eldv |= IBX_ELD_VALIDB << 4;
629647dc10d7SGordon Ross eldv |= IBX_ELD_VALIDB << 8;
629747dc10d7SGordon Ross } else {
629847dc10d7SGordon Ross DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
629947dc10d7SGordon Ross eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
630047dc10d7SGordon Ross }
630147dc10d7SGordon Ross
630247dc10d7SGordon Ross if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
630347dc10d7SGordon Ross DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
630447dc10d7SGordon Ross eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
630547dc10d7SGordon Ross I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
630647dc10d7SGordon Ross } else
630747dc10d7SGordon Ross I915_WRITE(aud_config, 0);
630847dc10d7SGordon Ross
630947dc10d7SGordon Ross if (intel_eld_uptodate(connector,
631047dc10d7SGordon Ross aud_cntrl_st2, eldv,
631147dc10d7SGordon Ross aud_cntl_st, IBX_ELD_ADDRESS,
631247dc10d7SGordon Ross hdmiw_hdmiedid))
631347dc10d7SGordon Ross return;
631447dc10d7SGordon Ross
631547dc10d7SGordon Ross i = I915_READ(aud_cntrl_st2);
631647dc10d7SGordon Ross i &= ~eldv;
631747dc10d7SGordon Ross I915_WRITE(aud_cntrl_st2, i);
631847dc10d7SGordon Ross
631947dc10d7SGordon Ross if (!eld[0])
632047dc10d7SGordon Ross return;
632147dc10d7SGordon Ross
632247dc10d7SGordon Ross i = I915_READ(aud_cntl_st);
632347dc10d7SGordon Ross i &= ~IBX_ELD_ADDRESS;
632447dc10d7SGordon Ross I915_WRITE(aud_cntl_st, i);
632547dc10d7SGordon Ross
632647dc10d7SGordon Ross len = min(eld[2], 21); /* 84 bytes of hw ELD buffer */
632747dc10d7SGordon Ross DRM_DEBUG_DRIVER("ELD size %d\n", len);
632847dc10d7SGordon Ross for (i = 0; i < len; i++)
632947dc10d7SGordon Ross I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)(uintptr_t)eld + i));
633047dc10d7SGordon Ross
633147dc10d7SGordon Ross i = I915_READ(aud_cntrl_st2);
633247dc10d7SGordon Ross i |= eldv;
633347dc10d7SGordon Ross I915_WRITE(aud_cntrl_st2, i);
633447dc10d7SGordon Ross }
633547dc10d7SGordon Ross
intel_write_eld(struct drm_encoder * encoder,struct drm_display_mode * mode)633647dc10d7SGordon Ross void intel_write_eld(struct drm_encoder *encoder,
633747dc10d7SGordon Ross struct drm_display_mode *mode)
633847dc10d7SGordon Ross {
633947dc10d7SGordon Ross struct drm_crtc *crtc = encoder->crtc;
634047dc10d7SGordon Ross struct drm_connector *connector;
634147dc10d7SGordon Ross struct drm_device *dev = encoder->dev;
634247dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
634347dc10d7SGordon Ross
634447dc10d7SGordon Ross connector = drm_select_eld(encoder, mode);
634547dc10d7SGordon Ross if (!connector)
634647dc10d7SGordon Ross return;
634747dc10d7SGordon Ross
634847dc10d7SGordon Ross DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
634947dc10d7SGordon Ross connector->base.id,
635047dc10d7SGordon Ross drm_get_connector_name(connector),
635147dc10d7SGordon Ross connector->encoder->base.id,
635247dc10d7SGordon Ross drm_get_encoder_name(connector->encoder));
635347dc10d7SGordon Ross
635447dc10d7SGordon Ross connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
635547dc10d7SGordon Ross
635647dc10d7SGordon Ross if (dev_priv->display.write_eld)
635747dc10d7SGordon Ross dev_priv->display.write_eld(connector, crtc);
635847dc10d7SGordon Ross }
635947dc10d7SGordon Ross
636047dc10d7SGordon Ross /** Loads the palette/gamma unit for the CRTC with the prepared values */
intel_crtc_load_lut(struct drm_crtc * crtc)636147dc10d7SGordon Ross void intel_crtc_load_lut(struct drm_crtc *crtc)
636247dc10d7SGordon Ross {
636347dc10d7SGordon Ross struct drm_device *dev = crtc->dev;
636447dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
636547dc10d7SGordon Ross struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
636647dc10d7SGordon Ross enum pipe pipe = intel_crtc->pipe;
636747dc10d7SGordon Ross int palreg = PALETTE(pipe);
636847dc10d7SGordon Ross int i;
636947dc10d7SGordon Ross bool reenable_ips = false;
637047dc10d7SGordon Ross
637147dc10d7SGordon Ross /* The clocks have to be on to load the palette. */
637247dc10d7SGordon Ross if (!crtc->enabled || !intel_crtc->active)
637347dc10d7SGordon Ross return;
637447dc10d7SGordon Ross
637547dc10d7SGordon Ross if (!HAS_PCH_SPLIT(dev_priv->dev))
637647dc10d7SGordon Ross assert_pll_enabled(dev_priv, pipe);
637747dc10d7SGordon Ross
637847dc10d7SGordon Ross /* use legacy palette for Ironlake */
637947dc10d7SGordon Ross if (HAS_PCH_SPLIT(dev))
638047dc10d7SGordon Ross palreg = LGC_PALETTE(pipe);
638147dc10d7SGordon Ross
638247dc10d7SGordon Ross /* Workaround : Do not read or write the pipe palette/gamma data while
638347dc10d7SGordon Ross * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
638447dc10d7SGordon Ross */
638547dc10d7SGordon Ross if (intel_crtc->config.ips_enabled &&
638647dc10d7SGordon Ross ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
638747dc10d7SGordon Ross GAMMA_MODE_MODE_SPLIT)) {
638847dc10d7SGordon Ross hsw_disable_ips(intel_crtc);
638947dc10d7SGordon Ross reenable_ips = true;
639047dc10d7SGordon Ross }
639147dc10d7SGordon Ross
639247dc10d7SGordon Ross for (i = 0; i < 256; i++) {
639347dc10d7SGordon Ross I915_WRITE(palreg + 4 * i,
639447dc10d7SGordon Ross (intel_crtc->lut_r[i] << 16) |
639547dc10d7SGordon Ross (intel_crtc->lut_g[i] << 8) |
639647dc10d7SGordon Ross intel_crtc->lut_b[i]);
639747dc10d7SGordon Ross }
639847dc10d7SGordon Ross
639947dc10d7SGordon Ross if (reenable_ips)
640047dc10d7SGordon Ross hsw_enable_ips(intel_crtc);
640147dc10d7SGordon Ross }
640247dc10d7SGordon Ross
i845_update_cursor(struct drm_crtc * crtc,u32 base)640347dc10d7SGordon Ross static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
640447dc10d7SGordon Ross {
640547dc10d7SGordon Ross struct drm_device *dev = crtc->dev;
640647dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
640747dc10d7SGordon Ross struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
640847dc10d7SGordon Ross bool visible = base != 0;
640947dc10d7SGordon Ross u32 cntl;
641047dc10d7SGordon Ross
641147dc10d7SGordon Ross if (intel_crtc->cursor_visible == visible)
641247dc10d7SGordon Ross return;
641347dc10d7SGordon Ross
641447dc10d7SGordon Ross cntl = I915_READ(_CURACNTR);
641547dc10d7SGordon Ross if (visible) {
641647dc10d7SGordon Ross /* On these chipsets we can only modify the base whilst
641747dc10d7SGordon Ross * the cursor is disabled.
641847dc10d7SGordon Ross */
641947dc10d7SGordon Ross I915_WRITE(_CURABASE, base);
642047dc10d7SGordon Ross
642147dc10d7SGordon Ross cntl &= ~(CURSOR_FORMAT_MASK);
642247dc10d7SGordon Ross /* XXX width must be 64, stride 256 => 0x00 << 28 */
642347dc10d7SGordon Ross cntl |= CURSOR_ENABLE |
642447dc10d7SGordon Ross CURSOR_GAMMA_ENABLE |
642547dc10d7SGordon Ross CURSOR_FORMAT_ARGB;
642647dc10d7SGordon Ross } else
642747dc10d7SGordon Ross cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
642847dc10d7SGordon Ross I915_WRITE(_CURACNTR, cntl);
642947dc10d7SGordon Ross
643047dc10d7SGordon Ross intel_crtc->cursor_visible = visible;
643147dc10d7SGordon Ross }
643247dc10d7SGordon Ross
i9xx_update_cursor(struct drm_crtc * crtc,u32 base)643347dc10d7SGordon Ross static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
643447dc10d7SGordon Ross {
643547dc10d7SGordon Ross struct drm_device *dev = crtc->dev;
643647dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
643747dc10d7SGordon Ross struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
643847dc10d7SGordon Ross int pipe = intel_crtc->pipe;
643947dc10d7SGordon Ross bool visible = base != 0;
644047dc10d7SGordon Ross
644147dc10d7SGordon Ross if (intel_crtc->cursor_visible != visible) {
644247dc10d7SGordon Ross uint32_t cntl = I915_READ(CURCNTR(pipe));
644347dc10d7SGordon Ross if (base) {
644447dc10d7SGordon Ross cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
644547dc10d7SGordon Ross cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
644647dc10d7SGordon Ross cntl |= pipe << 28; /* Connect to correct pipe */
644747dc10d7SGordon Ross } else {
644847dc10d7SGordon Ross cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
644947dc10d7SGordon Ross cntl |= CURSOR_MODE_DISABLE;
645047dc10d7SGordon Ross }
645147dc10d7SGordon Ross I915_WRITE(CURCNTR(pipe), cntl);
645247dc10d7SGordon Ross
645347dc10d7SGordon Ross intel_crtc->cursor_visible = visible;
645447dc10d7SGordon Ross }
645547dc10d7SGordon Ross /* and commit changes on next vblank */
645647dc10d7SGordon Ross I915_WRITE(CURBASE(pipe), base);
645747dc10d7SGordon Ross }
645847dc10d7SGordon Ross
ivb_update_cursor(struct drm_crtc * crtc,u32 base)645947dc10d7SGordon Ross static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
646047dc10d7SGordon Ross {
646147dc10d7SGordon Ross struct drm_device *dev = crtc->dev;
646247dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
646347dc10d7SGordon Ross struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
646447dc10d7SGordon Ross int pipe = intel_crtc->pipe;
646547dc10d7SGordon Ross bool visible = base != 0;
646647dc10d7SGordon Ross
646747dc10d7SGordon Ross if (intel_crtc->cursor_visible != visible) {
646847dc10d7SGordon Ross uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
646947dc10d7SGordon Ross if (base) {
647047dc10d7SGordon Ross cntl &= ~CURSOR_MODE;
647147dc10d7SGordon Ross cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
647247dc10d7SGordon Ross } else {
647347dc10d7SGordon Ross cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
647447dc10d7SGordon Ross cntl |= CURSOR_MODE_DISABLE;
647547dc10d7SGordon Ross }
647647dc10d7SGordon Ross if (IS_HASWELL(dev))
647747dc10d7SGordon Ross cntl |= CURSOR_PIPE_CSC_ENABLE;
647847dc10d7SGordon Ross I915_WRITE(CURCNTR_IVB(pipe), cntl);
647947dc10d7SGordon Ross
648047dc10d7SGordon Ross intel_crtc->cursor_visible = visible;
648147dc10d7SGordon Ross }
648247dc10d7SGordon Ross /* and commit changes on next vblank */
648347dc10d7SGordon Ross I915_WRITE(CURBASE_IVB(pipe), base);
648447dc10d7SGordon Ross }
648547dc10d7SGordon Ross
648647dc10d7SGordon Ross /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
intel_crtc_update_cursor(struct drm_crtc * crtc,bool on)648747dc10d7SGordon Ross static void intel_crtc_update_cursor(struct drm_crtc *crtc,
648847dc10d7SGordon Ross bool on)
648947dc10d7SGordon Ross {
649047dc10d7SGordon Ross struct drm_device *dev = crtc->dev;
649147dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
649247dc10d7SGordon Ross struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
649347dc10d7SGordon Ross int pipe = intel_crtc->pipe;
649447dc10d7SGordon Ross int x = intel_crtc->cursor_x;
649547dc10d7SGordon Ross int y = intel_crtc->cursor_y;
649647dc10d7SGordon Ross u32 base, pos;
649747dc10d7SGordon Ross bool visible;
649847dc10d7SGordon Ross
649947dc10d7SGordon Ross pos = 0;
650047dc10d7SGordon Ross
650147dc10d7SGordon Ross if (on && crtc->enabled && crtc->fb) {
650247dc10d7SGordon Ross base = intel_crtc->cursor_addr;
650347dc10d7SGordon Ross if (x > (int) crtc->fb->width)
650447dc10d7SGordon Ross base = 0;
650547dc10d7SGordon Ross
650647dc10d7SGordon Ross if (y > (int) crtc->fb->height)
650747dc10d7SGordon Ross base = 0;
650847dc10d7SGordon Ross } else
650947dc10d7SGordon Ross base = 0;
651047dc10d7SGordon Ross
651147dc10d7SGordon Ross if (x < 0) {
651247dc10d7SGordon Ross if (x + intel_crtc->cursor_width < 0)
651347dc10d7SGordon Ross base = 0;
651447dc10d7SGordon Ross
651547dc10d7SGordon Ross pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
651647dc10d7SGordon Ross x = -x;
651747dc10d7SGordon Ross }
651847dc10d7SGordon Ross pos |= x << CURSOR_X_SHIFT;
651947dc10d7SGordon Ross
652047dc10d7SGordon Ross if (y < 0) {
652147dc10d7SGordon Ross if (y + intel_crtc->cursor_height < 0)
652247dc10d7SGordon Ross base = 0;
652347dc10d7SGordon Ross
652447dc10d7SGordon Ross pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
652547dc10d7SGordon Ross y = -y;
652647dc10d7SGordon Ross }
652747dc10d7SGordon Ross pos |= y << CURSOR_Y_SHIFT;
652847dc10d7SGordon Ross
652947dc10d7SGordon Ross visible = base != 0;
653047dc10d7SGordon Ross if (!visible && !intel_crtc->cursor_visible)
653147dc10d7SGordon Ross return;
653247dc10d7SGordon Ross
653347dc10d7SGordon Ross if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
653447dc10d7SGordon Ross I915_WRITE(CURPOS_IVB(pipe), pos);
653547dc10d7SGordon Ross ivb_update_cursor(crtc, base);
653647dc10d7SGordon Ross } else {
653747dc10d7SGordon Ross I915_WRITE(CURPOS(pipe), pos);
653847dc10d7SGordon Ross if (IS_845G(dev) || IS_I865G(dev))
653947dc10d7SGordon Ross i845_update_cursor(crtc, base);
654047dc10d7SGordon Ross else
654147dc10d7SGordon Ross i9xx_update_cursor(crtc, base);
654247dc10d7SGordon Ross }
654347dc10d7SGordon Ross }
654447dc10d7SGordon Ross
intel_crtc_cursor_set(struct drm_crtc * crtc,struct drm_file * file,uint32_t handle,uint32_t width,uint32_t height)654547dc10d7SGordon Ross static int intel_crtc_cursor_set(struct drm_crtc *crtc,
654647dc10d7SGordon Ross struct drm_file *file,
654747dc10d7SGordon Ross uint32_t handle,
654847dc10d7SGordon Ross uint32_t width, uint32_t height)
654947dc10d7SGordon Ross {
655047dc10d7SGordon Ross struct drm_device *dev = crtc->dev;
655147dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
655247dc10d7SGordon Ross struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
655347dc10d7SGordon Ross struct drm_i915_gem_object *obj;
655447dc10d7SGordon Ross uint32_t addr;
655547dc10d7SGordon Ross int ret;
655647dc10d7SGordon Ross
655747dc10d7SGordon Ross /* if we want to turn off the cursor ignore width and height */
655847dc10d7SGordon Ross if (!handle) {
655947dc10d7SGordon Ross DRM_DEBUG_KMS("cursor off\n");
656047dc10d7SGordon Ross addr = 0;
656147dc10d7SGordon Ross obj = NULL;
656247dc10d7SGordon Ross mutex_lock(&dev->struct_mutex);
656347dc10d7SGordon Ross goto finish;
656447dc10d7SGordon Ross }
656547dc10d7SGordon Ross
656647dc10d7SGordon Ross /* Currently we only support 64x64 cursors */
656747dc10d7SGordon Ross if (width != 64 || height != 64) {
656847dc10d7SGordon Ross DRM_ERROR("we currently only support 64x64 cursors\n");
656947dc10d7SGordon Ross return -EINVAL;
657047dc10d7SGordon Ross }
657147dc10d7SGordon Ross
657247dc10d7SGordon Ross obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
657347dc10d7SGordon Ross if (&obj->base == NULL)
657447dc10d7SGordon Ross return -ENOENT;
657547dc10d7SGordon Ross
657647dc10d7SGordon Ross if (obj->base.size < width * height * 4) {
657747dc10d7SGordon Ross DRM_ERROR("buffer is to small\n");
657847dc10d7SGordon Ross ret = -ENOMEM;
657947dc10d7SGordon Ross goto fail;
658047dc10d7SGordon Ross }
658147dc10d7SGordon Ross
658247dc10d7SGordon Ross /* we only need to pin inside GTT if cursor is non-phy */
658347dc10d7SGordon Ross mutex_lock(&dev->struct_mutex);
658447dc10d7SGordon Ross if (!dev_priv->info->cursor_needs_physical) {
658547dc10d7SGordon Ross unsigned alignment;
658647dc10d7SGordon Ross
658747dc10d7SGordon Ross if (obj->tiling_mode) {
658847dc10d7SGordon Ross DRM_ERROR("cursor cannot be tiled\n");
658947dc10d7SGordon Ross ret = -EINVAL;
659047dc10d7SGordon Ross goto fail_locked;
659147dc10d7SGordon Ross }
659247dc10d7SGordon Ross
659347dc10d7SGordon Ross /* Note that the w/a also requires 2 PTE of padding following
659447dc10d7SGordon Ross * the bo. We currently fill all unused PTE with the shadow
659547dc10d7SGordon Ross * page and so we should always have valid PTE following the
659647dc10d7SGordon Ross * cursor preventing the VT-d warning.
659747dc10d7SGordon Ross */
659847dc10d7SGordon Ross alignment = 0;
659947dc10d7SGordon Ross if (need_vtd_wa(dev))
660047dc10d7SGordon Ross alignment = 64*1024;
660147dc10d7SGordon Ross
660247dc10d7SGordon Ross ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
660347dc10d7SGordon Ross if (ret) {
660447dc10d7SGordon Ross DRM_ERROR("failed to move cursor bo into the GTT\n");
660547dc10d7SGordon Ross goto fail_locked;
660647dc10d7SGordon Ross }
660747dc10d7SGordon Ross
660847dc10d7SGordon Ross ret = i915_gem_object_put_fence(obj);
660947dc10d7SGordon Ross if (ret) {
661047dc10d7SGordon Ross DRM_ERROR("failed to release fence for cursor");
661147dc10d7SGordon Ross goto fail_unpin;
661247dc10d7SGordon Ross }
661347dc10d7SGordon Ross
661447dc10d7SGordon Ross addr = obj->gtt_offset;
661547dc10d7SGordon Ross obj->is_cursor = 1;
661647dc10d7SGordon Ross } else {
661747dc10d7SGordon Ross int align = IS_I830(dev) ? 16 * 1024 : 256;
661847dc10d7SGordon Ross ret = i915_gem_attach_phys_object(dev, obj,
661947dc10d7SGordon Ross (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
662047dc10d7SGordon Ross align);
662147dc10d7SGordon Ross if (ret) {
662247dc10d7SGordon Ross DRM_ERROR("failed to attach phys object\n");
662347dc10d7SGordon Ross goto fail_locked;
662447dc10d7SGordon Ross }
662547dc10d7SGordon Ross addr = obj->phys_obj->handle->paddr;
662647dc10d7SGordon Ross }
662747dc10d7SGordon Ross
662847dc10d7SGordon Ross if (IS_GEN2(dev))
662947dc10d7SGordon Ross I915_WRITE(CURSIZE, (height << 12) | width);
663047dc10d7SGordon Ross
663147dc10d7SGordon Ross finish:
663247dc10d7SGordon Ross if (intel_crtc->cursor_bo) {
663347dc10d7SGordon Ross if (dev_priv->info->cursor_needs_physical) {
663447dc10d7SGordon Ross if (intel_crtc->cursor_bo != obj)
663547dc10d7SGordon Ross i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
663647dc10d7SGordon Ross } else
663747dc10d7SGordon Ross i915_gem_object_unpin(intel_crtc->cursor_bo);
663847dc10d7SGordon Ross drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
663947dc10d7SGordon Ross }
664047dc10d7SGordon Ross
664147dc10d7SGordon Ross mutex_unlock(&dev->struct_mutex);
664247dc10d7SGordon Ross
664347dc10d7SGordon Ross intel_crtc->cursor_addr = addr;
664447dc10d7SGordon Ross intel_crtc->cursor_bo = obj;
664547dc10d7SGordon Ross intel_crtc->cursor_width = (int16_t)width;
664647dc10d7SGordon Ross intel_crtc->cursor_height = (int16_t)height;
664747dc10d7SGordon Ross
664847dc10d7SGordon Ross intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
664947dc10d7SGordon Ross
665047dc10d7SGordon Ross return 0;
665147dc10d7SGordon Ross fail_unpin:
665247dc10d7SGordon Ross i915_gem_object_unpin(obj);
665347dc10d7SGordon Ross fail_locked:
665447dc10d7SGordon Ross mutex_unlock(&dev->struct_mutex);
665547dc10d7SGordon Ross fail:
665647dc10d7SGordon Ross drm_gem_object_unreference_unlocked(&obj->base);
665747dc10d7SGordon Ross return ret;
665847dc10d7SGordon Ross }
665947dc10d7SGordon Ross
intel_crtc_cursor_move(struct drm_crtc * crtc,int x,int y)666047dc10d7SGordon Ross static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
666147dc10d7SGordon Ross {
666247dc10d7SGordon Ross struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
666347dc10d7SGordon Ross
666447dc10d7SGordon Ross intel_crtc->cursor_x = (int16_t)x;
666547dc10d7SGordon Ross intel_crtc->cursor_y = (int16_t)y;
666647dc10d7SGordon Ross
666747dc10d7SGordon Ross intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
666847dc10d7SGordon Ross
666947dc10d7SGordon Ross return 0;
667047dc10d7SGordon Ross }
667147dc10d7SGordon Ross
667247dc10d7SGordon Ross /** Sets the color ramps on behalf of RandR */
intel_crtc_fb_gamma_set(struct drm_crtc * crtc,u16 red,u16 green,u16 blue,int regno)667347dc10d7SGordon Ross void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
667447dc10d7SGordon Ross u16 blue, int regno)
667547dc10d7SGordon Ross {
667647dc10d7SGordon Ross struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
667747dc10d7SGordon Ross
667847dc10d7SGordon Ross intel_crtc->lut_r[regno] = red >> 8;
667947dc10d7SGordon Ross intel_crtc->lut_g[regno] = green >> 8;
668047dc10d7SGordon Ross intel_crtc->lut_b[regno] = blue >> 8;
668147dc10d7SGordon Ross }
668247dc10d7SGordon Ross
intel_crtc_fb_gamma_get(struct drm_crtc * crtc,u16 * red,u16 * green,u16 * blue,int regno)668347dc10d7SGordon Ross void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
668447dc10d7SGordon Ross u16 *blue, int regno)
668547dc10d7SGordon Ross {
668647dc10d7SGordon Ross struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
668747dc10d7SGordon Ross
668847dc10d7SGordon Ross *red = intel_crtc->lut_r[regno] << 8;
668947dc10d7SGordon Ross *green = intel_crtc->lut_g[regno] << 8;
669047dc10d7SGordon Ross *blue = intel_crtc->lut_b[regno] << 8;
669147dc10d7SGordon Ross }
669247dc10d7SGordon Ross
intel_crtc_gamma_set(struct drm_crtc * crtc,u16 * red,u16 * green,u16 * blue,uint32_t start,uint32_t size)669347dc10d7SGordon Ross static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
669447dc10d7SGordon Ross u16 *blue, uint32_t start, uint32_t size)
669547dc10d7SGordon Ross {
669647dc10d7SGordon Ross int end = (start + size > 256) ? 256 : start + size, i;
669747dc10d7SGordon Ross struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
669847dc10d7SGordon Ross
669947dc10d7SGordon Ross for (i = start; i < end; i++) {
670047dc10d7SGordon Ross intel_crtc->lut_r[i] = red[i] >> 8;
670147dc10d7SGordon Ross intel_crtc->lut_g[i] = green[i] >> 8;
670247dc10d7SGordon Ross intel_crtc->lut_b[i] = blue[i] >> 8;
670347dc10d7SGordon Ross }
670447dc10d7SGordon Ross
670547dc10d7SGordon Ross intel_crtc_load_lut(crtc);
670647dc10d7SGordon Ross }
670747dc10d7SGordon Ross
670847dc10d7SGordon Ross /* VESA 640x480x72Hz mode to set on the pipe */
670947dc10d7SGordon Ross static struct drm_display_mode load_detect_mode = {
671047dc10d7SGordon Ross DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
671147dc10d7SGordon Ross 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
671247dc10d7SGordon Ross };
671347dc10d7SGordon Ross
671447dc10d7SGordon Ross static struct drm_framebuffer *
intel_framebuffer_create(struct drm_device * dev,struct drm_mode_fb_cmd2 * mode_cmd,struct drm_i915_gem_object * obj)671547dc10d7SGordon Ross intel_framebuffer_create(struct drm_device *dev,
671647dc10d7SGordon Ross struct drm_mode_fb_cmd2 *mode_cmd,
671747dc10d7SGordon Ross struct drm_i915_gem_object *obj)
671847dc10d7SGordon Ross {
671947dc10d7SGordon Ross struct intel_framebuffer *intel_fb;
672047dc10d7SGordon Ross int ret;
672147dc10d7SGordon Ross
672247dc10d7SGordon Ross intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
672347dc10d7SGordon Ross if (!intel_fb) {
672447dc10d7SGordon Ross drm_gem_object_unreference_unlocked(&obj->base);
672547dc10d7SGordon Ross return (NULL);
672647dc10d7SGordon Ross }
672747dc10d7SGordon Ross
672847dc10d7SGordon Ross ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
672947dc10d7SGordon Ross if (ret) {
673047dc10d7SGordon Ross drm_gem_object_unreference_unlocked(&obj->base);
673147dc10d7SGordon Ross kfree(intel_fb, sizeof(struct intel_framebuffer));
673247dc10d7SGordon Ross return (NULL);
673347dc10d7SGordon Ross }
673447dc10d7SGordon Ross
673547dc10d7SGordon Ross return &intel_fb->base;
673647dc10d7SGordon Ross }
673747dc10d7SGordon Ross
673847dc10d7SGordon Ross static u32
intel_framebuffer_pitch_for_width(int width,int bpp)673947dc10d7SGordon Ross intel_framebuffer_pitch_for_width(int width, int bpp)
674047dc10d7SGordon Ross {
674147dc10d7SGordon Ross u32 pitch = DIV_ROUND_UP(width * bpp, 8);
674247dc10d7SGordon Ross return ALIGN(pitch, 64);
674347dc10d7SGordon Ross }
674447dc10d7SGordon Ross
674547dc10d7SGordon Ross static u32
intel_framebuffer_size_for_mode(struct drm_display_mode * mode,int bpp)674647dc10d7SGordon Ross intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
674747dc10d7SGordon Ross {
674847dc10d7SGordon Ross u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
674947dc10d7SGordon Ross return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
675047dc10d7SGordon Ross }
675147dc10d7SGordon Ross
675247dc10d7SGordon Ross static struct drm_framebuffer *
intel_framebuffer_create_for_mode(struct drm_device * dev,struct drm_display_mode * mode,int depth,int bpp)675347dc10d7SGordon Ross intel_framebuffer_create_for_mode(struct drm_device *dev,
675447dc10d7SGordon Ross struct drm_display_mode *mode,
675547dc10d7SGordon Ross int depth, int bpp)
675647dc10d7SGordon Ross {
675747dc10d7SGordon Ross struct drm_i915_gem_object *obj;
675847dc10d7SGordon Ross struct drm_mode_fb_cmd2 mode_cmd;
675947dc10d7SGordon Ross
676047dc10d7SGordon Ross obj = i915_gem_alloc_object(dev,
676147dc10d7SGordon Ross intel_framebuffer_size_for_mode(mode, bpp));
676247dc10d7SGordon Ross if (obj == NULL)
676347dc10d7SGordon Ross return (NULL);
676447dc10d7SGordon Ross
676547dc10d7SGordon Ross (void) memset(&mode_cmd, 0, sizeof(struct drm_mode_fb_cmd2));
676647dc10d7SGordon Ross
676747dc10d7SGordon Ross mode_cmd.width = mode->hdisplay;
676847dc10d7SGordon Ross mode_cmd.height = mode->vdisplay;
676947dc10d7SGordon Ross mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
677047dc10d7SGordon Ross bpp);
677147dc10d7SGordon Ross mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
677247dc10d7SGordon Ross
677347dc10d7SGordon Ross return intel_framebuffer_create(dev, &mode_cmd, obj);
677447dc10d7SGordon Ross }
677547dc10d7SGordon Ross
677647dc10d7SGordon Ross static struct drm_framebuffer *
mode_fits_in_fbdev(struct drm_device * dev,struct drm_display_mode * mode)677747dc10d7SGordon Ross mode_fits_in_fbdev(struct drm_device *dev,
677847dc10d7SGordon Ross struct drm_display_mode *mode)
677947dc10d7SGordon Ross {
678047dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
678147dc10d7SGordon Ross struct drm_i915_gem_object *obj;
678247dc10d7SGordon Ross struct drm_framebuffer *fb;
678347dc10d7SGordon Ross
678447dc10d7SGordon Ross if (dev_priv->fbdev == NULL)
678547dc10d7SGordon Ross return NULL;
678647dc10d7SGordon Ross
678747dc10d7SGordon Ross obj = dev_priv->fbdev->ifb.obj;
678847dc10d7SGordon Ross if (obj == NULL)
678947dc10d7SGordon Ross return NULL;
679047dc10d7SGordon Ross
679147dc10d7SGordon Ross fb = &dev_priv->fbdev->ifb.base;
679247dc10d7SGordon Ross if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
679347dc10d7SGordon Ross fb->bits_per_pixel))
679447dc10d7SGordon Ross return NULL;
679547dc10d7SGordon Ross
679647dc10d7SGordon Ross if (obj->base.size < mode->vdisplay * fb->pitches[0])
679747dc10d7SGordon Ross return NULL;
679847dc10d7SGordon Ross
679947dc10d7SGordon Ross return fb;
680047dc10d7SGordon Ross }
680147dc10d7SGordon Ross
intel_get_load_detect_pipe(struct drm_connector * connector,struct drm_display_mode * mode,struct intel_load_detect_pipe * old)680247dc10d7SGordon Ross bool intel_get_load_detect_pipe(struct drm_connector *connector,
680347dc10d7SGordon Ross struct drm_display_mode *mode,
680447dc10d7SGordon Ross struct intel_load_detect_pipe *old)
680547dc10d7SGordon Ross {
680647dc10d7SGordon Ross struct intel_crtc *intel_crtc;
680747dc10d7SGordon Ross struct intel_encoder *intel_encoder =
680847dc10d7SGordon Ross intel_attached_encoder(connector);
680947dc10d7SGordon Ross struct drm_crtc *possible_crtc;
681047dc10d7SGordon Ross struct drm_encoder *encoder = &intel_encoder->base;
681147dc10d7SGordon Ross struct drm_crtc *crtc = NULL;
681247dc10d7SGordon Ross struct drm_device *dev = encoder->dev;
681347dc10d7SGordon Ross struct drm_framebuffer *fb;
681447dc10d7SGordon Ross int i = -1;
681547dc10d7SGordon Ross
681647dc10d7SGordon Ross DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
681747dc10d7SGordon Ross connector->base.id, drm_get_connector_name(connector),
681847dc10d7SGordon Ross encoder->base.id, drm_get_encoder_name(encoder));
681947dc10d7SGordon Ross
682047dc10d7SGordon Ross /*
682147dc10d7SGordon Ross * Algorithm gets a little messy:
682247dc10d7SGordon Ross *
682347dc10d7SGordon Ross * - if the connector already has an assigned crtc, use it (but make
682447dc10d7SGordon Ross * sure it's on first)
682547dc10d7SGordon Ross *
682647dc10d7SGordon Ross * - try to find the first unused crtc that can drive this connector,
682747dc10d7SGordon Ross * and use that if we find one
682847dc10d7SGordon Ross */
682947dc10d7SGordon Ross
683047dc10d7SGordon Ross /* See if we already have a CRTC for this connector */
683147dc10d7SGordon Ross if (encoder->crtc) {
683247dc10d7SGordon Ross crtc = encoder->crtc;
683347dc10d7SGordon Ross
683447dc10d7SGordon Ross mutex_lock(&crtc->mutex);
683547dc10d7SGordon Ross
683647dc10d7SGordon Ross /* Make sure the crtc and connector are running */
683747dc10d7SGordon Ross old->dpms_mode = connector->dpms;
683847dc10d7SGordon Ross old->load_detect_temp = false;
683947dc10d7SGordon Ross
684047dc10d7SGordon Ross /* Make sure the crtc and connector are running */
684147dc10d7SGordon Ross if (connector->dpms != DRM_MODE_DPMS_ON)
684247dc10d7SGordon Ross connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
684347dc10d7SGordon Ross
684447dc10d7SGordon Ross return true;
684547dc10d7SGordon Ross }
684647dc10d7SGordon Ross
684747dc10d7SGordon Ross /* Find an unused one (if possible) */
684847dc10d7SGordon Ross list_for_each_entry(possible_crtc, struct drm_crtc, &dev->mode_config.crtc_list, head) {
684947dc10d7SGordon Ross i++;
685047dc10d7SGordon Ross if (!(encoder->possible_crtcs & (1 << i)))
685147dc10d7SGordon Ross continue;
685247dc10d7SGordon Ross if (!possible_crtc->enabled) {
685347dc10d7SGordon Ross crtc = possible_crtc;
685447dc10d7SGordon Ross break;
685547dc10d7SGordon Ross }
685647dc10d7SGordon Ross }
685747dc10d7SGordon Ross
685847dc10d7SGordon Ross /*
685947dc10d7SGordon Ross * If we didn't find an unused CRTC, don't use any.
686047dc10d7SGordon Ross */
686147dc10d7SGordon Ross if (!crtc) {
686247dc10d7SGordon Ross DRM_DEBUG_KMS("no pipe available for load-detect\n");
686347dc10d7SGordon Ross return false;
686447dc10d7SGordon Ross }
686547dc10d7SGordon Ross
686647dc10d7SGordon Ross mutex_lock(&crtc->mutex);
686747dc10d7SGordon Ross intel_encoder->new_crtc = to_intel_crtc(crtc);
686847dc10d7SGordon Ross to_intel_connector(connector)->new_encoder = intel_encoder;
686947dc10d7SGordon Ross
687047dc10d7SGordon Ross intel_crtc = to_intel_crtc(crtc);
687147dc10d7SGordon Ross old->dpms_mode = connector->dpms;
687247dc10d7SGordon Ross old->load_detect_temp = true;
687347dc10d7SGordon Ross old->release_fb = NULL;
687447dc10d7SGordon Ross
687547dc10d7SGordon Ross if (!mode)
687647dc10d7SGordon Ross mode = &load_detect_mode;
687747dc10d7SGordon Ross
687847dc10d7SGordon Ross /* We need a framebuffer large enough to accommodate all accesses
687947dc10d7SGordon Ross * that the plane may generate whilst we perform load detection.
688047dc10d7SGordon Ross * We can not rely on the fbcon either being present (we get called
688147dc10d7SGordon Ross * during its initialisation to detect all boot displays, or it may
688247dc10d7SGordon Ross * not even exist) or that it is large enough to satisfy the
688347dc10d7SGordon Ross * requested mode.
688447dc10d7SGordon Ross */
688547dc10d7SGordon Ross fb = mode_fits_in_fbdev(dev, mode);
688647dc10d7SGordon Ross if (fb == NULL) {
688747dc10d7SGordon Ross DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
688847dc10d7SGordon Ross fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
688947dc10d7SGordon Ross old->release_fb = fb;
689047dc10d7SGordon Ross } else
689147dc10d7SGordon Ross DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
689247dc10d7SGordon Ross if (IS_ERR(fb)) {
689347dc10d7SGordon Ross DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
689447dc10d7SGordon Ross mutex_unlock(&crtc->mutex);
689547dc10d7SGordon Ross return false;
689647dc10d7SGordon Ross }
689747dc10d7SGordon Ross
689847dc10d7SGordon Ross if (intel_set_mode(crtc, mode, 0, 0, fb)) {
689947dc10d7SGordon Ross DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
690047dc10d7SGordon Ross if (old->release_fb)
690147dc10d7SGordon Ross old->release_fb->funcs->destroy(old->release_fb);
690247dc10d7SGordon Ross mutex_unlock(&crtc->mutex);
690347dc10d7SGordon Ross return false;
690447dc10d7SGordon Ross }
690547dc10d7SGordon Ross
690647dc10d7SGordon Ross /* let the connector get through one full cycle before testing */
690747dc10d7SGordon Ross intel_wait_for_vblank(dev, intel_crtc->pipe);
690847dc10d7SGordon Ross return true;
690947dc10d7SGordon Ross }
691047dc10d7SGordon Ross
intel_release_load_detect_pipe(struct drm_connector * connector,struct intel_load_detect_pipe * old)691147dc10d7SGordon Ross void intel_release_load_detect_pipe(struct drm_connector *connector,
691247dc10d7SGordon Ross struct intel_load_detect_pipe *old)
691347dc10d7SGordon Ross {
691447dc10d7SGordon Ross struct intel_encoder *intel_encoder =
691547dc10d7SGordon Ross intel_attached_encoder(connector);
691647dc10d7SGordon Ross struct drm_encoder *encoder = &intel_encoder->base;
691747dc10d7SGordon Ross struct drm_crtc *crtc = encoder->crtc;
691847dc10d7SGordon Ross
691947dc10d7SGordon Ross DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
692047dc10d7SGordon Ross connector->base.id, drm_get_connector_name(connector),
692147dc10d7SGordon Ross encoder->base.id, drm_get_encoder_name(encoder));
692247dc10d7SGordon Ross
692347dc10d7SGordon Ross if (old->load_detect_temp) {
692447dc10d7SGordon Ross to_intel_connector(connector)->new_encoder = NULL;
692547dc10d7SGordon Ross intel_encoder->new_crtc = NULL;
692647dc10d7SGordon Ross intel_set_mode(crtc, NULL, 0, 0, NULL);
692747dc10d7SGordon Ross
692847dc10d7SGordon Ross if (old->release_fb) {
692947dc10d7SGordon Ross drm_framebuffer_unregister_private(old->release_fb);
693047dc10d7SGordon Ross drm_framebuffer_unreference(old->release_fb);
693147dc10d7SGordon Ross }
693247dc10d7SGordon Ross
693347dc10d7SGordon Ross mutex_unlock(&crtc->mutex);
693447dc10d7SGordon Ross return;
693547dc10d7SGordon Ross }
693647dc10d7SGordon Ross
693747dc10d7SGordon Ross /* Switch crtc and encoder back off if necessary */
693847dc10d7SGordon Ross if (old->dpms_mode != DRM_MODE_DPMS_ON)
693947dc10d7SGordon Ross connector->funcs->dpms(connector, old->dpms_mode);
694047dc10d7SGordon Ross
694147dc10d7SGordon Ross mutex_unlock(&crtc->mutex);
694247dc10d7SGordon Ross }
694347dc10d7SGordon Ross
694447dc10d7SGordon Ross /* Returns the clock of the currently programmed mode of the given pipe. */
intel_crtc_clock_get(struct drm_device * dev,struct drm_crtc * crtc)694547dc10d7SGordon Ross static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
694647dc10d7SGordon Ross {
694747dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
694847dc10d7SGordon Ross struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
694947dc10d7SGordon Ross int pipe = intel_crtc->pipe;
695047dc10d7SGordon Ross u32 dpll = I915_READ(DPLL(pipe));
695147dc10d7SGordon Ross u32 fp;
695247dc10d7SGordon Ross intel_clock_t clock;
695347dc10d7SGordon Ross
695447dc10d7SGordon Ross if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
695547dc10d7SGordon Ross fp = I915_READ(FP0(pipe));
695647dc10d7SGordon Ross else
695747dc10d7SGordon Ross fp = I915_READ(FP1(pipe));
695847dc10d7SGordon Ross
695947dc10d7SGordon Ross clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
696047dc10d7SGordon Ross if (IS_PINEVIEW(dev)) {
696147dc10d7SGordon Ross clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
696247dc10d7SGordon Ross clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
696347dc10d7SGordon Ross } else {
696447dc10d7SGordon Ross clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
696547dc10d7SGordon Ross clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
696647dc10d7SGordon Ross }
696747dc10d7SGordon Ross
696847dc10d7SGordon Ross if (!IS_GEN2(dev)) {
696947dc10d7SGordon Ross if (IS_PINEVIEW(dev))
697047dc10d7SGordon Ross clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
697147dc10d7SGordon Ross DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
697247dc10d7SGordon Ross else
697347dc10d7SGordon Ross clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
697447dc10d7SGordon Ross DPLL_FPA01_P1_POST_DIV_SHIFT);
697547dc10d7SGordon Ross
697647dc10d7SGordon Ross switch (dpll & DPLL_MODE_MASK) {
697747dc10d7SGordon Ross case DPLLB_MODE_DAC_SERIAL:
697847dc10d7SGordon Ross clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
697947dc10d7SGordon Ross 5 : 10;
698047dc10d7SGordon Ross break;
698147dc10d7SGordon Ross case DPLLB_MODE_LVDS:
698247dc10d7SGordon Ross clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
698347dc10d7SGordon Ross 7 : 14;
698447dc10d7SGordon Ross break;
698547dc10d7SGordon Ross default:
698647dc10d7SGordon Ross DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
698747dc10d7SGordon Ross "mode\n", (int)(dpll & DPLL_MODE_MASK));
698847dc10d7SGordon Ross return 0;
698947dc10d7SGordon Ross }
699047dc10d7SGordon Ross
699147dc10d7SGordon Ross if (IS_PINEVIEW(dev))
699247dc10d7SGordon Ross pineview_clock(96000, &clock);
699347dc10d7SGordon Ross else
699447dc10d7SGordon Ross i9xx_clock(96000, &clock);
699547dc10d7SGordon Ross } else {
699647dc10d7SGordon Ross bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
699747dc10d7SGordon Ross
699847dc10d7SGordon Ross if (is_lvds) {
699947dc10d7SGordon Ross clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
700047dc10d7SGordon Ross DPLL_FPA01_P1_POST_DIV_SHIFT);
700147dc10d7SGordon Ross clock.p2 = 14;
700247dc10d7SGordon Ross
700347dc10d7SGordon Ross if ((dpll & PLL_REF_INPUT_MASK) ==
700447dc10d7SGordon Ross PLLB_REF_INPUT_SPREADSPECTRUMIN) {
700547dc10d7SGordon Ross /* XXX: might not be 66MHz */
700647dc10d7SGordon Ross i9xx_clock(66000, &clock);
700747dc10d7SGordon Ross } else
700847dc10d7SGordon Ross i9xx_clock(48000, &clock);
700947dc10d7SGordon Ross } else {
701047dc10d7SGordon Ross if (dpll & PLL_P1_DIVIDE_BY_TWO)
701147dc10d7SGordon Ross clock.p1 = 2;
701247dc10d7SGordon Ross else {
701347dc10d7SGordon Ross clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
701447dc10d7SGordon Ross DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
701547dc10d7SGordon Ross }
701647dc10d7SGordon Ross if (dpll & PLL_P2_DIVIDE_BY_4)
701747dc10d7SGordon Ross clock.p2 = 4;
701847dc10d7SGordon Ross else
701947dc10d7SGordon Ross clock.p2 = 2;
702047dc10d7SGordon Ross
702147dc10d7SGordon Ross i9xx_clock(48000, &clock);
702247dc10d7SGordon Ross }
702347dc10d7SGordon Ross }
702447dc10d7SGordon Ross
702547dc10d7SGordon Ross /* XXX: It would be nice to validate the clocks, but we can't reuse
702647dc10d7SGordon Ross * i830PllIsValid() because it relies on the xf86_config connector
702747dc10d7SGordon Ross * configuration being accurate, which it isn't necessarily.
702847dc10d7SGordon Ross */
702947dc10d7SGordon Ross
703047dc10d7SGordon Ross return clock.dot;
703147dc10d7SGordon Ross }
703247dc10d7SGordon Ross
703347dc10d7SGordon Ross /** Returns the currently programmed mode of the given pipe. */
intel_crtc_mode_get(struct drm_device * dev,struct drm_crtc * crtc)703447dc10d7SGordon Ross struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
703547dc10d7SGordon Ross struct drm_crtc *crtc)
703647dc10d7SGordon Ross {
703747dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
703847dc10d7SGordon Ross struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
703947dc10d7SGordon Ross enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
704047dc10d7SGordon Ross struct drm_display_mode *mode;
704147dc10d7SGordon Ross int htot = I915_READ(HTOTAL(cpu_transcoder));
704247dc10d7SGordon Ross int hsync = I915_READ(HSYNC(cpu_transcoder));
704347dc10d7SGordon Ross int vtot = I915_READ(VTOTAL(cpu_transcoder));
704447dc10d7SGordon Ross int vsync = I915_READ(VSYNC(cpu_transcoder));
704547dc10d7SGordon Ross
704647dc10d7SGordon Ross mode = kzalloc(sizeof(*mode), GFP_KERNEL);
704747dc10d7SGordon Ross if (!mode)
704847dc10d7SGordon Ross return NULL;
704947dc10d7SGordon Ross
705047dc10d7SGordon Ross mode->clock = intel_crtc_clock_get(dev, crtc);
705147dc10d7SGordon Ross mode->hdisplay = (htot & 0xffff) + 1;
705247dc10d7SGordon Ross mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
705347dc10d7SGordon Ross mode->hsync_start = (hsync & 0xffff) + 1;
705447dc10d7SGordon Ross mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
705547dc10d7SGordon Ross mode->vdisplay = (vtot & 0xffff) + 1;
705647dc10d7SGordon Ross mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
705747dc10d7SGordon Ross mode->vsync_start = (vsync & 0xffff) + 1;
705847dc10d7SGordon Ross mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
705947dc10d7SGordon Ross
706047dc10d7SGordon Ross drm_mode_set_name(mode);
706147dc10d7SGordon Ross
706247dc10d7SGordon Ross return mode;
706347dc10d7SGordon Ross }
706447dc10d7SGordon Ross
intel_increase_pllclock(struct drm_crtc * crtc)706547dc10d7SGordon Ross void intel_increase_pllclock(struct drm_crtc *crtc)
706647dc10d7SGordon Ross {
706747dc10d7SGordon Ross struct drm_device *dev = crtc->dev;
706847dc10d7SGordon Ross drm_i915_private_t *dev_priv = dev->dev_private;
706947dc10d7SGordon Ross struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
707047dc10d7SGordon Ross int pipe = intel_crtc->pipe;
707147dc10d7SGordon Ross int dpll_reg = DPLL(pipe);
707247dc10d7SGordon Ross int dpll;
707347dc10d7SGordon Ross
707447dc10d7SGordon Ross if (HAS_PCH_SPLIT(dev))
707547dc10d7SGordon Ross return;
707647dc10d7SGordon Ross
707747dc10d7SGordon Ross if (!dev_priv->lvds_downclock_avail)
707847dc10d7SGordon Ross return;
707947dc10d7SGordon Ross
708047dc10d7SGordon Ross dpll = I915_READ(dpll_reg);
708147dc10d7SGordon Ross if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
708247dc10d7SGordon Ross DRM_DEBUG_DRIVER("upclocking LVDS\n");
708347dc10d7SGordon Ross
708447dc10d7SGordon Ross assert_panel_unlocked(dev_priv, pipe);
708547dc10d7SGordon Ross
708647dc10d7SGordon Ross dpll &= ~DISPLAY_RATE_SELECT_FPA1;
708747dc10d7SGordon Ross I915_WRITE(dpll_reg, dpll);
708847dc10d7SGordon Ross intel_wait_for_vblank(dev, pipe);
708947dc10d7SGordon Ross
709047dc10d7SGordon Ross dpll = I915_READ(dpll_reg);
709147dc10d7SGordon Ross if (dpll & DISPLAY_RATE_SELECT_FPA1)
709247dc10d7SGordon Ross DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
709347dc10d7SGordon Ross }
709447dc10d7SGordon Ross }
709547dc10d7SGordon Ross
intel_decrease_pllclock(struct drm_crtc * crtc)709647dc10d7SGordon Ross static void intel_decrease_pllclock(struct drm_crtc *crtc)
709747dc10d7SGordon Ross {
709847dc10d7SGordon Ross struct drm_device *dev = crtc->dev;
709947dc10d7SGordon Ross drm_i915_private_t *dev_priv = dev->dev_private;
710047dc10d7SGordon Ross struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
710147dc10d7SGordon Ross
710247dc10d7SGordon Ross if (HAS_PCH_SPLIT(dev))
710347dc10d7SGordon Ross return;
710447dc10d7SGordon Ross
710547dc10d7SGordon Ross if (!dev_priv->lvds_downclock_avail)
710647dc10d7SGordon Ross return;
710747dc10d7SGordon Ross
710847dc10d7SGordon Ross /*
710947dc10d7SGordon Ross * Since this is called by a timer, we should never get here in
711047dc10d7SGordon Ross * the manual case.
711147dc10d7SGordon Ross */
711247dc10d7SGordon Ross if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
711347dc10d7SGordon Ross int pipe = intel_crtc->pipe;
711447dc10d7SGordon Ross int dpll_reg = DPLL(pipe);
711547dc10d7SGordon Ross int dpll;
711647dc10d7SGordon Ross
711747dc10d7SGordon Ross DRM_DEBUG_DRIVER("downclocking LVDS\n");
711847dc10d7SGordon Ross
711947dc10d7SGordon Ross assert_panel_unlocked(dev_priv, pipe);
712047dc10d7SGordon Ross
712147dc10d7SGordon Ross dpll = I915_READ(dpll_reg);
712247dc10d7SGordon Ross dpll |= DISPLAY_RATE_SELECT_FPA1;
712347dc10d7SGordon Ross I915_WRITE(dpll_reg, dpll);
712447dc10d7SGordon Ross intel_wait_for_vblank(dev, pipe);
712547dc10d7SGordon Ross dpll = I915_READ(dpll_reg);
712647dc10d7SGordon Ross if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
712747dc10d7SGordon Ross DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
712847dc10d7SGordon Ross }
712947dc10d7SGordon Ross
713047dc10d7SGordon Ross }
713147dc10d7SGordon Ross
intel_mark_busy(struct drm_device * dev)713247dc10d7SGordon Ross void intel_mark_busy(struct drm_device *dev)
713347dc10d7SGordon Ross {
713447dc10d7SGordon Ross }
713547dc10d7SGordon Ross
intel_mark_idle(struct drm_device * dev)713647dc10d7SGordon Ross void intel_mark_idle(struct drm_device *dev)
713747dc10d7SGordon Ross {
713847dc10d7SGordon Ross struct drm_crtc *crtc;
713947dc10d7SGordon Ross
714047dc10d7SGordon Ross if (!i915_powersave)
714147dc10d7SGordon Ross return;
714247dc10d7SGordon Ross
714347dc10d7SGordon Ross list_for_each_entry(crtc, struct drm_crtc, &dev->mode_config.crtc_list, head) {
714447dc10d7SGordon Ross if (!crtc->fb)
714547dc10d7SGordon Ross continue;
714647dc10d7SGordon Ross
714747dc10d7SGordon Ross intel_decrease_pllclock(crtc);
714847dc10d7SGordon Ross }
714947dc10d7SGordon Ross }
715047dc10d7SGordon Ross
intel_mark_fb_busy(struct drm_i915_gem_object * obj,struct intel_ring_buffer * ring)715147dc10d7SGordon Ross void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
715247dc10d7SGordon Ross struct intel_ring_buffer *ring)
715347dc10d7SGordon Ross {
715447dc10d7SGordon Ross struct drm_device *dev = obj->base.dev;
715547dc10d7SGordon Ross struct drm_crtc *crtc;
715647dc10d7SGordon Ross
715747dc10d7SGordon Ross if (!i915_powersave)
715847dc10d7SGordon Ross return;
715947dc10d7SGordon Ross
716047dc10d7SGordon Ross list_for_each_entry(crtc, struct drm_crtc, &dev->mode_config.crtc_list, head) {
716147dc10d7SGordon Ross if (!crtc->fb)
716247dc10d7SGordon Ross continue;
716347dc10d7SGordon Ross
716447dc10d7SGordon Ross if (to_intel_framebuffer(crtc->fb)->obj != obj)
716547dc10d7SGordon Ross continue;
716647dc10d7SGordon Ross
7167e1cb3391SAlexander Pyhalov intel_increase_pllclock(crtc);
716847dc10d7SGordon Ross if (ring && intel_fbc_enabled(dev))
716947dc10d7SGordon Ross ring->fbc_dirty = true;
717047dc10d7SGordon Ross }
717147dc10d7SGordon Ross }
717247dc10d7SGordon Ross
intel_crtc_destroy(struct drm_crtc * crtc)717347dc10d7SGordon Ross static void intel_crtc_destroy(struct drm_crtc *crtc)
717447dc10d7SGordon Ross {
717547dc10d7SGordon Ross struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
717647dc10d7SGordon Ross struct drm_device *dev = crtc->dev;
717747dc10d7SGordon Ross drm_i915_private_t *dev_priv = dev->dev_private;
717847dc10d7SGordon Ross struct intel_unpin_work *work;
717947dc10d7SGordon Ross unsigned long flags;
718047dc10d7SGordon Ross
718147dc10d7SGordon Ross spin_lock_irqsave(&dev->event_lock, flags);
718247dc10d7SGordon Ross work = intel_crtc->unpin_work;
718347dc10d7SGordon Ross intel_crtc->unpin_work = NULL;
718447dc10d7SGordon Ross spin_unlock_irqrestore(&dev->event_lock, flags);
718547dc10d7SGordon Ross
718647dc10d7SGordon Ross if (work) {
718747dc10d7SGordon Ross cancel_delayed_work(dev_priv->other_wq);
718847dc10d7SGordon Ross kfree(work, sizeof(*work));
718947dc10d7SGordon Ross }
719047dc10d7SGordon Ross
719147dc10d7SGordon Ross intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
719247dc10d7SGordon Ross
719347dc10d7SGordon Ross drm_crtc_cleanup(crtc);
719447dc10d7SGordon Ross
719547dc10d7SGordon Ross kfree(intel_crtc, sizeof (struct intel_crtc) +
719647dc10d7SGordon Ross (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)));
719747dc10d7SGordon Ross }
719847dc10d7SGordon Ross
intel_unpin_work_fn(struct work_struct * __work)719947dc10d7SGordon Ross static void intel_unpin_work_fn(struct work_struct *__work)
720047dc10d7SGordon Ross {
720147dc10d7SGordon Ross struct intel_unpin_work *work =
720247dc10d7SGordon Ross container_of(__work, struct intel_unpin_work, work);
720347dc10d7SGordon Ross struct drm_device *dev = work->crtc->dev;
720447dc10d7SGordon Ross
720547dc10d7SGordon Ross mutex_lock(&dev->struct_mutex);
720647dc10d7SGordon Ross intel_unpin_fb_obj(work->old_fb_obj);
720747dc10d7SGordon Ross drm_gem_object_unreference(&work->pending_flip_obj->base);
720847dc10d7SGordon Ross drm_gem_object_unreference(&work->old_fb_obj->base);
720947dc10d7SGordon Ross
721047dc10d7SGordon Ross intel_update_fbc(dev);
721147dc10d7SGordon Ross mutex_unlock(&dev->struct_mutex);
721247dc10d7SGordon Ross
721347dc10d7SGordon Ross BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
721447dc10d7SGordon Ross atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
721547dc10d7SGordon Ross kfree(work, sizeof(struct intel_unpin_work));
721647dc10d7SGordon Ross }
721747dc10d7SGordon Ross
do_intel_finish_page_flip(struct drm_device * dev,struct drm_crtc * crtc)721847dc10d7SGordon Ross static void do_intel_finish_page_flip(struct drm_device *dev,
721947dc10d7SGordon Ross struct drm_crtc *crtc)
722047dc10d7SGordon Ross {
722147dc10d7SGordon Ross drm_i915_private_t *dev_priv = dev->dev_private;
722247dc10d7SGordon Ross struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
722347dc10d7SGordon Ross struct intel_unpin_work *work;
722447dc10d7SGordon Ross unsigned long flags;
722547dc10d7SGordon Ross
722647dc10d7SGordon Ross /* Ignore early vblank irqs */
722747dc10d7SGordon Ross if (intel_crtc == NULL)
722847dc10d7SGordon Ross return;
722947dc10d7SGordon Ross
723047dc10d7SGordon Ross spin_lock_irqsave(&dev->event_lock, flags);
723147dc10d7SGordon Ross work = intel_crtc->unpin_work;
723247dc10d7SGordon Ross if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
723347dc10d7SGordon Ross spin_unlock_irqrestore(&dev->event_lock, flags);
723447dc10d7SGordon Ross return;
723547dc10d7SGordon Ross }
723647dc10d7SGordon Ross
723747dc10d7SGordon Ross intel_crtc->unpin_work = NULL;
723847dc10d7SGordon Ross
723947dc10d7SGordon Ross if (work->event) {
724047dc10d7SGordon Ross drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
724147dc10d7SGordon Ross
724247dc10d7SGordon Ross pollwakeup(&work->event->base.file_priv->drm_pollhead, POLLIN | POLLRDNORM);
724347dc10d7SGordon Ross }
724447dc10d7SGordon Ross drm_vblank_put(dev, intel_crtc->pipe);
724547dc10d7SGordon Ross
724647dc10d7SGordon Ross spin_unlock_irqrestore(&dev->event_lock, flags);
724747dc10d7SGordon Ross
724847dc10d7SGordon Ross DRM_WAKEUP(&dev_priv->pending_flip_queue);
724947dc10d7SGordon Ross
725047dc10d7SGordon Ross (void) queue_work(dev_priv->wq, &work->work);
725147dc10d7SGordon Ross
725247dc10d7SGordon Ross }
725347dc10d7SGordon Ross
intel_finish_page_flip(struct drm_device * dev,int pipe)725447dc10d7SGordon Ross void intel_finish_page_flip(struct drm_device *dev, int pipe)
725547dc10d7SGordon Ross {
725647dc10d7SGordon Ross drm_i915_private_t *dev_priv = dev->dev_private;
725747dc10d7SGordon Ross struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
725847dc10d7SGordon Ross
725947dc10d7SGordon Ross do_intel_finish_page_flip(dev, crtc);
726047dc10d7SGordon Ross }
726147dc10d7SGordon Ross
intel_finish_page_flip_plane(struct drm_device * dev,int plane)726247dc10d7SGordon Ross void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
726347dc10d7SGordon Ross {
726447dc10d7SGordon Ross drm_i915_private_t *dev_priv = dev->dev_private;
726547dc10d7SGordon Ross struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
726647dc10d7SGordon Ross
726747dc10d7SGordon Ross do_intel_finish_page_flip(dev, crtc);
726847dc10d7SGordon Ross }
726947dc10d7SGordon Ross
intel_prepare_page_flip(struct drm_device * dev,int plane)727047dc10d7SGordon Ross void intel_prepare_page_flip(struct drm_device *dev, int plane)
727147dc10d7SGordon Ross {
727247dc10d7SGordon Ross drm_i915_private_t *dev_priv = dev->dev_private;
727347dc10d7SGordon Ross struct intel_crtc *intel_crtc =
727447dc10d7SGordon Ross to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
727547dc10d7SGordon Ross unsigned long flags;
727647dc10d7SGordon Ross
727747dc10d7SGordon Ross /* NB: An MMIO update of the plane base pointer will also
727847dc10d7SGordon Ross * generate a page-flip completion irq, i.e. every modeset
727947dc10d7SGordon Ross * is also accompanied by a spurious intel_prepare_page_flip().
728047dc10d7SGordon Ross */
728147dc10d7SGordon Ross spin_lock_irqsave(&dev->event_lock, flags);
728247dc10d7SGordon Ross if (intel_crtc->unpin_work)
728347dc10d7SGordon Ross atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
728447dc10d7SGordon Ross spin_unlock_irqrestore(&dev->event_lock, flags);
728547dc10d7SGordon Ross }
728647dc10d7SGordon Ross
intel_mark_page_flip_active(struct intel_crtc * intel_crtc)728747dc10d7SGordon Ross inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
728847dc10d7SGordon Ross {
728947dc10d7SGordon Ross /* Ensure that the work item is consistent when activating it ... */
729047dc10d7SGordon Ross membar_producer();
729147dc10d7SGordon Ross atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
729247dc10d7SGordon Ross /* and that it is marked active as soon as the irq could fire. */
729347dc10d7SGordon Ross membar_producer();
729447dc10d7SGordon Ross }
729547dc10d7SGordon Ross
intel_gen2_queue_flip(struct drm_device * dev,struct drm_crtc * crtc,struct drm_framebuffer * fb,struct drm_i915_gem_object * obj)729647dc10d7SGordon Ross static int intel_gen2_queue_flip(struct drm_device *dev,
729747dc10d7SGordon Ross struct drm_crtc *crtc,
729847dc10d7SGordon Ross struct drm_framebuffer *fb,
729947dc10d7SGordon Ross struct drm_i915_gem_object *obj)
730047dc10d7SGordon Ross {
730147dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
730247dc10d7SGordon Ross struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
730347dc10d7SGordon Ross u32 flip_mask;
730447dc10d7SGordon Ross struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
730547dc10d7SGordon Ross int ret;
730647dc10d7SGordon Ross
730747dc10d7SGordon Ross ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
730847dc10d7SGordon Ross if (ret)
730947dc10d7SGordon Ross goto err;
731047dc10d7SGordon Ross
731147dc10d7SGordon Ross ret = intel_ring_begin(ring, 6);
731247dc10d7SGordon Ross if (ret)
731347dc10d7SGordon Ross goto err_unpin;
731447dc10d7SGordon Ross
731547dc10d7SGordon Ross /* Can't queue multiple flips, so wait for the previous
731647dc10d7SGordon Ross * one to finish before executing the next.
731747dc10d7SGordon Ross */
731847dc10d7SGordon Ross if (intel_crtc->plane)
731947dc10d7SGordon Ross flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
732047dc10d7SGordon Ross else
732147dc10d7SGordon Ross flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
732247dc10d7SGordon Ross intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
732347dc10d7SGordon Ross intel_ring_emit(ring, MI_NOOP);
732447dc10d7SGordon Ross intel_ring_emit(ring, MI_DISPLAY_FLIP |
732547dc10d7SGordon Ross MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
732647dc10d7SGordon Ross intel_ring_emit(ring, fb->pitches[0]);
732747dc10d7SGordon Ross intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
732847dc10d7SGordon Ross intel_ring_emit(ring, 0); /* aux display base address, unused */
732947dc10d7SGordon Ross
733047dc10d7SGordon Ross intel_mark_page_flip_active(intel_crtc);
733147dc10d7SGordon Ross intel_ring_advance(ring);
733247dc10d7SGordon Ross return 0;
733347dc10d7SGordon Ross
733447dc10d7SGordon Ross err_unpin:
733547dc10d7SGordon Ross intel_unpin_fb_obj(obj);
733647dc10d7SGordon Ross err:
733747dc10d7SGordon Ross return ret;
733847dc10d7SGordon Ross }
733947dc10d7SGordon Ross
intel_gen3_queue_flip(struct drm_device * dev,struct drm_crtc * crtc,struct drm_framebuffer * fb,struct drm_i915_gem_object * obj)734047dc10d7SGordon Ross static int intel_gen3_queue_flip(struct drm_device *dev,
734147dc10d7SGordon Ross struct drm_crtc *crtc,
734247dc10d7SGordon Ross struct drm_framebuffer *fb,
734347dc10d7SGordon Ross struct drm_i915_gem_object *obj)
734447dc10d7SGordon Ross {
734547dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
734647dc10d7SGordon Ross struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
734747dc10d7SGordon Ross u32 flip_mask;
734847dc10d7SGordon Ross struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
734947dc10d7SGordon Ross int ret;
735047dc10d7SGordon Ross
735147dc10d7SGordon Ross ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
735247dc10d7SGordon Ross if (ret)
735347dc10d7SGordon Ross goto err;
735447dc10d7SGordon Ross
735547dc10d7SGordon Ross ret = intel_ring_begin(ring, 6);
735647dc10d7SGordon Ross if (ret)
735747dc10d7SGordon Ross goto err_unpin;
735847dc10d7SGordon Ross
735947dc10d7SGordon Ross if (intel_crtc->plane)
736047dc10d7SGordon Ross flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
736147dc10d7SGordon Ross else
736247dc10d7SGordon Ross flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
736347dc10d7SGordon Ross intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
736447dc10d7SGordon Ross intel_ring_emit(ring, MI_NOOP);
736547dc10d7SGordon Ross intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
736647dc10d7SGordon Ross MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
736747dc10d7SGordon Ross intel_ring_emit(ring, fb->pitches[0]);
736847dc10d7SGordon Ross intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
736947dc10d7SGordon Ross intel_ring_emit(ring, MI_NOOP);
737047dc10d7SGordon Ross
737147dc10d7SGordon Ross intel_mark_page_flip_active(intel_crtc);
737247dc10d7SGordon Ross intel_ring_advance(ring);
737347dc10d7SGordon Ross return 0;
737447dc10d7SGordon Ross
737547dc10d7SGordon Ross err_unpin:
737647dc10d7SGordon Ross intel_unpin_fb_obj(obj);
737747dc10d7SGordon Ross err:
737847dc10d7SGordon Ross return ret;
737947dc10d7SGordon Ross }
738047dc10d7SGordon Ross
intel_gen4_queue_flip(struct drm_device * dev,struct drm_crtc * crtc,struct drm_framebuffer * fb,struct drm_i915_gem_object * obj)738147dc10d7SGordon Ross static int intel_gen4_queue_flip(struct drm_device *dev,
738247dc10d7SGordon Ross struct drm_crtc *crtc,
738347dc10d7SGordon Ross struct drm_framebuffer *fb,
738447dc10d7SGordon Ross struct drm_i915_gem_object *obj)
738547dc10d7SGordon Ross {
738647dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
738747dc10d7SGordon Ross struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
738847dc10d7SGordon Ross uint32_t pf, pipesrc;
738947dc10d7SGordon Ross struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
739047dc10d7SGordon Ross int ret;
739147dc10d7SGordon Ross
739247dc10d7SGordon Ross ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
739347dc10d7SGordon Ross if (ret)
739447dc10d7SGordon Ross goto err;
739547dc10d7SGordon Ross
739647dc10d7SGordon Ross ret = intel_ring_begin(ring, 4);
739747dc10d7SGordon Ross if (ret)
739847dc10d7SGordon Ross goto err_unpin;
739947dc10d7SGordon Ross
740047dc10d7SGordon Ross /* i965+ uses the linear or tiled offsets from the
740147dc10d7SGordon Ross * Display Registers (which do not change across a page-flip)
740247dc10d7SGordon Ross * so we need only reprogram the base address.
740347dc10d7SGordon Ross */
740447dc10d7SGordon Ross intel_ring_emit(ring, MI_DISPLAY_FLIP |
740547dc10d7SGordon Ross MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
740647dc10d7SGordon Ross intel_ring_emit(ring, fb->pitches[0]);
740747dc10d7SGordon Ross intel_ring_emit(ring,
740847dc10d7SGordon Ross (obj->gtt_offset + intel_crtc->dspaddr_offset) |
740947dc10d7SGordon Ross obj->tiling_mode);
741047dc10d7SGordon Ross
741147dc10d7SGordon Ross /* XXX Enabling the panel-fitter across page-flip is so far
741247dc10d7SGordon Ross * untested on non-native modes, so ignore it for now.
741347dc10d7SGordon Ross * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
741447dc10d7SGordon Ross */
741547dc10d7SGordon Ross pf = 0;
741647dc10d7SGordon Ross pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
741747dc10d7SGordon Ross intel_ring_emit(ring, pf | pipesrc);
741847dc10d7SGordon Ross
741947dc10d7SGordon Ross intel_mark_page_flip_active(intel_crtc);
742047dc10d7SGordon Ross intel_ring_advance(ring);
742147dc10d7SGordon Ross return 0;
742247dc10d7SGordon Ross
742347dc10d7SGordon Ross err_unpin:
742447dc10d7SGordon Ross intel_unpin_fb_obj(obj);
742547dc10d7SGordon Ross err:
742647dc10d7SGordon Ross return ret;
742747dc10d7SGordon Ross }
742847dc10d7SGordon Ross
intel_gen6_queue_flip(struct drm_device * dev,struct drm_crtc * crtc,struct drm_framebuffer * fb,struct drm_i915_gem_object * obj)742947dc10d7SGordon Ross static int intel_gen6_queue_flip(struct drm_device *dev,
743047dc10d7SGordon Ross struct drm_crtc *crtc,
743147dc10d7SGordon Ross struct drm_framebuffer *fb,
743247dc10d7SGordon Ross struct drm_i915_gem_object *obj)
743347dc10d7SGordon Ross {
743447dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
743547dc10d7SGordon Ross struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
743647dc10d7SGordon Ross struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
743747dc10d7SGordon Ross uint32_t pf, pipesrc;
743847dc10d7SGordon Ross int ret;
743947dc10d7SGordon Ross
744047dc10d7SGordon Ross ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
744147dc10d7SGordon Ross if (ret)
744247dc10d7SGordon Ross goto err;
744347dc10d7SGordon Ross
744447dc10d7SGordon Ross ret = intel_ring_begin(ring, 4);
744547dc10d7SGordon Ross if (ret)
744647dc10d7SGordon Ross goto err_unpin;
744747dc10d7SGordon Ross
744847dc10d7SGordon Ross intel_ring_emit(ring, MI_DISPLAY_FLIP |
744947dc10d7SGordon Ross MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
745047dc10d7SGordon Ross intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
745147dc10d7SGordon Ross intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
745247dc10d7SGordon Ross
745347dc10d7SGordon Ross /* Contrary to the suggestions in the documentation,
745447dc10d7SGordon Ross * "Enable Panel Fitter" does not seem to be required when page
745547dc10d7SGordon Ross * flipping with a non-native mode, and worse causes a normal
745647dc10d7SGordon Ross * modeset to fail.
745747dc10d7SGordon Ross * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
745847dc10d7SGordon Ross */
745947dc10d7SGordon Ross pf = 0;
746047dc10d7SGordon Ross pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
746147dc10d7SGordon Ross intel_ring_emit(ring, pf | pipesrc);
746247dc10d7SGordon Ross
746347dc10d7SGordon Ross intel_mark_page_flip_active(intel_crtc);
746447dc10d7SGordon Ross intel_ring_advance(ring);
746547dc10d7SGordon Ross return 0;
746647dc10d7SGordon Ross
746747dc10d7SGordon Ross err_unpin:
746847dc10d7SGordon Ross intel_unpin_fb_obj(obj);
746947dc10d7SGordon Ross err:
747047dc10d7SGordon Ross return ret;
747147dc10d7SGordon Ross }
747247dc10d7SGordon Ross
747347dc10d7SGordon Ross /*
747447dc10d7SGordon Ross * On gen7 we currently use the blit ring because (in early silicon at least)
747547dc10d7SGordon Ross * the render ring doesn't give us interrpts for page flip completion, which
747647dc10d7SGordon Ross * means clients will hang after the first flip is queued. Fortunately the
747747dc10d7SGordon Ross * blit ring generates interrupts properly, so use it instead.
747847dc10d7SGordon Ross */
intel_gen7_queue_flip(struct drm_device * dev,struct drm_crtc * crtc,struct drm_framebuffer * fb,struct drm_i915_gem_object * obj)747947dc10d7SGordon Ross static int intel_gen7_queue_flip(struct drm_device *dev,
748047dc10d7SGordon Ross struct drm_crtc *crtc,
748147dc10d7SGordon Ross struct drm_framebuffer *fb,
748247dc10d7SGordon Ross struct drm_i915_gem_object *obj)
748347dc10d7SGordon Ross {
748447dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
748547dc10d7SGordon Ross struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
748647dc10d7SGordon Ross struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
748747dc10d7SGordon Ross uint32_t plane_bit = 0;
748847dc10d7SGordon Ross int ret;
748947dc10d7SGordon Ross
749047dc10d7SGordon Ross ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
749147dc10d7SGordon Ross if (ret)
749247dc10d7SGordon Ross goto err;
749347dc10d7SGordon Ross
749447dc10d7SGordon Ross switch(intel_crtc->plane) {
749547dc10d7SGordon Ross case PLANE_A:
749647dc10d7SGordon Ross plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
749747dc10d7SGordon Ross break;
749847dc10d7SGordon Ross case PLANE_B:
749947dc10d7SGordon Ross plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
750047dc10d7SGordon Ross break;
750147dc10d7SGordon Ross case PLANE_C:
750247dc10d7SGordon Ross plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
750347dc10d7SGordon Ross break;
750447dc10d7SGordon Ross default:
750547dc10d7SGordon Ross DRM_ERROR("unknown plane in flip command\n");
750647dc10d7SGordon Ross ret = -ENODEV;
750747dc10d7SGordon Ross goto err_unpin;
750847dc10d7SGordon Ross }
750947dc10d7SGordon Ross
751047dc10d7SGordon Ross ret = intel_ring_begin(ring, 4);
751147dc10d7SGordon Ross if (ret)
751247dc10d7SGordon Ross goto err_unpin;
751347dc10d7SGordon Ross
751447dc10d7SGordon Ross intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
751547dc10d7SGordon Ross intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
751647dc10d7SGordon Ross intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
751747dc10d7SGordon Ross intel_ring_emit(ring, (MI_NOOP));
751847dc10d7SGordon Ross
751947dc10d7SGordon Ross intel_mark_page_flip_active(intel_crtc);
752047dc10d7SGordon Ross intel_ring_advance(ring);
752147dc10d7SGordon Ross return 0;
752247dc10d7SGordon Ross
752347dc10d7SGordon Ross err_unpin:
752447dc10d7SGordon Ross intel_unpin_fb_obj(obj);
752547dc10d7SGordon Ross err:
752647dc10d7SGordon Ross return ret;
752747dc10d7SGordon Ross }
752847dc10d7SGordon Ross
intel_default_queue_flip(struct drm_device * dev,struct drm_crtc * crtc,struct drm_framebuffer * fb,struct drm_i915_gem_object * obj)752947dc10d7SGordon Ross static int intel_default_queue_flip(struct drm_device *dev,
753047dc10d7SGordon Ross struct drm_crtc *crtc,
753147dc10d7SGordon Ross struct drm_framebuffer *fb,
753247dc10d7SGordon Ross struct drm_i915_gem_object *obj)
753347dc10d7SGordon Ross {
753447dc10d7SGordon Ross return -ENODEV;
753547dc10d7SGordon Ross }
753647dc10d7SGordon Ross
intel_crtc_page_flip(struct drm_crtc * crtc,struct drm_framebuffer * fb,struct drm_pending_vblank_event * event)753747dc10d7SGordon Ross static int intel_crtc_page_flip(struct drm_crtc *crtc,
753847dc10d7SGordon Ross struct drm_framebuffer *fb,
753947dc10d7SGordon Ross struct drm_pending_vblank_event *event)
754047dc10d7SGordon Ross {
754147dc10d7SGordon Ross struct drm_device *dev = crtc->dev;
754247dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
754347dc10d7SGordon Ross struct drm_framebuffer *old_fb = crtc->fb;
754447dc10d7SGordon Ross struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
754547dc10d7SGordon Ross struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
754647dc10d7SGordon Ross struct intel_unpin_work *work;
754747dc10d7SGordon Ross unsigned long flags;
754847dc10d7SGordon Ross int ret;
754947dc10d7SGordon Ross
755047dc10d7SGordon Ross /* Can't change pixel format via MI display flips. */
755147dc10d7SGordon Ross if (fb->pixel_format != crtc->fb->pixel_format)
755247dc10d7SGordon Ross return -EINVAL;
755347dc10d7SGordon Ross
755447dc10d7SGordon Ross /*
755547dc10d7SGordon Ross * TILEOFF/LINOFF registers can't be changed via MI display flips.
755647dc10d7SGordon Ross * Note that pitch changes could also affect these register.
755747dc10d7SGordon Ross */
755847dc10d7SGordon Ross if (INTEL_INFO(dev)->gen > 3 &&
755947dc10d7SGordon Ross (fb->offsets[0] != crtc->fb->offsets[0] ||
756047dc10d7SGordon Ross fb->pitches[0] != crtc->fb->pitches[0]))
756147dc10d7SGordon Ross return -EINVAL;
756247dc10d7SGordon Ross
756347dc10d7SGordon Ross work = kzalloc(sizeof *work, GFP_KERNEL);
756447dc10d7SGordon Ross if (work == NULL)
756547dc10d7SGordon Ross return -ENOMEM;
756647dc10d7SGordon Ross
756747dc10d7SGordon Ross work->event = event;
756847dc10d7SGordon Ross work->crtc = crtc;
756947dc10d7SGordon Ross work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
757047dc10d7SGordon Ross INIT_WORK(&work->work, intel_unpin_work_fn);
757147dc10d7SGordon Ross
757247dc10d7SGordon Ross ret = drm_vblank_get(dev, intel_crtc->pipe);
757347dc10d7SGordon Ross if (ret)
757447dc10d7SGordon Ross goto free_work;
757547dc10d7SGordon Ross
757647dc10d7SGordon Ross /* We borrow the event spin lock for protecting unpin_work */
757747dc10d7SGordon Ross spin_lock_irqsave(&dev->event_lock, flags);
757847dc10d7SGordon Ross if (intel_crtc->unpin_work) {
757947dc10d7SGordon Ross spin_unlock_irqrestore(&dev->event_lock, flags);
758047dc10d7SGordon Ross kfree(work, sizeof(struct intel_unpin_work));
758147dc10d7SGordon Ross drm_vblank_put(dev, intel_crtc->pipe);
758247dc10d7SGordon Ross
758347dc10d7SGordon Ross DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
758447dc10d7SGordon Ross return -EBUSY;
758547dc10d7SGordon Ross }
758647dc10d7SGordon Ross intel_crtc->unpin_work = work;
758747dc10d7SGordon Ross spin_unlock_irqrestore(&dev->event_lock, flags);
758847dc10d7SGordon Ross
758947dc10d7SGordon Ross if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
759047dc10d7SGordon Ross flush_workqueue(dev_priv->wq);
759147dc10d7SGordon Ross
759247dc10d7SGordon Ross mutex_lock(&dev->struct_mutex);
759347dc10d7SGordon Ross
759447dc10d7SGordon Ross /* Reference the objects for the scheduled work. */
759547dc10d7SGordon Ross drm_gem_object_reference(&work->old_fb_obj->base);
759647dc10d7SGordon Ross drm_gem_object_reference(&obj->base);
759747dc10d7SGordon Ross
759847dc10d7SGordon Ross crtc->fb = fb;
759947dc10d7SGordon Ross
760047dc10d7SGordon Ross work->pending_flip_obj = obj;
760147dc10d7SGordon Ross work->enable_stall_check = true;
760247dc10d7SGordon Ross
760347dc10d7SGordon Ross atomic_inc(&intel_crtc->unpin_work_count);
760447dc10d7SGordon Ross intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
760547dc10d7SGordon Ross
760647dc10d7SGordon Ross ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
760747dc10d7SGordon Ross if (ret)
760847dc10d7SGordon Ross goto cleanup_pending;
760947dc10d7SGordon Ross
761047dc10d7SGordon Ross intel_disable_fbc(dev);
761147dc10d7SGordon Ross intel_mark_fb_busy(obj, NULL);
761247dc10d7SGordon Ross mutex_unlock(&dev->struct_mutex);
761347dc10d7SGordon Ross
761447dc10d7SGordon Ross return 0;
761547dc10d7SGordon Ross
761647dc10d7SGordon Ross cleanup_pending:
761747dc10d7SGordon Ross atomic_dec(&intel_crtc->unpin_work_count);
761847dc10d7SGordon Ross crtc->fb = old_fb;
761947dc10d7SGordon Ross drm_gem_object_unreference(&work->old_fb_obj->base);
762047dc10d7SGordon Ross drm_gem_object_unreference(&obj->base);
762147dc10d7SGordon Ross mutex_unlock(&dev->struct_mutex);
762247dc10d7SGordon Ross
762347dc10d7SGordon Ross spin_lock_irqsave(&dev->event_lock, flags);
762447dc10d7SGordon Ross intel_crtc->unpin_work = NULL;
762547dc10d7SGordon Ross spin_unlock_irqrestore(&dev->event_lock, flags);
762647dc10d7SGordon Ross
762747dc10d7SGordon Ross drm_vblank_put(dev, intel_crtc->pipe);
762847dc10d7SGordon Ross free_work:
762947dc10d7SGordon Ross kfree(work, sizeof(struct intel_unpin_work));
763047dc10d7SGordon Ross
763147dc10d7SGordon Ross return ret;
763247dc10d7SGordon Ross }
763347dc10d7SGordon Ross
763447dc10d7SGordon Ross static struct drm_crtc_helper_funcs intel_helper_funcs = {
763547dc10d7SGordon Ross .mode_set_base_atomic = intel_pipe_set_base_atomic,
763647dc10d7SGordon Ross .load_lut = intel_crtc_load_lut,
763747dc10d7SGordon Ross };
763847dc10d7SGordon Ross
intel_encoder_crtc_ok(struct drm_encoder * encoder,struct drm_crtc * crtc)763947dc10d7SGordon Ross static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
764047dc10d7SGordon Ross struct drm_crtc *crtc)
764147dc10d7SGordon Ross {
764247dc10d7SGordon Ross struct drm_device *dev;
764347dc10d7SGordon Ross struct drm_crtc *tmp;
764447dc10d7SGordon Ross int crtc_mask = 1;
764547dc10d7SGordon Ross
764647dc10d7SGordon Ross ASSERT(crtc);
764747dc10d7SGordon Ross
764847dc10d7SGordon Ross dev = crtc->dev;
764947dc10d7SGordon Ross
765047dc10d7SGordon Ross list_for_each_entry(tmp, struct drm_crtc, &dev->mode_config.crtc_list, head) {
765147dc10d7SGordon Ross if (tmp == crtc)
765247dc10d7SGordon Ross break;
765347dc10d7SGordon Ross crtc_mask <<= 1;
765447dc10d7SGordon Ross }
765547dc10d7SGordon Ross
765647dc10d7SGordon Ross if (encoder->possible_crtcs & crtc_mask)
765747dc10d7SGordon Ross return true;
765847dc10d7SGordon Ross return false;
765947dc10d7SGordon Ross }
766047dc10d7SGordon Ross
766147dc10d7SGordon Ross /**
766247dc10d7SGordon Ross * intel_modeset_update_staged_output_state
766347dc10d7SGordon Ross *
766447dc10d7SGordon Ross * Updates the staged output configuration state, e.g. after we've read out the
766547dc10d7SGordon Ross * current hw state.
766647dc10d7SGordon Ross */
intel_modeset_update_staged_output_state(struct drm_device * dev)766747dc10d7SGordon Ross static void intel_modeset_update_staged_output_state(struct drm_device *dev)
766847dc10d7SGordon Ross {
766947dc10d7SGordon Ross struct intel_encoder *encoder;
767047dc10d7SGordon Ross struct intel_connector *connector;
767147dc10d7SGordon Ross
767247dc10d7SGordon Ross list_for_each_entry(connector, struct intel_connector, &dev->mode_config.connector_list,
767347dc10d7SGordon Ross base.head) {
767447dc10d7SGordon Ross connector->new_encoder =
767547dc10d7SGordon Ross to_intel_encoder(connector->base.encoder);
767647dc10d7SGordon Ross }
767747dc10d7SGordon Ross
767847dc10d7SGordon Ross list_for_each_entry(encoder, struct intel_encoder, &dev->mode_config.encoder_list,
767947dc10d7SGordon Ross base.head) {
768047dc10d7SGordon Ross encoder->new_crtc =
768147dc10d7SGordon Ross to_intel_crtc(encoder->base.crtc);
768247dc10d7SGordon Ross }
768347dc10d7SGordon Ross }
768447dc10d7SGordon Ross
768547dc10d7SGordon Ross /**
768647dc10d7SGordon Ross * intel_modeset_commit_output_state
768747dc10d7SGordon Ross *
768847dc10d7SGordon Ross * This function copies the stage display pipe configuration to the real one.
768947dc10d7SGordon Ross */
intel_modeset_commit_output_state(struct drm_device * dev)769047dc10d7SGordon Ross static void intel_modeset_commit_output_state(struct drm_device *dev)
769147dc10d7SGordon Ross {
769247dc10d7SGordon Ross struct intel_encoder *encoder;
769347dc10d7SGordon Ross struct intel_connector *connector;
769447dc10d7SGordon Ross
769547dc10d7SGordon Ross list_for_each_entry(connector, struct intel_connector, &dev->mode_config.connector_list,
769647dc10d7SGordon Ross base.head) {
769747dc10d7SGordon Ross connector->base.encoder = &connector->new_encoder->base;
769847dc10d7SGordon Ross }
769947dc10d7SGordon Ross
770047dc10d7SGordon Ross list_for_each_entry(encoder, struct intel_encoder, &dev->mode_config.encoder_list,
770147dc10d7SGordon Ross base.head) {
770247dc10d7SGordon Ross encoder->base.crtc = &encoder->new_crtc->base;
770347dc10d7SGordon Ross }
770447dc10d7SGordon Ross }
770547dc10d7SGordon Ross
770647dc10d7SGordon Ross static void
connected_sink_compute_bpp(struct intel_connector * connector,struct intel_crtc_config * pipe_config)770747dc10d7SGordon Ross connected_sink_compute_bpp(struct intel_connector * connector,
770847dc10d7SGordon Ross struct intel_crtc_config *pipe_config)
770947dc10d7SGordon Ross {
771047dc10d7SGordon Ross int bpp = pipe_config->pipe_bpp;
771147dc10d7SGordon Ross
771247dc10d7SGordon Ross DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
771347dc10d7SGordon Ross connector->base.base.id,
771447dc10d7SGordon Ross drm_get_connector_name(&connector->base));
771547dc10d7SGordon Ross
771647dc10d7SGordon Ross /* Don't use an invalid EDID bpc value */
771747dc10d7SGordon Ross if (connector->base.display_info.bpc &&
771847dc10d7SGordon Ross connector->base.display_info.bpc * 3 < bpp) {
771947dc10d7SGordon Ross DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
772047dc10d7SGordon Ross bpp, connector->base.display_info.bpc*3);
772147dc10d7SGordon Ross pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
772247dc10d7SGordon Ross }
772347dc10d7SGordon Ross
772447dc10d7SGordon Ross /* Clamp bpp to 8 on screens without EDID 1.4 */
772547dc10d7SGordon Ross if (connector->base.display_info.bpc == 0 && bpp > 24) {
772647dc10d7SGordon Ross DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
772747dc10d7SGordon Ross bpp);
772847dc10d7SGordon Ross pipe_config->pipe_bpp = 24;
772947dc10d7SGordon Ross }
773047dc10d7SGordon Ross }
773147dc10d7SGordon Ross
773247dc10d7SGordon Ross static int
compute_baseline_pipe_bpp(struct intel_crtc * crtc,struct drm_framebuffer * fb,struct intel_crtc_config * pipe_config)773347dc10d7SGordon Ross compute_baseline_pipe_bpp(struct intel_crtc *crtc,
773447dc10d7SGordon Ross struct drm_framebuffer *fb,
773547dc10d7SGordon Ross struct intel_crtc_config *pipe_config)
773647dc10d7SGordon Ross {
773747dc10d7SGordon Ross struct drm_device *dev = crtc->base.dev;
773847dc10d7SGordon Ross struct intel_connector *connector;
773947dc10d7SGordon Ross int bpp;
774047dc10d7SGordon Ross
774147dc10d7SGordon Ross switch (fb->pixel_format) {
774247dc10d7SGordon Ross case DRM_FORMAT_C8:
774347dc10d7SGordon Ross bpp = 8*3; /* since we go through a colormap */
774447dc10d7SGordon Ross break;
774547dc10d7SGordon Ross case DRM_FORMAT_XRGB1555:
774647dc10d7SGordon Ross case DRM_FORMAT_ARGB1555:
774747dc10d7SGordon Ross /* checked in intel_framebuffer_init already */
774847dc10d7SGordon Ross if (INTEL_INFO(dev)->gen > 3)
774947dc10d7SGordon Ross return -EINVAL;
7750*46b209bcSAurelien Larcher /* FALLTHROUGH */
775147dc10d7SGordon Ross case DRM_FORMAT_RGB565:
775247dc10d7SGordon Ross bpp = 6*3; /* min is 18bpp */
775347dc10d7SGordon Ross break;
775447dc10d7SGordon Ross case DRM_FORMAT_XBGR8888:
775547dc10d7SGordon Ross case DRM_FORMAT_ABGR8888:
775647dc10d7SGordon Ross /* checked in intel_framebuffer_init already */
775747dc10d7SGordon Ross if (INTEL_INFO(dev)->gen < 4)
775847dc10d7SGordon Ross return -EINVAL;
7759*46b209bcSAurelien Larcher /* FALLTHROUGH */
776047dc10d7SGordon Ross case DRM_FORMAT_XRGB8888:
776147dc10d7SGordon Ross case DRM_FORMAT_ARGB8888:
776247dc10d7SGordon Ross bpp = 8*3;
776347dc10d7SGordon Ross break;
776447dc10d7SGordon Ross case DRM_FORMAT_XRGB2101010:
776547dc10d7SGordon Ross case DRM_FORMAT_ARGB2101010:
776647dc10d7SGordon Ross case DRM_FORMAT_XBGR2101010:
776747dc10d7SGordon Ross case DRM_FORMAT_ABGR2101010:
776847dc10d7SGordon Ross /* checked in intel_framebuffer_init already */
776947dc10d7SGordon Ross if (INTEL_INFO(dev)->gen < 4)
777047dc10d7SGordon Ross return -EINVAL;
777147dc10d7SGordon Ross bpp = 10*3;
777247dc10d7SGordon Ross break;
777347dc10d7SGordon Ross /* TODO: gen4+ supports 16 bpc floating point, too. */
777447dc10d7SGordon Ross default:
777547dc10d7SGordon Ross DRM_DEBUG_KMS("unsupported depth\n");
777647dc10d7SGordon Ross return -EINVAL;
777747dc10d7SGordon Ross }
777847dc10d7SGordon Ross
777947dc10d7SGordon Ross pipe_config->pipe_bpp = bpp;
778047dc10d7SGordon Ross
778147dc10d7SGordon Ross /* Clamp display bpp to EDID value */
778247dc10d7SGordon Ross list_for_each_entry(connector, struct intel_connector, &dev->mode_config.connector_list,
778347dc10d7SGordon Ross base.head) {
778447dc10d7SGordon Ross if (!connector->new_encoder ||
778547dc10d7SGordon Ross connector->new_encoder->new_crtc != crtc)
778647dc10d7SGordon Ross continue;
778747dc10d7SGordon Ross
778847dc10d7SGordon Ross connected_sink_compute_bpp(connector, pipe_config);
778947dc10d7SGordon Ross }
779047dc10d7SGordon Ross
779147dc10d7SGordon Ross return bpp;
779247dc10d7SGordon Ross }
779347dc10d7SGordon Ross
intel_dump_pipe_config(struct intel_crtc * crtc,struct intel_crtc_config * pipe_config,const char * context)779447dc10d7SGordon Ross static void intel_dump_pipe_config(struct intel_crtc *crtc,
779547dc10d7SGordon Ross struct intel_crtc_config *pipe_config,
779647dc10d7SGordon Ross const char *context)
779747dc10d7SGordon Ross {
779847dc10d7SGordon Ross DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
779947dc10d7SGordon Ross context, pipe_name(crtc->pipe));
780047dc10d7SGordon Ross
780147dc10d7SGordon Ross DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
780247dc10d7SGordon Ross DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
780347dc10d7SGordon Ross pipe_config->pipe_bpp, pipe_config->dither);
780447dc10d7SGordon Ross DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
780547dc10d7SGordon Ross pipe_config->has_pch_encoder,
780647dc10d7SGordon Ross pipe_config->fdi_lanes,
780747dc10d7SGordon Ross pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
780847dc10d7SGordon Ross pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
780947dc10d7SGordon Ross pipe_config->fdi_m_n.tu);
781047dc10d7SGordon Ross DRM_DEBUG_KMS("requested mode:\n");
781147dc10d7SGordon Ross drm_mode_debug_printmodeline(&pipe_config->requested_mode);
781247dc10d7SGordon Ross DRM_DEBUG_KMS("adjusted mode:\n");
781347dc10d7SGordon Ross drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
781447dc10d7SGordon Ross DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
781547dc10d7SGordon Ross pipe_config->gmch_pfit.control,
781647dc10d7SGordon Ross pipe_config->gmch_pfit.pgm_ratios,
781747dc10d7SGordon Ross pipe_config->gmch_pfit.lvds_border_bits);
781847dc10d7SGordon Ross DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x\n",
781947dc10d7SGordon Ross pipe_config->pch_pfit.pos,
782047dc10d7SGordon Ross pipe_config->pch_pfit.size);
782147dc10d7SGordon Ross DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
782247dc10d7SGordon Ross }
782347dc10d7SGordon Ross
check_encoder_cloning(struct drm_crtc * crtc)782447dc10d7SGordon Ross static bool check_encoder_cloning(struct drm_crtc *crtc)
782547dc10d7SGordon Ross {
782647dc10d7SGordon Ross int num_encoders = 0;
782747dc10d7SGordon Ross bool uncloneable_encoders = false;
782847dc10d7SGordon Ross struct intel_encoder *encoder;
782947dc10d7SGordon Ross
783047dc10d7SGordon Ross list_for_each_entry(encoder, struct intel_encoder, &crtc->dev->mode_config.encoder_list,
783147dc10d7SGordon Ross base.head) {
783247dc10d7SGordon Ross if (&encoder->new_crtc->base != crtc)
783347dc10d7SGordon Ross continue;
783447dc10d7SGordon Ross
783547dc10d7SGordon Ross num_encoders++;
783647dc10d7SGordon Ross if (!encoder->cloneable)
783747dc10d7SGordon Ross uncloneable_encoders = true;
783847dc10d7SGordon Ross }
783947dc10d7SGordon Ross
784047dc10d7SGordon Ross return !(num_encoders > 1 && uncloneable_encoders);
784147dc10d7SGordon Ross }
784247dc10d7SGordon Ross
784347dc10d7SGordon Ross static struct intel_crtc_config *
intel_modeset_pipe_config(struct drm_crtc * crtc,struct drm_framebuffer * fb,struct drm_display_mode * mode)784447dc10d7SGordon Ross intel_modeset_pipe_config(struct drm_crtc *crtc,
784547dc10d7SGordon Ross struct drm_framebuffer *fb,
784647dc10d7SGordon Ross struct drm_display_mode *mode)
784747dc10d7SGordon Ross {
784847dc10d7SGordon Ross struct drm_device *dev = crtc->dev;
784947dc10d7SGordon Ross struct drm_encoder_helper_funcs *encoder_funcs;
785047dc10d7SGordon Ross struct intel_encoder *encoder;
785147dc10d7SGordon Ross struct intel_crtc_config *pipe_config;
785247dc10d7SGordon Ross int plane_bpp, ret = -EINVAL;
785347dc10d7SGordon Ross bool retry = true;
785447dc10d7SGordon Ross
785547dc10d7SGordon Ross if (!check_encoder_cloning(crtc)) {
785647dc10d7SGordon Ross DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
785747dc10d7SGordon Ross return NULL;
785847dc10d7SGordon Ross }
785947dc10d7SGordon Ross
786047dc10d7SGordon Ross pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
786147dc10d7SGordon Ross if (!pipe_config)
786247dc10d7SGordon Ross return NULL;
786347dc10d7SGordon Ross
786447dc10d7SGordon Ross drm_mode_copy(&pipe_config->adjusted_mode, mode);
786547dc10d7SGordon Ross drm_mode_copy(&pipe_config->requested_mode, mode);
786647dc10d7SGordon Ross pipe_config->cpu_transcoder = (enum transcoder)to_intel_crtc(crtc)->pipe;
786747dc10d7SGordon Ross pipe_config->shared_dpll = DPLL_ID_PRIVATE;
786847dc10d7SGordon Ross
786947dc10d7SGordon Ross /* Compute a starting value for pipe_config->pipe_bpp taking the source
787047dc10d7SGordon Ross * plane pixel format and any sink constraints into account. Returns the
787147dc10d7SGordon Ross * source plane bpp so that dithering can be selected on mismatches
787247dc10d7SGordon Ross * after encoders and crtc also have had their say. */
787347dc10d7SGordon Ross plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
787447dc10d7SGordon Ross fb, pipe_config);
787547dc10d7SGordon Ross if (plane_bpp < 0)
787647dc10d7SGordon Ross goto fail;
787747dc10d7SGordon Ross
787847dc10d7SGordon Ross encoder_retry:
787947dc10d7SGordon Ross /* Ensure the port clock defaults are reset when retrying. */
788047dc10d7SGordon Ross pipe_config->port_clock = 0;
788147dc10d7SGordon Ross pipe_config->pixel_multiplier = 1;
788247dc10d7SGordon Ross
788347dc10d7SGordon Ross /* Pass our mode to the connectors and the CRTC to give them a chance to
788447dc10d7SGordon Ross * adjust it according to limitations or connector properties, and also
788547dc10d7SGordon Ross * a chance to reject the mode entirely.
788647dc10d7SGordon Ross */
788747dc10d7SGordon Ross list_for_each_entry(encoder, struct intel_encoder, &dev->mode_config.encoder_list,
788847dc10d7SGordon Ross base.head) {
788947dc10d7SGordon Ross
789047dc10d7SGordon Ross if (&encoder->new_crtc->base != crtc)
789147dc10d7SGordon Ross continue;
789247dc10d7SGordon Ross
789347dc10d7SGordon Ross if (encoder->compute_config) {
789447dc10d7SGordon Ross if (!(encoder->compute_config(encoder, pipe_config))) {
789547dc10d7SGordon Ross DRM_DEBUG_KMS("Encoder config failure\n");
789647dc10d7SGordon Ross goto fail;
789747dc10d7SGordon Ross }
789847dc10d7SGordon Ross
789947dc10d7SGordon Ross continue;
790047dc10d7SGordon Ross }
790147dc10d7SGordon Ross
790247dc10d7SGordon Ross encoder_funcs = encoder->base.helper_private;
790347dc10d7SGordon Ross if (!(encoder_funcs->mode_fixup(&encoder->base,
790447dc10d7SGordon Ross &pipe_config->requested_mode,
790547dc10d7SGordon Ross &pipe_config->adjusted_mode))) {
790647dc10d7SGordon Ross DRM_DEBUG_KMS("Encoder fixup failed\n");
790747dc10d7SGordon Ross goto fail;
790847dc10d7SGordon Ross }
790947dc10d7SGordon Ross }
791047dc10d7SGordon Ross
791147dc10d7SGordon Ross /* Set default port clock if not overwritten by the encoder. Needs to be
791247dc10d7SGordon Ross * done afterwards in case the encoder adjusts the mode. */
791347dc10d7SGordon Ross if (!pipe_config->port_clock)
791447dc10d7SGordon Ross pipe_config->port_clock = pipe_config->adjusted_mode.clock;
791547dc10d7SGordon Ross
791647dc10d7SGordon Ross ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
791747dc10d7SGordon Ross if (ret < 0) {
791847dc10d7SGordon Ross DRM_DEBUG_KMS("CRTC fixup failed\n");
791947dc10d7SGordon Ross goto fail;
792047dc10d7SGordon Ross }
792147dc10d7SGordon Ross
792247dc10d7SGordon Ross if (ret == RETRY) {
792347dc10d7SGordon Ross if (!retry) {
792447dc10d7SGordon Ross DRM_ERROR("loop in pipe configuration computation");
792547dc10d7SGordon Ross ret = -EINVAL;
792647dc10d7SGordon Ross goto fail;
792747dc10d7SGordon Ross }
792847dc10d7SGordon Ross
792947dc10d7SGordon Ross DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
793047dc10d7SGordon Ross retry = false;
793147dc10d7SGordon Ross goto encoder_retry;
793247dc10d7SGordon Ross }
793347dc10d7SGordon Ross
793447dc10d7SGordon Ross pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
793547dc10d7SGordon Ross DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
793647dc10d7SGordon Ross plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
793747dc10d7SGordon Ross
793847dc10d7SGordon Ross return pipe_config;
793947dc10d7SGordon Ross fail:
794047dc10d7SGordon Ross kfree(pipe_config, sizeof(*pipe_config));
794147dc10d7SGordon Ross return NULL;
794247dc10d7SGordon Ross }
794347dc10d7SGordon Ross
794447dc10d7SGordon Ross /* Computes which crtcs are affected and sets the relevant bits in the mask. For
794547dc10d7SGordon Ross * simplicity we use the crtc's pipe number (because it's easier to obtain). */
794647dc10d7SGordon Ross static void
intel_modeset_affected_pipes(struct drm_crtc * crtc,unsigned * modeset_pipes,unsigned * prepare_pipes,unsigned * disable_pipes)794747dc10d7SGordon Ross intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
794847dc10d7SGordon Ross unsigned *prepare_pipes, unsigned *disable_pipes)
794947dc10d7SGordon Ross {
795047dc10d7SGordon Ross struct intel_crtc *intel_crtc;
795147dc10d7SGordon Ross struct drm_device *dev = crtc->dev;
795247dc10d7SGordon Ross struct intel_encoder *encoder;
795347dc10d7SGordon Ross struct intel_connector *connector;
795447dc10d7SGordon Ross struct drm_crtc *tmp_crtc;
795547dc10d7SGordon Ross
795647dc10d7SGordon Ross *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
795747dc10d7SGordon Ross
795847dc10d7SGordon Ross /* Check which crtcs have changed outputs connected to them, these need
795947dc10d7SGordon Ross * to be part of the prepare_pipes mask. We don't (yet) support global
796047dc10d7SGordon Ross * modeset across multiple crtcs, so modeset_pipes will only have one
796147dc10d7SGordon Ross * bit set at most. */
796247dc10d7SGordon Ross list_for_each_entry(connector, struct intel_connector, &dev->mode_config.connector_list,
796347dc10d7SGordon Ross base.head) {
796447dc10d7SGordon Ross if (connector->base.encoder == &connector->new_encoder->base)
796547dc10d7SGordon Ross continue;
796647dc10d7SGordon Ross
796747dc10d7SGordon Ross if (connector->base.encoder) {
796847dc10d7SGordon Ross tmp_crtc = connector->base.encoder->crtc;
796947dc10d7SGordon Ross
797047dc10d7SGordon Ross *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
797147dc10d7SGordon Ross }
797247dc10d7SGordon Ross
797347dc10d7SGordon Ross if (connector->new_encoder)
797447dc10d7SGordon Ross *prepare_pipes |=
797547dc10d7SGordon Ross 1 << connector->new_encoder->new_crtc->pipe;
797647dc10d7SGordon Ross }
797747dc10d7SGordon Ross
797847dc10d7SGordon Ross list_for_each_entry(encoder, struct intel_encoder, &dev->mode_config.encoder_list,
797947dc10d7SGordon Ross base.head) {
798047dc10d7SGordon Ross if (encoder->base.crtc == &encoder->new_crtc->base)
798147dc10d7SGordon Ross continue;
798247dc10d7SGordon Ross
798347dc10d7SGordon Ross if (encoder->base.crtc) {
798447dc10d7SGordon Ross tmp_crtc = encoder->base.crtc;
798547dc10d7SGordon Ross
798647dc10d7SGordon Ross *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
798747dc10d7SGordon Ross }
798847dc10d7SGordon Ross
798947dc10d7SGordon Ross if (encoder->new_crtc)
799047dc10d7SGordon Ross *prepare_pipes |= 1 << encoder->new_crtc->pipe;
799147dc10d7SGordon Ross }
799247dc10d7SGordon Ross
799347dc10d7SGordon Ross /* Check for any pipes that will be fully disabled ... */
799447dc10d7SGordon Ross list_for_each_entry(intel_crtc, struct intel_crtc, &dev->mode_config.crtc_list,
799547dc10d7SGordon Ross base.head) {
799647dc10d7SGordon Ross bool used = false;
799747dc10d7SGordon Ross
799847dc10d7SGordon Ross /* Don't try to disable disabled crtcs. */
799947dc10d7SGordon Ross if (!intel_crtc->base.enabled)
800047dc10d7SGordon Ross continue;
800147dc10d7SGordon Ross
800247dc10d7SGordon Ross list_for_each_entry(encoder, struct intel_encoder, &dev->mode_config.encoder_list,
800347dc10d7SGordon Ross base.head) {
800447dc10d7SGordon Ross if (encoder->new_crtc == intel_crtc)
800547dc10d7SGordon Ross used = true;
800647dc10d7SGordon Ross }
800747dc10d7SGordon Ross
800847dc10d7SGordon Ross if (!used)
800947dc10d7SGordon Ross *disable_pipes |= 1 << intel_crtc->pipe;
801047dc10d7SGordon Ross }
801147dc10d7SGordon Ross
801247dc10d7SGordon Ross
801347dc10d7SGordon Ross /* set_mode is also used to update properties on life display pipes. */
801447dc10d7SGordon Ross intel_crtc = to_intel_crtc(crtc);
801547dc10d7SGordon Ross if (crtc->enabled)
801647dc10d7SGordon Ross *prepare_pipes |= 1 << intel_crtc->pipe;
801747dc10d7SGordon Ross
801847dc10d7SGordon Ross /*
801947dc10d7SGordon Ross * For simplicity do a full modeset on any pipe where the output routing
802047dc10d7SGordon Ross * changed. We could be more clever, but that would require us to be
802147dc10d7SGordon Ross * more careful with calling the relevant encoder->mode_set functions.
802247dc10d7SGordon Ross */
802347dc10d7SGordon Ross if (*prepare_pipes)
802447dc10d7SGordon Ross *modeset_pipes = *prepare_pipes;
802547dc10d7SGordon Ross
802647dc10d7SGordon Ross /* ... and mask these out. */
802747dc10d7SGordon Ross *modeset_pipes &= ~(*disable_pipes);
802847dc10d7SGordon Ross *prepare_pipes &= ~(*disable_pipes);
802947dc10d7SGordon Ross
803047dc10d7SGordon Ross /*
803147dc10d7SGordon Ross * HACK: We don't (yet) fully support global modesets. intel_set_config
803247dc10d7SGordon Ross * obies this rule, but the modeset restore mode of
803347dc10d7SGordon Ross * intel_modeset_setup_hw_state does not.
803447dc10d7SGordon Ross */
803547dc10d7SGordon Ross *modeset_pipes &= 1 << intel_crtc->pipe;
803647dc10d7SGordon Ross *prepare_pipes &= 1 << intel_crtc->pipe;
803747dc10d7SGordon Ross
803847dc10d7SGordon Ross DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
803947dc10d7SGordon Ross *modeset_pipes, *prepare_pipes, *disable_pipes);
804047dc10d7SGordon Ross }
804147dc10d7SGordon Ross
intel_crtc_in_use(struct drm_crtc * crtc)804247dc10d7SGordon Ross static bool intel_crtc_in_use(struct drm_crtc *crtc)
804347dc10d7SGordon Ross {
804447dc10d7SGordon Ross struct drm_encoder *encoder;
804547dc10d7SGordon Ross struct drm_device *dev = crtc->dev;
804647dc10d7SGordon Ross
804747dc10d7SGordon Ross list_for_each_entry(encoder, struct drm_encoder, &dev->mode_config.encoder_list, head)
804847dc10d7SGordon Ross if (encoder->crtc == crtc)
804947dc10d7SGordon Ross return true;
805047dc10d7SGordon Ross
805147dc10d7SGordon Ross return false;
805247dc10d7SGordon Ross }
805347dc10d7SGordon Ross
805447dc10d7SGordon Ross static void
intel_modeset_update_state(struct drm_device * dev,unsigned prepare_pipes)805547dc10d7SGordon Ross intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
805647dc10d7SGordon Ross {
805747dc10d7SGordon Ross struct intel_encoder *intel_encoder;
805847dc10d7SGordon Ross struct intel_crtc *intel_crtc;
805947dc10d7SGordon Ross struct drm_connector *connector;
806047dc10d7SGordon Ross
806147dc10d7SGordon Ross list_for_each_entry(intel_encoder, struct intel_encoder, &dev->mode_config.encoder_list,
806247dc10d7SGordon Ross base.head) {
806347dc10d7SGordon Ross if (!intel_encoder->base.crtc)
806447dc10d7SGordon Ross continue;
806547dc10d7SGordon Ross
806647dc10d7SGordon Ross intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
806747dc10d7SGordon Ross
806847dc10d7SGordon Ross if (prepare_pipes & (1 << intel_crtc->pipe))
806947dc10d7SGordon Ross intel_encoder->connectors_active = false;
807047dc10d7SGordon Ross }
807147dc10d7SGordon Ross
807247dc10d7SGordon Ross intel_modeset_commit_output_state(dev);
807347dc10d7SGordon Ross
807447dc10d7SGordon Ross /* Update computed state. */
807547dc10d7SGordon Ross list_for_each_entry(intel_crtc, struct intel_crtc, &dev->mode_config.crtc_list,
807647dc10d7SGordon Ross base.head) {
807747dc10d7SGordon Ross intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
807847dc10d7SGordon Ross }
807947dc10d7SGordon Ross
808047dc10d7SGordon Ross list_for_each_entry(connector, struct drm_connector, &dev->mode_config.connector_list, head) {
808147dc10d7SGordon Ross if (!connector->encoder || !connector->encoder->crtc)
808247dc10d7SGordon Ross continue;
808347dc10d7SGordon Ross
808447dc10d7SGordon Ross intel_crtc = to_intel_crtc(connector->encoder->crtc);
808547dc10d7SGordon Ross
808647dc10d7SGordon Ross if (prepare_pipes & (1 << intel_crtc->pipe)) {
808747dc10d7SGordon Ross struct drm_property *dpms_property =
808847dc10d7SGordon Ross dev->mode_config.dpms_property;
808947dc10d7SGordon Ross
809047dc10d7SGordon Ross connector->dpms = DRM_MODE_DPMS_ON;
809147dc10d7SGordon Ross drm_object_property_set_value(&connector->base,
809247dc10d7SGordon Ross dpms_property,
809347dc10d7SGordon Ross DRM_MODE_DPMS_ON);
809447dc10d7SGordon Ross
809547dc10d7SGordon Ross intel_encoder = to_intel_encoder(connector->encoder);
809647dc10d7SGordon Ross intel_encoder->connectors_active = true;
809747dc10d7SGordon Ross }
809847dc10d7SGordon Ross }
809947dc10d7SGordon Ross
810047dc10d7SGordon Ross }
810147dc10d7SGordon Ross
810247dc10d7SGordon Ross #define for_each_intel_crtc_masked(dev, mask, _intel_crtc) \
810347dc10d7SGordon Ross list_for_each_entry((_intel_crtc), struct intel_crtc, \
810447dc10d7SGordon Ross &(dev)->mode_config.crtc_list, \
810547dc10d7SGordon Ross base.head) \
810647dc10d7SGordon Ross if (mask & (1 <<(_intel_crtc)->pipe)) \
810747dc10d7SGordon Ross
810847dc10d7SGordon Ross static bool
intel_pipe_config_compare(struct drm_device * dev,struct intel_crtc_config * current_config,struct intel_crtc_config * pipe_config)810947dc10d7SGordon Ross intel_pipe_config_compare(struct drm_device *dev,
811047dc10d7SGordon Ross struct intel_crtc_config *current_config,
811147dc10d7SGordon Ross struct intel_crtc_config *pipe_config)
811247dc10d7SGordon Ross {
811347dc10d7SGordon Ross #define PIPE_CONF_CHECK_X(name) \
811447dc10d7SGordon Ross if (current_config->name != pipe_config->name) { \
811547dc10d7SGordon Ross DRM_DEBUG_KMS("mismatch in " #name " " \
811647dc10d7SGordon Ross "(expected 0x%08x, found 0x%08x)\n", \
811747dc10d7SGordon Ross current_config->name, \
811847dc10d7SGordon Ross pipe_config->name); \
811947dc10d7SGordon Ross return false; \
812047dc10d7SGordon Ross }
812147dc10d7SGordon Ross
812247dc10d7SGordon Ross #define PIPE_CONF_CHECK_I(name) \
812347dc10d7SGordon Ross if (current_config->name != pipe_config->name) { \
812447dc10d7SGordon Ross DRM_DEBUG_KMS("mismatch in " #name " " \
812547dc10d7SGordon Ross "(expected %i, found %i)\n", \
812647dc10d7SGordon Ross current_config->name, \
812747dc10d7SGordon Ross pipe_config->name); \
812847dc10d7SGordon Ross return false; \
812947dc10d7SGordon Ross }
813047dc10d7SGordon Ross
813147dc10d7SGordon Ross #define PIPE_CONF_CHECK_FLAGS(name, mask) \
813247dc10d7SGordon Ross if ((current_config->name ^ pipe_config->name) & (mask)) { \
813347dc10d7SGordon Ross DRM_DEBUG_KMS("mismatch in " #name " " \
813447dc10d7SGordon Ross "(expected %i, found %i)\n", \
813547dc10d7SGordon Ross current_config->name & (mask), \
813647dc10d7SGordon Ross pipe_config->name & (mask)); \
813747dc10d7SGordon Ross return false; \
813847dc10d7SGordon Ross }
813947dc10d7SGordon Ross
814047dc10d7SGordon Ross #define PIPE_CONF_QUIRK(quirk) \
814147dc10d7SGordon Ross ((current_config->quirks | pipe_config->quirks) & (quirk))
814247dc10d7SGordon Ross
814347dc10d7SGordon Ross PIPE_CONF_CHECK_I(cpu_transcoder);
814447dc10d7SGordon Ross
814547dc10d7SGordon Ross PIPE_CONF_CHECK_I(has_pch_encoder);
814647dc10d7SGordon Ross PIPE_CONF_CHECK_I(fdi_lanes);
814747dc10d7SGordon Ross PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
814847dc10d7SGordon Ross PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
814947dc10d7SGordon Ross PIPE_CONF_CHECK_I(fdi_m_n.link_m);
815047dc10d7SGordon Ross PIPE_CONF_CHECK_I(fdi_m_n.link_n);
815147dc10d7SGordon Ross PIPE_CONF_CHECK_I(fdi_m_n.tu);
815247dc10d7SGordon Ross
815347dc10d7SGordon Ross PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
815447dc10d7SGordon Ross PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
815547dc10d7SGordon Ross PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
815647dc10d7SGordon Ross PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
815747dc10d7SGordon Ross PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
815847dc10d7SGordon Ross PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
815947dc10d7SGordon Ross
816047dc10d7SGordon Ross PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
816147dc10d7SGordon Ross PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
816247dc10d7SGordon Ross PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
816347dc10d7SGordon Ross PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
816447dc10d7SGordon Ross PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
816547dc10d7SGordon Ross PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
816647dc10d7SGordon Ross
816747dc10d7SGordon Ross if (!HAS_PCH_SPLIT(dev))
816847dc10d7SGordon Ross PIPE_CONF_CHECK_I(pixel_multiplier);
816947dc10d7SGordon Ross
817047dc10d7SGordon Ross PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
817147dc10d7SGordon Ross DRM_MODE_FLAG_INTERLACE);
817247dc10d7SGordon Ross
817347dc10d7SGordon Ross if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
817447dc10d7SGordon Ross PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
817547dc10d7SGordon Ross DRM_MODE_FLAG_PHSYNC);
817647dc10d7SGordon Ross PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
817747dc10d7SGordon Ross DRM_MODE_FLAG_NHSYNC);
817847dc10d7SGordon Ross PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
817947dc10d7SGordon Ross DRM_MODE_FLAG_PVSYNC);
818047dc10d7SGordon Ross PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
818147dc10d7SGordon Ross DRM_MODE_FLAG_NVSYNC);
818247dc10d7SGordon Ross }
818347dc10d7SGordon Ross
818447dc10d7SGordon Ross PIPE_CONF_CHECK_I(requested_mode.hdisplay);
818547dc10d7SGordon Ross PIPE_CONF_CHECK_I(requested_mode.vdisplay);
818647dc10d7SGordon Ross
818747dc10d7SGordon Ross PIPE_CONF_CHECK_I(gmch_pfit.control);
818847dc10d7SGordon Ross /* pfit ratios are autocomputed by the hw on gen4+ */
818947dc10d7SGordon Ross if (INTEL_INFO(dev)->gen < 4)
819047dc10d7SGordon Ross PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
819147dc10d7SGordon Ross PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
819247dc10d7SGordon Ross PIPE_CONF_CHECK_I(pch_pfit.pos);
819347dc10d7SGordon Ross PIPE_CONF_CHECK_I(pch_pfit.size);
819447dc10d7SGordon Ross
819547dc10d7SGordon Ross PIPE_CONF_CHECK_I(ips_enabled);
819647dc10d7SGordon Ross
819747dc10d7SGordon Ross PIPE_CONF_CHECK_I(shared_dpll);
819847dc10d7SGordon Ross PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
819947dc10d7SGordon Ross PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
820047dc10d7SGordon Ross PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
820147dc10d7SGordon Ross
820247dc10d7SGordon Ross #undef PIPE_CONF_CHECK_X
820347dc10d7SGordon Ross #undef PIPE_CONF_CHECK_I
820447dc10d7SGordon Ross #undef PIPE_CONF_CHECK_FLAGS
820547dc10d7SGordon Ross #undef PIPE_CONF_QUIRK
820647dc10d7SGordon Ross
820747dc10d7SGordon Ross return true;
820847dc10d7SGordon Ross }
820947dc10d7SGordon Ross
821047dc10d7SGordon Ross static void
check_connector_state(struct drm_device * dev)821147dc10d7SGordon Ross check_connector_state(struct drm_device *dev)
821247dc10d7SGordon Ross {
821347dc10d7SGordon Ross struct intel_connector *connector;
821447dc10d7SGordon Ross
821547dc10d7SGordon Ross list_for_each_entry(connector, struct intel_connector, &dev->mode_config.connector_list,
821647dc10d7SGordon Ross base.head) {
821747dc10d7SGordon Ross /* This also checks the encoder/connector hw state with the
821847dc10d7SGordon Ross * ->get_hw_state callbacks. */
821947dc10d7SGordon Ross intel_connector_check_state(connector);
822047dc10d7SGordon Ross
822147dc10d7SGordon Ross if (&connector->new_encoder->base != connector->base.encoder)
822247dc10d7SGordon Ross DRM_ERROR("connector's staged encoder doesn't match current encoder\n");
822347dc10d7SGordon Ross }
822447dc10d7SGordon Ross }
822547dc10d7SGordon Ross
822647dc10d7SGordon Ross static void
check_encoder_state(struct drm_device * dev)822747dc10d7SGordon Ross check_encoder_state(struct drm_device *dev)
822847dc10d7SGordon Ross {
822947dc10d7SGordon Ross struct intel_encoder *encoder;
823047dc10d7SGordon Ross struct intel_connector *connector;
823147dc10d7SGordon Ross
823247dc10d7SGordon Ross list_for_each_entry(encoder, struct intel_encoder, &dev->mode_config.encoder_list,
823347dc10d7SGordon Ross base.head) {
823447dc10d7SGordon Ross bool enabled = false;
823547dc10d7SGordon Ross bool active = false;
823647dc10d7SGordon Ross enum pipe pipe, tracked_pipe;
823747dc10d7SGordon Ross
823847dc10d7SGordon Ross DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
823947dc10d7SGordon Ross encoder->base.base.id,
824047dc10d7SGordon Ross drm_get_encoder_name(&encoder->base));
824147dc10d7SGordon Ross
824247dc10d7SGordon Ross if (&encoder->new_crtc->base != encoder->base.crtc)
824347dc10d7SGordon Ross DRM_ERROR("encoder's stage crtc doesn't match current crtc\n");
824447dc10d7SGordon Ross if (encoder->connectors_active && !encoder->base.crtc)
824547dc10d7SGordon Ross DRM_ERROR("encoder's active_connectors set, but no crtc\n");
824647dc10d7SGordon Ross
824747dc10d7SGordon Ross list_for_each_entry(connector, struct intel_connector, &dev->mode_config.connector_list,
824847dc10d7SGordon Ross base.head) {
824947dc10d7SGordon Ross if (connector->base.encoder != &encoder->base)
825047dc10d7SGordon Ross continue;
825147dc10d7SGordon Ross enabled = true;
825247dc10d7SGordon Ross if (connector->base.dpms != DRM_MODE_DPMS_OFF)
825347dc10d7SGordon Ross active = true;
825447dc10d7SGordon Ross }
825547dc10d7SGordon Ross if (!!encoder->base.crtc != enabled)
825647dc10d7SGordon Ross DRM_ERROR("encoder's enabled state mismatch "
825747dc10d7SGordon Ross "(expected %i, found %i)\n",
825847dc10d7SGordon Ross !!encoder->base.crtc, enabled);
825947dc10d7SGordon Ross if (active && !encoder->base.crtc)
826047dc10d7SGordon Ross DRM_ERROR("active encoder with no crtc\n");
826147dc10d7SGordon Ross
826247dc10d7SGordon Ross if (encoder->connectors_active != active)
826347dc10d7SGordon Ross DRM_ERROR("encoder's computed active state doesn't match tracked active state "
826447dc10d7SGordon Ross "(expected %i, found %i)\n", active, encoder->connectors_active);
826547dc10d7SGordon Ross
826647dc10d7SGordon Ross active = encoder->get_hw_state(encoder, &pipe);
826747dc10d7SGordon Ross if (active != encoder->connectors_active)
826847dc10d7SGordon Ross DRM_ERROR("encoder's hw state doesn't match sw tracking "
826947dc10d7SGordon Ross "(expected %i, found %i)\n",
827047dc10d7SGordon Ross encoder->connectors_active, active);
827147dc10d7SGordon Ross
827247dc10d7SGordon Ross if (!encoder->base.crtc)
827347dc10d7SGordon Ross continue;
827447dc10d7SGordon Ross
827547dc10d7SGordon Ross tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
827647dc10d7SGordon Ross if (active && pipe != tracked_pipe)
827747dc10d7SGordon Ross DRM_ERROR("active encoder's pipe doesn't match"
827847dc10d7SGordon Ross "(expected %i, found %i)\n",
827947dc10d7SGordon Ross tracked_pipe, pipe);
828047dc10d7SGordon Ross
828147dc10d7SGordon Ross }
828247dc10d7SGordon Ross }
828347dc10d7SGordon Ross
828447dc10d7SGordon Ross static void
check_crtc_state(struct drm_device * dev)828547dc10d7SGordon Ross check_crtc_state(struct drm_device *dev)
828647dc10d7SGordon Ross {
828747dc10d7SGordon Ross drm_i915_private_t *dev_priv = dev->dev_private;
828847dc10d7SGordon Ross struct intel_crtc *crtc;
828947dc10d7SGordon Ross struct intel_encoder *encoder;
829047dc10d7SGordon Ross struct intel_crtc_config pipe_config;
829147dc10d7SGordon Ross
829247dc10d7SGordon Ross list_for_each_entry(crtc, struct intel_crtc, &dev->mode_config.crtc_list,
829347dc10d7SGordon Ross base.head) {
829447dc10d7SGordon Ross bool enabled = false;
829547dc10d7SGordon Ross bool active = false;
829647dc10d7SGordon Ross
829747dc10d7SGordon Ross (void) memset(&pipe_config, 0, sizeof(pipe_config));
829847dc10d7SGordon Ross
829947dc10d7SGordon Ross DRM_DEBUG_KMS("[CRTC:%d]\n",
830047dc10d7SGordon Ross crtc->base.base.id);
830147dc10d7SGordon Ross
830247dc10d7SGordon Ross if (crtc->active && !crtc->base.enabled)
830347dc10d7SGordon Ross DRM_ERROR("active crtc, but not enabled in sw tracking\n");
830447dc10d7SGordon Ross
830547dc10d7SGordon Ross list_for_each_entry(encoder, struct intel_encoder, &dev->mode_config.encoder_list,
830647dc10d7SGordon Ross base.head) {
830747dc10d7SGordon Ross if (encoder->base.crtc != &crtc->base)
830847dc10d7SGordon Ross continue;
830947dc10d7SGordon Ross enabled = true;
831047dc10d7SGordon Ross if (encoder->connectors_active)
831147dc10d7SGordon Ross active = true;
831247dc10d7SGordon Ross }
831347dc10d7SGordon Ross
831447dc10d7SGordon Ross if (active != crtc->active)
831547dc10d7SGordon Ross DRM_ERROR("crtc's computed active state doesn't match tracked active state "
831647dc10d7SGordon Ross "(expected %i, found %i)\n", active, crtc->active);
831747dc10d7SGordon Ross if (enabled != crtc->base.enabled)
831847dc10d7SGordon Ross DRM_ERROR("crtc's computed enabled state doesn't match tracked enabled state "
831947dc10d7SGordon Ross "(expected %i, found %i)\n", enabled, crtc->base.enabled);
832047dc10d7SGordon Ross
832147dc10d7SGordon Ross active = dev_priv->display.get_pipe_config(crtc,
832247dc10d7SGordon Ross &pipe_config);
832347dc10d7SGordon Ross
832447dc10d7SGordon Ross /* hw state is inconsistent with the pipe A quirk */
832547dc10d7SGordon Ross if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
832647dc10d7SGordon Ross active = crtc->active;
832747dc10d7SGordon Ross
832847dc10d7SGordon Ross list_for_each_entry(encoder, struct intel_encoder, &dev->mode_config.encoder_list,
832947dc10d7SGordon Ross base.head) {
833047dc10d7SGordon Ross enum pipe pipe;
833147dc10d7SGordon Ross if (encoder->base.crtc != &crtc->base)
833247dc10d7SGordon Ross continue;
833347dc10d7SGordon Ross if (encoder->get_config &&
833447dc10d7SGordon Ross encoder->get_hw_state(encoder, &pipe))
833547dc10d7SGordon Ross encoder->get_config(encoder, &pipe_config);
833647dc10d7SGordon Ross }
833747dc10d7SGordon Ross
833847dc10d7SGordon Ross if(crtc->active != active)
833947dc10d7SGordon Ross DRM_ERROR("crtc active state doesn't match with hw state "
834047dc10d7SGordon Ross "(expected %i, found %i)\n", crtc->active, active);
834147dc10d7SGordon Ross
834247dc10d7SGordon Ross if (active &&
834347dc10d7SGordon Ross !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
834447dc10d7SGordon Ross DRM_DEBUG_KMS("pipe state doesn't match!\n");
834547dc10d7SGordon Ross intel_dump_pipe_config(crtc, &pipe_config,
834647dc10d7SGordon Ross "[hw state]");
834747dc10d7SGordon Ross intel_dump_pipe_config(crtc, &crtc->config,
834847dc10d7SGordon Ross "[sw state]");
834947dc10d7SGordon Ross }
835047dc10d7SGordon Ross }
835147dc10d7SGordon Ross }
835247dc10d7SGordon Ross
835347dc10d7SGordon Ross static void
check_shared_dpll_state(struct drm_device * dev)835447dc10d7SGordon Ross check_shared_dpll_state(struct drm_device *dev)
835547dc10d7SGordon Ross {
835647dc10d7SGordon Ross drm_i915_private_t *dev_priv = dev->dev_private;
835747dc10d7SGordon Ross struct intel_crtc *crtc;
835847dc10d7SGordon Ross struct intel_dpll_hw_state dpll_hw_state;
835947dc10d7SGordon Ross int i;
836047dc10d7SGordon Ross
836147dc10d7SGordon Ross for (i = 0; i < dev_priv->num_shared_dpll; i++) {
836247dc10d7SGordon Ross struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
836347dc10d7SGordon Ross int enabled_crtcs = 0, active_crtcs = 0;
836447dc10d7SGordon Ross bool active;
836547dc10d7SGordon Ross
836647dc10d7SGordon Ross memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
836747dc10d7SGordon Ross
836847dc10d7SGordon Ross DRM_DEBUG_KMS("%s\n", pll->name);
836947dc10d7SGordon Ross
837047dc10d7SGordon Ross active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
837147dc10d7SGordon Ross
837247dc10d7SGordon Ross if(pll->active > pll->refcount)
837347dc10d7SGordon Ross DRM_DEBUG_KMS("more active pll users than references: %i vs %i\n",
837447dc10d7SGordon Ross pll->active, pll->refcount);
837547dc10d7SGordon Ross if(pll->active && !pll->on)
837647dc10d7SGordon Ross DRM_DEBUG_KMS("pll in active use but not on in sw tracking\n");
837747dc10d7SGordon Ross if(pll->on && !pll->active)
837847dc10d7SGordon Ross DRM_DEBUG_KMS("pll in on but not on in use in sw tracking\n");
837947dc10d7SGordon Ross if(pll->on != active)
838047dc10d7SGordon Ross DRM_DEBUG_KMS("pll on state mismatch (expected %i, found %i)\n",
838147dc10d7SGordon Ross pll->on, active);
838247dc10d7SGordon Ross
838347dc10d7SGordon Ross list_for_each_entry(crtc, struct intel_crtc, &dev->mode_config.crtc_list,
838447dc10d7SGordon Ross base.head) {
838547dc10d7SGordon Ross if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
838647dc10d7SGordon Ross enabled_crtcs++;
838747dc10d7SGordon Ross if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
838847dc10d7SGordon Ross active_crtcs++;
838947dc10d7SGordon Ross }
839047dc10d7SGordon Ross if(pll->active != active_crtcs)
839147dc10d7SGordon Ross DRM_DEBUG_KMS("pll active crtcs mismatch (expected %i, found %i)\n",
839247dc10d7SGordon Ross pll->active, active_crtcs);
839347dc10d7SGordon Ross if(pll->refcount != enabled_crtcs)
839447dc10d7SGordon Ross DRM_DEBUG_KMS("pll enabled crtcs mismatch (expected %i, found %i)\n",
839547dc10d7SGordon Ross pll->refcount, enabled_crtcs);
839647dc10d7SGordon Ross
839747dc10d7SGordon Ross if(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
839847dc10d7SGordon Ross sizeof(dpll_hw_state)))
839947dc10d7SGordon Ross DRM_ERROR("pll hw state mismatch\n");
840047dc10d7SGordon Ross }
840147dc10d7SGordon Ross }
840247dc10d7SGordon Ross
840347dc10d7SGordon Ross void
intel_modeset_check_state(struct drm_device * dev)840447dc10d7SGordon Ross intel_modeset_check_state(struct drm_device *dev)
840547dc10d7SGordon Ross {
840647dc10d7SGordon Ross check_connector_state(dev);
840747dc10d7SGordon Ross check_encoder_state(dev);
840847dc10d7SGordon Ross check_crtc_state(dev);
840947dc10d7SGordon Ross check_shared_dpll_state(dev);
841047dc10d7SGordon Ross }
841147dc10d7SGordon Ross
__intel_set_mode(struct drm_crtc * crtc,struct drm_display_mode * mode,int x,int y,struct drm_framebuffer * fb)841247dc10d7SGordon Ross static int __intel_set_mode(struct drm_crtc *crtc,
841347dc10d7SGordon Ross struct drm_display_mode *mode,
841447dc10d7SGordon Ross int x, int y, struct drm_framebuffer *fb)
841547dc10d7SGordon Ross {
841647dc10d7SGordon Ross struct drm_device *dev = crtc->dev;
841747dc10d7SGordon Ross drm_i915_private_t *dev_priv = dev->dev_private;
841847dc10d7SGordon Ross struct drm_display_mode *saved_mode, *saved_hwmode;
841947dc10d7SGordon Ross struct intel_crtc_config *pipe_config = NULL;
842047dc10d7SGordon Ross struct intel_crtc *intel_crtc;
842147dc10d7SGordon Ross unsigned disable_pipes, prepare_pipes, modeset_pipes;
842247dc10d7SGordon Ross int ret = 0;
842347dc10d7SGordon Ross
842447dc10d7SGordon Ross saved_mode = kzalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
842547dc10d7SGordon Ross if (!saved_mode)
842647dc10d7SGordon Ross return -ENOMEM;
842747dc10d7SGordon Ross saved_hwmode = saved_mode + 1;
842847dc10d7SGordon Ross
842947dc10d7SGordon Ross intel_modeset_affected_pipes(crtc, &modeset_pipes,
843047dc10d7SGordon Ross &prepare_pipes, &disable_pipes);
843147dc10d7SGordon Ross
843247dc10d7SGordon Ross *saved_hwmode = crtc->hwmode;
843347dc10d7SGordon Ross *saved_mode = crtc->mode;
843447dc10d7SGordon Ross
843547dc10d7SGordon Ross /* Hack: Because we don't (yet) support global modeset on multiple
843647dc10d7SGordon Ross * crtcs, we don't keep track of the new mode for more than one crtc.
843747dc10d7SGordon Ross * Hence simply check whether any bit is set in modeset_pipes in all the
843847dc10d7SGordon Ross * pieces of code that are not yet converted to deal with mutliple crtcs
843947dc10d7SGordon Ross * changing their mode at the same time. */
844047dc10d7SGordon Ross if (modeset_pipes) {
844147dc10d7SGordon Ross pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
844247dc10d7SGordon Ross if (!(pipe_config)) {
844347dc10d7SGordon Ross ret = -EINVAL;
844447dc10d7SGordon Ross pipe_config = NULL;
844547dc10d7SGordon Ross
844647dc10d7SGordon Ross goto out;
844747dc10d7SGordon Ross }
844847dc10d7SGordon Ross intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
844947dc10d7SGordon Ross "[modeset]");
845047dc10d7SGordon Ross }
845147dc10d7SGordon Ross
845247dc10d7SGordon Ross for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
845347dc10d7SGordon Ross intel_crtc_disable(&intel_crtc->base);
845447dc10d7SGordon Ross
845547dc10d7SGordon Ross for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
845647dc10d7SGordon Ross if (intel_crtc->base.enabled)
845747dc10d7SGordon Ross dev_priv->display.crtc_disable(&intel_crtc->base);
845847dc10d7SGordon Ross }
845947dc10d7SGordon Ross
846047dc10d7SGordon Ross /* crtc->mode is already used by the ->mode_set callbacks, hence we need
846147dc10d7SGordon Ross * to set it here already despite that we pass it down the callchain.
846247dc10d7SGordon Ross */
846347dc10d7SGordon Ross if (modeset_pipes) {
846447dc10d7SGordon Ross crtc->mode = *mode;
846547dc10d7SGordon Ross /* mode_set/enable/disable functions rely on a correct pipe
846647dc10d7SGordon Ross * config. */
846747dc10d7SGordon Ross to_intel_crtc(crtc)->config = *pipe_config;
846847dc10d7SGordon Ross }
846947dc10d7SGordon Ross
847047dc10d7SGordon Ross /* Only after disabling all output pipelines that will be changed can we
847147dc10d7SGordon Ross * update the the output configuration. */
847247dc10d7SGordon Ross intel_modeset_update_state(dev, prepare_pipes);
847347dc10d7SGordon Ross
847447dc10d7SGordon Ross if (dev_priv->display.modeset_global_resources)
847547dc10d7SGordon Ross dev_priv->display.modeset_global_resources(dev);
847647dc10d7SGordon Ross
847747dc10d7SGordon Ross /* Set up the DPLL and any encoders state that needs to adjust or depend
847847dc10d7SGordon Ross * on the DPLL.
847947dc10d7SGordon Ross */
848047dc10d7SGordon Ross for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
848147dc10d7SGordon Ross ret = intel_crtc_mode_set(&intel_crtc->base,
848247dc10d7SGordon Ross x, y, fb);
848347dc10d7SGordon Ross if (ret)
848447dc10d7SGordon Ross goto done;
848547dc10d7SGordon Ross }
848647dc10d7SGordon Ross
848747dc10d7SGordon Ross /* Now enable the clocks, plane, pipe, and connectors that we set up. */
848847dc10d7SGordon Ross for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
848947dc10d7SGordon Ross dev_priv->display.crtc_enable(&intel_crtc->base);
849047dc10d7SGordon Ross
849147dc10d7SGordon Ross if (modeset_pipes) {
849247dc10d7SGordon Ross /* Store real post-adjustment hardware mode. */
849347dc10d7SGordon Ross crtc->hwmode = pipe_config->adjusted_mode;
849447dc10d7SGordon Ross
849547dc10d7SGordon Ross /* Calculate and store various constants which
849647dc10d7SGordon Ross * are later needed by vblank and swap-completion
849747dc10d7SGordon Ross * timestamping. They are derived from true hwmode.
849847dc10d7SGordon Ross */
849947dc10d7SGordon Ross drm_calc_timestamping_constants(crtc);
850047dc10d7SGordon Ross }
850147dc10d7SGordon Ross
850247dc10d7SGordon Ross /* FIXME: add subpixel order */
850347dc10d7SGordon Ross done:
850447dc10d7SGordon Ross if (ret && crtc->enabled) {
850547dc10d7SGordon Ross crtc->hwmode = *saved_hwmode;
850647dc10d7SGordon Ross crtc->mode = *saved_mode;
850747dc10d7SGordon Ross }
850847dc10d7SGordon Ross
850947dc10d7SGordon Ross out:
851047dc10d7SGordon Ross if (pipe_config)
851147dc10d7SGordon Ross kfree(pipe_config, sizeof(*pipe_config));
851247dc10d7SGordon Ross kfree(saved_mode, 2 * sizeof(*saved_mode));
851347dc10d7SGordon Ross return ret;
851447dc10d7SGordon Ross }
851547dc10d7SGordon Ross
intel_set_mode(struct drm_crtc * crtc,struct drm_display_mode * mode,int x,int y,struct drm_framebuffer * fb)851647dc10d7SGordon Ross int intel_set_mode(struct drm_crtc *crtc,
851747dc10d7SGordon Ross struct drm_display_mode *mode,
851847dc10d7SGordon Ross int x, int y, struct drm_framebuffer *fb)
851947dc10d7SGordon Ross {
852047dc10d7SGordon Ross int ret;
852147dc10d7SGordon Ross
852247dc10d7SGordon Ross ret = __intel_set_mode(crtc, mode, x, y, fb);
852347dc10d7SGordon Ross
852447dc10d7SGordon Ross if (ret == 0)
852547dc10d7SGordon Ross intel_modeset_check_state(crtc->dev);
852647dc10d7SGordon Ross
852747dc10d7SGordon Ross return ret;
852847dc10d7SGordon Ross }
852947dc10d7SGordon Ross
intel_crtc_restore_mode(struct drm_crtc * crtc)853047dc10d7SGordon Ross void intel_crtc_restore_mode(struct drm_crtc *crtc)
853147dc10d7SGordon Ross {
853247dc10d7SGordon Ross intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
853347dc10d7SGordon Ross }
853447dc10d7SGordon Ross
853547dc10d7SGordon Ross #undef for_each_intel_crtc_masked
853647dc10d7SGordon Ross
intel_set_config_free(struct drm_device * dev,struct intel_set_config * config)853747dc10d7SGordon Ross static void intel_set_config_free(struct drm_device *dev, struct intel_set_config *config)
853847dc10d7SGordon Ross {
853947dc10d7SGordon Ross if (!config)
854047dc10d7SGordon Ross return;
854147dc10d7SGordon Ross
854247dc10d7SGordon Ross kfree(config->save_connector_encoders, dev->mode_config.num_connector * sizeof(struct drm_encoder *));
854347dc10d7SGordon Ross kfree(config->save_encoder_crtcs, dev->mode_config.num_encoder * sizeof(struct drm_crtc *));
854447dc10d7SGordon Ross kfree(config, sizeof(*config));
854547dc10d7SGordon Ross }
854647dc10d7SGordon Ross
intel_set_config_save_state(struct drm_device * dev,struct intel_set_config * config)854747dc10d7SGordon Ross static int intel_set_config_save_state(struct drm_device *dev,
854847dc10d7SGordon Ross struct intel_set_config *config)
854947dc10d7SGordon Ross {
855047dc10d7SGordon Ross struct drm_encoder *encoder;
855147dc10d7SGordon Ross struct drm_connector *connector;
855247dc10d7SGordon Ross int count;
855347dc10d7SGordon Ross
855447dc10d7SGordon Ross config->save_encoder_crtcs =
855547dc10d7SGordon Ross kcalloc(dev->mode_config.num_encoder,
855647dc10d7SGordon Ross sizeof(struct drm_crtc *), GFP_KERNEL);
855747dc10d7SGordon Ross if (!config->save_encoder_crtcs)
855847dc10d7SGordon Ross return -ENOMEM;
855947dc10d7SGordon Ross
856047dc10d7SGordon Ross config->save_connector_encoders =
856147dc10d7SGordon Ross kcalloc(dev->mode_config.num_connector,
856247dc10d7SGordon Ross sizeof(struct drm_encoder *), GFP_KERNEL);
856347dc10d7SGordon Ross if (!config->save_connector_encoders)
856447dc10d7SGordon Ross return -ENOMEM;
856547dc10d7SGordon Ross
856647dc10d7SGordon Ross /* Copy data. Note that driver private data is not affected.
856747dc10d7SGordon Ross * Should anything bad happen only the expected state is
856847dc10d7SGordon Ross * restored, not the drivers personal bookkeeping.
856947dc10d7SGordon Ross */
857047dc10d7SGordon Ross count = 0;
857147dc10d7SGordon Ross list_for_each_entry(encoder, struct drm_encoder, &dev->mode_config.encoder_list, head) {
857247dc10d7SGordon Ross config->save_encoder_crtcs[count++] = encoder->crtc;
857347dc10d7SGordon Ross }
857447dc10d7SGordon Ross
857547dc10d7SGordon Ross count = 0;
857647dc10d7SGordon Ross list_for_each_entry(connector, struct drm_connector, &dev->mode_config.connector_list, head) {
857747dc10d7SGordon Ross config->save_connector_encoders[count++] = connector->encoder;
857847dc10d7SGordon Ross }
857947dc10d7SGordon Ross
858047dc10d7SGordon Ross return 0;
858147dc10d7SGordon Ross }
858247dc10d7SGordon Ross
intel_set_config_restore_state(struct drm_device * dev,struct intel_set_config * config)858347dc10d7SGordon Ross static void intel_set_config_restore_state(struct drm_device *dev,
858447dc10d7SGordon Ross struct intel_set_config *config)
858547dc10d7SGordon Ross {
858647dc10d7SGordon Ross struct intel_encoder *encoder;
858747dc10d7SGordon Ross struct intel_connector *connector;
858847dc10d7SGordon Ross int count;
858947dc10d7SGordon Ross
859047dc10d7SGordon Ross count = 0;
859147dc10d7SGordon Ross list_for_each_entry(encoder, struct intel_encoder, &dev->mode_config.encoder_list, base.head) {
859247dc10d7SGordon Ross encoder->new_crtc =
859347dc10d7SGordon Ross to_intel_crtc(config->save_encoder_crtcs[count++]);
859447dc10d7SGordon Ross }
859547dc10d7SGordon Ross
859647dc10d7SGordon Ross count = 0;
859747dc10d7SGordon Ross list_for_each_entry(connector, struct intel_connector, &dev->mode_config.connector_list, base.head) {
859847dc10d7SGordon Ross connector->new_encoder =
859947dc10d7SGordon Ross to_intel_encoder(config->save_connector_encoders[count++]);
860047dc10d7SGordon Ross }
860147dc10d7SGordon Ross }
860247dc10d7SGordon Ross
860347dc10d7SGordon Ross static bool
is_crtc_connector_off(struct drm_mode_set * set)860447dc10d7SGordon Ross is_crtc_connector_off(struct drm_mode_set *set)
860547dc10d7SGordon Ross {
860647dc10d7SGordon Ross int i;
860747dc10d7SGordon Ross
860847dc10d7SGordon Ross if (set->num_connectors == 0)
860947dc10d7SGordon Ross return false;
861047dc10d7SGordon Ross
861147dc10d7SGordon Ross if ((set->connectors == NULL))
861247dc10d7SGordon Ross return false;
861347dc10d7SGordon Ross
861447dc10d7SGordon Ross for (i = 0; i < set->num_connectors; i++)
861547dc10d7SGordon Ross if (set->connectors[i]->encoder &&
861647dc10d7SGordon Ross set->connectors[i]->encoder->crtc == set->crtc &&
861747dc10d7SGordon Ross set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
861847dc10d7SGordon Ross return true;
861947dc10d7SGordon Ross
862047dc10d7SGordon Ross return false;
862147dc10d7SGordon Ross }
862247dc10d7SGordon Ross
862347dc10d7SGordon Ross static void
intel_set_config_compute_mode_changes(struct drm_mode_set * set,struct intel_set_config * config)862447dc10d7SGordon Ross intel_set_config_compute_mode_changes(struct drm_mode_set *set,
862547dc10d7SGordon Ross struct intel_set_config *config)
862647dc10d7SGordon Ross {
862747dc10d7SGordon Ross
862847dc10d7SGordon Ross /* We should be able to check here if the fb has the same properties
862947dc10d7SGordon Ross * and then just flip_or_move it */
863047dc10d7SGordon Ross if (is_crtc_connector_off(set)) {
863147dc10d7SGordon Ross config->mode_changed = true;
863247dc10d7SGordon Ross } else if (set->crtc->fb != set->fb) {
863347dc10d7SGordon Ross /* If we have no fb then treat it as a full mode set */
863447dc10d7SGordon Ross if (set->crtc->fb == NULL) {
863547dc10d7SGordon Ross DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
863647dc10d7SGordon Ross config->mode_changed = true;
863747dc10d7SGordon Ross } else if (set->fb == NULL) {
863847dc10d7SGordon Ross config->mode_changed = true;
863947dc10d7SGordon Ross } else if (set->fb->pixel_format !=
864047dc10d7SGordon Ross set->crtc->fb->pixel_format) {
864147dc10d7SGordon Ross config->mode_changed = true;
864247dc10d7SGordon Ross } else {
864347dc10d7SGordon Ross config->fb_changed = true;
864447dc10d7SGordon Ross }
864547dc10d7SGordon Ross }
864647dc10d7SGordon Ross
864747dc10d7SGordon Ross if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
864847dc10d7SGordon Ross config->fb_changed = true;
864947dc10d7SGordon Ross
865047dc10d7SGordon Ross if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
865147dc10d7SGordon Ross DRM_DEBUG_KMS("modes are different, full mode set\n");
865247dc10d7SGordon Ross drm_mode_debug_printmodeline(&set->crtc->mode);
865347dc10d7SGordon Ross drm_mode_debug_printmodeline(set->mode);
865447dc10d7SGordon Ross config->mode_changed = true;
865547dc10d7SGordon Ross }
865647dc10d7SGordon Ross }
865747dc10d7SGordon Ross
865847dc10d7SGordon Ross static int
intel_modeset_stage_output_state(struct drm_device * dev,struct drm_mode_set * set,struct intel_set_config * config)865947dc10d7SGordon Ross intel_modeset_stage_output_state(struct drm_device *dev,
866047dc10d7SGordon Ross struct drm_mode_set *set,
866147dc10d7SGordon Ross struct intel_set_config *config)
866247dc10d7SGordon Ross {
866347dc10d7SGordon Ross struct drm_crtc *new_crtc;
866447dc10d7SGordon Ross struct intel_connector *connector;
866547dc10d7SGordon Ross struct intel_encoder *encoder;
866647dc10d7SGordon Ross /* LINTED */
866747dc10d7SGordon Ross int count, ro;
866847dc10d7SGordon Ross
866947dc10d7SGordon Ross /* The upper layers ensure that we either disabl a crtc or have a list
867047dc10d7SGordon Ross * of connectors. For paranoia, double-check this. */
867147dc10d7SGordon Ross WARN_ON(!set->fb && (set->num_connectors != 0));
867247dc10d7SGordon Ross WARN_ON(set->fb && (set->num_connectors == 0));
867347dc10d7SGordon Ross
867447dc10d7SGordon Ross count = 0;
867547dc10d7SGordon Ross list_for_each_entry(connector, struct intel_connector, &dev->mode_config.connector_list,
867647dc10d7SGordon Ross base.head) {
867747dc10d7SGordon Ross /* Otherwise traverse passed in connector list and get encoders
867847dc10d7SGordon Ross * for them. */
867947dc10d7SGordon Ross for (ro = 0; ro < set->num_connectors; ro++) {
868047dc10d7SGordon Ross if (set->connectors[ro] == &connector->base) {
868147dc10d7SGordon Ross connector->new_encoder = connector->encoder;
868247dc10d7SGordon Ross break;
868347dc10d7SGordon Ross }
868447dc10d7SGordon Ross }
868547dc10d7SGordon Ross
868647dc10d7SGordon Ross /* If we disable the crtc, disable all its connectors. Also, if
868747dc10d7SGordon Ross * the connector is on the changing crtc but not on the new
868847dc10d7SGordon Ross * connector list, disable it. */
868947dc10d7SGordon Ross if ((!set->fb || ro == set->num_connectors) &&
869047dc10d7SGordon Ross connector->base.encoder &&
869147dc10d7SGordon Ross connector->base.encoder->crtc == set->crtc) {
869247dc10d7SGordon Ross connector->new_encoder = NULL;
869347dc10d7SGordon Ross
869447dc10d7SGordon Ross DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
869547dc10d7SGordon Ross connector->base.base.id,
869647dc10d7SGordon Ross drm_get_connector_name(&connector->base));
869747dc10d7SGordon Ross }
869847dc10d7SGordon Ross
869947dc10d7SGordon Ross
870047dc10d7SGordon Ross if (&connector->new_encoder->base != connector->base.encoder) {
870147dc10d7SGordon Ross DRM_DEBUG_KMS("encoder changed, full mode switch\n");
870247dc10d7SGordon Ross config->mode_changed = true;
870347dc10d7SGordon Ross }
870447dc10d7SGordon Ross }
870547dc10d7SGordon Ross /* connector->new_encoder is now updated for all connectors. */
870647dc10d7SGordon Ross
870747dc10d7SGordon Ross /* Update crtc of enabled connectors. */
870847dc10d7SGordon Ross count = 0;
870947dc10d7SGordon Ross list_for_each_entry(connector, struct intel_connector, &dev->mode_config.connector_list,
871047dc10d7SGordon Ross base.head) {
871147dc10d7SGordon Ross if (!connector->new_encoder)
871247dc10d7SGordon Ross continue;
871347dc10d7SGordon Ross
871447dc10d7SGordon Ross new_crtc = connector->new_encoder->base.crtc;
871547dc10d7SGordon Ross
871647dc10d7SGordon Ross for (ro = 0; ro < set->num_connectors; ro++) {
871747dc10d7SGordon Ross if (set->connectors[ro] == &connector->base)
871847dc10d7SGordon Ross new_crtc = set->crtc;
871947dc10d7SGordon Ross }
872047dc10d7SGordon Ross
872147dc10d7SGordon Ross /* Make sure the new CRTC will work with the encoder */
872247dc10d7SGordon Ross if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
872347dc10d7SGordon Ross new_crtc)) {
872447dc10d7SGordon Ross return -EINVAL;
872547dc10d7SGordon Ross }
872647dc10d7SGordon Ross connector->encoder->new_crtc = to_intel_crtc(new_crtc);
872747dc10d7SGordon Ross
872847dc10d7SGordon Ross DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
872947dc10d7SGordon Ross connector->base.base.id,
873047dc10d7SGordon Ross drm_get_connector_name(&connector->base),
873147dc10d7SGordon Ross new_crtc->base.id);
873247dc10d7SGordon Ross }
873347dc10d7SGordon Ross
873447dc10d7SGordon Ross /* Check for any encoders that needs to be disabled. */
873547dc10d7SGordon Ross list_for_each_entry(encoder, struct intel_encoder, &dev->mode_config.encoder_list,
873647dc10d7SGordon Ross base.head) {
873747dc10d7SGordon Ross list_for_each_entry(connector, struct intel_connector,
873847dc10d7SGordon Ross &dev->mode_config.connector_list,
873947dc10d7SGordon Ross base.head) {
874047dc10d7SGordon Ross if (connector->new_encoder == encoder) {
874147dc10d7SGordon Ross WARN_ON(!connector->new_encoder->new_crtc);
874247dc10d7SGordon Ross
874347dc10d7SGordon Ross goto next_encoder;
874447dc10d7SGordon Ross }
874547dc10d7SGordon Ross }
874647dc10d7SGordon Ross encoder->new_crtc = NULL;
874747dc10d7SGordon Ross next_encoder:
874847dc10d7SGordon Ross /* Only now check for crtc changes so we don't miss encoders
874947dc10d7SGordon Ross * that will be disabled. */
875047dc10d7SGordon Ross if (&encoder->new_crtc->base != encoder->base.crtc) {
875147dc10d7SGordon Ross DRM_DEBUG_KMS("crtc changed, full mode switch\n");
875247dc10d7SGordon Ross config->mode_changed = true;
875347dc10d7SGordon Ross }
875447dc10d7SGordon Ross }
875547dc10d7SGordon Ross /* Now we've also updated encoder->new_crtc for all encoders. */
875647dc10d7SGordon Ross
875747dc10d7SGordon Ross return 0;
875847dc10d7SGordon Ross }
875947dc10d7SGordon Ross
intel_crtc_set_config(struct drm_mode_set * set)876047dc10d7SGordon Ross static int intel_crtc_set_config(struct drm_mode_set *set)
876147dc10d7SGordon Ross {
876247dc10d7SGordon Ross struct drm_device *dev;
876347dc10d7SGordon Ross struct drm_mode_set save_set;
876447dc10d7SGordon Ross struct intel_set_config *config;
876547dc10d7SGordon Ross int ret;
876647dc10d7SGordon Ross
876747dc10d7SGordon Ross BUG_ON(!set);
876847dc10d7SGordon Ross BUG_ON(!set->crtc);
876947dc10d7SGordon Ross BUG_ON(!set->crtc->helper_private);
877047dc10d7SGordon Ross
877147dc10d7SGordon Ross /* Enforce sane interface api - has been abused by the fb helper. */
877247dc10d7SGordon Ross BUG_ON(!set->mode && set->fb);
877347dc10d7SGordon Ross BUG_ON(set->fb && set->num_connectors == 0);
877447dc10d7SGordon Ross
877547dc10d7SGordon Ross if (set->fb) {
877647dc10d7SGordon Ross DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
877747dc10d7SGordon Ross set->crtc->base.id, set->fb->base.id,
877847dc10d7SGordon Ross (int)set->num_connectors, set->x, set->y);
877947dc10d7SGordon Ross } else {
878047dc10d7SGordon Ross DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
878147dc10d7SGordon Ross }
878247dc10d7SGordon Ross
878347dc10d7SGordon Ross dev = set->crtc->dev;
878447dc10d7SGordon Ross
878547dc10d7SGordon Ross ret = -ENOMEM;
878647dc10d7SGordon Ross config = kzalloc(sizeof(*config), GFP_KERNEL);
878747dc10d7SGordon Ross if (!config)
878847dc10d7SGordon Ross goto out_config;
878947dc10d7SGordon Ross
879047dc10d7SGordon Ross ret = intel_set_config_save_state(dev, config);
879147dc10d7SGordon Ross if (ret)
879247dc10d7SGordon Ross goto out_config;
879347dc10d7SGordon Ross
879447dc10d7SGordon Ross save_set.crtc = set->crtc;
879547dc10d7SGordon Ross save_set.mode = &set->crtc->mode;
879647dc10d7SGordon Ross save_set.x = set->crtc->x;
879747dc10d7SGordon Ross save_set.y = set->crtc->y;
879847dc10d7SGordon Ross save_set.fb = set->crtc->fb;
879947dc10d7SGordon Ross
880047dc10d7SGordon Ross /* Compute whether we need a full modeset, only an fb base update or no
880147dc10d7SGordon Ross * change at all. In the future we might also check whether only the
880247dc10d7SGordon Ross * mode changed, e.g. for LVDS where we only change the panel fitter in
880347dc10d7SGordon Ross * such cases. */
880447dc10d7SGordon Ross intel_set_config_compute_mode_changes(set, config);
880547dc10d7SGordon Ross
880647dc10d7SGordon Ross ret = intel_modeset_stage_output_state(dev, set, config);
880747dc10d7SGordon Ross if (ret)
880847dc10d7SGordon Ross goto fail;
880947dc10d7SGordon Ross
881047dc10d7SGordon Ross if (config->mode_changed) {
881147dc10d7SGordon Ross if ((set->mode == NULL) && set->fb) {
881247dc10d7SGordon Ross DRM_DEBUG_KMS("fb changed without set->mode");
881347dc10d7SGordon Ross ret = -EINVAL;
881447dc10d7SGordon Ross goto fail;
881547dc10d7SGordon Ross }
881647dc10d7SGordon Ross
881747dc10d7SGordon Ross ret = intel_set_mode(set->crtc, set->mode,
881847dc10d7SGordon Ross set->x, set->y, set->fb);
881947dc10d7SGordon Ross } else if (config->fb_changed) {
882047dc10d7SGordon Ross intel_crtc_wait_for_pending_flips(set->crtc);
882147dc10d7SGordon Ross
882247dc10d7SGordon Ross ret = intel_pipe_set_base(set->crtc,
882347dc10d7SGordon Ross set->x, set->y, set->fb);
882447dc10d7SGordon Ross }
882547dc10d7SGordon Ross
882647dc10d7SGordon Ross if (ret) {
882747dc10d7SGordon Ross DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
882847dc10d7SGordon Ross set->crtc->base.id, ret);
882947dc10d7SGordon Ross fail:
883047dc10d7SGordon Ross intel_set_config_restore_state(dev, config);
883147dc10d7SGordon Ross
883247dc10d7SGordon Ross /* Try to restore the config */
883347dc10d7SGordon Ross if (config->mode_changed &&
883447dc10d7SGordon Ross intel_set_mode(save_set.crtc, save_set.mode,
883547dc10d7SGordon Ross save_set.x, save_set.y, save_set.fb))
883647dc10d7SGordon Ross DRM_ERROR("failed to restore config after modeset failure\n");
883747dc10d7SGordon Ross }
883847dc10d7SGordon Ross
883947dc10d7SGordon Ross out_config:
884047dc10d7SGordon Ross intel_set_config_free(dev, config);
884147dc10d7SGordon Ross return ret;
884247dc10d7SGordon Ross }
884347dc10d7SGordon Ross
884447dc10d7SGordon Ross static const struct drm_crtc_funcs intel_crtc_funcs = {
884547dc10d7SGordon Ross .cursor_set = intel_crtc_cursor_set,
884647dc10d7SGordon Ross .cursor_move = intel_crtc_cursor_move,
884747dc10d7SGordon Ross .gamma_set = intel_crtc_gamma_set,
884847dc10d7SGordon Ross .set_config = intel_crtc_set_config,
884947dc10d7SGordon Ross .destroy = intel_crtc_destroy,
885047dc10d7SGordon Ross .page_flip = intel_crtc_page_flip,
885147dc10d7SGordon Ross };
885247dc10d7SGordon Ross
intel_cpu_pll_init(struct drm_device * dev)885347dc10d7SGordon Ross static void intel_cpu_pll_init(struct drm_device *dev)
885447dc10d7SGordon Ross {
885547dc10d7SGordon Ross if (HAS_DDI(dev))
885647dc10d7SGordon Ross intel_ddi_pll_init(dev);
885747dc10d7SGordon Ross }
885847dc10d7SGordon Ross
ibx_pch_dpll_get_hw_state(struct drm_i915_private * dev_priv,struct intel_shared_dpll * pll,struct intel_dpll_hw_state * hw_state)885947dc10d7SGordon Ross static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
886047dc10d7SGordon Ross struct intel_shared_dpll *pll,
886147dc10d7SGordon Ross struct intel_dpll_hw_state *hw_state)
886247dc10d7SGordon Ross {
886347dc10d7SGordon Ross uint32_t val;
886447dc10d7SGordon Ross
886547dc10d7SGordon Ross val = I915_READ(PCH_DPLL(pll->id));
886647dc10d7SGordon Ross hw_state->dpll = val;
886747dc10d7SGordon Ross hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
886847dc10d7SGordon Ross hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
886947dc10d7SGordon Ross
887047dc10d7SGordon Ross return val & DPLL_VCO_ENABLE;
887147dc10d7SGordon Ross }
887247dc10d7SGordon Ross
ibx_pch_dpll_enable(struct drm_i915_private * dev_priv,struct intel_shared_dpll * pll)887347dc10d7SGordon Ross static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
887447dc10d7SGordon Ross struct intel_shared_dpll *pll)
887547dc10d7SGordon Ross {
887647dc10d7SGordon Ross uint32_t reg, val;
887747dc10d7SGordon Ross
887847dc10d7SGordon Ross /* PCH refclock must be enabled first */
887947dc10d7SGordon Ross assert_pch_refclk_enabled(dev_priv);
888047dc10d7SGordon Ross
888147dc10d7SGordon Ross reg = PCH_DPLL(pll->id);
888247dc10d7SGordon Ross val = I915_READ(reg);
888347dc10d7SGordon Ross val |= DPLL_VCO_ENABLE;
888447dc10d7SGordon Ross I915_WRITE(reg, val);
888547dc10d7SGordon Ross POSTING_READ(reg);
888647dc10d7SGordon Ross udelay(200);
888747dc10d7SGordon Ross }
888847dc10d7SGordon Ross
ibx_pch_dpll_disable(struct drm_i915_private * dev_priv,struct intel_shared_dpll * pll)888947dc10d7SGordon Ross static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
889047dc10d7SGordon Ross struct intel_shared_dpll *pll)
889147dc10d7SGordon Ross {
889247dc10d7SGordon Ross struct drm_device *dev = dev_priv->dev;
889347dc10d7SGordon Ross struct intel_crtc *crtc;
889447dc10d7SGordon Ross uint32_t reg, val;
889547dc10d7SGordon Ross
889647dc10d7SGordon Ross /* Make sure no transcoder isn't still depending on us. */
889747dc10d7SGordon Ross list_for_each_entry(crtc, struct intel_crtc, &dev->mode_config.crtc_list, base.head) {
889847dc10d7SGordon Ross if (intel_crtc_to_shared_dpll(crtc) == pll)
889947dc10d7SGordon Ross assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
890047dc10d7SGordon Ross }
890147dc10d7SGordon Ross
890247dc10d7SGordon Ross reg = PCH_DPLL(pll->id);
890347dc10d7SGordon Ross val = I915_READ(reg);
890447dc10d7SGordon Ross val &= ~DPLL_VCO_ENABLE;
890547dc10d7SGordon Ross I915_WRITE(reg, val);
890647dc10d7SGordon Ross POSTING_READ(reg);
890747dc10d7SGordon Ross udelay(200);
890847dc10d7SGordon Ross }
890947dc10d7SGordon Ross
891047dc10d7SGordon Ross static char *ibx_pch_dpll_names[] = {
891147dc10d7SGordon Ross "PCH DPLL A",
891247dc10d7SGordon Ross "PCH DPLL B",
891347dc10d7SGordon Ross };
891447dc10d7SGordon Ross
ibx_pch_dpll_init(struct drm_device * dev)891547dc10d7SGordon Ross static void ibx_pch_dpll_init(struct drm_device *dev)
891647dc10d7SGordon Ross {
891747dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
891847dc10d7SGordon Ross int i;
891947dc10d7SGordon Ross
892047dc10d7SGordon Ross dev_priv->num_shared_dpll = 2;
892147dc10d7SGordon Ross
892247dc10d7SGordon Ross for (i = 0; i < dev_priv->num_shared_dpll; i++) {
892347dc10d7SGordon Ross dev_priv->shared_dplls[i].id = i;
892447dc10d7SGordon Ross dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
892547dc10d7SGordon Ross dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
892647dc10d7SGordon Ross dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
892747dc10d7SGordon Ross dev_priv->shared_dplls[i].get_hw_state =
892847dc10d7SGordon Ross ibx_pch_dpll_get_hw_state;
892947dc10d7SGordon Ross }
893047dc10d7SGordon Ross }
893147dc10d7SGordon Ross
intel_shared_dpll_init(struct drm_device * dev)893247dc10d7SGordon Ross static void intel_shared_dpll_init(struct drm_device *dev)
893347dc10d7SGordon Ross {
893447dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
893547dc10d7SGordon Ross
893647dc10d7SGordon Ross if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
893747dc10d7SGordon Ross ibx_pch_dpll_init(dev);
893847dc10d7SGordon Ross else
893947dc10d7SGordon Ross dev_priv->num_shared_dpll = 0;
894047dc10d7SGordon Ross
894147dc10d7SGordon Ross BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
894247dc10d7SGordon Ross DRM_DEBUG_KMS("%i shared PLLs initialized\n",
894347dc10d7SGordon Ross dev_priv->num_shared_dpll);
894447dc10d7SGordon Ross }
894547dc10d7SGordon Ross
intel_crtc_init(struct drm_device * dev,int pipe)894647dc10d7SGordon Ross static void intel_crtc_init(struct drm_device *dev, int pipe)
894747dc10d7SGordon Ross {
894847dc10d7SGordon Ross drm_i915_private_t *dev_priv = dev->dev_private;
894947dc10d7SGordon Ross struct intel_crtc *intel_crtc;
895047dc10d7SGordon Ross int i;
895147dc10d7SGordon Ross
895247dc10d7SGordon Ross intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
895347dc10d7SGordon Ross if (intel_crtc == NULL)
895447dc10d7SGordon Ross return;
895547dc10d7SGordon Ross
895647dc10d7SGordon Ross drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
895747dc10d7SGordon Ross
895847dc10d7SGordon Ross (void) drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
895947dc10d7SGordon Ross for (i = 0; i < 256; i++) {
896047dc10d7SGordon Ross intel_crtc->lut_r[i] = (u8) i;
896147dc10d7SGordon Ross intel_crtc->lut_g[i] = (u8) i;
896247dc10d7SGordon Ross intel_crtc->lut_b[i] = (u8) i;
896347dc10d7SGordon Ross }
896447dc10d7SGordon Ross
896547dc10d7SGordon Ross /* Swap pipes & planes for FBC on pre-965 */
896647dc10d7SGordon Ross intel_crtc->pipe = pipe;
896747dc10d7SGordon Ross intel_crtc->plane = pipe;
896847dc10d7SGordon Ross if (IS_MOBILE(dev) && IS_GEN3(dev)) {
896947dc10d7SGordon Ross DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
897047dc10d7SGordon Ross intel_crtc->plane = !pipe;
897147dc10d7SGordon Ross }
897247dc10d7SGordon Ross
897347dc10d7SGordon Ross BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
897447dc10d7SGordon Ross dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
897547dc10d7SGordon Ross dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
897647dc10d7SGordon Ross dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
897747dc10d7SGordon Ross
897847dc10d7SGordon Ross drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
897947dc10d7SGordon Ross }
898047dc10d7SGordon Ross
898147dc10d7SGordon Ross /* LINTED */
intel_get_pipe_from_crtc_id(DRM_IOCTL_ARGS)898247dc10d7SGordon Ross int intel_get_pipe_from_crtc_id(DRM_IOCTL_ARGS)
898347dc10d7SGordon Ross {
898447dc10d7SGordon Ross struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
898547dc10d7SGordon Ross struct drm_mode_object *drmmode_obj;
898647dc10d7SGordon Ross struct intel_crtc *crtc;
898747dc10d7SGordon Ross
898847dc10d7SGordon Ross if (!drm_core_check_feature(dev, DRIVER_MODESET))
898947dc10d7SGordon Ross return -ENODEV;
899047dc10d7SGordon Ross
899147dc10d7SGordon Ross drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
899247dc10d7SGordon Ross DRM_MODE_OBJECT_CRTC);
899347dc10d7SGordon Ross
899447dc10d7SGordon Ross if (!drmmode_obj) {
899547dc10d7SGordon Ross DRM_ERROR("no such CRTC id\n");
899647dc10d7SGordon Ross return -EINVAL;
899747dc10d7SGordon Ross }
899847dc10d7SGordon Ross
899947dc10d7SGordon Ross crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
900047dc10d7SGordon Ross pipe_from_crtc_id->pipe = crtc->pipe;
900147dc10d7SGordon Ross
900247dc10d7SGordon Ross return 0;
900347dc10d7SGordon Ross }
900447dc10d7SGordon Ross
intel_encoder_clones(struct intel_encoder * encoder)900547dc10d7SGordon Ross static int intel_encoder_clones(struct intel_encoder *encoder)
900647dc10d7SGordon Ross {
900747dc10d7SGordon Ross struct drm_device *dev = encoder->base.dev;
900847dc10d7SGordon Ross struct intel_encoder *source_encoder;
900947dc10d7SGordon Ross int index_mask = 0;
901047dc10d7SGordon Ross int entry = 0;
901147dc10d7SGordon Ross
901247dc10d7SGordon Ross list_for_each_entry(source_encoder, struct intel_encoder,
901347dc10d7SGordon Ross &dev->mode_config.encoder_list, base.head) {
901447dc10d7SGordon Ross
901547dc10d7SGordon Ross if (encoder == source_encoder)
901647dc10d7SGordon Ross index_mask |= (1 << entry);
901747dc10d7SGordon Ross
901847dc10d7SGordon Ross /* Intel hw has only one MUX where enocoders could be cloned. */
901947dc10d7SGordon Ross if (encoder->cloneable && source_encoder->cloneable)
902047dc10d7SGordon Ross index_mask |= (1 << entry);
902147dc10d7SGordon Ross
902247dc10d7SGordon Ross entry++;
902347dc10d7SGordon Ross }
902447dc10d7SGordon Ross
902547dc10d7SGordon Ross return index_mask;
902647dc10d7SGordon Ross }
902747dc10d7SGordon Ross
has_edp_a(struct drm_device * dev)902847dc10d7SGordon Ross static bool has_edp_a(struct drm_device *dev)
902947dc10d7SGordon Ross {
903047dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
903147dc10d7SGordon Ross
903247dc10d7SGordon Ross if (!IS_MOBILE(dev))
903347dc10d7SGordon Ross return false;
903447dc10d7SGordon Ross
903547dc10d7SGordon Ross if ((I915_READ(DP_A) & DP_DETECTED) == 0)
903647dc10d7SGordon Ross return false;
903747dc10d7SGordon Ross
903847dc10d7SGordon Ross if (IS_GEN5(dev) &&
903947dc10d7SGordon Ross (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
904047dc10d7SGordon Ross return false;
904147dc10d7SGordon Ross
904247dc10d7SGordon Ross return true;
904347dc10d7SGordon Ross }
904447dc10d7SGordon Ross
intel_setup_outputs(struct drm_device * dev)904547dc10d7SGordon Ross static void intel_setup_outputs(struct drm_device *dev)
904647dc10d7SGordon Ross {
904747dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
904847dc10d7SGordon Ross struct intel_encoder *encoder;
904947dc10d7SGordon Ross bool dpd_is_edp = false;
905047dc10d7SGordon Ross
905147dc10d7SGordon Ross intel_lvds_init(dev);
905247dc10d7SGordon Ross
905347dc10d7SGordon Ross if (!IS_ULT(dev))
905447dc10d7SGordon Ross intel_crt_init(dev);
905547dc10d7SGordon Ross
905647dc10d7SGordon Ross if (HAS_DDI(dev)) {
905747dc10d7SGordon Ross int found;
905847dc10d7SGordon Ross
905947dc10d7SGordon Ross /* Haswell uses DDI functions to detect digital outputs */
906047dc10d7SGordon Ross found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
906147dc10d7SGordon Ross /* DDI A only supports eDP */
906247dc10d7SGordon Ross if (found)
906347dc10d7SGordon Ross intel_ddi_init(dev, PORT_A);
906447dc10d7SGordon Ross
906547dc10d7SGordon Ross /* DDI B, C and D detection is indicated by the SFUSE_STRAP
906647dc10d7SGordon Ross * register */
906747dc10d7SGordon Ross found = I915_READ(SFUSE_STRAP);
906847dc10d7SGordon Ross
906947dc10d7SGordon Ross if (found & SFUSE_STRAP_DDIB_DETECTED)
907047dc10d7SGordon Ross intel_ddi_init(dev, PORT_B);
907147dc10d7SGordon Ross if (found & SFUSE_STRAP_DDIC_DETECTED)
907247dc10d7SGordon Ross intel_ddi_init(dev, PORT_C);
907347dc10d7SGordon Ross if (found & SFUSE_STRAP_DDID_DETECTED)
907447dc10d7SGordon Ross intel_ddi_init(dev, PORT_D);
907547dc10d7SGordon Ross } else if (HAS_PCH_SPLIT(dev)) {
907647dc10d7SGordon Ross int found;
907747dc10d7SGordon Ross dpd_is_edp = intel_dpd_is_edp(dev);
907847dc10d7SGordon Ross
907947dc10d7SGordon Ross if (has_edp_a(dev))
908047dc10d7SGordon Ross intel_dp_init(dev, DP_A, PORT_A);
908147dc10d7SGordon Ross
908247dc10d7SGordon Ross if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
908347dc10d7SGordon Ross /* PCH SDVOB multiplex with HDMIB */
908447dc10d7SGordon Ross found = intel_sdvo_init(dev, PCH_SDVOB, true);
908547dc10d7SGordon Ross if (!found)
908647dc10d7SGordon Ross intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
908747dc10d7SGordon Ross if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
908847dc10d7SGordon Ross intel_dp_init(dev, PCH_DP_B, PORT_B);
908947dc10d7SGordon Ross }
909047dc10d7SGordon Ross
909147dc10d7SGordon Ross if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
909247dc10d7SGordon Ross intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
909347dc10d7SGordon Ross
909447dc10d7SGordon Ross if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
909547dc10d7SGordon Ross intel_hdmi_init(dev, PCH_HDMID, PORT_D);
909647dc10d7SGordon Ross
909747dc10d7SGordon Ross if (I915_READ(PCH_DP_C) & DP_DETECTED)
909847dc10d7SGordon Ross intel_dp_init(dev, PCH_DP_C, PORT_C);
909947dc10d7SGordon Ross
910047dc10d7SGordon Ross if (I915_READ(PCH_DP_D) & DP_DETECTED)
910147dc10d7SGordon Ross intel_dp_init(dev, PCH_DP_D, PORT_D);
910247dc10d7SGordon Ross } else if (IS_VALLEYVIEW(dev)) {
910347dc10d7SGordon Ross /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
910447dc10d7SGordon Ross if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
910547dc10d7SGordon Ross intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
910647dc10d7SGordon Ross
910747dc10d7SGordon Ross if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
910847dc10d7SGordon Ross intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
910947dc10d7SGordon Ross PORT_B);
911047dc10d7SGordon Ross if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
911147dc10d7SGordon Ross intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
911247dc10d7SGordon Ross }
911347dc10d7SGordon Ross } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
911447dc10d7SGordon Ross bool found = false;
911547dc10d7SGordon Ross
911647dc10d7SGordon Ross if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
911747dc10d7SGordon Ross DRM_DEBUG_KMS("probing SDVOB\n");
911847dc10d7SGordon Ross found = intel_sdvo_init(dev, GEN3_SDVOB, true);
911947dc10d7SGordon Ross if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
912047dc10d7SGordon Ross DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
912147dc10d7SGordon Ross intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
912247dc10d7SGordon Ross }
912347dc10d7SGordon Ross
912447dc10d7SGordon Ross if (!found && SUPPORTS_INTEGRATED_DP(dev))
912547dc10d7SGordon Ross intel_dp_init(dev, DP_B, PORT_B);
912647dc10d7SGordon Ross }
912747dc10d7SGordon Ross
912847dc10d7SGordon Ross /* Before G4X SDVOC doesn't have its own detect register */
912947dc10d7SGordon Ross
913047dc10d7SGordon Ross if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
913147dc10d7SGordon Ross DRM_DEBUG_KMS("probing SDVOC\n");
913247dc10d7SGordon Ross found = intel_sdvo_init(dev, GEN3_SDVOC, false);
913347dc10d7SGordon Ross }
913447dc10d7SGordon Ross
913547dc10d7SGordon Ross if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
913647dc10d7SGordon Ross
913747dc10d7SGordon Ross if (SUPPORTS_INTEGRATED_HDMI(dev)) {
913847dc10d7SGordon Ross DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
913947dc10d7SGordon Ross intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
914047dc10d7SGordon Ross }
914147dc10d7SGordon Ross if (SUPPORTS_INTEGRATED_DP(dev))
914247dc10d7SGordon Ross intel_dp_init(dev, DP_C, PORT_C);
914347dc10d7SGordon Ross }
914447dc10d7SGordon Ross
914547dc10d7SGordon Ross if (SUPPORTS_INTEGRATED_DP(dev) &&
914647dc10d7SGordon Ross (I915_READ(DP_D) & DP_DETECTED))
914747dc10d7SGordon Ross intel_dp_init(dev, DP_D, PORT_D);
914847dc10d7SGordon Ross } else if (IS_GEN2(dev))
914947dc10d7SGordon Ross intel_dvo_init(dev);
915047dc10d7SGordon Ross
915147dc10d7SGordon Ross if (SUPPORTS_TV(dev))
915247dc10d7SGordon Ross intel_tv_init(dev);
915347dc10d7SGordon Ross
915447dc10d7SGordon Ross list_for_each_entry(encoder, struct intel_encoder, &dev->mode_config.encoder_list, base.head) {
915547dc10d7SGordon Ross encoder->base.possible_crtcs = encoder->crtc_mask;
915647dc10d7SGordon Ross encoder->base.possible_clones =
915747dc10d7SGordon Ross intel_encoder_clones(encoder);
915847dc10d7SGordon Ross }
915947dc10d7SGordon Ross
916047dc10d7SGordon Ross intel_init_pch_refclk(dev);
916147dc10d7SGordon Ross
916247dc10d7SGordon Ross drm_helper_move_panel_connectors_to_head(dev);
916347dc10d7SGordon Ross }
916447dc10d7SGordon Ross
intel_user_framebuffer_destroy(struct drm_framebuffer * fb)916547dc10d7SGordon Ross static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
916647dc10d7SGordon Ross {
916747dc10d7SGordon Ross struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
916847dc10d7SGordon Ross
916947dc10d7SGordon Ross drm_framebuffer_cleanup(fb);
917047dc10d7SGordon Ross drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
917147dc10d7SGordon Ross
917247dc10d7SGordon Ross kfree(intel_fb, sizeof (struct intel_framebuffer));
917347dc10d7SGordon Ross }
917447dc10d7SGordon Ross
intel_user_framebuffer_create_handle(struct drm_framebuffer * fb,struct drm_file * file,unsigned int * handle)917547dc10d7SGordon Ross static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
917647dc10d7SGordon Ross struct drm_file *file,
917747dc10d7SGordon Ross unsigned int *handle)
917847dc10d7SGordon Ross {
917947dc10d7SGordon Ross struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
918047dc10d7SGordon Ross struct drm_i915_gem_object *obj = intel_fb->obj;
918147dc10d7SGordon Ross
918247dc10d7SGordon Ross return drm_gem_handle_create(file, &obj->base, handle);
918347dc10d7SGordon Ross }
918447dc10d7SGordon Ross
918547dc10d7SGordon Ross static const struct drm_framebuffer_funcs intel_fb_funcs = {
918647dc10d7SGordon Ross .destroy = intel_user_framebuffer_destroy,
918747dc10d7SGordon Ross .create_handle = intel_user_framebuffer_create_handle,
918847dc10d7SGordon Ross };
918947dc10d7SGordon Ross
intel_framebuffer_init(struct drm_device * dev,struct intel_framebuffer * intel_fb,struct drm_mode_fb_cmd2 * mode_cmd,struct drm_i915_gem_object * obj)919047dc10d7SGordon Ross int intel_framebuffer_init(struct drm_device *dev,
919147dc10d7SGordon Ross struct intel_framebuffer *intel_fb,
919247dc10d7SGordon Ross struct drm_mode_fb_cmd2 *mode_cmd,
919347dc10d7SGordon Ross struct drm_i915_gem_object *obj)
919447dc10d7SGordon Ross {
919547dc10d7SGordon Ross int pitch_limit;
919647dc10d7SGordon Ross int ret;
919747dc10d7SGordon Ross
919847dc10d7SGordon Ross if (obj->tiling_mode == I915_TILING_Y) {
919947dc10d7SGordon Ross DRM_DEBUG("hardware does not support tiling Y\n");
920047dc10d7SGordon Ross return -EINVAL;
920147dc10d7SGordon Ross }
920247dc10d7SGordon Ross
920347dc10d7SGordon Ross if (mode_cmd->pitches[0] & 63) {
920447dc10d7SGordon Ross DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
920547dc10d7SGordon Ross mode_cmd->pitches[0]);
920647dc10d7SGordon Ross return -EINVAL;
920747dc10d7SGordon Ross }
920847dc10d7SGordon Ross
920947dc10d7SGordon Ross if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
921047dc10d7SGordon Ross pitch_limit = 32*1024;
921147dc10d7SGordon Ross } else if (INTEL_INFO(dev)->gen >= 4) {
921247dc10d7SGordon Ross if (obj->tiling_mode)
921347dc10d7SGordon Ross pitch_limit = 16*1024;
921447dc10d7SGordon Ross else
921547dc10d7SGordon Ross pitch_limit = 32*1024;
921647dc10d7SGordon Ross } else if (INTEL_INFO(dev)->gen >= 3) {
921747dc10d7SGordon Ross if (obj->tiling_mode)
921847dc10d7SGordon Ross pitch_limit = 8*1024;
921947dc10d7SGordon Ross else
922047dc10d7SGordon Ross pitch_limit = 16*1024;
922147dc10d7SGordon Ross } else
922247dc10d7SGordon Ross /* XXX DSPC is limited to 4k tiled */
922347dc10d7SGordon Ross pitch_limit = 8*1024;
922447dc10d7SGordon Ross
922547dc10d7SGordon Ross if (mode_cmd->pitches[0] > pitch_limit) {
922647dc10d7SGordon Ross DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
922747dc10d7SGordon Ross obj->tiling_mode ? "tiled" : "linear",
922847dc10d7SGordon Ross mode_cmd->pitches[0], pitch_limit);
922947dc10d7SGordon Ross return -EINVAL;
923047dc10d7SGordon Ross }
923147dc10d7SGordon Ross
923247dc10d7SGordon Ross if (obj->tiling_mode != I915_TILING_NONE &&
923347dc10d7SGordon Ross mode_cmd->pitches[0] != obj->stride) {
923447dc10d7SGordon Ross DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
923547dc10d7SGordon Ross mode_cmd->pitches[0], obj->stride);
923647dc10d7SGordon Ross return -EINVAL;
923747dc10d7SGordon Ross }
923847dc10d7SGordon Ross
923947dc10d7SGordon Ross /* Reject formats not supported by any plane early. */
924047dc10d7SGordon Ross switch (mode_cmd->pixel_format) {
924147dc10d7SGordon Ross case DRM_FORMAT_C8:
924247dc10d7SGordon Ross case DRM_FORMAT_RGB565:
924347dc10d7SGordon Ross case DRM_FORMAT_XRGB8888:
924447dc10d7SGordon Ross case DRM_FORMAT_ARGB8888:
924547dc10d7SGordon Ross break;
924647dc10d7SGordon Ross case DRM_FORMAT_XRGB1555:
924747dc10d7SGordon Ross case DRM_FORMAT_ARGB1555:
924847dc10d7SGordon Ross if (INTEL_INFO(dev)->gen > 3) {
924947dc10d7SGordon Ross DRM_DEBUG("unsupported pixel format: %s\n",
925047dc10d7SGordon Ross drm_get_format_name(mode_cmd->pixel_format));
925147dc10d7SGordon Ross return -EINVAL;
925247dc10d7SGordon Ross }
925347dc10d7SGordon Ross break;
925447dc10d7SGordon Ross case DRM_FORMAT_XBGR8888:
925547dc10d7SGordon Ross case DRM_FORMAT_ABGR8888:
925647dc10d7SGordon Ross case DRM_FORMAT_XRGB2101010:
925747dc10d7SGordon Ross case DRM_FORMAT_ARGB2101010:
925847dc10d7SGordon Ross case DRM_FORMAT_XBGR2101010:
925947dc10d7SGordon Ross case DRM_FORMAT_ABGR2101010:
926047dc10d7SGordon Ross if (INTEL_INFO(dev)->gen < 4) {
926147dc10d7SGordon Ross DRM_DEBUG("unsupported pixel format: %s\n",
926247dc10d7SGordon Ross drm_get_format_name(mode_cmd->pixel_format));
926347dc10d7SGordon Ross return -EINVAL;
926447dc10d7SGordon Ross }
926547dc10d7SGordon Ross break;
926647dc10d7SGordon Ross case DRM_FORMAT_YUYV:
926747dc10d7SGordon Ross case DRM_FORMAT_UYVY:
926847dc10d7SGordon Ross case DRM_FORMAT_YVYU:
926947dc10d7SGordon Ross case DRM_FORMAT_VYUY:
927047dc10d7SGordon Ross if (INTEL_INFO(dev)->gen < 5) {
927147dc10d7SGordon Ross DRM_DEBUG("unsupported pixel format: %s\n",
927247dc10d7SGordon Ross drm_get_format_name(mode_cmd->pixel_format));
927347dc10d7SGordon Ross return -EINVAL;
927447dc10d7SGordon Ross }
927547dc10d7SGordon Ross break;
927647dc10d7SGordon Ross default:
927747dc10d7SGordon Ross DRM_DEBUG("unsupported pixel format: %s\n",
927847dc10d7SGordon Ross drm_get_format_name(mode_cmd->pixel_format));
927947dc10d7SGordon Ross return -EINVAL;
928047dc10d7SGordon Ross }
928147dc10d7SGordon Ross
928247dc10d7SGordon Ross /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
928347dc10d7SGordon Ross if (mode_cmd->offsets[0] != 0)
928447dc10d7SGordon Ross return -EINVAL;
928547dc10d7SGordon Ross
928647dc10d7SGordon Ross (void) drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
928747dc10d7SGordon Ross intel_fb->obj = obj;
928847dc10d7SGordon Ross
928947dc10d7SGordon Ross ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
929047dc10d7SGordon Ross if (ret) {
929147dc10d7SGordon Ross DRM_ERROR("framebuffer init failed %d\n", ret);
929247dc10d7SGordon Ross return ret;
929347dc10d7SGordon Ross }
929447dc10d7SGordon Ross
929547dc10d7SGordon Ross return 0;
929647dc10d7SGordon Ross }
929747dc10d7SGordon Ross
929847dc10d7SGordon Ross static struct drm_framebuffer *
intel_user_framebuffer_create(struct drm_device * dev,struct drm_file * filp,struct drm_mode_fb_cmd2 * mode_cmd)929947dc10d7SGordon Ross intel_user_framebuffer_create(struct drm_device *dev,
930047dc10d7SGordon Ross struct drm_file *filp,
930147dc10d7SGordon Ross struct drm_mode_fb_cmd2 *mode_cmd)
930247dc10d7SGordon Ross {
930347dc10d7SGordon Ross struct drm_i915_gem_object *obj;
930447dc10d7SGordon Ross
930547dc10d7SGordon Ross obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
930647dc10d7SGordon Ross mode_cmd->handles[0]));
930747dc10d7SGordon Ross if (&obj->base == NULL)
930847dc10d7SGordon Ross return (NULL);
930947dc10d7SGordon Ross
931047dc10d7SGordon Ross return intel_framebuffer_create(dev, mode_cmd, obj);
931147dc10d7SGordon Ross }
931247dc10d7SGordon Ross
931347dc10d7SGordon Ross static const struct drm_mode_config_funcs intel_mode_funcs = {
931447dc10d7SGordon Ross .fb_create = intel_user_framebuffer_create,
931547dc10d7SGordon Ross .output_poll_changed = intel_fb_output_poll_changed,
931647dc10d7SGordon Ross };
931747dc10d7SGordon Ross
931847dc10d7SGordon Ross /* Set up chip specific display functions */
intel_init_display(struct drm_device * dev)931947dc10d7SGordon Ross static void intel_init_display(struct drm_device *dev)
932047dc10d7SGordon Ross {
932147dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
932247dc10d7SGordon Ross
932347dc10d7SGordon Ross if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
932447dc10d7SGordon Ross dev_priv->display.find_dpll = g4x_find_best_dpll;
932547dc10d7SGordon Ross else if (IS_VALLEYVIEW(dev))
932647dc10d7SGordon Ross dev_priv->display.find_dpll = vlv_find_best_dpll;
932747dc10d7SGordon Ross else if (IS_PINEVIEW(dev))
932847dc10d7SGordon Ross dev_priv->display.find_dpll = pnv_find_best_dpll;
932947dc10d7SGordon Ross else
933047dc10d7SGordon Ross dev_priv->display.find_dpll = i9xx_find_best_dpll;
933147dc10d7SGordon Ross
933247dc10d7SGordon Ross if (HAS_DDI(dev)) {
933347dc10d7SGordon Ross dev_priv->display.get_pipe_config = haswell_get_pipe_config;
933447dc10d7SGordon Ross dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
933547dc10d7SGordon Ross dev_priv->display.crtc_enable = haswell_crtc_enable;
933647dc10d7SGordon Ross dev_priv->display.crtc_disable = haswell_crtc_disable;
933747dc10d7SGordon Ross dev_priv->display.off = haswell_crtc_off;
933847dc10d7SGordon Ross dev_priv->display.update_plane = ironlake_update_plane;
933947dc10d7SGordon Ross } else if (HAS_PCH_SPLIT(dev)) {
934047dc10d7SGordon Ross dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
934147dc10d7SGordon Ross dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
934247dc10d7SGordon Ross dev_priv->display.crtc_enable = ironlake_crtc_enable;
934347dc10d7SGordon Ross dev_priv->display.crtc_disable = ironlake_crtc_disable;
934447dc10d7SGordon Ross dev_priv->display.off = ironlake_crtc_off;
934547dc10d7SGordon Ross dev_priv->display.update_plane = ironlake_update_plane;
934647dc10d7SGordon Ross } else if (IS_VALLEYVIEW(dev)) {
934747dc10d7SGordon Ross dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
934847dc10d7SGordon Ross dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
934947dc10d7SGordon Ross dev_priv->display.crtc_enable = valleyview_crtc_enable;
935047dc10d7SGordon Ross dev_priv->display.crtc_disable = i9xx_crtc_disable;
935147dc10d7SGordon Ross dev_priv->display.off = i9xx_crtc_off;
935247dc10d7SGordon Ross dev_priv->display.update_plane = i9xx_update_plane;
935347dc10d7SGordon Ross } else {
935447dc10d7SGordon Ross dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
935547dc10d7SGordon Ross dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
935647dc10d7SGordon Ross dev_priv->display.crtc_enable = i9xx_crtc_enable;
935747dc10d7SGordon Ross dev_priv->display.crtc_disable = i9xx_crtc_disable;
935847dc10d7SGordon Ross dev_priv->display.off = i9xx_crtc_off;
935947dc10d7SGordon Ross dev_priv->display.update_plane = i9xx_update_plane;
936047dc10d7SGordon Ross }
936147dc10d7SGordon Ross
936247dc10d7SGordon Ross /* Returns the core display clock speed */
936347dc10d7SGordon Ross if (IS_VALLEYVIEW(dev))
936447dc10d7SGordon Ross dev_priv->display.get_display_clock_speed =
936547dc10d7SGordon Ross valleyview_get_display_clock_speed;
936647dc10d7SGordon Ross else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
936747dc10d7SGordon Ross dev_priv->display.get_display_clock_speed =
936847dc10d7SGordon Ross i945_get_display_clock_speed;
936947dc10d7SGordon Ross else if (IS_I915G(dev))
937047dc10d7SGordon Ross dev_priv->display.get_display_clock_speed =
937147dc10d7SGordon Ross i915_get_display_clock_speed;
937247dc10d7SGordon Ross else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
937347dc10d7SGordon Ross dev_priv->display.get_display_clock_speed =
937447dc10d7SGordon Ross i9xx_misc_get_display_clock_speed;
937547dc10d7SGordon Ross else if (IS_I915GM(dev))
937647dc10d7SGordon Ross dev_priv->display.get_display_clock_speed =
937747dc10d7SGordon Ross i915gm_get_display_clock_speed;
937847dc10d7SGordon Ross else if (IS_I865G(dev))
937947dc10d7SGordon Ross dev_priv->display.get_display_clock_speed =
938047dc10d7SGordon Ross i865_get_display_clock_speed;
938147dc10d7SGordon Ross else if (IS_I85X(dev))
938247dc10d7SGordon Ross dev_priv->display.get_display_clock_speed =
938347dc10d7SGordon Ross i855_get_display_clock_speed;
938447dc10d7SGordon Ross else /* 852, 830 */
938547dc10d7SGordon Ross dev_priv->display.get_display_clock_speed =
938647dc10d7SGordon Ross i830_get_display_clock_speed;
938747dc10d7SGordon Ross
938847dc10d7SGordon Ross if (HAS_PCH_SPLIT(dev)) {
938947dc10d7SGordon Ross if (IS_GEN5(dev)) {
939047dc10d7SGordon Ross dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
939147dc10d7SGordon Ross dev_priv->display.write_eld = ironlake_write_eld;
939247dc10d7SGordon Ross } else if (IS_GEN6(dev)) {
939347dc10d7SGordon Ross dev_priv->display.fdi_link_train = gen6_fdi_link_train;
939447dc10d7SGordon Ross dev_priv->display.write_eld = ironlake_write_eld;
939547dc10d7SGordon Ross } else if (IS_IVYBRIDGE(dev)) {
939647dc10d7SGordon Ross /* FIXME: detect B0+ stepping and use auto training */
939747dc10d7SGordon Ross dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
939847dc10d7SGordon Ross dev_priv->display.write_eld = ironlake_write_eld;
939947dc10d7SGordon Ross dev_priv->display.modeset_global_resources =
940047dc10d7SGordon Ross ivb_modeset_global_resources;
940147dc10d7SGordon Ross } else if (IS_HASWELL(dev)) {
940247dc10d7SGordon Ross dev_priv->display.fdi_link_train = hsw_fdi_link_train;
940347dc10d7SGordon Ross dev_priv->display.write_eld = haswell_write_eld;
940447dc10d7SGordon Ross dev_priv->display.modeset_global_resources =
940547dc10d7SGordon Ross haswell_modeset_global_resources;
940647dc10d7SGordon Ross }
940747dc10d7SGordon Ross } else if (IS_G4X(dev)) {
940847dc10d7SGordon Ross dev_priv->display.write_eld = g4x_write_eld;
940947dc10d7SGordon Ross }
941047dc10d7SGordon Ross
941147dc10d7SGordon Ross /* Default just returns -ENODEV to indicate unsupported */
941247dc10d7SGordon Ross dev_priv->display.queue_flip = intel_default_queue_flip;
941347dc10d7SGordon Ross
941447dc10d7SGordon Ross switch (INTEL_INFO(dev)->gen) {
941547dc10d7SGordon Ross case 2:
941647dc10d7SGordon Ross dev_priv->display.queue_flip = intel_gen2_queue_flip;
941747dc10d7SGordon Ross break;
941847dc10d7SGordon Ross
941947dc10d7SGordon Ross case 3:
942047dc10d7SGordon Ross dev_priv->display.queue_flip = intel_gen3_queue_flip;
942147dc10d7SGordon Ross break;
942247dc10d7SGordon Ross
942347dc10d7SGordon Ross case 4:
942447dc10d7SGordon Ross case 5:
942547dc10d7SGordon Ross dev_priv->display.queue_flip = intel_gen4_queue_flip;
942647dc10d7SGordon Ross break;
942747dc10d7SGordon Ross
942847dc10d7SGordon Ross case 6:
942947dc10d7SGordon Ross dev_priv->display.queue_flip = intel_gen6_queue_flip;
943047dc10d7SGordon Ross break;
943147dc10d7SGordon Ross case 7:
943247dc10d7SGordon Ross dev_priv->display.queue_flip = intel_gen7_queue_flip;
943347dc10d7SGordon Ross break;
943447dc10d7SGordon Ross }
943547dc10d7SGordon Ross }
943647dc10d7SGordon Ross
943747dc10d7SGordon Ross /*
943847dc10d7SGordon Ross * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
943947dc10d7SGordon Ross * resume, or other times. This quirk makes sure that's the case for
944047dc10d7SGordon Ross * affected systems.
944147dc10d7SGordon Ross */
quirk_pipea_force(struct drm_device * dev)944247dc10d7SGordon Ross static void quirk_pipea_force (struct drm_device *dev)
944347dc10d7SGordon Ross {
944447dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
944547dc10d7SGordon Ross
944647dc10d7SGordon Ross dev_priv->quirks |= QUIRK_PIPEA_FORCE;
944747dc10d7SGordon Ross DRM_INFO("applying pipe a force quirk\n");
944847dc10d7SGordon Ross }
944947dc10d7SGordon Ross
945047dc10d7SGordon Ross /*
945147dc10d7SGordon Ross * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
945247dc10d7SGordon Ross */
quirk_ssc_force_disable(struct drm_device * dev)945347dc10d7SGordon Ross static void quirk_ssc_force_disable(struct drm_device *dev)
945447dc10d7SGordon Ross {
945547dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
945647dc10d7SGordon Ross dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
945747dc10d7SGordon Ross DRM_INFO("applying lvds SSC disable quirk\n");
945847dc10d7SGordon Ross }
945947dc10d7SGordon Ross
946047dc10d7SGordon Ross /*
946147dc10d7SGordon Ross * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
946247dc10d7SGordon Ross * brightness value
946347dc10d7SGordon Ross */
quirk_invert_brightness(struct drm_device * dev)946447dc10d7SGordon Ross static void quirk_invert_brightness(struct drm_device *dev)
946547dc10d7SGordon Ross {
946647dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
946747dc10d7SGordon Ross dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
946847dc10d7SGordon Ross DRM_INFO("applying inverted panel brightness quirk\n");
946947dc10d7SGordon Ross }
947047dc10d7SGordon Ross
947147dc10d7SGordon Ross #if 0
947247dc10d7SGordon Ross /*
947347dc10d7SGordon Ross * Some machines (Dell XPS13) suffer broken backlight controls if
947447dc10d7SGordon Ross * BLM_PCH_PWM_ENABLE is set.
947547dc10d7SGordon Ross */
947647dc10d7SGordon Ross static void quirk_no_pcm_pwm_enable(struct drm_device *dev)
947747dc10d7SGordon Ross {
947847dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
947947dc10d7SGordon Ross dev_priv->quirks |= QUIRK_NO_PCH_PWM_ENABLE;
948047dc10d7SGordon Ross DRM_INFO("applying no-PCH_PWM_ENABLE quirk\n");
948147dc10d7SGordon Ross }
948247dc10d7SGordon Ross
948347dc10d7SGordon Ross struct intel_quirk {
948447dc10d7SGordon Ross int device;
948547dc10d7SGordon Ross int subsystem_vendor;
948647dc10d7SGordon Ross int subsystem_device;
948747dc10d7SGordon Ross void (*hook)(struct drm_device *dev);
948847dc10d7SGordon Ross };
948947dc10d7SGordon Ross
949047dc10d7SGordon Ross /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
949147dc10d7SGordon Ross struct intel_dmi_quirk {
949247dc10d7SGordon Ross void (*hook)(struct drm_device *dev);
949347dc10d7SGordon Ross const struct dmi_system_id (*dmi_id_list)[];
949447dc10d7SGordon Ross };
949547dc10d7SGordon Ross
949647dc10d7SGordon Ross static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
949747dc10d7SGordon Ross {
949847dc10d7SGordon Ross DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
949947dc10d7SGordon Ross return 1;
950047dc10d7SGordon Ross }
950147dc10d7SGordon Ross
950247dc10d7SGordon Ross static const struct intel_dmi_quirk intel_dmi_quirks[] = {
950347dc10d7SGordon Ross {
950447dc10d7SGordon Ross .dmi_id_list = &(const struct dmi_system_id[]) {
950547dc10d7SGordon Ross {
950647dc10d7SGordon Ross .callback = intel_dmi_reverse_brightness,
950747dc10d7SGordon Ross .ident = "NCR Corporation",
950847dc10d7SGordon Ross .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
950947dc10d7SGordon Ross DMI_MATCH(DMI_PRODUCT_NAME, ""),
951047dc10d7SGordon Ross },
951147dc10d7SGordon Ross },
951247dc10d7SGordon Ross { } /* terminating entry */
951347dc10d7SGordon Ross },
951447dc10d7SGordon Ross .hook = quirk_invert_brightness,
951547dc10d7SGordon Ross },
951647dc10d7SGordon Ross };
951747dc10d7SGordon Ross
951847dc10d7SGordon Ross static struct intel_quirk intel_quirks[] = {
951947dc10d7SGordon Ross /* HP Mini needs pipe A force quirk (LP: #322104) */
952047dc10d7SGordon Ross { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
952147dc10d7SGordon Ross
952247dc10d7SGordon Ross /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
952347dc10d7SGordon Ross { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
952447dc10d7SGordon Ross
952547dc10d7SGordon Ross /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
952647dc10d7SGordon Ross { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
952747dc10d7SGordon Ross
952847dc10d7SGordon Ross /* 830/845 need to leave pipe A & dpll A up */
952947dc10d7SGordon Ross { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
953047dc10d7SGordon Ross { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
953147dc10d7SGordon Ross
953247dc10d7SGordon Ross /* Lenovo U160 cannot use SSC on LVDS */
953347dc10d7SGordon Ross { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
953447dc10d7SGordon Ross
953547dc10d7SGordon Ross /* Sony Vaio Y cannot use SSC on LVDS */
953647dc10d7SGordon Ross { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
953747dc10d7SGordon Ross
953847dc10d7SGordon Ross /* Acer Aspire 5734Z must invert backlight brightness */
953947dc10d7SGordon Ross { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
954047dc10d7SGordon Ross
954147dc10d7SGordon Ross /* Acer/eMachines G725 */
954247dc10d7SGordon Ross { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
954347dc10d7SGordon Ross
954447dc10d7SGordon Ross /* Acer/eMachines e725 */
954547dc10d7SGordon Ross { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
954647dc10d7SGordon Ross
954747dc10d7SGordon Ross /* Acer/Packard Bell NCL20 */
954847dc10d7SGordon Ross { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
954947dc10d7SGordon Ross
955047dc10d7SGordon Ross /* Acer Aspire 4736Z */
955147dc10d7SGordon Ross { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
955247dc10d7SGordon Ross
955347dc10d7SGordon Ross /* Dell XPS13 HD Sandy Bridge */
955447dc10d7SGordon Ross { 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable },
955547dc10d7SGordon Ross /* Dell XPS13 HD and XPS13 FHD Ivy Bridge */
955647dc10d7SGordon Ross { 0x0166, 0x1028, 0x058b, quirk_no_pcm_pwm_enable },
955747dc10d7SGordon Ross };
955847dc10d7SGordon Ross
955947dc10d7SGordon Ross static void intel_init_quirks(struct drm_device *dev)
956047dc10d7SGordon Ross {
956147dc10d7SGordon Ross struct pci_dev *d = dev->pdev;
956247dc10d7SGordon Ross int i;
956347dc10d7SGordon Ross
956447dc10d7SGordon Ross for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
956547dc10d7SGordon Ross struct intel_quirk *q = &intel_quirks[i];
956647dc10d7SGordon Ross
956747dc10d7SGordon Ross if (d->device == q->device &&
956847dc10d7SGordon Ross (d->subsystem_vendor == q->subsystem_vendor ||
956947dc10d7SGordon Ross q->subsystem_vendor == PCI_ANY_ID) &&
957047dc10d7SGordon Ross (d->subsystem_device == q->subsystem_device ||
957147dc10d7SGordon Ross q->subsystem_device == PCI_ANY_ID))
957247dc10d7SGordon Ross q->hook(dev);
957347dc10d7SGordon Ross }
957447dc10d7SGordon Ross for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
957547dc10d7SGordon Ross if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
957647dc10d7SGordon Ross intel_dmi_quirks[i].hook(dev);
957747dc10d7SGordon Ross }
957847dc10d7SGordon Ross }
957947dc10d7SGordon Ross #endif
958047dc10d7SGordon Ross /* Disable the VGA plane that we never use */
i915_disable_vga(struct drm_device * dev)958147dc10d7SGordon Ross static void i915_disable_vga(struct drm_device *dev)
958247dc10d7SGordon Ross {
958347dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
958447dc10d7SGordon Ross u8 sr1;
958547dc10d7SGordon Ross u32 vga_reg = i915_vgacntrl_reg(dev);
958647dc10d7SGordon Ross
958747dc10d7SGordon Ross I915_WRITE8(VGA_SR_INDEX, SR01);
958847dc10d7SGordon Ross sr1 = I915_READ8(VGA_SR_DATA);
958947dc10d7SGordon Ross I915_WRITE8(VGA_SR_DATA, sr1 | (1 << 5));
959047dc10d7SGordon Ross udelay(300);
959147dc10d7SGordon Ross
959247dc10d7SGordon Ross I915_WRITE(vga_reg, VGA_DISP_DISABLE);
959347dc10d7SGordon Ross POSTING_READ(vga_reg);
959447dc10d7SGordon Ross }
959547dc10d7SGordon Ross
intel_modeset_init_hw(struct drm_device * dev)959647dc10d7SGordon Ross void intel_modeset_init_hw(struct drm_device *dev)
959747dc10d7SGordon Ross {
959847dc10d7SGordon Ross intel_init_power_well(dev);
959947dc10d7SGordon Ross
960047dc10d7SGordon Ross intel_prepare_ddi(dev);
960147dc10d7SGordon Ross
960247dc10d7SGordon Ross intel_init_clock_gating(dev);
960347dc10d7SGordon Ross
960447dc10d7SGordon Ross mutex_lock(&dev->struct_mutex);
960547dc10d7SGordon Ross intel_enable_gt_powersave(dev);
960647dc10d7SGordon Ross mutex_unlock(&dev->struct_mutex);
960747dc10d7SGordon Ross }
960847dc10d7SGordon Ross
intel_modeset_suspend_hw(struct drm_device * dev)960947dc10d7SGordon Ross void intel_modeset_suspend_hw(struct drm_device *dev)
961047dc10d7SGordon Ross {
961147dc10d7SGordon Ross intel_suspend_hw(dev);
961247dc10d7SGordon Ross }
961347dc10d7SGordon Ross
intel_modeset_init(struct drm_device * dev)961447dc10d7SGordon Ross void intel_modeset_init(struct drm_device *dev)
961547dc10d7SGordon Ross {
961647dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
961747dc10d7SGordon Ross int i, j, ret;
961847dc10d7SGordon Ross
961947dc10d7SGordon Ross drm_mode_config_init(dev);
962047dc10d7SGordon Ross
962147dc10d7SGordon Ross dev->mode_config.min_width = 0;
962247dc10d7SGordon Ross dev->mode_config.min_height = 0;
962347dc10d7SGordon Ross
962447dc10d7SGordon Ross dev->mode_config.preferred_depth = 24;
962547dc10d7SGordon Ross dev->mode_config.prefer_shadow = 1;
962647dc10d7SGordon Ross
962747dc10d7SGordon Ross dev->mode_config.funcs = (void *)&intel_mode_funcs;
962847dc10d7SGordon Ross
962947dc10d7SGordon Ross /* OSOL_I915 intel_init_quirks(dev); */
963047dc10d7SGordon Ross
963147dc10d7SGordon Ross intel_init_pm(dev);
963247dc10d7SGordon Ross
963347dc10d7SGordon Ross if (INTEL_INFO(dev)->num_pipes == 0)
963447dc10d7SGordon Ross return;
963547dc10d7SGordon Ross
963647dc10d7SGordon Ross intel_init_display(dev);
963747dc10d7SGordon Ross
963847dc10d7SGordon Ross if (IS_GEN2(dev)) {
963947dc10d7SGordon Ross dev->mode_config.max_width = 2048;
964047dc10d7SGordon Ross dev->mode_config.max_height = 2048;
964147dc10d7SGordon Ross } else if (IS_GEN3(dev)) {
964247dc10d7SGordon Ross dev->mode_config.max_width = 4096;
964347dc10d7SGordon Ross dev->mode_config.max_height = 4096;
964447dc10d7SGordon Ross } else {
964547dc10d7SGordon Ross dev->mode_config.max_width = 8192;
964647dc10d7SGordon Ross dev->mode_config.max_height = 8192;
964747dc10d7SGordon Ross }
964847dc10d7SGordon Ross dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
964947dc10d7SGordon Ross
965047dc10d7SGordon Ross DRM_DEBUG_KMS("%d display pipe%s available.\n",
965147dc10d7SGordon Ross INTEL_INFO(dev)->num_pipes,
965247dc10d7SGordon Ross INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
965347dc10d7SGordon Ross
965447dc10d7SGordon Ross for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
965547dc10d7SGordon Ross intel_crtc_init(dev, i);
965647dc10d7SGordon Ross for (j = 0; j < dev_priv->num_plane; j++) {
965747dc10d7SGordon Ross ret = intel_plane_init(dev, i, j);
965847dc10d7SGordon Ross if (ret)
965947dc10d7SGordon Ross DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
966047dc10d7SGordon Ross pipe_name(i), sprite_name(i, j), ret);
966147dc10d7SGordon Ross }
966247dc10d7SGordon Ross }
966347dc10d7SGordon Ross
966447dc10d7SGordon Ross intel_cpu_pll_init(dev);
966547dc10d7SGordon Ross intel_shared_dpll_init(dev);
966647dc10d7SGordon Ross
966747dc10d7SGordon Ross /* Just disable it once at startup */
966847dc10d7SGordon Ross i915_disable_vga(dev);
966947dc10d7SGordon Ross intel_setup_outputs(dev);
967047dc10d7SGordon Ross
967147dc10d7SGordon Ross /* Just in case the BIOS is doing something questionable. */
967247dc10d7SGordon Ross intel_disable_fbc(dev);
967347dc10d7SGordon Ross }
967447dc10d7SGordon Ross
967547dc10d7SGordon Ross static void
intel_connector_break_all_links(struct intel_connector * connector)967647dc10d7SGordon Ross intel_connector_break_all_links(struct intel_connector *connector)
967747dc10d7SGordon Ross {
967847dc10d7SGordon Ross connector->base.dpms = DRM_MODE_DPMS_OFF;
967947dc10d7SGordon Ross connector->base.encoder = NULL;
968047dc10d7SGordon Ross connector->encoder->connectors_active = false;
968147dc10d7SGordon Ross connector->encoder->base.crtc = NULL;
968247dc10d7SGordon Ross }
968347dc10d7SGordon Ross
intel_enable_pipe_a(struct drm_device * dev)968447dc10d7SGordon Ross static void intel_enable_pipe_a(struct drm_device *dev)
968547dc10d7SGordon Ross {
968647dc10d7SGordon Ross struct intel_connector *connector;
968747dc10d7SGordon Ross struct drm_connector *crt = NULL;
968847dc10d7SGordon Ross struct intel_load_detect_pipe load_detect_temp;
968947dc10d7SGordon Ross
969047dc10d7SGordon Ross /* We can't just switch on the pipe A, we need to set things up with a
969147dc10d7SGordon Ross * proper mode and output configuration. As a gross hack, enable pipe A
969247dc10d7SGordon Ross * by enabling the load detect pipe once. */
969347dc10d7SGordon Ross list_for_each_entry(connector, struct intel_connector,
969447dc10d7SGordon Ross &dev->mode_config.connector_list,
969547dc10d7SGordon Ross base.head) {
969647dc10d7SGordon Ross if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
969747dc10d7SGordon Ross crt = &connector->base;
969847dc10d7SGordon Ross break;
969947dc10d7SGordon Ross }
970047dc10d7SGordon Ross }
970147dc10d7SGordon Ross
970247dc10d7SGordon Ross if (!crt)
970347dc10d7SGordon Ross return;
970447dc10d7SGordon Ross
970547dc10d7SGordon Ross if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
970647dc10d7SGordon Ross intel_release_load_detect_pipe(crt, &load_detect_temp);
970747dc10d7SGordon Ross
970847dc10d7SGordon Ross
970947dc10d7SGordon Ross }
971047dc10d7SGordon Ross
971147dc10d7SGordon Ross static bool
intel_check_plane_mapping(struct intel_crtc * crtc)971247dc10d7SGordon Ross intel_check_plane_mapping(struct intel_crtc *crtc)
971347dc10d7SGordon Ross {
971447dc10d7SGordon Ross struct drm_device *dev = crtc->base.dev;
971547dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
971647dc10d7SGordon Ross u32 reg, val;
971747dc10d7SGordon Ross
971847dc10d7SGordon Ross if (INTEL_INFO(dev)->num_pipes == 1)
971947dc10d7SGordon Ross return true;
972047dc10d7SGordon Ross
972147dc10d7SGordon Ross reg = DSPCNTR(!crtc->plane);
972247dc10d7SGordon Ross val = I915_READ(reg);
972347dc10d7SGordon Ross
972447dc10d7SGordon Ross if ((val & DISPLAY_PLANE_ENABLE) &&
972547dc10d7SGordon Ross (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
972647dc10d7SGordon Ross return false;
972747dc10d7SGordon Ross
972847dc10d7SGordon Ross return true;
972947dc10d7SGordon Ross }
973047dc10d7SGordon Ross
intel_sanitize_crtc(struct intel_crtc * crtc)973147dc10d7SGordon Ross static void intel_sanitize_crtc(struct intel_crtc *crtc)
973247dc10d7SGordon Ross {
973347dc10d7SGordon Ross struct drm_device *dev = crtc->base.dev;
973447dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
973547dc10d7SGordon Ross u32 reg;
973647dc10d7SGordon Ross
973747dc10d7SGordon Ross /* Clear any frame start delays used for debugging left by the BIOS */
973847dc10d7SGordon Ross reg = PIPECONF(crtc->config.cpu_transcoder);
973947dc10d7SGordon Ross I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
974047dc10d7SGordon Ross
974147dc10d7SGordon Ross /* We need to sanitize the plane -> pipe mapping first because this will
974247dc10d7SGordon Ross * disable the crtc (and hence change the state) if it is wrong. Note
974347dc10d7SGordon Ross * that gen4+ has a fixed plane -> pipe mapping. */
974447dc10d7SGordon Ross if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
974547dc10d7SGordon Ross struct intel_connector *connector;
974647dc10d7SGordon Ross bool plane;
974747dc10d7SGordon Ross
974847dc10d7SGordon Ross DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
974947dc10d7SGordon Ross crtc->base.base.id);
975047dc10d7SGordon Ross
975147dc10d7SGordon Ross /* Pipe has the wrong plane attached and the plane is active.
975247dc10d7SGordon Ross * Temporarily change the plane mapping and disable everything
975347dc10d7SGordon Ross * ... */
975447dc10d7SGordon Ross plane = crtc->plane;
975547dc10d7SGordon Ross crtc->plane = !plane;
975647dc10d7SGordon Ross dev_priv->display.crtc_disable(&crtc->base);
975747dc10d7SGordon Ross crtc->plane = plane;
975847dc10d7SGordon Ross
975947dc10d7SGordon Ross /* ... and break all links. */
976047dc10d7SGordon Ross list_for_each_entry(connector, struct intel_connector, &dev->mode_config.connector_list,
976147dc10d7SGordon Ross base.head) {
976247dc10d7SGordon Ross if (connector->encoder->base.crtc != &crtc->base)
976347dc10d7SGordon Ross continue;
976447dc10d7SGordon Ross
976547dc10d7SGordon Ross intel_connector_break_all_links(connector);
976647dc10d7SGordon Ross }
976747dc10d7SGordon Ross
976847dc10d7SGordon Ross WARN_ON(crtc->active);
976947dc10d7SGordon Ross crtc->base.enabled = false;
977047dc10d7SGordon Ross }
977147dc10d7SGordon Ross
977247dc10d7SGordon Ross if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
977347dc10d7SGordon Ross crtc->pipe == PIPE_A && !crtc->active) {
977447dc10d7SGordon Ross /* BIOS forgot to enable pipe A, this mostly happens after
977547dc10d7SGordon Ross * resume. Force-enable the pipe to fix this, the update_dpms
977647dc10d7SGordon Ross * call below we restore the pipe to the right state, but leave
977747dc10d7SGordon Ross * the required bits on. */
977847dc10d7SGordon Ross intel_enable_pipe_a(dev);
977947dc10d7SGordon Ross }
978047dc10d7SGordon Ross
978147dc10d7SGordon Ross /* Adjust the state of the output pipe according to whether we
978247dc10d7SGordon Ross * have active connectors/encoders. */
978347dc10d7SGordon Ross intel_crtc_update_dpms(&crtc->base);
978447dc10d7SGordon Ross
978547dc10d7SGordon Ross if (crtc->active != crtc->base.enabled) {
978647dc10d7SGordon Ross struct intel_encoder *encoder;
978747dc10d7SGordon Ross
978847dc10d7SGordon Ross /* This can happen either due to bugs in the get_hw_state
978947dc10d7SGordon Ross * functions or because the pipe is force-enabled due to the
979047dc10d7SGordon Ross * pipe A quirk. */
979147dc10d7SGordon Ross DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
979247dc10d7SGordon Ross crtc->base.base.id,
979347dc10d7SGordon Ross crtc->base.enabled ? "enabled" : "disabled",
979447dc10d7SGordon Ross crtc->active ? "enabled" : "disabled");
979547dc10d7SGordon Ross
979647dc10d7SGordon Ross crtc->base.enabled = crtc->active;
979747dc10d7SGordon Ross
979847dc10d7SGordon Ross /* Because we only establish the connector -> encoder ->
979947dc10d7SGordon Ross * crtc links if something is active, this means the
980047dc10d7SGordon Ross * crtc is now deactivated. Break the links. connector
980147dc10d7SGordon Ross * -> encoder links are only establish when things are
980247dc10d7SGordon Ross * actually up, hence no need to break them. */
980347dc10d7SGordon Ross WARN_ON(crtc->active);
980447dc10d7SGordon Ross
980547dc10d7SGordon Ross for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
980647dc10d7SGordon Ross WARN_ON(encoder->connectors_active);
980747dc10d7SGordon Ross encoder->base.crtc = NULL;
980847dc10d7SGordon Ross }
980947dc10d7SGordon Ross }
981047dc10d7SGordon Ross }
981147dc10d7SGordon Ross
intel_sanitize_encoder(struct intel_encoder * encoder)981247dc10d7SGordon Ross static void intel_sanitize_encoder(struct intel_encoder *encoder)
981347dc10d7SGordon Ross {
981447dc10d7SGordon Ross struct intel_connector *connector;
981547dc10d7SGordon Ross struct drm_device *dev = encoder->base.dev;
981647dc10d7SGordon Ross
981747dc10d7SGordon Ross /* We need to check both for a crtc link (meaning that the
981847dc10d7SGordon Ross * encoder is active and trying to read from a pipe) and the
981947dc10d7SGordon Ross * pipe itself being active. */
982047dc10d7SGordon Ross bool has_active_crtc = encoder->base.crtc &&
982147dc10d7SGordon Ross to_intel_crtc(encoder->base.crtc)->active;
982247dc10d7SGordon Ross
982347dc10d7SGordon Ross if (encoder->connectors_active && !has_active_crtc) {
982447dc10d7SGordon Ross DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
982547dc10d7SGordon Ross encoder->base.base.id,
982647dc10d7SGordon Ross drm_get_encoder_name(&encoder->base));
982747dc10d7SGordon Ross
982847dc10d7SGordon Ross /* Connector is active, but has no active pipe. This is
982947dc10d7SGordon Ross * fallout from our resume register restoring. Disable
983047dc10d7SGordon Ross * the encoder manually again. */
983147dc10d7SGordon Ross if (encoder->base.crtc) {
983247dc10d7SGordon Ross DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
983347dc10d7SGordon Ross encoder->base.base.id,
983447dc10d7SGordon Ross drm_get_encoder_name(&encoder->base));
983547dc10d7SGordon Ross encoder->disable(encoder);
983647dc10d7SGordon Ross }
983747dc10d7SGordon Ross
983847dc10d7SGordon Ross /* Inconsistent output/port/pipe state happens presumably due to
983947dc10d7SGordon Ross * a bug in one of the get_hw_state functions. Or someplace else
984047dc10d7SGordon Ross * in our code, like the register restore mess on resume. Clamp
984147dc10d7SGordon Ross * things to off as a safer default. */
984247dc10d7SGordon Ross list_for_each_entry(connector, struct intel_connector,
984347dc10d7SGordon Ross &dev->mode_config.connector_list,
984447dc10d7SGordon Ross base.head) {
984547dc10d7SGordon Ross if (connector->encoder != encoder)
984647dc10d7SGordon Ross continue;
984747dc10d7SGordon Ross
984847dc10d7SGordon Ross intel_connector_break_all_links(connector);
984947dc10d7SGordon Ross }
985047dc10d7SGordon Ross }
985147dc10d7SGordon Ross /* Enabled encoders without active connectors will be fixed in
985247dc10d7SGordon Ross * the crtc fixup. */
985347dc10d7SGordon Ross }
985447dc10d7SGordon Ross
i915_redisable_vga(struct drm_device * dev)985547dc10d7SGordon Ross void i915_redisable_vga(struct drm_device *dev)
985647dc10d7SGordon Ross {
985747dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
985847dc10d7SGordon Ross u32 vga_reg = i915_vgacntrl_reg(dev);
985947dc10d7SGordon Ross
986047dc10d7SGordon Ross if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
986147dc10d7SGordon Ross DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
986247dc10d7SGordon Ross i915_disable_vga(dev);
986347dc10d7SGordon Ross }
986447dc10d7SGordon Ross }
986547dc10d7SGordon Ross
intel_modeset_readout_hw_state(struct drm_device * dev)986647dc10d7SGordon Ross static void intel_modeset_readout_hw_state(struct drm_device *dev)
986747dc10d7SGordon Ross {
986847dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
986947dc10d7SGordon Ross enum pipe pipe;
987047dc10d7SGordon Ross struct intel_crtc *crtc;
987147dc10d7SGordon Ross struct intel_encoder *encoder;
987247dc10d7SGordon Ross struct intel_connector *connector;
987347dc10d7SGordon Ross int i;
987447dc10d7SGordon Ross
987547dc10d7SGordon Ross list_for_each_entry(crtc, struct intel_crtc, &dev->mode_config.crtc_list,
987647dc10d7SGordon Ross base.head) {
987747dc10d7SGordon Ross (void) memset(&crtc->config, 0, sizeof(crtc->config));
987847dc10d7SGordon Ross
987947dc10d7SGordon Ross crtc->active = dev_priv->display.get_pipe_config(crtc,
988047dc10d7SGordon Ross &crtc->config);
988147dc10d7SGordon Ross
988247dc10d7SGordon Ross crtc->base.enabled = crtc->active;
988347dc10d7SGordon Ross
988447dc10d7SGordon Ross DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
988547dc10d7SGordon Ross crtc->base.base.id,
988647dc10d7SGordon Ross crtc->active ? "enabled" : "disabled");
988747dc10d7SGordon Ross }
988847dc10d7SGordon Ross
988947dc10d7SGordon Ross /* FIXME: Smash this into the new shared dpll infrastructure. */
989047dc10d7SGordon Ross if (HAS_DDI(dev))
989147dc10d7SGordon Ross intel_ddi_setup_hw_pll_state(dev);
989247dc10d7SGordon Ross
989347dc10d7SGordon Ross for (i = 0; i < dev_priv->num_shared_dpll; i++) {
989447dc10d7SGordon Ross struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
989547dc10d7SGordon Ross
989647dc10d7SGordon Ross pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
989747dc10d7SGordon Ross pll->active = 0;
989847dc10d7SGordon Ross list_for_each_entry(crtc, struct intel_crtc, &dev->mode_config.crtc_list,
989947dc10d7SGordon Ross base.head) {
990047dc10d7SGordon Ross if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
990147dc10d7SGordon Ross pll->active++;
990247dc10d7SGordon Ross }
990347dc10d7SGordon Ross pll->refcount = pll->active;
990447dc10d7SGordon Ross
990547dc10d7SGordon Ross DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
990647dc10d7SGordon Ross pll->name, pll->refcount, pll->on);
990747dc10d7SGordon Ross }
990847dc10d7SGordon Ross
990947dc10d7SGordon Ross list_for_each_entry(encoder, struct intel_encoder, &dev->mode_config.encoder_list,
991047dc10d7SGordon Ross base.head) {
991147dc10d7SGordon Ross pipe = 0;
991247dc10d7SGordon Ross
991347dc10d7SGordon Ross if (encoder->get_hw_state(encoder, &pipe)) {
991447dc10d7SGordon Ross crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
991547dc10d7SGordon Ross encoder->base.crtc = &crtc->base;
991647dc10d7SGordon Ross if (encoder->get_config)
991747dc10d7SGordon Ross encoder->get_config(encoder, &crtc->config);
991847dc10d7SGordon Ross } else {
991947dc10d7SGordon Ross encoder->base.crtc = NULL;
992047dc10d7SGordon Ross }
992147dc10d7SGordon Ross
992247dc10d7SGordon Ross encoder->connectors_active = false;
992347dc10d7SGordon Ross DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
992447dc10d7SGordon Ross encoder->base.base.id,
992547dc10d7SGordon Ross drm_get_encoder_name(&encoder->base),
992647dc10d7SGordon Ross encoder->base.crtc ? "enabled" : "disabled",
992747dc10d7SGordon Ross pipe);
992847dc10d7SGordon Ross }
992947dc10d7SGordon Ross
993047dc10d7SGordon Ross list_for_each_entry(connector, struct intel_connector, &dev->mode_config.connector_list,
993147dc10d7SGordon Ross base.head) {
993247dc10d7SGordon Ross if (connector->get_hw_state(connector)) {
993347dc10d7SGordon Ross connector->base.dpms = DRM_MODE_DPMS_ON;
993447dc10d7SGordon Ross connector->encoder->connectors_active = true;
993547dc10d7SGordon Ross connector->base.encoder = &connector->encoder->base;
993647dc10d7SGordon Ross } else {
993747dc10d7SGordon Ross connector->base.dpms = DRM_MODE_DPMS_OFF;
993847dc10d7SGordon Ross connector->base.encoder = NULL;
993947dc10d7SGordon Ross }
994047dc10d7SGordon Ross DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
994147dc10d7SGordon Ross connector->base.base.id,
994247dc10d7SGordon Ross drm_get_connector_name(&connector->base),
994347dc10d7SGordon Ross connector->base.encoder ? "enabled" : "disabled");
994447dc10d7SGordon Ross }
994547dc10d7SGordon Ross }
994647dc10d7SGordon Ross
994747dc10d7SGordon Ross /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
994847dc10d7SGordon Ross * and i915 state tracking structures. */
intel_modeset_setup_hw_state(struct drm_device * dev,bool force_restore)994947dc10d7SGordon Ross void intel_modeset_setup_hw_state(struct drm_device *dev,
995047dc10d7SGordon Ross bool force_restore)
995147dc10d7SGordon Ross {
995247dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
995347dc10d7SGordon Ross enum pipe pipe;
995447dc10d7SGordon Ross struct drm_plane *plane;
995547dc10d7SGordon Ross struct intel_crtc *crtc;
995647dc10d7SGordon Ross struct intel_encoder *encoder;
995747dc10d7SGordon Ross int i;
995847dc10d7SGordon Ross
995947dc10d7SGordon Ross intel_modeset_readout_hw_state(dev);
996047dc10d7SGordon Ross
996147dc10d7SGordon Ross /* HW state is read out, now we need to sanitize this mess. */
996247dc10d7SGordon Ross list_for_each_entry(encoder, struct intel_encoder, &dev->mode_config.encoder_list,
996347dc10d7SGordon Ross base.head) {
996447dc10d7SGordon Ross intel_sanitize_encoder(encoder);
996547dc10d7SGordon Ross }
996647dc10d7SGordon Ross
996747dc10d7SGordon Ross for_each_pipe(pipe) {
996847dc10d7SGordon Ross crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
996947dc10d7SGordon Ross intel_sanitize_crtc(crtc);
997047dc10d7SGordon Ross intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
997147dc10d7SGordon Ross }
997247dc10d7SGordon Ross
997347dc10d7SGordon Ross for (i = 0; i < dev_priv->num_shared_dpll; i++) {
997447dc10d7SGordon Ross struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
997547dc10d7SGordon Ross
997647dc10d7SGordon Ross if (!pll->on || pll->active)
997747dc10d7SGordon Ross continue;
997847dc10d7SGordon Ross
997947dc10d7SGordon Ross DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
998047dc10d7SGordon Ross
998147dc10d7SGordon Ross pll->disable(dev_priv, pll);
998247dc10d7SGordon Ross pll->on = false;
998347dc10d7SGordon Ross }
998447dc10d7SGordon Ross
998547dc10d7SGordon Ross if (force_restore) {
998647dc10d7SGordon Ross /*
998747dc10d7SGordon Ross * We need to use raw interfaces for restoring state to avoid
998847dc10d7SGordon Ross * checking (bogus) intermediate states.
998947dc10d7SGordon Ross */
999047dc10d7SGordon Ross for_each_pipe(pipe) {
999147dc10d7SGordon Ross struct drm_crtc *crtc =
999247dc10d7SGordon Ross dev_priv->pipe_to_crtc_mapping[pipe];
999347dc10d7SGordon Ross
999447dc10d7SGordon Ross __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
999547dc10d7SGordon Ross crtc->fb);
999647dc10d7SGordon Ross }
999747dc10d7SGordon Ross list_for_each_entry(plane, struct drm_plane, &dev->mode_config.plane_list, head)
999847dc10d7SGordon Ross intel_plane_restore(plane);
999947dc10d7SGordon Ross
1000047dc10d7SGordon Ross i915_redisable_vga(dev);
1000147dc10d7SGordon Ross } else {
1000247dc10d7SGordon Ross intel_modeset_update_staged_output_state(dev);
1000347dc10d7SGordon Ross }
1000447dc10d7SGordon Ross
1000547dc10d7SGordon Ross intel_modeset_check_state(dev);
1000647dc10d7SGordon Ross
1000747dc10d7SGordon Ross drm_mode_config_reset(dev);
1000847dc10d7SGordon Ross }
1000947dc10d7SGordon Ross
intel_modeset_gem_init(struct drm_device * dev)1001047dc10d7SGordon Ross void intel_modeset_gem_init(struct drm_device *dev)
1001147dc10d7SGordon Ross {
1001247dc10d7SGordon Ross intel_modeset_init_hw(dev);
1001347dc10d7SGordon Ross
1001447dc10d7SGordon Ross intel_setup_overlay(dev);
1001547dc10d7SGordon Ross
1001647dc10d7SGordon Ross intel_modeset_setup_hw_state(dev, false);
1001747dc10d7SGordon Ross }
1001847dc10d7SGordon Ross
intel_modeset_cleanup(struct drm_device * dev)1001947dc10d7SGordon Ross void intel_modeset_cleanup(struct drm_device *dev)
1002047dc10d7SGordon Ross {
1002147dc10d7SGordon Ross struct drm_i915_private *dev_priv = dev->dev_private;
1002247dc10d7SGordon Ross struct drm_crtc *crtc;
1002347dc10d7SGordon Ross /* LINTED */
1002447dc10d7SGordon Ross struct intel_crtc *intel_crtc;
1002547dc10d7SGordon Ross
1002647dc10d7SGordon Ross /*
1002747dc10d7SGordon Ross * Interrupts and polling as the first thing to avoid creating havoc.
1002847dc10d7SGordon Ross * Too much stuff here (turning of rps, connectors, ...) would
1002947dc10d7SGordon Ross * experience fancy races otherwise.
1003047dc10d7SGordon Ross */
1003147dc10d7SGordon Ross drm_irq_uninstall(dev);
1003247dc10d7SGordon Ross /* OSOL_I915 cancel_work_sync(&dev_priv->hotplug_work); */
1003347dc10d7SGordon Ross cancel_delayed_work(dev_priv->wq);
1003447dc10d7SGordon Ross /*
1003547dc10d7SGordon Ross * Due to the hpd irq storm handling the hotplug work can re-arm the
1003647dc10d7SGordon Ross * poll handlers. Hence disable polling after hpd handling is shut down.
1003747dc10d7SGordon Ross */
1003847dc10d7SGordon Ross drm_kms_helper_poll_fini(dev);
1003947dc10d7SGordon Ross mutex_lock(&dev->struct_mutex);
1004047dc10d7SGordon Ross
1004147dc10d7SGordon Ross list_for_each_entry(crtc, struct drm_crtc, &dev->mode_config.crtc_list, head) {
1004247dc10d7SGordon Ross /* Skip inactive CRTCs */
1004347dc10d7SGordon Ross if (!crtc->fb)
1004447dc10d7SGordon Ross continue;
1004547dc10d7SGordon Ross
1004647dc10d7SGordon Ross intel_crtc = to_intel_crtc(crtc);
1004747dc10d7SGordon Ross intel_increase_pllclock(crtc);
1004847dc10d7SGordon Ross }
1004947dc10d7SGordon Ross
1005047dc10d7SGordon Ross intel_disable_fbc(dev);
1005147dc10d7SGordon Ross
1005247dc10d7SGordon Ross intel_disable_gt_powersave(dev);
1005347dc10d7SGordon Ross
1005447dc10d7SGordon Ross ironlake_teardown_rc6(dev);
1005547dc10d7SGordon Ross
1005647dc10d7SGordon Ross mutex_unlock(&dev->struct_mutex);
1005747dc10d7SGordon Ross
1005847dc10d7SGordon Ross /* flush any delayed tasks or pending work */
1005947dc10d7SGordon Ross /* OSOL_I915 flush_scheduled_work(); */
1006047dc10d7SGordon Ross
1006147dc10d7SGordon Ross /* destroy backlight, if any, before the connectors */
1006247dc10d7SGordon Ross intel_panel_destroy_backlight(dev);
1006347dc10d7SGordon Ross
1006447dc10d7SGordon Ross drm_mode_config_cleanup(dev);
1006547dc10d7SGordon Ross
1006647dc10d7SGordon Ross intel_cleanup_overlay(dev);
1006747dc10d7SGordon Ross }
1006847dc10d7SGordon Ross
1006947dc10d7SGordon Ross
1007047dc10d7SGordon Ross /* current intel driver doesn't take advantage of encoders
1007147dc10d7SGordon Ross always give back the encoder for the connector
1007247dc10d7SGordon Ross */
intel_best_encoder(struct drm_connector * connector)1007347dc10d7SGordon Ross struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
1007447dc10d7SGordon Ross {
1007547dc10d7SGordon Ross return &intel_attached_encoder(connector)->base;
1007647dc10d7SGordon Ross }
1007747dc10d7SGordon Ross
intel_connector_attach_encoder(struct intel_connector * connector,struct intel_encoder * encoder)1007847dc10d7SGordon Ross void intel_connector_attach_encoder(struct intel_connector *connector,
1007947dc10d7SGordon Ross struct intel_encoder *encoder)
1008047dc10d7SGordon Ross {
1008147dc10d7SGordon Ross connector->encoder = encoder;
1008247dc10d7SGordon Ross (void) drm_mode_connector_attach_encoder(&connector->base,
1008347dc10d7SGordon Ross &encoder->base);
1008447dc10d7SGordon Ross }
1008547dc10d7SGordon Ross
1008647dc10d7SGordon Ross /*
1008747dc10d7SGordon Ross * set vga decode state - true == enable VGA decode
1008847dc10d7SGordon Ross */
intel_modeset_vga_set_state(struct drm_device * dev,bool state)1008947dc10d7SGordon Ross int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
1009047dc10d7SGordon Ross {
1009147dc10d7SGordon Ross u16 gmch_ctrl;
1009247dc10d7SGordon Ross
1009347dc10d7SGordon Ross pci_read_config_word(dev->pdev, INTEL_GMCH_CTRL, &gmch_ctrl);
1009447dc10d7SGordon Ross if (state)
1009547dc10d7SGordon Ross gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
1009647dc10d7SGordon Ross else
1009747dc10d7SGordon Ross gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
1009847dc10d7SGordon Ross pci_write_config_word(dev->pdev, INTEL_GMCH_CTRL, gmch_ctrl);
1009947dc10d7SGordon Ross return 0;
1010047dc10d7SGordon Ross }
1010147dc10d7SGordon Ross
1010247dc10d7SGordon Ross #ifdef CONFIG_DEBUG_FS
1010347dc10d7SGordon Ross #include <linux/seq_file.h>
1010447dc10d7SGordon Ross
1010547dc10d7SGordon Ross struct intel_display_error_state {
1010647dc10d7SGordon Ross
1010747dc10d7SGordon Ross u32 power_well_driver;
1010847dc10d7SGordon Ross
1010947dc10d7SGordon Ross int num_transcoders;
1011047dc10d7SGordon Ross
1011147dc10d7SGordon Ross struct intel_cursor_error_state {
1011247dc10d7SGordon Ross u32 control;
1011347dc10d7SGordon Ross u32 position;
1011447dc10d7SGordon Ross u32 base;
1011547dc10d7SGordon Ross u32 size;
1011647dc10d7SGordon Ross } cursor[I915_MAX_PIPES];
1011747dc10d7SGordon Ross
1011847dc10d7SGordon Ross struct intel_pipe_error_state {
1011947dc10d7SGordon Ross u32 source;
1012047dc10d7SGordon Ross } pipe[I915_MAX_PIPES];
1012147dc10d7SGordon Ross
1012247dc10d7SGordon Ross struct intel_plane_error_state {
1012347dc10d7SGordon Ross u32 control;
1012447dc10d7SGordon Ross u32 stride;
1012547dc10d7SGordon Ross u32 size;
1012647dc10d7SGordon Ross u32 pos;
1012747dc10d7SGordon Ross u32 addr;
1012847dc10d7SGordon Ross u32 surface;
1012947dc10d7SGordon Ross u32 tile_offset;
1013047dc10d7SGordon Ross } plane[I915_MAX_PIPES];
1013147dc10d7SGordon Ross
1013247dc10d7SGordon Ross struct intel_transcoder_error_state {
1013347dc10d7SGordon Ross enum transcoder cpu_transcoder;
1013447dc10d7SGordon Ross
1013547dc10d7SGordon Ross u32 conf;
1013647dc10d7SGordon Ross
1013747dc10d7SGordon Ross u32 htotal;
1013847dc10d7SGordon Ross u32 hblank;
1013947dc10d7SGordon Ross u32 hsync;
1014047dc10d7SGordon Ross u32 vtotal;
1014147dc10d7SGordon Ross u32 vblank;
1014247dc10d7SGordon Ross u32 vsync;
1014347dc10d7SGordon Ross } transcoder[4];
1014447dc10d7SGordon Ross
1014547dc10d7SGordon Ross };
1014647dc10d7SGordon Ross
1014747dc10d7SGordon Ross struct intel_display_error_state *
intel_display_capture_error_state(struct drm_device * dev)1014847dc10d7SGordon Ross intel_display_capture_error_state(struct drm_device *dev)
1014947dc10d7SGordon Ross {
1015047dc10d7SGordon Ross drm_i915_private_t *dev_priv = dev->dev_private;
1015147dc10d7SGordon Ross struct intel_display_error_state *error;
1015247dc10d7SGordon Ross int transcoders[4] = {
1015347dc10d7SGordon Ross TRANSCODER_A,
1015447dc10d7SGordon Ross TRANSCODER_B,
1015547dc10d7SGordon Ross TRANSCODER_C,
1015647dc10d7SGordon Ross TRANSCODER_EDP,
1015747dc10d7SGordon Ross };
1015847dc10d7SGordon Ross int i;
1015947dc10d7SGordon Ross
1016047dc10d7SGordon Ross if (INTEL_INFO(dev)->num_pipes == 0)
1016147dc10d7SGordon Ross return NULL;
1016247dc10d7SGordon Ross
1016347dc10d7SGordon Ross error = kmalloc(sizeof(*error), GFP_ATOMIC);
1016447dc10d7SGordon Ross if (error == NULL)
1016547dc10d7SGordon Ross return NULL;
1016647dc10d7SGordon Ross
1016747dc10d7SGordon Ross if (HAS_POWER_WELL(dev))
1016847dc10d7SGordon Ross error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
1016947dc10d7SGordon Ross
1017047dc10d7SGordon Ross for_each_pipe(i) {
1017147dc10d7SGordon Ross
1017247dc10d7SGordon Ross if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
1017347dc10d7SGordon Ross error->cursor[i].control = I915_READ(CURCNTR(i));
1017447dc10d7SGordon Ross error->cursor[i].position = I915_READ(CURPOS(i));
1017547dc10d7SGordon Ross error->cursor[i].base = I915_READ(CURBASE(i));
1017647dc10d7SGordon Ross } else {
1017747dc10d7SGordon Ross error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
1017847dc10d7SGordon Ross error->cursor[i].position = I915_READ(CURPOS_IVB(i));
1017947dc10d7SGordon Ross error->cursor[i].base = I915_READ(CURBASE_IVB(i));
1018047dc10d7SGordon Ross }
1018147dc10d7SGordon Ross
1018247dc10d7SGordon Ross error->plane[i].control = I915_READ(DSPCNTR(i));
1018347dc10d7SGordon Ross error->plane[i].stride = I915_READ(DSPSTRIDE(i));
1018447dc10d7SGordon Ross if (INTEL_INFO(dev)->gen <= 3) {
1018547dc10d7SGordon Ross error->plane[i].size = I915_READ(DSPSIZE(i));
1018647dc10d7SGordon Ross error->plane[i].pos = I915_READ(DSPPOS(i));
1018747dc10d7SGordon Ross }
1018847dc10d7SGordon Ross if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
1018947dc10d7SGordon Ross error->plane[i].addr = I915_READ(DSPADDR(i));
1019047dc10d7SGordon Ross if (INTEL_INFO(dev)->gen >= 4) {
1019147dc10d7SGordon Ross error->plane[i].surface = I915_READ(DSPSURF(i));
1019247dc10d7SGordon Ross error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
1019347dc10d7SGordon Ross }
1019447dc10d7SGordon Ross
1019547dc10d7SGordon Ross error->pipe[i].source = I915_READ(PIPESRC(i));
1019647dc10d7SGordon Ross }
1019747dc10d7SGordon Ross error->num_transcoders = INTEL_INFO(dev)->num_pipes;
1019847dc10d7SGordon Ross if (HAS_DDI(dev_priv->dev))
1019947dc10d7SGordon Ross error->num_transcoders++; /* Account for eDP. */
1020047dc10d7SGordon Ross
1020147dc10d7SGordon Ross for (i = 0; i < error->num_transcoders; i++) {
1020247dc10d7SGordon Ross enum transcoder cpu_transcoder = transcoders[i];
1020347dc10d7SGordon Ross
1020447dc10d7SGordon Ross error->transcoder[i].cpu_transcoder = cpu_transcoder;
1020547dc10d7SGordon Ross
1020647dc10d7SGordon Ross error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
1020747dc10d7SGordon Ross error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
1020847dc10d7SGordon Ross error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
1020947dc10d7SGordon Ross error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
1021047dc10d7SGordon Ross error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
1021147dc10d7SGordon Ross error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
1021247dc10d7SGordon Ross error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
1021347dc10d7SGordon Ross }
1021447dc10d7SGordon Ross
1021547dc10d7SGordon Ross /* In the code above we read the registers without checking if the power
1021647dc10d7SGordon Ross * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
1021747dc10d7SGordon Ross * prevent the next I915_WRITE from detecting it and printing an error
1021847dc10d7SGordon Ross * message. */
1021947dc10d7SGordon Ross if (HAS_POWER_WELL(dev))
1022047dc10d7SGordon Ross I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
1022147dc10d7SGordon Ross
1022247dc10d7SGordon Ross return error;
1022347dc10d7SGordon Ross }
1022447dc10d7SGordon Ross
1022547dc10d7SGordon Ross #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
1022647dc10d7SGordon Ross
1022747dc10d7SGordon Ross void
intel_display_print_error_state(struct drm_i915_error_state_buf * m,struct drm_device * dev,struct intel_display_error_state * error)1022847dc10d7SGordon Ross intel_display_print_error_state(struct drm_i915_error_state_buf *m,
1022947dc10d7SGordon Ross struct drm_device *dev,
1023047dc10d7SGordon Ross struct intel_display_error_state *error)
1023147dc10d7SGordon Ross {
1023247dc10d7SGordon Ross int i;
1023347dc10d7SGordon Ross
1023447dc10d7SGordon Ross if (!error)
1023547dc10d7SGordon Ross return;
1023647dc10d7SGordon Ross
1023747dc10d7SGordon Ross err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
1023847dc10d7SGordon Ross if (HAS_POWER_WELL(dev))
1023947dc10d7SGordon Ross err_printf(m, "PWR_WELL_CTL2: %08x\n",
1024047dc10d7SGordon Ross error->power_well_driver);
1024147dc10d7SGordon Ross for_each_pipe(i) {
1024247dc10d7SGordon Ross err_printf(m, "Pipe [%d]:\n", i);
1024347dc10d7SGordon Ross err_printf(m, " CONF: %08x\n", error->pipe[i].conf);
1024447dc10d7SGordon Ross
1024547dc10d7SGordon Ross err_printf(m, "Plane [%d]:\n", i);
1024647dc10d7SGordon Ross err_printf(m, " CNTR: %08x\n", error->plane[i].control);
1024747dc10d7SGordon Ross err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
1024847dc10d7SGordon Ross if (INTEL_INFO(dev)->gen <= 3) {
1024947dc10d7SGordon Ross err_printf(m, " SIZE: %08x\n", error->plane[i].size);
1025047dc10d7SGordon Ross err_printf(m, " POS: %08x\n", error->plane[i].pos);
1025147dc10d7SGordon Ross }
1025247dc10d7SGordon Ross if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
1025347dc10d7SGordon Ross err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
1025447dc10d7SGordon Ross if (INTEL_INFO(dev)->gen >= 4) {
1025547dc10d7SGordon Ross err_printf(m, " SURF: %08x\n", error->plane[i].surface);
1025647dc10d7SGordon Ross err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
1025747dc10d7SGordon Ross }
1025847dc10d7SGordon Ross
1025947dc10d7SGordon Ross err_printf(m, "Cursor [%d]:\n", i);
1026047dc10d7SGordon Ross err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
1026147dc10d7SGordon Ross err_printf(m, " POS: %08x\n", error->cursor[i].position);
1026247dc10d7SGordon Ross err_printf(m, " BASE: %08x\n", error->cursor[i].base);
1026347dc10d7SGordon Ross }
1026447dc10d7SGordon Ross
1026547dc10d7SGordon Ross for (i = 0; i < error->num_transcoders; i++) {
1026647dc10d7SGordon Ross err_printf(m, " CPU transcoder: %c\n",
1026747dc10d7SGordon Ross transcoder_name(error->transcoder[i].cpu_transcoder));
1026847dc10d7SGordon Ross err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
1026947dc10d7SGordon Ross err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
1027047dc10d7SGordon Ross err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
1027147dc10d7SGordon Ross err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
1027247dc10d7SGordon Ross err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
1027347dc10d7SGordon Ross err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
1027447dc10d7SGordon Ross err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
1027547dc10d7SGordon Ross + }
1027647dc10d7SGordon Ross }
1027747dc10d7SGordon Ross #endif
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