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Searched refs:PCH_PP_CONTROL (Results 1 – 5 of 5) sorted by relevance

/gfx-drm/usr/src/uts/intel/io/i915/
H A Dintel_dp.c236 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL; in ironlake_edp_have_panel_vdd()
251 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL; in intel_dp_check_edp()
925 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL; in ironlake_wait_panel_status()
969 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL; in ironlake_get_pp_control()
1005 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL; in ironlake_edp_panel_vdd_on()
1104 I915_WRITE(PCH_PP_CONTROL, pp); in ironlake_edp_panel_on()
1105 POSTING_READ(PCH_PP_CONTROL); in ironlake_edp_panel_on()
1112 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL; in ironlake_edp_panel_on()
1121 I915_WRITE(PCH_PP_CONTROL, pp); in ironlake_edp_panel_on()
1122 POSTING_READ(PCH_PP_CONTROL); in ironlake_edp_panel_on()
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H A Dintel_lvds.c199 ctl_reg = PCH_PP_CONTROL; in intel_enable_lvds()
224 ctl_reg = PCH_PP_CONTROL; in intel_disable_lvds()
1085 I915_WRITE(PCH_PP_CONTROL, in intel_lvds_init()
1086 I915_READ(PCH_PP_CONTROL) | PANEL_UNLOCK_REGS); in intel_lvds_init()
H A Di915_suspend.c215 dev_priv->regfile.savePP_CONTROL = I915_READ(PCH_PP_CONTROL); in i915_save_display()
307 I915_WRITE(PCH_PP_CONTROL, dev_priv->regfile.savePP_CONTROL); in i915_restore_display()
H A Di915_reg.h4414 #define PCH_PP_CONTROL 0xc7204 macro
H A Dintel_display.c1029 pp_reg = PCH_PP_CONTROL; in assert_panel_unlocked()