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Searched refs:I915_READ (Results 1 – 25 of 30) sorted by relevance

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/gfx-drm/usr/src/uts/intel/io/i915/
H A Di915_ums.c48 return (I915_READ(dpll_reg) & DPLL_VCO_ENABLE); in i915_pipe_enabled()
70 array[i] = I915_READ(reg + (i << 2)); in i915_save_palette()
123 dev_priv->regfile.saveFPA0 = I915_READ(_FPA0); in i915_save_display_reg()
124 dev_priv->regfile.saveFPA1 = I915_READ(_FPA1); in i915_save_display_reg()
180 dev_priv->regfile.saveFPB0 = I915_READ(_FPB0); in i915_save_display_reg()
256 dev_priv->regfile.saveADPA = I915_READ(ADPA); in i915_save_display_reg()
260 dev_priv->regfile.saveDP_B = I915_READ(DP_B); in i915_save_display_reg()
261 dev_priv->regfile.saveDP_C = I915_READ(DP_C); in i915_save_display_reg()
262 dev_priv->regfile.saveDP_D = I915_READ(DP_D); in i915_save_display_reg()
408 I915_WRITE(_DSPAADDR, I915_READ(_DSPAADDR)); in i915_restore_display_reg()
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H A Di915_suspend.c78 dev_priv->regfile.saveVGA0 = I915_READ(VGA0); in i915_save_vga()
79 dev_priv->regfile.saveVGA1 = I915_READ(VGA1); in i915_save_vga()
80 dev_priv->regfile.saveVGA_PD = I915_READ(VGA_PD); in i915_save_vga()
204 dev_priv->regfile.saveDSPARB = I915_READ(DSPARB); in i915_save_display()
230 dev_priv->regfile.saveLVDS = I915_READ(LVDS); in i915_save_display()
357 dev_priv->regfile.saveDEIER = I915_READ(DEIER); in i915_save_state()
358 dev_priv->regfile.saveDEIMR = I915_READ(DEIMR); in i915_save_state()
359 dev_priv->regfile.saveGTIER = I915_READ(GTIER); in i915_save_state()
364 I915_READ(RSTDBYCTL); in i915_save_state()
367 dev_priv->regfile.saveIER = I915_READ(IER); in i915_save_state()
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H A Di915_irq.c417 return I915_READ(reg); in gm45_get_vblank_counter()
929 iir = I915_READ(VLV_IIR); in valleyview_irq_handler()
1155 de_ier = I915_READ(DEIER); in ivybridge_irq_handler()
1854 error->ier = I915_READ(DEIER) | I915_READ(GTIER); in i915_capture_error_state()
1856 error->ier = I915_READ(GTIER) | I915_READ(VLV_IER); in i915_capture_error_state()
1962 u32 eir = I915_READ(EIR); in i915_report_and_clear_eir()
2058 eir = I915_READ(EIR); in i915_report_and_clear_eir()
2218 imr = I915_READ(VLV_IMR); in valleyview_enable_vblank()
2280 imr = I915_READ(VLV_IMR); in valleyview_disable_vblank()
3170 iir = I915_READ(IIR); in i915_irq_handler()
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H A Di915_gem_debug.c923 I915_READ(0x22064)); in register_dump()
925 I915_READ(0x22068)); in register_dump()
927 I915_READ(0x2206C)); in register_dump()
929 I915_READ(0x22074)); in register_dump()
932 I915_READ(IPEIR_I965)); in register_dump()
938 I915_READ(INSTPS)); in register_dump()
940 I915_READ(INSTDONE1)); in register_dump()
944 I915_READ(0x2078)); in register_dump()
947 I915_READ(0x04094)); in register_dump()
949 I915_READ(0x04194)); in register_dump()
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H A Dintel_sideband.c42 if (wait_for((I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) == 0, 5)) { in vlv_sideband_rw()
53 if (wait_for((I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) == 0, 5)) { in vlv_sideband_rw()
60 *val = I915_READ(VLV_IOSF_DATA); in vlv_sideband_rw()
127 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0, in intel_sbi_read()
141 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0, in intel_sbi_read()
147 return I915_READ(SBI_DATA); in intel_sbi_read()
157 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0, in intel_sbi_write()
172 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0, in intel_sbi_write()
H A Dintel_pm.c624 tmp = I915_READ(CLKCFG); in i915_pineview_get_mem_freq()
654 tmp = I915_READ(CSHRDDR3CTL); in i915_pineview_get_mem_freq()
1118 reg = I915_READ(DSPFW1); in pineview_update_wm()
1128 reg = I915_READ(DSPFW3); in pineview_update_wm()
1137 reg = I915_READ(DSPFW3); in pineview_update_wm()
1146 reg = I915_READ(DSPFW3); in pineview_update_wm()
2577 val = I915_READ(WM_MISC); in hsw_write_wm_values()
2767 val = I915_READ(reg); in sandybridge_update_sprite_wm()
2992 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) + in ironlake_enable_drps()
2993 I915_READ(0x112e0); in ironlake_enable_drps()
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H A Dintel_crt.c77 tmp = I915_READ(crt->adpa_reg); in intel_crt_get_hw_state()
97 tmp = I915_READ(crt->adpa_reg); in intel_crt_get_config()
121 temp = I915_READ(crt->adpa_reg); in intel_crt_set_dpms()
320 adpa = I915_READ(crt->adpa_reg); in intel_ironlake_crt_detect_hotplug()
353 adpa = I915_READ(crt->adpa_reg); in valleyview_crt_detect_hotplug()
411 stat = I915_READ(PORT_HOTPLUG_STAT); in intel_crt_detect_hotplug()
522 save_bclrpat = I915_READ(bclrpat_reg); in intel_crt_load_detect()
523 save_vtotal = I915_READ(vtotal_reg); in intel_crt_load_detect()
524 vblank = I915_READ(vblank_reg); in intel_crt_load_detect()
557 uint32_t vsync = I915_READ(vsync_reg); in intel_crt_load_detect()
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H A Dintel_ddi.c236 temp = I915_READ(_FDI_RXA_MISC); in hsw_fdi_link_train()
277 temp = I915_READ(_FDI_RXA_MISC); in hsw_fdi_link_train()
376 val = I915_READ(SPLL_CTL); in intel_ddi_put_crtc_pll()
386 val = I915_READ(WRPLL_CTL1); in intel_ddi_put_crtc_pll()
396 val = I915_READ(WRPLL_CTL2); in intel_ddi_put_crtc_pll()
854 uint32_t val = I915_READ(reg); in intel_ddi_disable_transcoder_func()
1083 val = I915_READ(DP_TP_CTL(port)); in intel_ddi_post_disable()
1246 val = I915_READ(_FDI_RXA_CTL); in intel_ddi_fdi_disable()
1250 val = I915_READ(_FDI_RXA_MISC); in intel_ddi_fdi_disable()
1255 val = I915_READ(_FDI_RXA_CTL); in intel_ddi_fdi_disable()
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H A Dintel_display.c899 val = I915_READ(reg); in assert_pll()
961 val = I915_READ(reg); in assert_fdi_tx()
979 val = I915_READ(reg); in assert_fdi_rx()
1003 val = I915_READ(reg); in assert_fdi_tx_pll_enabled()
1015 val = I915_READ(reg); in assert_fdi_rx_pll_enabled()
1084 val = I915_READ(reg); in assert_plane()
1179 val = I915_READ(reg); in assert_pch_transcoder_disabled()
1288 val = I915_READ(reg); in assert_pch_ports_disabled()
1294 val = I915_READ(reg); in assert_pch_ports_disabled()
1332 val = I915_READ(reg); in intel_enable_pll()
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H A Dintel_ringbuffer.h54 #define I915_READ_TAIL(ring) I915_READ(RING_TAIL((ring)->mmio_base))
57 #define I915_READ_START(ring) I915_READ(RING_START((ring)->mmio_base))
60 #define I915_READ_HEAD(ring) I915_READ(RING_HEAD((ring)->mmio_base))
63 #define I915_READ_CTL(ring) I915_READ(RING_CTL((ring)->mmio_base))
66 #define I915_READ_IMR(ring) I915_READ(RING_IMR((ring)->mmio_base))
69 #define I915_READ_NOPID(ring) I915_READ(RING_NOPID((ring)->mmio_base))
70 #define I915_READ_SYNC_0(ring) I915_READ(RING_SYNC_0((ring)->mmio_base))
71 #define I915_READ_SYNC_1(ring) I915_READ(RING_SYNC_1((ring)->mmio_base))
H A Dintel_sprite.c56 sprctl = I915_READ(SPCNTR(pipe, plane)); in vlv_update_plane()
175 sprctl = I915_READ(SPCNTR(pipe, plane)); in vlv_update_colorkey()
197 key->min_value = I915_READ(SPKEYMINVAL(pipe, plane)); in vlv_get_colorkey()
198 key->max_value = I915_READ(SPKEYMAXVAL(pipe, plane)); in vlv_get_colorkey()
201 sprctl = I915_READ(SPCNTR(pipe, plane)); in vlv_get_colorkey()
224 sprctl = I915_READ(SPRCTL(pipe)); in ivb_update_plane()
361 sprctl = I915_READ(SPRCTL(intel_plane->pipe)); in ivb_update_colorkey()
389 sprctl = I915_READ(SPRCTL(intel_plane->pipe)); in ivb_get_colorkey()
414 dvscntr = I915_READ(DVSCNTR(pipe)); in ilk_update_plane()
550 dvscntr = I915_READ(DVSCNTR(intel_plane->pipe)); in ilk_update_colorkey()
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H A Dintel_lvds.c76 tmp = I915_READ(lvds_encoder->reg); in intel_lvds_get_hw_state()
101 tmp = I915_READ(lvds_reg); in intel_lvds_get_config()
115 tmp = I915_READ(PFIT_CONTROL); in intel_lvds_get_config()
136 temp = I915_READ(lvds_encoder->reg); in intel_pre_pll_enable_lvds()
210 if (wait_for((I915_READ(stat_reg) & PP_ON) != 0, 1000)) in intel_enable_lvds()
234 if (wait_for((I915_READ(stat_reg) & PP_ON) == 0, 1000)) in intel_disable_lvds()
854 val = I915_READ(lvds_encoder->reg); in compute_is_dual_link_lvds()
914 if ((I915_READ(PCH_LVDS) & LVDS_DETECTED) == 0) in intel_lvds_init()
1057 lvds = I915_READ(LVDS); in intel_lvds_init()
1086 I915_READ(PCH_PP_CONTROL) | PANEL_UNLOCK_REGS); in intel_lvds_init()
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H A Dintel_panel.c323 return I915_READ(BLC_PWM_CTL2) & BLM_COMBINATION_MODE; in is_backlight_combination_mode()
326 return I915_READ(BLC_PWM_CTL) & BLM_LEGACY_MODE; in is_backlight_combination_mode()
339 val = I915_READ(BLC_PWM_PCH_CTL2); in i915_read_blc_pwm_ctl()
347 val = I915_READ(BLC_PWM_CTL); in i915_read_blc_pwm_ctl()
352 I915_READ(BLC_PWM_CTL2); in i915_read_blc_pwm_ctl()
416 val = I915_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK; in intel_panel_get_backlight()
469 tmp = I915_READ(BLC_PWM_CTL); in intel_panel_actually_set_backlight()
533 I915_WRITE(reg, I915_READ(reg) & ~BLM_PWM_ENABLE); in intel_panel_disable_backlight()
536 tmp = I915_READ(BLC_PWM_PCH_CTL1); in intel_panel_disable_backlight()
568 tmp = I915_READ(reg); in intel_panel_enable_backlight()
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H A Dintel_dvo.c133 tmp = I915_READ(intel_dvo->dev.dvo_reg); in intel_dvo_get_hw_state()
150 tmp = I915_READ(intel_dvo->dev.dvo_reg); in intel_dvo_get_config()
168 u32 temp = I915_READ(dvo_reg); in intel_disable_dvo()
172 I915_READ(dvo_reg); in intel_disable_dvo()
180 u32 temp = I915_READ(dvo_reg); in intel_enable_dvo()
183 I915_READ(dvo_reg); in intel_enable_dvo()
308 dvo_val = I915_READ(dvo_reg) & in intel_dvo_mode_set()
321 I915_WRITE(dpll_reg, I915_READ(dpll_reg) | DPLL_DVO_HIGH_SPEED); in intel_dvo_mode_set()
424 uint32_t dvo_val = I915_READ(intel_dvo->dev.dvo_reg); in intel_dvo_get_current_mode()
H A Dintel_dp.c197 clkcfg = I915_READ(CLKCFG); in intel_hrawclk()
256 I915_READ(pp_stat_reg), in intel_dp_check_edp()
257 I915_READ(pp_ctrl_reg)); in intel_dp_check_edp()
348 I915_READ(ch_ctl)); in intel_dp_aux_ch()
804 dpa_ctl = I915_READ(DP_A); in ironlake_set_pll_cpu_edp()
929 I915_READ(pp_stat_reg), in ironlake_wait_panel_status()
930 I915_READ(pp_ctrl_reg)); in ironlake_wait_panel_status()
934 I915_READ(pp_stat_reg), in ironlake_wait_panel_status()
1010 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); in ironlake_edp_panel_vdd_on()
1042 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); in ironlake_panel_vdd_off_sync()
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H A Dintel_hdmi.c147 u32 val = I915_READ(VIDEO_DIP_CTL); in g4x_write_infoframe()
188 u32 val = I915_READ(reg); in ibx_write_infoframe()
228 u32 val = I915_READ(reg); in cpt_write_infoframe()
271 u32 val = I915_READ(reg); in vlv_write_infoframe()
312 u32 val = I915_READ(ctl_reg); in hsw_write_infoframe()
392 u32 val = I915_READ(reg); in g4x_set_infoframes()
457 u32 val = I915_READ(reg); in ibx_set_infoframes()
517 u32 val = I915_READ(reg); in cpt_set_infoframes()
552 u32 val = I915_READ(reg); in vlv_set_infoframes()
586 u32 val = I915_READ(reg); in hsw_set_infoframes()
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H A Dintel_overlay.c282 tmp = I915_READ(DOVSTA); in intel_overlay_continue()
852 ratio = I915_READ(PFIT_AUTO_RATIOS); in update_pfit_vscale_ratio()
854 ratio = I915_READ(PFIT_PGM_RATIOS); in update_pfit_vscale_ratio()
1252 attrs->gamma0 = I915_READ(OGAMC0); in intel_overlay_attrs()
1253 attrs->gamma1 = I915_READ(OGAMC1); in intel_overlay_attrs()
1254 attrs->gamma2 = I915_READ(OGAMC2); in intel_overlay_attrs()
1255 attrs->gamma3 = I915_READ(OGAMC3); in intel_overlay_attrs()
1256 attrs->gamma4 = I915_READ(OGAMC4); in intel_overlay_attrs()
1257 attrs->gamma5 = I915_READ(OGAMC5); in intel_overlay_attrs()
1460 error->dovsta = I915_READ(DOVSTA); in intel_overlay_capture_error_state()
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H A Dintel_tv.c849 u32 tmp = I915_READ(TV_CTL); in intel_tv_get_hw_state()
955 tv_ctl = I915_READ(TV_CTL); in intel_tv_mode_set()
1096 int pipeconf = I915_READ(pipeconf_reg); in intel_tv_mode_set()
1097 int dspcntr = I915_READ(dspcntr_reg); in intel_tv_mode_set()
1143 I915_WRITE(TV_DAC, I915_READ(TV_DAC) & TV_DAC_SAVE); in intel_tv_mode_set()
1195 save_tv_dac = tv_dac = I915_READ(TV_DAC); in intel_tv_detect_type()
1196 save_tv_ctl = tv_ctl = I915_READ(TV_CTL); in intel_tv_detect_type()
1233 tv_dac = I915_READ(TV_DAC); in intel_tv_detect_type()
1584 save_tv_dac = I915_READ(TV_DAC); in intel_tv_init()
1587 tv_dac_on = I915_READ(TV_DAC); in intel_tv_init()
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H A Ddvo_ns2501.c109 ns->dvoc = I915_READ(DVO_C); in enable_dvo()
110 ns->pll_a = I915_READ(_DPLL_A); in enable_dvo()
111 ns->srcdim = I915_READ(DVOC_SRCDIM); in enable_dvo()
112 ns->fw_blc = I915_READ(FW_BLC); in enable_dvo()
H A Di915_gem_tiling.c103 dimm_c0 = I915_READ(MAD_DIMM_C0); in i915_gem_detect_bit_6_swizzle()
104 dimm_c1 = I915_READ(MAD_DIMM_C1); in i915_gem_detect_bit_6_swizzle()
142 dcc = I915_READ(DCC); in i915_gem_detect_bit_6_swizzle()
H A Di915_gem_gtt.c246 ecobits = I915_READ(GAC_ECO_BITS); in gen6_ppgtt_enable()
250 gab_ctl = I915_READ(GAB_CTL); in gen6_ppgtt_enable()
253 ecochk = I915_READ(GAM_ECOCHK); in gen6_ppgtt_enable()
260 ecobits = I915_READ(GAC_ECO_BITS); in gen6_ppgtt_enable()
263 ecochk = I915_READ(GAM_ECOCHK); in gen6_ppgtt_enable()
999 pgetbl_ctl2 = I915_READ(I965_PGETBL_CTL2); in i965_adjust_pgetbl_size()
1004 pgetbl_ctl = I915_READ(I810_PGETBL_CTL); in i965_adjust_pgetbl_size()
1037 pgetbl_ctl = I915_READ(I810_PGETBL_CTL); in i965_gtt_total_entries()
H A Di915_drv.c648 I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830); in i8xx_do_reset()
665 I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830); in i8xx_do_reset()
711 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR); in ironlake_do_reset()
715 ret = wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500); in ironlake_do_reset()
720 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR); in ironlake_do_reset()
724 return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500); in ironlake_do_reset()
1441 reg->val = I915_READ(reg->offset); in i915_reg_read_ioctl()
H A Dintel_i2c.c80 val = I915_READ(DSPCLK_GATE_D); in intel_i2c_quirk_set()
251 ret = wait_for((gmbus2 = I915_READ(GMBUS2 + reg_offset)) in gmbus_wait_hw_status()
315 val = I915_READ(GMBUS3 + reg_offset); in gmbus_xfer_read()
H A Dintel_sdvo.c247 I915_READ(intel_sdvo->sdvo_reg); in intel_sdvo_write_sdvox()
252 cval = I915_READ(GEN3_SDVOC); in intel_sdvo_write_sdvox()
254 bval = I915_READ(GEN3_SDVOB); in intel_sdvo_write_sdvox()
264 I915_READ(GEN3_SDVOB); in intel_sdvo_write_sdvox()
266 I915_READ(GEN3_SDVOC); in intel_sdvo_write_sdvox()
1237 sdvox = I915_READ(intel_sdvo->sdvo_reg); in intel_sdvo_mode_set()
1298 tmp = I915_READ(intel_sdvo->sdvo_reg); in intel_sdvo_get_hw_state()
1352 sdvox = I915_READ(intel_sdvo->sdvo_reg); in intel_sdvo_get_config()
1391 temp = I915_READ(intel_sdvo->sdvo_reg); in intel_disable_sdvo()
1432 temp = I915_READ(intel_sdvo->sdvo_reg); in intel_enable_sdvo()
H A Di915_gem_context.c118 reg = I915_READ(CXT_SIZE); in get_context_size()
122 reg = I915_READ(GEN7_CXT_SIZE); in get_context_size()

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