Searched refs:DR_RW_MASK (Results 1 – 2 of 2) sorted by relevance
| /illumos-gate/usr/src/cmd/mdb/intel/mdb/ |
| H A D | mdb_bhyve.c | 626 { "0:W", DR_RW(0, DR_RW_MASK), DR_RW(0, DR_RW_WRITE) }, in bhyve_dbgregs_dcmd()
627 { "0:IO", DR_RW(0, DR_RW_MASK), DR_RW(0, DR_RW_IO_RW) }, in bhyve_dbgregs_dcmd()
628 { "0:RW", DR_RW(0, DR_RW_MASK), DR_RW(0, DR_RW_READ) }, in bhyve_dbgregs_dcmd()
630 { "1:W", DR_RW(1, DR_RW_MASK), DR_RW(1, DR_RW_WRITE) }, in bhyve_dbgregs_dcmd()
631 { "1:IO", DR_RW(1, DR_RW_MASK), DR_RW(1, DR_RW_IO_RW) }, in bhyve_dbgregs_dcmd()
632 { "1:RW", DR_RW(1, DR_RW_MASK), DR_RW(1, DR_RW_READ) }, in bhyve_dbgregs_dcmd()
634 { "2:W", DR_RW(2, DR_RW_MASK), DR_RW(2, DR_RW_WRITE) }, in bhyve_dbgregs_dcmd()
635 { "2:IO", DR_RW(2, DR_RW_MASK), DR_RW(2, DR_RW_IO_RW) }, in bhyve_dbgregs_dcmd()
636 { "2:RW", DR_RW(2, DR_RW_MASK), DR_RW(2, DR_RW_READ) }, in bhyve_dbgregs_dcmd()
638 { "3:W", DR_RW(3, DR_RW_MASK), DR_RW(3, DR_RW_WRITE) }, in bhyve_dbgregs_dcmd()
[all …]
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| /illumos-gate/usr/src/uts/intel/sys/ |
| H A D | debugreg.h | 95 #define DR_RW_MASK 0x3 /* Two bits specify r/w access */ macro
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