17c478bd9Sstevel@tonic-gate /* 27c478bd9Sstevel@tonic-gate * CDDL HEADER START 37c478bd9Sstevel@tonic-gate * 47c478bd9Sstevel@tonic-gate * The contents of this file are subject to the terms of the 57c478bd9Sstevel@tonic-gate * Common Development and Distribution License, Version 1.0 only 67c478bd9Sstevel@tonic-gate * (the "License"). You may not use this file except in compliance 77c478bd9Sstevel@tonic-gate * with the License. 87c478bd9Sstevel@tonic-gate * 97c478bd9Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 107c478bd9Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 117c478bd9Sstevel@tonic-gate * See the License for the specific language governing permissions 127c478bd9Sstevel@tonic-gate * and limitations under the License. 137c478bd9Sstevel@tonic-gate * 147c478bd9Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 157c478bd9Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 167c478bd9Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 177c478bd9Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 187c478bd9Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 197c478bd9Sstevel@tonic-gate * 207c478bd9Sstevel@tonic-gate * CDDL HEADER END 217c478bd9Sstevel@tonic-gate */ 227c478bd9Sstevel@tonic-gate /* 237c478bd9Sstevel@tonic-gate * Copyright (c) 1999 by Sun Microsystems, Inc. 247c478bd9Sstevel@tonic-gate * All rights reserved. 257c478bd9Sstevel@tonic-gate */ 267c478bd9Sstevel@tonic-gate /* Copyright (c) 1990, 1991 UNIX System Laboratories, Inc. */ 277c478bd9Sstevel@tonic-gate /* Copyright (c) 1984, 1986, 1987, 1988, 1989, 1990 AT&T */ 28b4203d75SMarcel Telka /* All Rights Reserved */ 29*9c3024a3SHans Rosenfeld /* 30*9c3024a3SHans Rosenfeld * Copyright (c) 2018, Joyent, Inc. All rights reserved. 31*9c3024a3SHans Rosenfeld */ 327c478bd9Sstevel@tonic-gate 337c478bd9Sstevel@tonic-gate #ifndef _SYS_DEBUGREG_H 347c478bd9Sstevel@tonic-gate #define _SYS_DEBUGREG_H 357c478bd9Sstevel@tonic-gate 367c478bd9Sstevel@tonic-gate #ifdef __cplusplus 377c478bd9Sstevel@tonic-gate extern "C" { 387c478bd9Sstevel@tonic-gate #endif 397c478bd9Sstevel@tonic-gate 407c478bd9Sstevel@tonic-gate /* 417c478bd9Sstevel@tonic-gate * Specify masks for accessing the i386 debug registers. 427c478bd9Sstevel@tonic-gate */ 437c478bd9Sstevel@tonic-gate 447c478bd9Sstevel@tonic-gate /* 457c478bd9Sstevel@tonic-gate * The debug registers are found in an array (debugreg) in the u block. 467c478bd9Sstevel@tonic-gate * On the i386, there are 4 registers to specify linear addresses. 477c478bd9Sstevel@tonic-gate * dr4 and dr5 are reserved. 487c478bd9Sstevel@tonic-gate */ 497c478bd9Sstevel@tonic-gate #define DR_FIRSTADDR 0 /* u.u_debugreg[DR_FIRSTADDR] */ 507c478bd9Sstevel@tonic-gate #define DR_LASTADDR 3 /* u.u_debugreg[DR_LASTADDR] */ 517c478bd9Sstevel@tonic-gate 527c478bd9Sstevel@tonic-gate /* 537c478bd9Sstevel@tonic-gate * The debug status is found in dr6 after a debug trap. 547c478bd9Sstevel@tonic-gate */ 557c478bd9Sstevel@tonic-gate #define DR_STATUS 6 /* u.u_debugreg[DR_STATUS] */ 567c478bd9Sstevel@tonic-gate #define DR_TRAP0 0x1 /* Trap from debug register #0 */ 577c478bd9Sstevel@tonic-gate #define DR_TRAP1 0x2 /* Trap from debug register #1 */ 587c478bd9Sstevel@tonic-gate #define DR_TRAP2 0x4 /* Trap from debug register #2 */ 597c478bd9Sstevel@tonic-gate #define DR_TRAP3 0x8 /* Trap from debug register #3 */ 607c478bd9Sstevel@tonic-gate #define DR_ICEALSO 0x2000 /* Flag bit reserved for in-circuit-emulator */ 617c478bd9Sstevel@tonic-gate #define DR_SINGLESTEP 0x4000 /* Trap resulting from the single-step flag */ 627c478bd9Sstevel@tonic-gate #define DR_TASKSWITCH 0x8000 /* Trap resulting from a task-switch */ 63*9c3024a3SHans Rosenfeld #define DR_IN_RTM 0x10000 /* Trap inside an RTM region */ 647c478bd9Sstevel@tonic-gate 657c478bd9Sstevel@tonic-gate /* 667c478bd9Sstevel@tonic-gate * dr7 controls the rest of the debug registers. 677c478bd9Sstevel@tonic-gate * use shifts and masks because arrays of fields tend to get aligned. 687c478bd9Sstevel@tonic-gate * For example, 697c478bd9Sstevel@tonic-gate * dr7 & DR_LOCAL_ENABLE_MASK 707c478bd9Sstevel@tonic-gate * dr7 >> (DR_LOCAL_ENABLE_SHIFT + r# * DR_ENABLE_SIZE) & 0x1 717c478bd9Sstevel@tonic-gate * dr7 >> (DR_CONTROL_SHIFT + r# * DR_CONTROL_SIZE) & DR_RW_MASK 727c478bd9Sstevel@tonic-gate * Note that the GLOBAL bits below and always turned off by the kernel. 737c478bd9Sstevel@tonic-gate */ 747c478bd9Sstevel@tonic-gate #define DR_CONTROL 7 /* u.u_debugreg[DR_CONTROL] */ 757c478bd9Sstevel@tonic-gate #define DR_LOCAL_ENABLE_MASK 0x55 /* Enable all 4 regs for ldt addrs */ 767c478bd9Sstevel@tonic-gate #define DR_GLOBAL_ENABLE_MASK 0xAA /* Enable all 4 regs for gdt addrs */ 777c478bd9Sstevel@tonic-gate #define DR_CONTROL_RESERVED 0xFC00 /* Bits reserved by Intel */ 787c478bd9Sstevel@tonic-gate #define DR_LOCAL_SLOWDOWN 0x100 /* Slow the pipeline for ldt addrs */ 797c478bd9Sstevel@tonic-gate #define DR_GLOBAL_SLOWDOWN 0x200 /* Slow the pipeline for gdt addrs */ 80*9c3024a3SHans Rosenfeld #define DR_RTM 0x800 /* Restricted Transactional Memory */ 81*9c3024a3SHans Rosenfeld #define DR_GENERAL_DETECT 0x2000 /* General Detect Enable */ 827c478bd9Sstevel@tonic-gate 837c478bd9Sstevel@tonic-gate #define DR_LOCAL_ENABLE_SHIFT 0 /* Additional shift: local enable */ 847c478bd9Sstevel@tonic-gate #define DR_GLOBAL_ENABLE_SHIFT 1 /* Additional shift: global enable */ 857c478bd9Sstevel@tonic-gate #define DR_ENABLE_SIZE 2 /* 2 enable bits per register */ 867c478bd9Sstevel@tonic-gate 877c478bd9Sstevel@tonic-gate #define DR_TRAPS (DR_TRAP0|DR_TRAP1|DR_TRAP2|DR_TRAP3) 887c478bd9Sstevel@tonic-gate #define DR_ENABLE0 0x03 /* Local or Global enable of trap 0 */ 897c478bd9Sstevel@tonic-gate #define DR_ENABLE1 0x0C /* Local or Global enable of trap 1 */ 907c478bd9Sstevel@tonic-gate #define DR_ENABLE2 0x30 /* Local or Global enable of trap 2 */ 917c478bd9Sstevel@tonic-gate #define DR_ENABLE3 0xC0 /* Local or Global enable of trap 3 */ 927c478bd9Sstevel@tonic-gate 937c478bd9Sstevel@tonic-gate #define DR_CONTROL_SHIFT 16 /* Shift to register control bits */ 947c478bd9Sstevel@tonic-gate #define DR_CONTROL_SIZE 4 /* 4 control bits per register */ 957c478bd9Sstevel@tonic-gate #define DR_RW_MASK 0x3 /* Two bits specify r/w access */ 967c478bd9Sstevel@tonic-gate #define DR_RW_EXECUTE 0x0 /* Settings for the read/write mask */ 977c478bd9Sstevel@tonic-gate #define DR_RW_WRITE 0x1 987c478bd9Sstevel@tonic-gate #define DR_RW_IO_RW 0x2 /* I/O space on Pentium and beyond */ 997c478bd9Sstevel@tonic-gate #define DR_RW_READ 0x3 1007c478bd9Sstevel@tonic-gate #define DR_LEN_MASK 0xC /* Two bits specify data length */ 1017c478bd9Sstevel@tonic-gate #define DR_LEN_1 0x0 /* Settings for data length */ 1027c478bd9Sstevel@tonic-gate #define DR_LEN_2 0x4 1037c478bd9Sstevel@tonic-gate #define DR_LEN_4 0xC 104*9c3024a3SHans Rosenfeld #define DR_LEN_8 0x8 1057c478bd9Sstevel@tonic-gate 1067c478bd9Sstevel@tonic-gate #ifdef __cplusplus 1077c478bd9Sstevel@tonic-gate } 1087c478bd9Sstevel@tonic-gate #endif 1097c478bd9Sstevel@tonic-gate 1107c478bd9Sstevel@tonic-gate #endif /* _SYS_DEBUGREG_H */ 111