17c478bd9Sstevel@tonic-gate/* 27c478bd9Sstevel@tonic-gate * CDDL HEADER START 37c478bd9Sstevel@tonic-gate * 47c478bd9Sstevel@tonic-gate * The contents of this file are subject to the terms of the 51ae08745Sheppo * Common Development and Distribution License (the "License"). 61ae08745Sheppo * You may not use this file except in compliance with the License. 77c478bd9Sstevel@tonic-gate * 87c478bd9Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 97c478bd9Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 107c478bd9Sstevel@tonic-gate * See the License for the specific language governing permissions 117c478bd9Sstevel@tonic-gate * and limitations under the License. 127c478bd9Sstevel@tonic-gate * 137c478bd9Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 147c478bd9Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 157c478bd9Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 167c478bd9Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 177c478bd9Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 187c478bd9Sstevel@tonic-gate * 197c478bd9Sstevel@tonic-gate * CDDL HEADER END 207c478bd9Sstevel@tonic-gate */ 217c478bd9Sstevel@tonic-gate/* 22bd28a477SPrashanth Sreenivasa * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved. 237c478bd9Sstevel@tonic-gate */ 247c478bd9Sstevel@tonic-gate 257c478bd9Sstevel@tonic-gate/* 267c478bd9Sstevel@tonic-gate * General machine architecture & implementation specific 277c478bd9Sstevel@tonic-gate * assembly language routines. 287c478bd9Sstevel@tonic-gate */ 297c478bd9Sstevel@tonic-gate#include "assym.h" 307c478bd9Sstevel@tonic-gate 31bd28a477SPrashanth Sreenivasa#define CPU_MODULE /* need it for NSEC_SHIFT used by NATIVE_TIME_TO_NSEC() */ 32bd28a477SPrashanth Sreenivasa 337c478bd9Sstevel@tonic-gate#include <sys/asm_linkage.h> 347c478bd9Sstevel@tonic-gate#include <sys/machsystm.h> 357c478bd9Sstevel@tonic-gate#include <sys/machthread.h> 36023e71deSHaik Aftandilian#include <sys/machclock.h> 377c478bd9Sstevel@tonic-gate#include <sys/privregs.h> 387c478bd9Sstevel@tonic-gate#include <sys/cmpregs.h> 397c478bd9Sstevel@tonic-gate#include <sys/clock.h> 407c478bd9Sstevel@tonic-gate#include <sys/fpras.h> 413b890a5bSjb#include <sys/soft_state.h> 427c478bd9Sstevel@tonic-gate 43023e71deSHaik Aftandilian/* 44023e71deSHaik Aftandilian * This isn't the routine you're looking for. 45023e71deSHaik Aftandilian * 46023e71deSHaik Aftandilian * The routine simply returns the value of %tick on the *current* processor. 47023e71deSHaik Aftandilian * Most of the time, gettick() [which in turn maps to %stick on platforms 48023e71deSHaik Aftandilian * that have different CPU %tick rates] is what you want. 49023e71deSHaik Aftandilian */ 50023e71deSHaik Aftandilian 51023e71deSHaik Aftandilian ENTRY(ultra_gettick) 52023e71deSHaik Aftandilian RD_TICK(%o0,%o1,%o2,__LINE__) 53023e71deSHaik Aftandilian retl 54023e71deSHaik Aftandilian nop 55023e71deSHaik Aftandilian SET_SIZE(ultra_gettick) 56023e71deSHaik Aftandilian 577c478bd9Sstevel@tonic-gate ENTRY(set_mmfsa_scratchpad) 58*55fea89dSDan Cross stxa %o0, [%g0]ASI_SCRATCHPAD 597c478bd9Sstevel@tonic-gate retl 607c478bd9Sstevel@tonic-gate nop 617c478bd9Sstevel@tonic-gate SET_SIZE(set_mmfsa_scratchpad) 627c478bd9Sstevel@tonic-gate 637c478bd9Sstevel@tonic-gate ENTRY(get_mmfsa_scratchpad) 64*55fea89dSDan Cross ldxa [%g0]ASI_SCRATCHPAD, %o0 657c478bd9Sstevel@tonic-gate retl 667c478bd9Sstevel@tonic-gate nop 677c478bd9Sstevel@tonic-gate SET_SIZE(get_mmfsa_scratchpad) 681ae08745Sheppo 691ae08745Sheppo 701ae08745Sheppo 711ae08745Sheppo/* 721ae08745Sheppo * Called from a x-trap at tl1 must use %g1 as arg 731ae08745Sheppo * and save/restore %o0-%o5 after hypervisor calls 741ae08745Sheppo */ 751ae08745Sheppo 761ae08745Sheppo ENTRY(cpu_intrq_unregister_powerdown) 771ae08745Sheppo 781ae08745Sheppo CPU_ADDR(%g2, %g3) 79*55fea89dSDan Cross add %g2, CPU_MCPU, %g2 801ae08745Sheppo /* 811ae08745Sheppo * Save %o regs 821ae08745Sheppo */ 831ae08745Sheppo mov %o0, %g3 841ae08745Sheppo mov %o1, %g4 851ae08745Sheppo mov %o2, %g5 861ae08745Sheppo mov %o5, %g6 871ae08745Sheppo 881ae08745Sheppo ldx [%g2 + MCPU_CPU_Q_BASE], %o1 891ae08745Sheppo mov INTR_CPU_Q, %o0 901ae08745Sheppo call hv_cpu_qconf 911ae08745Sheppo mov %g0, %o2 921ae08745Sheppo 931ae08745Sheppo ldx [%g2 + MCPU_DEV_Q_BASE], %o1 941ae08745Sheppo mov INTR_DEV_Q, %o0 951ae08745Sheppo call hv_cpu_qconf 961ae08745Sheppo mov %g0, %o2 971ae08745Sheppo 981ae08745Sheppo ldx [%g2 + MCPU_RQ_BASE], %o1 991ae08745Sheppo mov CPU_RQ, %o0 1001ae08745Sheppo call hv_cpu_qconf 1011ae08745Sheppo mov %g0, %o2 1021ae08745Sheppo 1031ae08745Sheppo ldx [%g2 + MCPU_NRQ_BASE], %o1 1041ae08745Sheppo mov CPU_NRQ, %o0 1051ae08745Sheppo call hv_cpu_qconf 1061ae08745Sheppo mov %g0, %o2 1071ae08745Sheppo 1081ae08745Sheppo /* 1091ae08745Sheppo * set done flag to 0 1101ae08745Sheppo */ 1111ae08745Sheppo stub %g0, [%g1] 1121ae08745Sheppo 1131ae08745Sheppo /* 1141ae08745Sheppo * Restore %o regs 1151ae08745Sheppo */ 1161ae08745Sheppo mov %g3, %o0 1171ae08745Sheppo mov %g4, %o1 1181ae08745Sheppo mov %g5, %o2 1191ae08745Sheppo mov %g6, %o5 1201ae08745Sheppo 1211ae08745Sheppo /* 1221ae08745Sheppo * This CPU is on its way out. Spin here 1231ae08745Sheppo * until the DR unconfigure code stops it. 1241ae08745Sheppo * Returning would put it back in the OS 1251ae08745Sheppo * where it might grab resources like locks, 1261ae08745Sheppo * causing some nastiness to occur. 1271ae08745Sheppo */ 1281ae08745Sheppo0: 1291ae08745Sheppo ba,a 0b 1301ae08745Sheppo 1311ae08745Sheppo SET_SIZE(cpu_intrq_unregister_powerdown) 1321ae08745Sheppo 1337c478bd9Sstevel@tonic-gate 1347c478bd9Sstevel@tonic-gate/* 1357c478bd9Sstevel@tonic-gate * Get the processor ID. 1367c478bd9Sstevel@tonic-gate * === MID reg as specified in 15dec89 sun4u spec, sec 5.4.3 1377c478bd9Sstevel@tonic-gate */ 1387c478bd9Sstevel@tonic-gate 1397c478bd9Sstevel@tonic-gate ENTRY(getprocessorid) 1407c478bd9Sstevel@tonic-gate CPU_INDEX(%o0, %o1) 1417c478bd9Sstevel@tonic-gate retl 1427c478bd9Sstevel@tonic-gate nop 1437c478bd9Sstevel@tonic-gate SET_SIZE(getprocessorid) 1447c478bd9Sstevel@tonic-gate 1457c478bd9Sstevel@tonic-gate ENTRY_NP(tick2ns) 1467c478bd9Sstevel@tonic-gate ! 147bd28a477SPrashanth Sreenivasa ! Use nsec_scale for sun4v which is based on %stick 1487c478bd9Sstevel@tonic-gate ! 149bd28a477SPrashanth Sreenivasa NATIVE_TIME_TO_NSEC(%o0, %o2, %o3) 1507c478bd9Sstevel@tonic-gate retl 1517c478bd9Sstevel@tonic-gate nop 1527c478bd9Sstevel@tonic-gate SET_SIZE(tick2ns) 1537c478bd9Sstevel@tonic-gate 1547c478bd9Sstevel@tonic-gate ENTRY(set_cmp_error_steering) 1557c478bd9Sstevel@tonic-gate retl 1567c478bd9Sstevel@tonic-gate nop 1577c478bd9Sstevel@tonic-gate SET_SIZE(set_cmp_error_steering) 1587c478bd9Sstevel@tonic-gate 1597c478bd9Sstevel@tonic-gate ENTRY(ultra_getver) 1607c478bd9Sstevel@tonic-gate retl 1617c478bd9Sstevel@tonic-gate mov -1, %o0 ! XXXQ no version available 1627c478bd9Sstevel@tonic-gate SET_SIZE(ultra_getver) 1637c478bd9Sstevel@tonic-gate 1647c478bd9Sstevel@tonic-gate /* 1657c478bd9Sstevel@tonic-gate * Check instructions using just the AX pipelines, designed by 1667c478bd9Sstevel@tonic-gate * C.B. Liaw of PNP. 1677c478bd9Sstevel@tonic-gate * 1687c478bd9Sstevel@tonic-gate * This function must match a struct fpras_chkfn and must be 1697c478bd9Sstevel@tonic-gate * block aligned. A zero return means all was well. These 1707c478bd9Sstevel@tonic-gate * instructions are chosen to be sensitive to bit corruptions 1717c478bd9Sstevel@tonic-gate * on the fpras rewrite, so if a bit corruption still produces 1727c478bd9Sstevel@tonic-gate * a valid instruction we should still get an incorrect result 1737c478bd9Sstevel@tonic-gate * here. This function is never called directly - it is copied 1747c478bd9Sstevel@tonic-gate * into per-cpu and per-operation buffers; it must therefore 1757c478bd9Sstevel@tonic-gate * be absolutely position independent. If an illegal instruction 1767c478bd9Sstevel@tonic-gate * is encountered then the trap handler trampolines to the final 1777c478bd9Sstevel@tonic-gate * three instructions of this function. 1787c478bd9Sstevel@tonic-gate * 1797c478bd9Sstevel@tonic-gate * We want two instructions that are complements of one another, 1807c478bd9Sstevel@tonic-gate * and which can perform a calculation with a known result. 1817c478bd9Sstevel@tonic-gate * 1827c478bd9Sstevel@tonic-gate * SETHI: 1837c478bd9Sstevel@tonic-gate * 1847c478bd9Sstevel@tonic-gate * | 0 0 | rd | 1 0 0 | imm22 | 1857c478bd9Sstevel@tonic-gate * 31 30 29 25 24 22 21 0 1867c478bd9Sstevel@tonic-gate * 1877c478bd9Sstevel@tonic-gate * ADDCCC with two source registers: 1887c478bd9Sstevel@tonic-gate * 1897c478bd9Sstevel@tonic-gate * | 1 0 | rd | 0 1 1 0 0 0 | rs1 | 0 | - | rs2 | 1907c478bd9Sstevel@tonic-gate * 31 30 29 25 24 19 18 14 13 12 5 4 0 1917c478bd9Sstevel@tonic-gate * 1927c478bd9Sstevel@tonic-gate * We can choose rd and imm2 of the SETHI and rd, rs1 and rs2 of 1937c478bd9Sstevel@tonic-gate * the ADDCCC to obtain instructions that are complements in all but 1947c478bd9Sstevel@tonic-gate * bit 30. 1957c478bd9Sstevel@tonic-gate * 1967c478bd9Sstevel@tonic-gate * Registers are numbered as follows: 1977c478bd9Sstevel@tonic-gate * 1987c478bd9Sstevel@tonic-gate * r[31] %i7 1997c478bd9Sstevel@tonic-gate * r[30] %i6 2007c478bd9Sstevel@tonic-gate * r[29] %i5 2017c478bd9Sstevel@tonic-gate * r[28] %i4 2027c478bd9Sstevel@tonic-gate * r[27] %i3 2037c478bd9Sstevel@tonic-gate * r[26] %i2 2047c478bd9Sstevel@tonic-gate * r[25] %i1 2057c478bd9Sstevel@tonic-gate * r[24] %i0 2067c478bd9Sstevel@tonic-gate * r[23] %l7 2077c478bd9Sstevel@tonic-gate * r[22] %l6 2087c478bd9Sstevel@tonic-gate * r[21] %l5 2097c478bd9Sstevel@tonic-gate * r[20] %l4 2107c478bd9Sstevel@tonic-gate * r[19] %l3 2117c478bd9Sstevel@tonic-gate * r[18] %l2 2127c478bd9Sstevel@tonic-gate * r[17] %l1 2137c478bd9Sstevel@tonic-gate * r[16] %l0 2147c478bd9Sstevel@tonic-gate * r[15] %o7 2157c478bd9Sstevel@tonic-gate * r[14] %o6 2167c478bd9Sstevel@tonic-gate * r[13] %o5 2177c478bd9Sstevel@tonic-gate * r[12] %o4 2187c478bd9Sstevel@tonic-gate * r[11] %o3 2197c478bd9Sstevel@tonic-gate * r[10] %o2 2207c478bd9Sstevel@tonic-gate * r[9] %o1 221*55fea89dSDan Cross * r[8] %o0 2227c478bd9Sstevel@tonic-gate * r[7] %g7 2237c478bd9Sstevel@tonic-gate * r[6] %g6 2247c478bd9Sstevel@tonic-gate * r[5] %g5 2257c478bd9Sstevel@tonic-gate * r[4] %g4 2267c478bd9Sstevel@tonic-gate * r[3] %g3 2277c478bd9Sstevel@tonic-gate * r[2] %g2 2287c478bd9Sstevel@tonic-gate * r[1] %g1 2297c478bd9Sstevel@tonic-gate * r[0] %g0 2307c478bd9Sstevel@tonic-gate * 2317c478bd9Sstevel@tonic-gate * For register r[n], register r[31-n] is the complement. We must 2327c478bd9Sstevel@tonic-gate * avoid use of %i6/%i7 and %o6/%o7 as well as %g7. Clearly we need 2337c478bd9Sstevel@tonic-gate * to use a local or input register as one half of the pair, which 2347c478bd9Sstevel@tonic-gate * requires us to obtain our own register window or take steps 2357c478bd9Sstevel@tonic-gate * to preserve any local or input we choose to use. We choose 2367c478bd9Sstevel@tonic-gate * %o1 as rd for the SETHI, so rd of the ADDCCC must be %l6. 2377c478bd9Sstevel@tonic-gate * We'll use %o1 as rs1 and %l6 as rs2 of the ADDCCC, which then 2387c478bd9Sstevel@tonic-gate * requires that imm22 be 0b111 10110 1 11111111 01001 or 0x3dbfe9, 2397c478bd9Sstevel@tonic-gate * or %hi(0xf6ffa400). This determines the value of the constant 2407c478bd9Sstevel@tonic-gate * CBV2 below. 2417c478bd9Sstevel@tonic-gate * 2427c478bd9Sstevel@tonic-gate * The constant CBV1 is chosen such that an initial subcc %g0, CBV1 2437c478bd9Sstevel@tonic-gate * will set the carry bit and every addccc thereafter will continue 2447c478bd9Sstevel@tonic-gate * to generate a carry. Other values are possible for CBV1 - this 2457c478bd9Sstevel@tonic-gate * is just one that works this way. 2467c478bd9Sstevel@tonic-gate * 2477c478bd9Sstevel@tonic-gate * Finally CBV3 is the expected answer when we perform our repeated 2487c478bd9Sstevel@tonic-gate * calculations on CBV1 and CBV2 - it is not otherwise specially 2497c478bd9Sstevel@tonic-gate * derived. If this result is not obtained then a corruption has 2507c478bd9Sstevel@tonic-gate * occured during the FPRAS_REWRITE of one of the two blocks of 2517c478bd9Sstevel@tonic-gate * 16 instructions. A corruption could also result in an illegal 2527c478bd9Sstevel@tonic-gate * instruction or other unexpected trap - we catch illegal 2537c478bd9Sstevel@tonic-gate * instruction traps in the PC range and trampoline to the 2547c478bd9Sstevel@tonic-gate * last instructions of the function to return a failure indication. 2557c478bd9Sstevel@tonic-gate * 2567c478bd9Sstevel@tonic-gate */ 2577c478bd9Sstevel@tonic-gate 2587c478bd9Sstevel@tonic-gate#define CBV1 0xc11 2597c478bd9Sstevel@tonic-gate#define CBV2 0xf6ffa400 2607c478bd9Sstevel@tonic-gate#define CBV3 0x66f9d800 2617c478bd9Sstevel@tonic-gate#define CBR1 %o1 2627c478bd9Sstevel@tonic-gate#define CBR2 %l6 2637c478bd9Sstevel@tonic-gate#define CBO2 %o2 2647c478bd9Sstevel@tonic-gate#define SETHI_CBV2_CBR1 sethi %hi(CBV2), CBR1 2657c478bd9Sstevel@tonic-gate#define ADDCCC_CBR1_CBR2_CBR2 addccc CBR1, CBR2, CBR2 2667c478bd9Sstevel@tonic-gate 2677c478bd9Sstevel@tonic-gate .align 64 2687c478bd9Sstevel@tonic-gate ENTRY_NP(fpras_chkfn_type1) 2697c478bd9Sstevel@tonic-gate mov CBR2, CBO2 ! 1, preserve CBR2 of (callers) window 2707c478bd9Sstevel@tonic-gate mov FPRAS_OK, %o0 ! 2, default return value 2717c478bd9Sstevel@tonic-gate ba,pt %icc, 1f ! 3 2727c478bd9Sstevel@tonic-gate subcc %g0, CBV1, CBR2 ! 4 2737c478bd9Sstevel@tonic-gate ! 5 - 16 2747c478bd9Sstevel@tonic-gate .align 64 2757c478bd9Sstevel@tonic-gate1: SETHI_CBV2_CBR1 ! 1 2767c478bd9Sstevel@tonic-gate ADDCCC_CBR1_CBR2_CBR2 ! 2 2777c478bd9Sstevel@tonic-gate SETHI_CBV2_CBR1 ! 3 2787c478bd9Sstevel@tonic-gate ADDCCC_CBR1_CBR2_CBR2 ! 4 2797c478bd9Sstevel@tonic-gate SETHI_CBV2_CBR1 ! 5 2807c478bd9Sstevel@tonic-gate ADDCCC_CBR1_CBR2_CBR2 ! 6 2817c478bd9Sstevel@tonic-gate SETHI_CBV2_CBR1 ! 7 2827c478bd9Sstevel@tonic-gate ADDCCC_CBR1_CBR2_CBR2 ! 8 2837c478bd9Sstevel@tonic-gate SETHI_CBV2_CBR1 ! 9 2847c478bd9Sstevel@tonic-gate ADDCCC_CBR1_CBR2_CBR2 ! 10 2857c478bd9Sstevel@tonic-gate SETHI_CBV2_CBR1 ! 11 2867c478bd9Sstevel@tonic-gate ADDCCC_CBR1_CBR2_CBR2 ! 12 2877c478bd9Sstevel@tonic-gate SETHI_CBV2_CBR1 ! 13 2887c478bd9Sstevel@tonic-gate ADDCCC_CBR1_CBR2_CBR2 ! 14 2897c478bd9Sstevel@tonic-gate SETHI_CBV2_CBR1 ! 15 2907c478bd9Sstevel@tonic-gate ADDCCC_CBR1_CBR2_CBR2 ! 16 2917c478bd9Sstevel@tonic-gate 2927c478bd9Sstevel@tonic-gate ADDCCC_CBR1_CBR2_CBR2 ! 1 2937c478bd9Sstevel@tonic-gate SETHI_CBV2_CBR1 ! 2 2947c478bd9Sstevel@tonic-gate ADDCCC_CBR1_CBR2_CBR2 ! 3 2957c478bd9Sstevel@tonic-gate SETHI_CBV2_CBR1 ! 4 2967c478bd9Sstevel@tonic-gate ADDCCC_CBR1_CBR2_CBR2 ! 5 2977c478bd9Sstevel@tonic-gate SETHI_CBV2_CBR1 ! 6 2987c478bd9Sstevel@tonic-gate ADDCCC_CBR1_CBR2_CBR2 ! 7 2997c478bd9Sstevel@tonic-gate SETHI_CBV2_CBR1 ! 8 3007c478bd9Sstevel@tonic-gate ADDCCC_CBR1_CBR2_CBR2 ! 9 3017c478bd9Sstevel@tonic-gate SETHI_CBV2_CBR1 ! 10 3027c478bd9Sstevel@tonic-gate ADDCCC_CBR1_CBR2_CBR2 ! 11 3037c478bd9Sstevel@tonic-gate SETHI_CBV2_CBR1 ! 12 3047c478bd9Sstevel@tonic-gate ADDCCC_CBR1_CBR2_CBR2 ! 13 3057c478bd9Sstevel@tonic-gate SETHI_CBV2_CBR1 ! 14 3067c478bd9Sstevel@tonic-gate ADDCCC_CBR1_CBR2_CBR2 ! 15 3077c478bd9Sstevel@tonic-gate SETHI_CBV2_CBR1 ! 16 3087c478bd9Sstevel@tonic-gate 3097c478bd9Sstevel@tonic-gate addc CBR1, CBR2, CBR2 ! 1 3107c478bd9Sstevel@tonic-gate sethi %hi(CBV3), CBR1 ! 2 3117c478bd9Sstevel@tonic-gate cmp CBR1, CBR2 ! 3 3127c478bd9Sstevel@tonic-gate movnz %icc, FPRAS_BADCALC, %o0! 4, how detected 3137c478bd9Sstevel@tonic-gate retl ! 5 3147c478bd9Sstevel@tonic-gate mov CBO2, CBR2 ! 6, restore borrowed register 3157c478bd9Sstevel@tonic-gate .skip 4*(13-7+1) ! 7 - 13 3167c478bd9Sstevel@tonic-gate ! 3177c478bd9Sstevel@tonic-gate ! illegal instr'n trap comes here 3187c478bd9Sstevel@tonic-gate ! 3197c478bd9Sstevel@tonic-gate mov CBO2, CBR2 ! 14, restore borrowed register 3207c478bd9Sstevel@tonic-gate retl ! 15 3217c478bd9Sstevel@tonic-gate mov FPRAS_BADTRAP, %o0 ! 16, how detected 3227c478bd9Sstevel@tonic-gate SET_SIZE(fpras_chkfn_type1) 3237c478bd9Sstevel@tonic-gate 3243b890a5bSjb .seg ".data" 3253b890a5bSjb .global soft_state_message_strings 3263b890a5bSjb 3273b890a5bSjb .align SSM_SIZE 3283b890a5bSjbsoft_state_message_strings: 3293b890a5bSjb .asciz SOLARIS_SOFT_STATE_BOOT_MSG_STR 3303b890a5bSjb .align SSM_SIZE 3313b890a5bSjb .asciz SOLARIS_SOFT_STATE_RUN_MSG_STR 3323b890a5bSjb .align SSM_SIZE 3333b890a5bSjb .asciz SOLARIS_SOFT_STATE_HALT_MSG_STR 3343b890a5bSjb .align SSM_SIZE 3353b890a5bSjb .asciz SOLARIS_SOFT_STATE_POWER_MSG_STR 3363b890a5bSjb .align SSM_SIZE 3373b890a5bSjb .asciz SOLARIS_SOFT_STATE_PANIC_MSG_STR 3383b890a5bSjb .align SSM_SIZE 3393b890a5bSjb .asciz SOLARIS_SOFT_STATE_REBOOT_MSG_STR 3403b890a5bSjb .align SSM_SIZE 3413b890a5bSjb .asciz SOLARIS_SOFT_STATE_DEBUG_MSG_STR 3423b890a5bSjb .align SSM_SIZE 3433b890a5bSjb .skip SSM_SIZE /* saved message */ 3443b890a5bSjb .nword 0 3453b890a5bSjb 3463b890a5bSjb .seg ".text" 347