17c478bd9Sstevel@tonic-gate /* 27c478bd9Sstevel@tonic-gate * CDDL HEADER START 37c478bd9Sstevel@tonic-gate * 47c478bd9Sstevel@tonic-gate * The contents of this file are subject to the terms of the 544bb982bSgovinda * Common Development and Distribution License (the "License"). 644bb982bSgovinda * You may not use this file except in compliance with the License. 77c478bd9Sstevel@tonic-gate * 87c478bd9Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 97c478bd9Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 107c478bd9Sstevel@tonic-gate * See the License for the specific language governing permissions 117c478bd9Sstevel@tonic-gate * and limitations under the License. 127c478bd9Sstevel@tonic-gate * 137c478bd9Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 147c478bd9Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 157c478bd9Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 167c478bd9Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 177c478bd9Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 187c478bd9Sstevel@tonic-gate * 197c478bd9Sstevel@tonic-gate * CDDL HEADER END 207c478bd9Sstevel@tonic-gate */ 217c478bd9Sstevel@tonic-gate /* 2244bb982bSgovinda * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 237c478bd9Sstevel@tonic-gate * Use is subject to license terms. 247c478bd9Sstevel@tonic-gate */ 257c478bd9Sstevel@tonic-gate 267c478bd9Sstevel@tonic-gate #ifndef _SYS_PX_LIB4V_H 277c478bd9Sstevel@tonic-gate #define _SYS_PX_LIB4V_H 287c478bd9Sstevel@tonic-gate 297c478bd9Sstevel@tonic-gate #pragma ident "%Z%%M% %I% %E% SMI" 307c478bd9Sstevel@tonic-gate 317c478bd9Sstevel@tonic-gate #ifdef __cplusplus 327c478bd9Sstevel@tonic-gate extern "C" { 337c478bd9Sstevel@tonic-gate #endif 347c478bd9Sstevel@tonic-gate 35*0ad689d6Sschwartz /* 36*0ad689d6Sschwartz * Fasttrap numbers for VPCI hypervisor functions. 37*0ad689d6Sschwartz */ 38*0ad689d6Sschwartz 39*0ad689d6Sschwartz #define HVIO_IOMMU_MAP 0xb0 40*0ad689d6Sschwartz #define HVIO_IOMMU_DEMAP 0xb1 41*0ad689d6Sschwartz #define HVIO_IOMMU_GETMAP 0xb2 42*0ad689d6Sschwartz #define HVIO_IOMMU_GETBYPASS 0xb3 43*0ad689d6Sschwartz 44*0ad689d6Sschwartz #define HVIO_CONFIG_GET 0xb4 45*0ad689d6Sschwartz #define HVIO_CONFIG_PUT 0xb5 46*0ad689d6Sschwartz 47*0ad689d6Sschwartz #define HVIO_PEEK 0xb6 48*0ad689d6Sschwartz #define HVIO_POKE 0xb7 49*0ad689d6Sschwartz 50*0ad689d6Sschwartz #define HVIO_DMA_SYNC 0xb8 51*0ad689d6Sschwartz 52*0ad689d6Sschwartz #define HVIO_MSIQ_CONF 0xc0 53*0ad689d6Sschwartz #define HVIO_MSIQ_INFO 0xc1 54*0ad689d6Sschwartz #define HVIO_MSIQ_GETVALID 0xc2 55*0ad689d6Sschwartz #define HVIO_MSIQ_SETVALID 0xc3 56*0ad689d6Sschwartz #define HVIO_MSIQ_GETSTATE 0xc4 57*0ad689d6Sschwartz #define HVIO_MSIQ_SETSTATE 0xc5 58*0ad689d6Sschwartz #define HVIO_MSIQ_GETHEAD 0xc6 59*0ad689d6Sschwartz #define HVIO_MSIQ_SETHEAD 0xc7 60*0ad689d6Sschwartz #define HVIO_MSIQ_GETTAIL 0xc8 61*0ad689d6Sschwartz 62*0ad689d6Sschwartz #define HVIO_MSI_GETVALID 0xc9 63*0ad689d6Sschwartz #define HVIO_MSI_SETVALID 0xca 64*0ad689d6Sschwartz #define HVIO_MSI_GETMSIQ 0xcb 65*0ad689d6Sschwartz #define HVIO_MSI_SETMSIQ 0xcc 66*0ad689d6Sschwartz #define HVIO_MSI_GETSTATE 0xcd 67*0ad689d6Sschwartz #define HVIO_MSI_SETSTATE 0xce 68*0ad689d6Sschwartz 69*0ad689d6Sschwartz #define HVIO_MSG_GETMSIQ 0xd0 70*0ad689d6Sschwartz #define HVIO_MSG_SETMSIQ 0xd1 71*0ad689d6Sschwartz #define HVIO_MSG_GETVALID 0xd2 72*0ad689d6Sschwartz #define HVIO_MSG_SETVALID 0xd3 73*0ad689d6Sschwartz 74*0ad689d6Sschwartz #ifndef _ASM 75*0ad689d6Sschwartz 767c478bd9Sstevel@tonic-gate /* 777c478bd9Sstevel@tonic-gate * The device handle uniquely identifies a SUN4V device. 787c478bd9Sstevel@tonic-gate * It consists of the lower 28-bits of the hi-cell of the 797c478bd9Sstevel@tonic-gate * first entry of the SUN4V device's "reg" property as 807c478bd9Sstevel@tonic-gate * defined by the SUN4V Bus Binding to Open Firmware. 817c478bd9Sstevel@tonic-gate */ 827c478bd9Sstevel@tonic-gate #define DEVHDLE_MASK 0xFFFFFFF 837c478bd9Sstevel@tonic-gate 848bc7d88aSet /* PX BDF Shift in a Phyiscal Address - used FMA Fabric only */ 858bc7d88aSet #define PX_RA_BDF_SHIFT 8 868bc7d88aSet 8744bb982bSgovinda #define PX_ADDR2PFN(addr, index, flags, i) \ 8844bb982bSgovinda ((flags & MMU_MAP_PFN) ? \ 895bc7e870Sgovinda PX_GET_MP_PFN((ddi_dma_impl_t *)(addr), (index + i)) : \ 905bc7e870Sgovinda hat_getpfnum(kas.a_hat, ((caddr_t)addr + (MMU_PAGE_SIZE * i)))) 915bc7e870Sgovinda 9244bb982bSgovinda /* 9344bb982bSgovinda * VPCI API versioning. 9444bb982bSgovinda * 95*0ad689d6Sschwartz * Currently PX nexus driver supports VPCI API version 1.0 9644bb982bSgovinda */ 9744bb982bSgovinda #define PX_VPCI_MAJOR_VER_1 0x1ull 9844bb982bSgovinda #define PX_VPCI_MAJOR_VER PX_VPCI_MAJOR_VER_1 9944bb982bSgovinda 10044bb982bSgovinda #define PX_VPCI_MINOR_VER_0 0x0ull 10144bb982bSgovinda #define PX_VPCI_MINOR_VER PX_VPCI_MINOR_VER_0 10244bb982bSgovinda 1037c478bd9Sstevel@tonic-gate extern uint64_t hvio_config_get(devhandle_t dev_hdl, pci_device_t bdf, 1047c478bd9Sstevel@tonic-gate pci_config_offset_t off, pci_config_size_t size, pci_cfg_data_t *data_p); 1057c478bd9Sstevel@tonic-gate extern uint64_t hvio_config_put(devhandle_t dev_hdl, pci_device_t bdf, 1067c478bd9Sstevel@tonic-gate pci_config_offset_t off, pci_config_size_t size, pci_cfg_data_t data); 1077c478bd9Sstevel@tonic-gate 1087c478bd9Sstevel@tonic-gate extern uint64_t hvio_iommu_map(devhandle_t dev_hdl, tsbid_t tsbid, 10944bb982bSgovinda pages_t pages, io_attributes_t attr, io_page_list_t *io_page_list_p, 11044bb982bSgovinda pages_t *pages_mapped); 1117c478bd9Sstevel@tonic-gate extern uint64_t hvio_iommu_demap(devhandle_t dev_hdl, tsbid_t tsbid, 1127c478bd9Sstevel@tonic-gate pages_t pages, pages_t *pages_demapped); 1137c478bd9Sstevel@tonic-gate extern uint64_t hvio_iommu_getmap(devhandle_t dev_hdl, tsbid_t tsbid, 11444bb982bSgovinda io_attributes_t *attr_p, r_addr_t *r_addr_p); 1157c478bd9Sstevel@tonic-gate extern uint64_t hvio_iommu_getbypass(devhandle_t dev_hdl, r_addr_t ra, 11644bb982bSgovinda io_attributes_t attr, io_addr_t *io_addr_p); 1177c478bd9Sstevel@tonic-gate extern uint64_t hvio_dma_sync(devhandle_t dev_hdl, r_addr_t ra, 1187c478bd9Sstevel@tonic-gate size_t num_bytes, io_sync_direction_t io_sync_direction, 1197c478bd9Sstevel@tonic-gate size_t *bytes_synched); 1207c478bd9Sstevel@tonic-gate 1217c478bd9Sstevel@tonic-gate /* 1227c478bd9Sstevel@tonic-gate * MSIQ Functions: 1237c478bd9Sstevel@tonic-gate */ 1247c478bd9Sstevel@tonic-gate extern uint64_t hvio_msiq_conf(devhandle_t dev_hdl, msiqid_t msiq_id, 1257c478bd9Sstevel@tonic-gate r_addr_t ra, uint_t msiq_rec_cnt); 1267c478bd9Sstevel@tonic-gate extern uint64_t hvio_msiq_info(devhandle_t dev_hdl, msiqid_t msiq_id, 1277c478bd9Sstevel@tonic-gate r_addr_t *ra_p, uint_t *msiq_rec_cnt_p); 1287c478bd9Sstevel@tonic-gate extern uint64_t hvio_msiq_getvalid(devhandle_t dev_hdl, msiqid_t msiq_id, 1297c478bd9Sstevel@tonic-gate pci_msiq_valid_state_t *msiq_valid_state); 1307c478bd9Sstevel@tonic-gate extern uint64_t hvio_msiq_setvalid(devhandle_t dev_hdl, msiqid_t msiq_id, 1317c478bd9Sstevel@tonic-gate pci_msiq_valid_state_t msiq_valid_state); 1327c478bd9Sstevel@tonic-gate extern uint64_t hvio_msiq_getstate(devhandle_t dev_hdl, msiqid_t msiq_id, 1337c478bd9Sstevel@tonic-gate pci_msiq_state_t *msiq_state); 1347c478bd9Sstevel@tonic-gate extern uint64_t hvio_msiq_setstate(devhandle_t dev_hdl, msiqid_t msiq_id, 1357c478bd9Sstevel@tonic-gate pci_msiq_state_t msiq_state); 1367c478bd9Sstevel@tonic-gate extern uint64_t hvio_msiq_gethead(devhandle_t dev_hdl, msiqid_t msiq_id, 1377c478bd9Sstevel@tonic-gate msiqhead_t *msiq_head); 1387c478bd9Sstevel@tonic-gate extern uint64_t hvio_msiq_sethead(devhandle_t dev_hdl, msiqid_t msiq_id, 1397c478bd9Sstevel@tonic-gate msiqhead_t msiq_head); 1407c478bd9Sstevel@tonic-gate extern uint64_t hvio_msiq_gettail(devhandle_t dev_hdl, msiqid_t msiq_id, 1417c478bd9Sstevel@tonic-gate msiqtail_t *msiq_tail); 1427c478bd9Sstevel@tonic-gate 1437c478bd9Sstevel@tonic-gate /* 1447c478bd9Sstevel@tonic-gate * MSI Functions: 1457c478bd9Sstevel@tonic-gate */ 1467c478bd9Sstevel@tonic-gate extern uint64_t hvio_msi_getmsiq(devhandle_t dev_hdl, msinum_t msi_num, 1477c478bd9Sstevel@tonic-gate msiqid_t *msiq_id); 1487c478bd9Sstevel@tonic-gate extern uint64_t hvio_msi_setmsiq(devhandle_t dev_hdl, msinum_t msi_num, 1497c478bd9Sstevel@tonic-gate msiqid_t msiq_id, msi_type_t msitype); 1507c478bd9Sstevel@tonic-gate extern uint64_t hvio_msi_getvalid(devhandle_t dev_hdl, msinum_t msi_num, 1517c478bd9Sstevel@tonic-gate pci_msi_valid_state_t *msi_valid_state); 1527c478bd9Sstevel@tonic-gate extern uint64_t hvio_msi_setvalid(devhandle_t dev_hdl, msinum_t msi_num, 1537c478bd9Sstevel@tonic-gate pci_msi_valid_state_t msi_valid_state); 1547c478bd9Sstevel@tonic-gate extern uint64_t hvio_msi_getstate(devhandle_t dev_hdl, msinum_t msi_num, 1557c478bd9Sstevel@tonic-gate pci_msi_state_t *msi_state); 1567c478bd9Sstevel@tonic-gate extern uint64_t hvio_msi_setstate(devhandle_t dev_hdl, msinum_t msi_num, 1577c478bd9Sstevel@tonic-gate pci_msi_state_t msi_state); 1587c478bd9Sstevel@tonic-gate 1597c478bd9Sstevel@tonic-gate /* 1607c478bd9Sstevel@tonic-gate * MSG Functions: 1617c478bd9Sstevel@tonic-gate */ 1627c478bd9Sstevel@tonic-gate extern uint64_t hvio_msg_getmsiq(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 1637c478bd9Sstevel@tonic-gate msiqid_t *msiq_id); 1647c478bd9Sstevel@tonic-gate extern uint64_t hvio_msg_setmsiq(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 1657c478bd9Sstevel@tonic-gate msiqid_t msiq_id); 1667c478bd9Sstevel@tonic-gate extern uint64_t hvio_msg_getvalid(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 1677c478bd9Sstevel@tonic-gate pcie_msg_valid_state_t *msg_valid_state); 1687c478bd9Sstevel@tonic-gate extern uint64_t hvio_msg_setvalid(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 1697c478bd9Sstevel@tonic-gate pcie_msg_valid_state_t msg_valid_state); 1707c478bd9Sstevel@tonic-gate 1717c478bd9Sstevel@tonic-gate typedef struct px_config_acc_pvt { 1727c478bd9Sstevel@tonic-gate dev_info_t *dip; 1737c478bd9Sstevel@tonic-gate uint32_t raddr; 1747c478bd9Sstevel@tonic-gate uint32_t vaddr; 1757c478bd9Sstevel@tonic-gate } px_config_acc_pvt_t; 1767c478bd9Sstevel@tonic-gate 1777c478bd9Sstevel@tonic-gate /* 1787c478bd9Sstevel@tonic-gate * Peek/poke functionality: 1797c478bd9Sstevel@tonic-gate */ 1807c478bd9Sstevel@tonic-gate 1817c478bd9Sstevel@tonic-gate extern uint64_t hvio_peek(devhandle_t dev_hdl, r_addr_t ra, size_t size, 1827c478bd9Sstevel@tonic-gate uint32_t *status, uint64_t *data_p); 1837c478bd9Sstevel@tonic-gate extern uint64_t hvio_poke(devhandle_t dev_hdl, r_addr_t ra, size_t size, 1847c478bd9Sstevel@tonic-gate uint64_t data, pci_device_t bdf, uint32_t *wrt_stat); 1857c478bd9Sstevel@tonic-gate 18669cd775fSschwartz /* 18769cd775fSschwartz * Priviledged physical access: 18869cd775fSschwartz */ 18969cd775fSschwartz extern uint64_t hv_ra2pa(uint64_t ra); 19069cd775fSschwartz extern uint64_t hv_hpriv(void *func, uint64_t arg1, uint64_t arg2, 19169cd775fSschwartz uint64_t arg3); 19244bb982bSgovinda extern int px_phys_acc_4v(uint64_t dummy, uint64_t from_addr, uint64_t to_addr); 19369cd775fSschwartz 194*0ad689d6Sschwartz #endif /* _ASM */ 195*0ad689d6Sschwartz 1967c478bd9Sstevel@tonic-gate #ifdef __cplusplus 1977c478bd9Sstevel@tonic-gate } 1987c478bd9Sstevel@tonic-gate #endif 1997c478bd9Sstevel@tonic-gate 2007c478bd9Sstevel@tonic-gate #endif /* _SYS_PX_LIB4V_H */ 201