xref: /illumos-gate/usr/src/uts/sun4v/io/px/px_lib4v.c (revision d5ebc493)
17c478bd9Sstevel@tonic-gate /*
27c478bd9Sstevel@tonic-gate  * CDDL HEADER START
37c478bd9Sstevel@tonic-gate  *
47c478bd9Sstevel@tonic-gate  * The contents of this file are subject to the terms of the
57aadd8d4Skini  * Common Development and Distribution License (the "License").
67aadd8d4Skini  * You may not use this file except in compliance with the License.
77c478bd9Sstevel@tonic-gate  *
87c478bd9Sstevel@tonic-gate  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
97c478bd9Sstevel@tonic-gate  * or http://www.opensolaris.org/os/licensing.
107c478bd9Sstevel@tonic-gate  * See the License for the specific language governing permissions
117c478bd9Sstevel@tonic-gate  * and limitations under the License.
127c478bd9Sstevel@tonic-gate  *
137c478bd9Sstevel@tonic-gate  * When distributing Covered Code, include this CDDL HEADER in each
147c478bd9Sstevel@tonic-gate  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
157c478bd9Sstevel@tonic-gate  * If applicable, add the following below this CDDL HEADER, with the
167c478bd9Sstevel@tonic-gate  * fields enclosed by brackets "[]" replaced with your own identifying
177c478bd9Sstevel@tonic-gate  * information: Portions Copyright [yyyy] [name of copyright owner]
187c478bd9Sstevel@tonic-gate  *
197c478bd9Sstevel@tonic-gate  * CDDL HEADER END
207c478bd9Sstevel@tonic-gate  */
217c478bd9Sstevel@tonic-gate /*
223d78e6abSAlan Adamson, SD OSSD  * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved.
237c478bd9Sstevel@tonic-gate  */
247c478bd9Sstevel@tonic-gate 
253fe80ca4SDan Cross /*
263fe80ca4SDan Cross  * Copyright 2023 Oxide Computer Company
273fe80ca4SDan Cross  */
283fe80ca4SDan Cross 
297c478bd9Sstevel@tonic-gate #include <sys/types.h>
307c478bd9Sstevel@tonic-gate #include <sys/sysmacros.h>
317c478bd9Sstevel@tonic-gate #include <sys/ddi.h>
329c75c6bfSgovinda #include <sys/async.h>
337c478bd9Sstevel@tonic-gate #include <sys/sunddi.h>
347c478bd9Sstevel@tonic-gate #include <sys/ddifm.h>
357c478bd9Sstevel@tonic-gate #include <sys/fm/protocol.h>
367c478bd9Sstevel@tonic-gate #include <sys/vmem.h>
37f8d2de6bSjchu #include <sys/intr.h>
38f8d2de6bSjchu #include <sys/ivintr.h>
39f8d2de6bSjchu #include <sys/errno.h>
407c478bd9Sstevel@tonic-gate #include <sys/hypervisor_api.h>
4144bb982bSgovinda #include <sys/hsvc.h>
427c478bd9Sstevel@tonic-gate #include <px_obj.h>
43f8d2de6bSjchu #include <sys/machsystm.h>
44fc256490SJason Beloro #include <sys/sunndi.h>
45fc256490SJason Beloro #include <sys/pcie_impl.h>
467c478bd9Sstevel@tonic-gate #include "px_lib4v.h"
47f8d2de6bSjchu #include "px_err.h"
48c0da6274SZhi-Jun Robin Fu #include <sys/pci_cfgacc.h>
49c0da6274SZhi-Jun Robin Fu #include <sys/pci_cfgacc_4v.h>
50c0da6274SZhi-Jun Robin Fu 
517c478bd9Sstevel@tonic-gate 
527c478bd9Sstevel@tonic-gate /* mask for the ranges property in calculating the real PFN range */
537c478bd9Sstevel@tonic-gate uint_t px_ranges_phi_mask = ((1 << 28) -1);
547c478bd9Sstevel@tonic-gate 
5544bb982bSgovinda /*
5644bb982bSgovinda  * Hypervisor VPCI services information for the px nexus driver.
5744bb982bSgovinda  */
583d78e6abSAlan Adamson, SD OSSD static	uint64_t	px_vpci_maj_ver; /* Negotiated VPCI API major version */
5944bb982bSgovinda static	uint64_t	px_vpci_min_ver; /* Negotiated VPCI API minor version */
6044bb982bSgovinda static	uint_t		px_vpci_users = 0; /* VPCI API users */
61fc256490SJason Beloro static	hsvc_info_t px_hsvc_vpci = {
6244bb982bSgovinda 	HSVC_REV_1, NULL, HSVC_GROUP_VPCI, PX_VPCI_MAJOR_VER,
6344bb982bSgovinda 	PX_VPCI_MINOR_VER, "PX"
6444bb982bSgovinda };
6544bb982bSgovinda 
66fc256490SJason Beloro /*
67fc256490SJason Beloro  * Hypervisor SDIO services information for the px nexus driver.
68fc256490SJason Beloro  */
69fc256490SJason Beloro static	uint64_t	px_sdio_min_ver; /* Negotiated SDIO API minor version */
70fc256490SJason Beloro static	uint_t		px_sdio_users = 0; /* SDIO API users */
71fc256490SJason Beloro static	hsvc_info_t px_hsvc_sdio = {
72fc256490SJason Beloro 	HSVC_REV_1, NULL, HSVC_GROUP_SDIO, PX_SDIO_MAJOR_VER,
73fc256490SJason Beloro 	PX_SDIO_MINOR_VER, "PX"
74fc256490SJason Beloro };
75fc256490SJason Beloro 
76fc256490SJason Beloro /*
77fc256490SJason Beloro  * Hypervisor SDIO ERR services information for the px nexus driver.
78fc256490SJason Beloro  */
79fc256490SJason Beloro static	uint64_t	px_sdio_err_min_ver; /* Negotiated SDIO ERR API */
80fc256490SJason Beloro 						/* minor version */
81fc256490SJason Beloro static	uint_t		px_sdio_err_users = 0; /* SDIO ERR API users */
82fc256490SJason Beloro static	hsvc_info_t px_hsvc_sdio_err = {
83fc256490SJason Beloro 	HSVC_REV_1, NULL, HSVC_GROUP_SDIO_ERR, PX_SDIO_ERR_MAJOR_VER,
84fc256490SJason Beloro 	PX_SDIO_ERR_MINOR_VER, "PX"
85fc256490SJason Beloro };
86fc256490SJason Beloro 
87fc256490SJason Beloro #define	CHILD_LOANED	"child_loaned"
88fc256490SJason Beloro static int px_lib_count_waiting_dev(dev_info_t *);
89fc256490SJason Beloro 
907c478bd9Sstevel@tonic-gate int
px_lib_dev_init(dev_info_t * dip,devhandle_t * dev_hdl)917c478bd9Sstevel@tonic-gate px_lib_dev_init(dev_info_t *dip, devhandle_t *dev_hdl)
927c478bd9Sstevel@tonic-gate {
937c478bd9Sstevel@tonic-gate 	px_nexus_regspec_t	*rp;
94c9f965e3Set 	uint_t			reglen;
95c9f965e3Set 	int			ret;
96fc256490SJason Beloro 	px_t			*px_p = DIP_TO_STATE(dip);
97d66f8315Sjb 	uint64_t mjrnum;
98d66f8315Sjb 	uint64_t mnrnum;
99d66f8315Sjb 
1007c478bd9Sstevel@tonic-gate 	DBG(DBG_ATTACH, dip, "px_lib_dev_init: dip 0x%p\n", dip);
1017c478bd9Sstevel@tonic-gate 
102d66f8315Sjb 	/*
103d66f8315Sjb 	 * Check HV intr group api versioning.
104d66f8315Sjb 	 * This driver uses the old interrupt routines which are supported
105d66f8315Sjb 	 * in old firmware in the CORE API group and in newer firmware in
106d66f8315Sjb 	 * the INTR API group.  Support for these calls will be dropped
107d66f8315Sjb 	 * once the INTR API group major goes to 2.
108d66f8315Sjb 	 */
109d66f8315Sjb 	if ((hsvc_version(HSVC_GROUP_INTR, &mjrnum, &mnrnum) == 0) &&
110d66f8315Sjb 	    (mjrnum > 1)) {
111350effc1SZach Kissel 		cmn_err(CE_WARN, "px: unsupported intr api group: "
112d66f8315Sjb 		    "maj:0x%lx, min:0x%lx", mjrnum, mnrnum);
113d66f8315Sjb 		return (ENOTSUP);
114d66f8315Sjb 	}
115d66f8315Sjb 
116c9f965e3Set 	ret = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS,
117c9f965e3Set 	    "reg", (uchar_t **)&rp, &reglen);
118c9f965e3Set 	if (ret != DDI_PROP_SUCCESS) {
119c9f965e3Set 		DBG(DBG_ATTACH, dip, "px_lib_dev_init failed ret=%d\n", ret);
1207c478bd9Sstevel@tonic-gate 		return (DDI_FAILURE);
1217c478bd9Sstevel@tonic-gate 	}
1227c478bd9Sstevel@tonic-gate 
1237c478bd9Sstevel@tonic-gate 	/*
1247c478bd9Sstevel@tonic-gate 	 * Initilize device handle. The device handle uniquely identifies
1257c478bd9Sstevel@tonic-gate 	 * a SUN4V device. It consists of the lower 28-bits of the hi-cell
1267c478bd9Sstevel@tonic-gate 	 * of the first entry of the SUN4V device's "reg" property as
1277c478bd9Sstevel@tonic-gate 	 * defined by the SUN4V Bus Binding to Open Firmware.
1287c478bd9Sstevel@tonic-gate 	 */
1297c478bd9Sstevel@tonic-gate 	*dev_hdl = (devhandle_t)((rp->phys_addr >> 32) & DEVHDLE_MASK);
130c9f965e3Set 	ddi_prop_free(rp);
131c9f965e3Set 
132b65731f1Skini 	/*
133b65731f1Skini 	 * hotplug implementation requires this property to be associated with
134b65731f1Skini 	 * any indirect PCI config access services
135b65731f1Skini 	 */
136b65731f1Skini 	(void) ddi_prop_update_int(makedevice(ddi_driver_major(dip),
13726947304SEvan Yan 	    PCI_MINOR_NUM(ddi_get_instance(dip), PCI_DEVCTL_MINOR)), dip,
138b65731f1Skini 	    PCI_BUS_CONF_MAP_PROP, 1);
139b65731f1Skini 
1407c478bd9Sstevel@tonic-gate 	DBG(DBG_ATTACH, dip, "px_lib_dev_init: dev_hdl 0x%llx\n", *dev_hdl);
1417c478bd9Sstevel@tonic-gate 
14244bb982bSgovinda 	/*
143fc256490SJason Beloro 	 * If a /pci node has a pci-intx-not-supported property, this property
144fc256490SJason Beloro 	 * represents that the fabric doesn't support fixed interrupt.
14544bb982bSgovinda 	 */
146fc256490SJason Beloro 	if (!ddi_prop_exists(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS,
147fc256490SJason Beloro 	    "pci-intx-not-supported")) {
148fc256490SJason Beloro 		DBG(DBG_ATTACH, dip, "px_lib_dev_init: "
149fc256490SJason Beloro 		    "pci-intx-not-supported is not found, dip=0x%p\n", dip);
150fc256490SJason Beloro 		px_p->px_supp_intr_types |= DDI_INTR_TYPE_FIXED;
151fc256490SJason Beloro 	}
15244bb982bSgovinda 
153fc256490SJason Beloro 	/*
154fc256490SJason Beloro 	 * Negotiate the API version for VPCI hypervisor services.
155fc256490SJason Beloro 	 */
1563d78e6abSAlan Adamson, SD OSSD 	if (px_vpci_users == 0) {
1573d78e6abSAlan Adamson, SD OSSD 		if ((ret = hsvc_register(&px_hsvc_vpci, &px_vpci_min_ver))
1583d78e6abSAlan Adamson, SD OSSD 		    == 0) {
1593d78e6abSAlan Adamson, SD OSSD 			px_vpci_maj_ver = px_hsvc_vpci.hsvc_major;
1603d78e6abSAlan Adamson, SD OSSD 			goto hv_negotiation_complete;
1613d78e6abSAlan Adamson, SD OSSD 		}
1623d78e6abSAlan Adamson, SD OSSD 		/*
1633d78e6abSAlan Adamson, SD OSSD 		 * Negotiation with the latest known VPCI hypervisor services
1643d78e6abSAlan Adamson, SD OSSD 		 * failed.  Fallback to version 1.0.
1653d78e6abSAlan Adamson, SD OSSD 		 */
1663d78e6abSAlan Adamson, SD OSSD 		px_hsvc_vpci.hsvc_major = PX_HSVC_MAJOR_VER_1;
1673d78e6abSAlan Adamson, SD OSSD 		px_hsvc_vpci.hsvc_minor = PX_HSVC_MINOR_VER_0;
1683d78e6abSAlan Adamson, SD OSSD 
1693d78e6abSAlan Adamson, SD OSSD 		if ((ret = hsvc_register(&px_hsvc_vpci, &px_vpci_min_ver))
1703d78e6abSAlan Adamson, SD OSSD 		    == 0) {
1713d78e6abSAlan Adamson, SD OSSD 			px_vpci_maj_ver = px_hsvc_vpci.hsvc_major;
1723d78e6abSAlan Adamson, SD OSSD 			goto hv_negotiation_complete;
1733d78e6abSAlan Adamson, SD OSSD 		}
1743d78e6abSAlan Adamson, SD OSSD 
17544bb982bSgovinda 		cmn_err(CE_WARN, "%s: cannot negotiate hypervisor services "
17644bb982bSgovinda 		    "group: 0x%lx major: 0x%lx minor: 0x%lx errno: %d\n",
177fc256490SJason Beloro 		    px_hsvc_vpci.hsvc_modname, px_hsvc_vpci.hsvc_group,
178fc256490SJason Beloro 		    px_hsvc_vpci.hsvc_major, px_hsvc_vpci.hsvc_minor, ret);
1793d78e6abSAlan Adamson, SD OSSD 
18044bb982bSgovinda 		return (DDI_FAILURE);
18144bb982bSgovinda 	}
1823d78e6abSAlan Adamson, SD OSSD hv_negotiation_complete:
1833d78e6abSAlan Adamson, SD OSSD 
184fc256490SJason Beloro 	px_vpci_users++;
1853d78e6abSAlan Adamson, SD OSSD 
18644bb982bSgovinda 	DBG(DBG_ATTACH, dip, "px_lib_dev_init: negotiated VPCI API version, "
1873d78e6abSAlan Adamson, SD OSSD 	    "major 0x%lx minor 0x%lx\n", px_vpci_maj_ver,
188fc256490SJason Beloro 	    px_vpci_min_ver);
189fc256490SJason Beloro 
190fc256490SJason Beloro 	/*
191fc256490SJason Beloro 	 * Negotiate the API version for SDIO hypervisor services.
192fc256490SJason Beloro 	 */
193fc256490SJason Beloro 	if ((px_sdio_users == 0) &&
194fc256490SJason Beloro 	    ((ret = hsvc_register(&px_hsvc_sdio, &px_sdio_min_ver)) != 0)) {
195fc256490SJason Beloro 		DBG(DBG_ATTACH, dip, "%s: cannot negotiate hypervisor "
196fc256490SJason Beloro 		    "services group: 0x%lx major: 0x%lx minor: 0x%lx "
197fc256490SJason Beloro 		    "errno: %d\n", px_hsvc_sdio.hsvc_modname,
198fc256490SJason Beloro 		    px_hsvc_sdio.hsvc_group, px_hsvc_sdio.hsvc_major,
199fc256490SJason Beloro 		    px_hsvc_sdio.hsvc_minor, ret);
200fc256490SJason Beloro 	} else {
201fc256490SJason Beloro 		px_sdio_users++;
202fc256490SJason Beloro 		DBG(DBG_ATTACH, dip, "px_lib_dev_init: negotiated SDIO API"
203fc256490SJason Beloro 		    "version, major 0x%lx minor 0x%lx\n",
204fc256490SJason Beloro 		    px_hsvc_sdio.hsvc_major, px_sdio_min_ver);
205fc256490SJason Beloro 	}
206fc256490SJason Beloro 
207fc256490SJason Beloro 	/*
208fc256490SJason Beloro 	 * Negotiate the API version for SDIO ERR hypervisor services.
209fc256490SJason Beloro 	 */
210fc256490SJason Beloro 	if ((px_sdio_err_users == 0) &&
211fc256490SJason Beloro 	    ((ret = hsvc_register(&px_hsvc_sdio_err,
212fc256490SJason Beloro 	    &px_sdio_err_min_ver)) != 0)) {
213fc256490SJason Beloro 		DBG(DBG_ATTACH, dip, "%s: cannot negotiate SDIO ERR hypervisor "
214fc256490SJason Beloro 		    "services group: 0x%lx major: 0x%lx minor: 0x%lx "
215fc256490SJason Beloro 		    "errno: %d\n", px_hsvc_sdio_err.hsvc_modname,
216fc256490SJason Beloro 		    px_hsvc_sdio_err.hsvc_group, px_hsvc_sdio_err.hsvc_major,
217fc256490SJason Beloro 		    px_hsvc_sdio_err.hsvc_minor, ret);
218fc256490SJason Beloro 	} else {
219fc256490SJason Beloro 		px_sdio_err_users++;
220fc256490SJason Beloro 		DBG(DBG_ATTACH, dip, "px_lib_dev_init: negotiated SDIO ERR API "
221fc256490SJason Beloro 		    "version, major 0x%lx minor 0x%lx\n",
222fc256490SJason Beloro 		    px_hsvc_sdio_err.hsvc_major, px_sdio_err_min_ver);
223fc256490SJason Beloro 	}
22444bb982bSgovinda 
225fc256490SJason Beloro 	/*
226fc256490SJason Beloro 	 * Find out the number of dev we need to wait under this RC
227fc256490SJason Beloro 	 * before we issue fabric sync hypercall
228fc256490SJason Beloro 	 */
229fc256490SJason Beloro 	px_p->px_plat_p = (void *)(uintptr_t)px_lib_count_waiting_dev(dip);
230fc256490SJason Beloro 	DBG(DBG_ATTACH, dip, "Found %d bridges need waiting under RC %p",
231fc256490SJason Beloro 	    (int)(uintptr_t)px_p->px_plat_p, dip);
2327c478bd9Sstevel@tonic-gate 	return (DDI_SUCCESS);
2337c478bd9Sstevel@tonic-gate }
2347c478bd9Sstevel@tonic-gate 
2357c478bd9Sstevel@tonic-gate /*ARGSUSED*/
2367c478bd9Sstevel@tonic-gate int
px_lib_dev_fini(dev_info_t * dip)2377c478bd9Sstevel@tonic-gate px_lib_dev_fini(dev_info_t *dip)
2387c478bd9Sstevel@tonic-gate {
2397c478bd9Sstevel@tonic-gate 	DBG(DBG_DETACH, dip, "px_lib_dev_fini: dip 0x%p\n", dip);
2407c478bd9Sstevel@tonic-gate 
241b65731f1Skini 	(void) ddi_prop_remove(makedevice(ddi_driver_major(dip),
24226947304SEvan Yan 	    PCI_MINOR_NUM(ddi_get_instance(dip), PCI_DEVCTL_MINOR)), dip,
243b65731f1Skini 	    PCI_BUS_CONF_MAP_PROP);
244b65731f1Skini 
24544bb982bSgovinda 	if (--px_vpci_users == 0)
246fc256490SJason Beloro 		(void) hsvc_unregister(&px_hsvc_vpci);
247fc256490SJason Beloro 
248fc256490SJason Beloro 	if (--px_sdio_users == 0)
249fc256490SJason Beloro 		(void) hsvc_unregister(&px_hsvc_sdio);
250fc256490SJason Beloro 
251fc256490SJason Beloro 	if (--px_sdio_err_users == 0)
252fc256490SJason Beloro 		(void) hsvc_unregister(&px_hsvc_sdio_err);
25344bb982bSgovinda 
2547c478bd9Sstevel@tonic-gate 	return (DDI_SUCCESS);
2557c478bd9Sstevel@tonic-gate }
2567c478bd9Sstevel@tonic-gate 
2577c478bd9Sstevel@tonic-gate /*ARGSUSED*/
2587c478bd9Sstevel@tonic-gate int
px_lib_intr_devino_to_sysino(dev_info_t * dip,devino_t devino,sysino_t * sysino)2597c478bd9Sstevel@tonic-gate px_lib_intr_devino_to_sysino(dev_info_t *dip, devino_t devino,
2607c478bd9Sstevel@tonic-gate     sysino_t *sysino)
2617c478bd9Sstevel@tonic-gate {
2627c478bd9Sstevel@tonic-gate 	uint64_t	ret;
2637c478bd9Sstevel@tonic-gate 
2647c478bd9Sstevel@tonic-gate 	DBG(DBG_LIB_INT, dip, "px_lib_intr_devino_to_sysino: dip 0x%p "
2657c478bd9Sstevel@tonic-gate 	    "devino 0x%x\n", dip, devino);
2667c478bd9Sstevel@tonic-gate 
2677c478bd9Sstevel@tonic-gate 	if ((ret = hvio_intr_devino_to_sysino(DIP_TO_HANDLE(dip),
2687c478bd9Sstevel@tonic-gate 	    devino, sysino)) != H_EOK) {
2697c478bd9Sstevel@tonic-gate 		DBG(DBG_LIB_INT, dip,
2707c478bd9Sstevel@tonic-gate 		    "hvio_intr_devino_to_sysino failed, ret 0x%lx\n", ret);
2717c478bd9Sstevel@tonic-gate 		return (DDI_FAILURE);
2727c478bd9Sstevel@tonic-gate 	}
2737c478bd9Sstevel@tonic-gate 
2747c478bd9Sstevel@tonic-gate 	DBG(DBG_LIB_INT, dip, "px_lib_intr_devino_to_sysino: sysino 0x%llx\n",
2757c478bd9Sstevel@tonic-gate 	    *sysino);
2767c478bd9Sstevel@tonic-gate 
2777c478bd9Sstevel@tonic-gate 	return (DDI_SUCCESS);
2787c478bd9Sstevel@tonic-gate }
2797c478bd9Sstevel@tonic-gate 
2807c478bd9Sstevel@tonic-gate /*ARGSUSED*/
2817c478bd9Sstevel@tonic-gate int
px_lib_intr_getvalid(dev_info_t * dip,sysino_t sysino,intr_valid_state_t * intr_valid_state)2827c478bd9Sstevel@tonic-gate px_lib_intr_getvalid(dev_info_t *dip, sysino_t sysino,
2837c478bd9Sstevel@tonic-gate     intr_valid_state_t *intr_valid_state)
2847c478bd9Sstevel@tonic-gate {
2857c478bd9Sstevel@tonic-gate 	uint64_t	ret;
2867c478bd9Sstevel@tonic-gate 
2877c478bd9Sstevel@tonic-gate 	DBG(DBG_LIB_INT, dip, "px_lib_intr_getvalid: dip 0x%p sysino 0x%llx\n",
2887c478bd9Sstevel@tonic-gate 	    dip, sysino);
2897c478bd9Sstevel@tonic-gate 
2907c478bd9Sstevel@tonic-gate 	if ((ret = hvio_intr_getvalid(sysino,
2917c478bd9Sstevel@tonic-gate 	    (int *)intr_valid_state)) != H_EOK) {
2927c478bd9Sstevel@tonic-gate 		DBG(DBG_LIB_INT, dip, "hvio_intr_getvalid failed, ret 0x%lx\n",
2937c478bd9Sstevel@tonic-gate 		    ret);
2947c478bd9Sstevel@tonic-gate 		return (DDI_FAILURE);
2957c478bd9Sstevel@tonic-gate 	}
2967c478bd9Sstevel@tonic-gate 
2977c478bd9Sstevel@tonic-gate 	DBG(DBG_LIB_INT, dip, "px_lib_intr_getvalid: intr_valid_state 0x%x\n",
2987c478bd9Sstevel@tonic-gate 	    *intr_valid_state);
2997c478bd9Sstevel@tonic-gate 
3007c478bd9Sstevel@tonic-gate 	return (DDI_SUCCESS);
3017c478bd9Sstevel@tonic-gate }
3027c478bd9Sstevel@tonic-gate 
3037c478bd9Sstevel@tonic-gate /*ARGSUSED*/
3047c478bd9Sstevel@tonic-gate int
px_lib_intr_setvalid(dev_info_t * dip,sysino_t sysino,intr_valid_state_t intr_valid_state)3057c478bd9Sstevel@tonic-gate px_lib_intr_setvalid(dev_info_t *dip, sysino_t sysino,
3067c478bd9Sstevel@tonic-gate     intr_valid_state_t intr_valid_state)
3077c478bd9Sstevel@tonic-gate {
3087c478bd9Sstevel@tonic-gate 	uint64_t	ret;
3097c478bd9Sstevel@tonic-gate 
3107c478bd9Sstevel@tonic-gate 	DBG(DBG_LIB_INT, dip, "px_lib_intr_setvalid: dip 0x%p sysino 0x%llx "
3117c478bd9Sstevel@tonic-gate 	    "intr_valid_state 0x%x\n", dip, sysino, intr_valid_state);
3127c478bd9Sstevel@tonic-gate 
3137c478bd9Sstevel@tonic-gate 	if ((ret = hvio_intr_setvalid(sysino, intr_valid_state)) != H_EOK) {
3147c478bd9Sstevel@tonic-gate 		DBG(DBG_LIB_INT, dip, "hvio_intr_setvalid failed, ret 0x%lx\n",
3157c478bd9Sstevel@tonic-gate 		    ret);
3167c478bd9Sstevel@tonic-gate 		return (DDI_FAILURE);
3177c478bd9Sstevel@tonic-gate 	}
3187c478bd9Sstevel@tonic-gate 
3197c478bd9Sstevel@tonic-gate 	return (DDI_SUCCESS);
3207c478bd9Sstevel@tonic-gate }
3217c478bd9Sstevel@tonic-gate 
3227c478bd9Sstevel@tonic-gate /*ARGSUSED*/
3237c478bd9Sstevel@tonic-gate int
px_lib_intr_getstate(dev_info_t * dip,sysino_t sysino,intr_state_t * intr_state)3247c478bd9Sstevel@tonic-gate px_lib_intr_getstate(dev_info_t *dip, sysino_t sysino,
3257c478bd9Sstevel@tonic-gate     intr_state_t *intr_state)
3267c478bd9Sstevel@tonic-gate {
3277c478bd9Sstevel@tonic-gate 	uint64_t	ret;
3287c478bd9Sstevel@tonic-gate 
3297c478bd9Sstevel@tonic-gate 	DBG(DBG_LIB_INT, dip, "px_lib_intr_getstate: dip 0x%p sysino 0x%llx\n",
3307c478bd9Sstevel@tonic-gate 	    dip, sysino);
3317c478bd9Sstevel@tonic-gate 
3327c478bd9Sstevel@tonic-gate 	if ((ret = hvio_intr_getstate(sysino, (int *)intr_state)) != H_EOK) {
3337c478bd9Sstevel@tonic-gate 		DBG(DBG_LIB_INT, dip, "hvio_intr_getstate failed, ret 0x%lx\n",
3347c478bd9Sstevel@tonic-gate 		    ret);
3357c478bd9Sstevel@tonic-gate 		return (DDI_FAILURE);
3367c478bd9Sstevel@tonic-gate 	}
3377c478bd9Sstevel@tonic-gate 
3387c478bd9Sstevel@tonic-gate 	DBG(DBG_LIB_INT, dip, "px_lib_intr_getstate: intr_state 0x%x\n",
3397c478bd9Sstevel@tonic-gate 	    *intr_state);
3407c478bd9Sstevel@tonic-gate 
3417c478bd9Sstevel@tonic-gate 	return (DDI_SUCCESS);
3427c478bd9Sstevel@tonic-gate }
3437c478bd9Sstevel@tonic-gate 
3447c478bd9Sstevel@tonic-gate /*ARGSUSED*/
3457c478bd9Sstevel@tonic-gate int
px_lib_intr_setstate(dev_info_t * dip,sysino_t sysino,intr_state_t intr_state)3467c478bd9Sstevel@tonic-gate px_lib_intr_setstate(dev_info_t *dip, sysino_t sysino,
3477c478bd9Sstevel@tonic-gate     intr_state_t intr_state)
3487c478bd9Sstevel@tonic-gate {
3497c478bd9Sstevel@tonic-gate 	uint64_t	ret;
3507c478bd9Sstevel@tonic-gate 
3517c478bd9Sstevel@tonic-gate 	DBG(DBG_LIB_INT, dip, "px_lib_intr_setstate: dip 0x%p sysino 0x%llx "
3527c478bd9Sstevel@tonic-gate 	    "intr_state 0x%x\n", dip, sysino, intr_state);
3537c478bd9Sstevel@tonic-gate 
3547c478bd9Sstevel@tonic-gate 	if ((ret = hvio_intr_setstate(sysino, intr_state)) != H_EOK) {
3557c478bd9Sstevel@tonic-gate 		DBG(DBG_LIB_INT, dip, "hvio_intr_setstate failed, ret 0x%lx\n",
3567c478bd9Sstevel@tonic-gate 		    ret);
3577c478bd9Sstevel@tonic-gate 		return (DDI_FAILURE);
3587c478bd9Sstevel@tonic-gate 	}
3597c478bd9Sstevel@tonic-gate 
3607c478bd9Sstevel@tonic-gate 	return (DDI_SUCCESS);
3617c478bd9Sstevel@tonic-gate }
3627c478bd9Sstevel@tonic-gate 
3637c478bd9Sstevel@tonic-gate /*ARGSUSED*/
3647c478bd9Sstevel@tonic-gate int
px_lib_intr_gettarget(dev_info_t * dip,sysino_t sysino,cpuid_t * cpuid)3657c478bd9Sstevel@tonic-gate px_lib_intr_gettarget(dev_info_t *dip, sysino_t sysino, cpuid_t *cpuid)
3667c478bd9Sstevel@tonic-gate {
3677c478bd9Sstevel@tonic-gate 	uint64_t	ret;
3687c478bd9Sstevel@tonic-gate 
3697c478bd9Sstevel@tonic-gate 	DBG(DBG_LIB_INT, dip, "px_lib_intr_gettarget: dip 0x%p sysino 0x%llx\n",
3707c478bd9Sstevel@tonic-gate 	    dip, sysino);
3717c478bd9Sstevel@tonic-gate 
3727c478bd9Sstevel@tonic-gate 	if ((ret = hvio_intr_gettarget(sysino, cpuid)) != H_EOK) {
3737c478bd9Sstevel@tonic-gate 		DBG(DBG_LIB_INT, dip,
3747c478bd9Sstevel@tonic-gate 		    "hvio_intr_gettarget failed, ret 0x%lx\n", ret);
3757c478bd9Sstevel@tonic-gate 		return (DDI_FAILURE);
3767c478bd9Sstevel@tonic-gate 	}
3777c478bd9Sstevel@tonic-gate 
37809b1eac2SEvan Yan 	DBG(DBG_LIB_INT, dip, "px_lib_intr_gettarget: cpuid 0x%x\n", *cpuid);
3797c478bd9Sstevel@tonic-gate 
3807c478bd9Sstevel@tonic-gate 	return (DDI_SUCCESS);
3817c478bd9Sstevel@tonic-gate }
3827c478bd9Sstevel@tonic-gate 
3837c478bd9Sstevel@tonic-gate /*ARGSUSED*/
3847c478bd9Sstevel@tonic-gate int
px_lib_intr_settarget(dev_info_t * dip,sysino_t sysino,cpuid_t cpuid)3857c478bd9Sstevel@tonic-gate px_lib_intr_settarget(dev_info_t *dip, sysino_t sysino, cpuid_t cpuid)
3867c478bd9Sstevel@tonic-gate {
3877c478bd9Sstevel@tonic-gate 	uint64_t	ret;
3887c478bd9Sstevel@tonic-gate 
3897c478bd9Sstevel@tonic-gate 	DBG(DBG_LIB_INT, dip, "px_lib_intr_settarget: dip 0x%p sysino 0x%llx "
3907c478bd9Sstevel@tonic-gate 	    "cpuid 0x%x\n", dip, sysino, cpuid);
3917c478bd9Sstevel@tonic-gate 
392d8d130aeSanbui 	ret = hvio_intr_settarget(sysino, cpuid);
393d8d130aeSanbui 	if (ret == H_ECPUERROR) {
394d8d130aeSanbui 		cmn_err(CE_PANIC,
395d8d130aeSanbui 		    "px_lib_intr_settarget: hvio_intr_settarget failed, "
396d8d130aeSanbui 		    "ret = 0x%lx, cpuid = 0x%x, sysino = 0x%lx\n", ret,
397d8d130aeSanbui 		    cpuid, sysino);
398d8d130aeSanbui 	} else if (ret != H_EOK) {
3997c478bd9Sstevel@tonic-gate 		DBG(DBG_LIB_INT, dip,
4007c478bd9Sstevel@tonic-gate 		    "hvio_intr_settarget failed, ret 0x%lx\n", ret);
4017c478bd9Sstevel@tonic-gate 		return (DDI_FAILURE);
4027c478bd9Sstevel@tonic-gate 	}
4037c478bd9Sstevel@tonic-gate 
4047c478bd9Sstevel@tonic-gate 	return (DDI_SUCCESS);
4057c478bd9Sstevel@tonic-gate }
4067c478bd9Sstevel@tonic-gate 
4077c478bd9Sstevel@tonic-gate /*ARGSUSED*/
4087c478bd9Sstevel@tonic-gate int
px_lib_intr_reset(dev_info_t * dip)4097c478bd9Sstevel@tonic-gate px_lib_intr_reset(dev_info_t *dip)
4107c478bd9Sstevel@tonic-gate {
411b0fc0e77Sgovinda 	px_t		*px_p = DIP_TO_STATE(dip);
412b0fc0e77Sgovinda 	px_ib_t		*ib_p = px_p->px_ib_p;
413b0fc0e77Sgovinda 	px_ino_t	*ino_p;
4149c75c6bfSgovinda 
4157c478bd9Sstevel@tonic-gate 	DBG(DBG_LIB_INT, dip, "px_lib_intr_reset: dip 0x%p\n", dip);
4167c478bd9Sstevel@tonic-gate 
4179c75c6bfSgovinda 	mutex_enter(&ib_p->ib_ino_lst_mutex);
4189c75c6bfSgovinda 
4199c75c6bfSgovinda 	/* Reset all Interrupts */
420b0fc0e77Sgovinda 	for (ino_p = ib_p->ib_ino_lst; ino_p; ino_p = ino_p->ino_next_p) {
4219c75c6bfSgovinda 		if (px_lib_intr_setstate(dip, ino_p->ino_sysino,
4229c75c6bfSgovinda 		    INTR_IDLE_STATE) != DDI_SUCCESS)
4239c75c6bfSgovinda 			return (BF_FATAL);
4249c75c6bfSgovinda 	}
4259c75c6bfSgovinda 
4269c75c6bfSgovinda 	mutex_exit(&ib_p->ib_ino_lst_mutex);
4279c75c6bfSgovinda 
4289c75c6bfSgovinda 	return (BF_NONE);
4297c478bd9Sstevel@tonic-gate }
4307c478bd9Sstevel@tonic-gate 
4317c478bd9Sstevel@tonic-gate /*ARGSUSED*/
4327c478bd9Sstevel@tonic-gate int
px_lib_iommu_map(dev_info_t * dip,tsbid_t tsbid,pages_t pages,io_attributes_t attr,void * addr,size_t pfn_index,int flags)4337c478bd9Sstevel@tonic-gate px_lib_iommu_map(dev_info_t *dip, tsbid_t tsbid, pages_t pages,
43444bb982bSgovinda     io_attributes_t attr, void *addr, size_t pfn_index, int flags)
4357c478bd9Sstevel@tonic-gate {
4367c478bd9Sstevel@tonic-gate 	tsbnum_t	tsb_num = PCI_TSBID_TO_TSBNUM(tsbid);
4375bc7e870Sgovinda 	tsbindex_t	tsb_index = PCI_TSBID_TO_TSBINDEX(tsbid);
4385bc7e870Sgovinda 	io_page_list_t	*pfns, *pfn_p;
4395bc7e870Sgovinda 	pages_t		ttes_mapped = 0;
4407c478bd9Sstevel@tonic-gate 	int		i, err = DDI_SUCCESS;
4417c478bd9Sstevel@tonic-gate 
4427c478bd9Sstevel@tonic-gate 	DBG(DBG_LIB_DMA, dip, "px_lib_iommu_map: dip 0x%p tsbid 0x%llx "
443ef2504f2SDaniel Ice 	    "pages 0x%x attr 0x%llx addr 0x%p pfn_index 0x%llx flags 0x%x\n",
44444bb982bSgovinda 	    dip, tsbid, pages, attr, addr, pfn_index, flags);
4457c478bd9Sstevel@tonic-gate 
4465bc7e870Sgovinda 	if ((pfns = pfn_p = kmem_zalloc((pages * sizeof (io_page_list_t)),
4477c478bd9Sstevel@tonic-gate 	    KM_NOSLEEP)) == NULL) {
4487c478bd9Sstevel@tonic-gate 		DBG(DBG_LIB_DMA, dip, "px_lib_iommu_map: kmem_zalloc failed\n");
4497c478bd9Sstevel@tonic-gate 		return (DDI_FAILURE);
4507c478bd9Sstevel@tonic-gate 	}
4517c478bd9Sstevel@tonic-gate 
4525bc7e870Sgovinda 	for (i = 0; i < pages; i++)
45344bb982bSgovinda 		pfns[i] = MMU_PTOB(PX_ADDR2PFN(addr, pfn_index, flags, i));
4545bc7e870Sgovinda 
4555a40150bSam 	/*
4563d78e6abSAlan Adamson, SD OSSD 	 * If HV VPCI version is 2.0 and higher, pass BDF, phantom function,
45744961713Sgirish 	 * and relaxed ordering attributes. Otherwise, pass only read or write
45844961713Sgirish 	 * attribute.
4595a40150bSam 	 */
4603d78e6abSAlan Adamson, SD OSSD 	if ((px_vpci_maj_ver == PX_HSVC_MAJOR_VER_1) &&
4613d78e6abSAlan Adamson, SD OSSD 	    (px_vpci_min_ver == PX_HSVC_MINOR_VER_0))
4625a40150bSam 		attr = attr & (PCI_MAP_ATTR_READ | PCI_MAP_ATTR_WRITE);
4635a40150bSam 
4645bc7e870Sgovinda 	while ((ttes_mapped = pfn_p - pfns) < pages) {
4655bc7e870Sgovinda 		uintptr_t	ra = va_to_pa(pfn_p);
4665bc7e870Sgovinda 		pages_t		ttes2map;
4675bc7e870Sgovinda 		uint64_t	ret;
4685bc7e870Sgovinda 
4695bc7e870Sgovinda 		ttes2map = (MMU_PAGE_SIZE - P2PHASE(ra, MMU_PAGE_SIZE)) >> 3;
4705bc7e870Sgovinda 		ra = MMU_PTOB(MMU_BTOP(ra));
4715bc7e870Sgovinda 
4725bc7e870Sgovinda 		for (ttes2map = MIN(ttes2map, pages - ttes_mapped); ttes2map;
4735bc7e870Sgovinda 		    ttes2map -= ttes_mapped, pfn_p += ttes_mapped) {
4745bc7e870Sgovinda 
4755bc7e870Sgovinda 			ttes_mapped = 0;
4765bc7e870Sgovinda 			if ((ret = hvio_iommu_map(DIP_TO_HANDLE(dip),
4775bc7e870Sgovinda 			    PCI_TSBID(tsb_num, tsb_index + (pfn_p - pfns)),
47844bb982bSgovinda 			    ttes2map, attr, (io_page_list_t *)(ra |
4795bc7e870Sgovinda 			    ((uintptr_t)pfn_p & MMU_PAGE_OFFSET)),
4805bc7e870Sgovinda 			    &ttes_mapped)) != H_EOK) {
4815bc7e870Sgovinda 				DBG(DBG_LIB_DMA, dip, "hvio_iommu_map failed "
4825bc7e870Sgovinda 				    "ret 0x%lx\n", ret);
4835bc7e870Sgovinda 
4845bc7e870Sgovinda 				ttes_mapped = pfn_p - pfns;
4855bc7e870Sgovinda 				err = DDI_FAILURE;
4865bc7e870Sgovinda 				goto cleanup;
4875bc7e870Sgovinda 			}
4885bc7e870Sgovinda 
4895bc7e870Sgovinda 			DBG(DBG_LIB_DMA, dip, "px_lib_iommu_map: tsb_num 0x%x "
490ef2504f2SDaniel Ice 			    "tsb_index 0x%lx ttes_to_map 0x%lx attr 0x%llx "
4915bc7e870Sgovinda 			    "ra 0x%p ttes_mapped 0x%x\n", tsb_num,
49244bb982bSgovinda 			    tsb_index + (pfn_p - pfns), ttes2map, attr,
4935bc7e870Sgovinda 			    ra | ((uintptr_t)pfn_p & MMU_PAGE_OFFSET),
4945bc7e870Sgovinda 			    ttes_mapped);
4957c478bd9Sstevel@tonic-gate 		}
4967c478bd9Sstevel@tonic-gate 	}
4977c478bd9Sstevel@tonic-gate 
4985bc7e870Sgovinda cleanup:
4995bc7e870Sgovinda 	if ((err == DDI_FAILURE) && ttes_mapped)
5005bc7e870Sgovinda 		(void) px_lib_iommu_demap(dip, tsbid, ttes_mapped);
5017c478bd9Sstevel@tonic-gate 
5025bc7e870Sgovinda 	kmem_free(pfns, pages * sizeof (io_page_list_t));
5037c478bd9Sstevel@tonic-gate 	return (err);
5047c478bd9Sstevel@tonic-gate }
5057c478bd9Sstevel@tonic-gate 
5067c478bd9Sstevel@tonic-gate /*ARGSUSED*/
5077c478bd9Sstevel@tonic-gate int
px_lib_iommu_demap(dev_info_t * dip,tsbid_t tsbid,pages_t pages)5087c478bd9Sstevel@tonic-gate px_lib_iommu_demap(dev_info_t *dip, tsbid_t tsbid, pages_t pages)
5097c478bd9Sstevel@tonic-gate {
5107c478bd9Sstevel@tonic-gate 	tsbnum_t	tsb_num = PCI_TSBID_TO_TSBNUM(tsbid);
5115bc7e870Sgovinda 	tsbindex_t	tsb_index = PCI_TSBID_TO_TSBINDEX(tsbid);
5125bc7e870Sgovinda 	pages_t		ttes2demap, ttes_demapped = 0;
5137c478bd9Sstevel@tonic-gate 	uint64_t	ret;
5147c478bd9Sstevel@tonic-gate 
5157c478bd9Sstevel@tonic-gate 	DBG(DBG_LIB_DMA, dip, "px_lib_iommu_demap: dip 0x%p tsbid 0x%llx "
5167c478bd9Sstevel@tonic-gate 	    "pages 0x%x\n", dip, tsbid, pages);
5177c478bd9Sstevel@tonic-gate 
5185bc7e870Sgovinda 	for (ttes2demap = pages; ttes2demap;
5195bc7e870Sgovinda 	    ttes2demap -= ttes_demapped, tsb_index += ttes_demapped) {
5207c478bd9Sstevel@tonic-gate 		if ((ret = hvio_iommu_demap(DIP_TO_HANDLE(dip),
5215bc7e870Sgovinda 		    PCI_TSBID(tsb_num, tsb_index), ttes2demap,
5225bc7e870Sgovinda 		    &ttes_demapped)) != H_EOK) {
5235bc7e870Sgovinda 			DBG(DBG_LIB_DMA, dip, "hvio_iommu_demap failed, "
5245bc7e870Sgovinda 			    "ret 0x%lx\n", ret);
5255bc7e870Sgovinda 
5267c478bd9Sstevel@tonic-gate 			return (DDI_FAILURE);
5277c478bd9Sstevel@tonic-gate 		}
5287c478bd9Sstevel@tonic-gate 
5295bc7e870Sgovinda 		DBG(DBG_LIB_DMA, dip, "px_lib_iommu_demap: tsb_num 0x%x "
5305bc7e870Sgovinda 		    "tsb_index 0x%lx ttes_to_demap 0x%lx ttes_demapped 0x%x\n",
5315bc7e870Sgovinda 		    tsb_num, tsb_index, ttes2demap, ttes_demapped);
5327c478bd9Sstevel@tonic-gate 	}
5337c478bd9Sstevel@tonic-gate 
5347c478bd9Sstevel@tonic-gate 	return (DDI_SUCCESS);
5357c478bd9Sstevel@tonic-gate }
5367c478bd9Sstevel@tonic-gate 
5377c478bd9Sstevel@tonic-gate /*ARGSUSED*/
5387c478bd9Sstevel@tonic-gate int
px_lib_iommu_getmap(dev_info_t * dip,tsbid_t tsbid,io_attributes_t * attr_p,r_addr_t * r_addr_p)53944bb982bSgovinda px_lib_iommu_getmap(dev_info_t *dip, tsbid_t tsbid, io_attributes_t *attr_p,
54044bb982bSgovinda     r_addr_t *r_addr_p)
5417c478bd9Sstevel@tonic-gate {
5427c478bd9Sstevel@tonic-gate 	uint64_t	ret;
5437c478bd9Sstevel@tonic-gate 
5447c478bd9Sstevel@tonic-gate 	DBG(DBG_LIB_DMA, dip, "px_lib_iommu_getmap: dip 0x%p tsbid 0x%llx\n",
5457c478bd9Sstevel@tonic-gate 	    dip, tsbid);
5467c478bd9Sstevel@tonic-gate 
5477c478bd9Sstevel@tonic-gate 	if ((ret = hvio_iommu_getmap(DIP_TO_HANDLE(dip), tsbid,
54844bb982bSgovinda 	    attr_p, r_addr_p)) != H_EOK) {
5497c478bd9Sstevel@tonic-gate 		DBG(DBG_LIB_DMA, dip,
5507c478bd9Sstevel@tonic-gate 		    "hvio_iommu_getmap failed, ret 0x%lx\n", ret);
5517c478bd9Sstevel@tonic-gate 
5527c478bd9Sstevel@tonic-gate 		return ((ret == H_ENOMAP) ? DDI_DMA_NOMAPPING:DDI_FAILURE);
5537c478bd9Sstevel@tonic-gate 	}
5547c478bd9Sstevel@tonic-gate 
555ef2504f2SDaniel Ice 	DBG(DBG_LIB_DMA, dip, "px_lib_iommu_getmap: attr 0x%llx "
556ef2504f2SDaniel Ice 	    "r_addr 0x%llx\n", *attr_p, *r_addr_p);
5577c478bd9Sstevel@tonic-gate 
5587c478bd9Sstevel@tonic-gate 	return (DDI_SUCCESS);
5597c478bd9Sstevel@tonic-gate }
5607c478bd9Sstevel@tonic-gate 
56189b42a21Sandrew.rutz@sun.com /*ARGSUSED*/
56289b42a21Sandrew.rutz@sun.com int
px_lib_iommu_detach(px_t * px_p)56389b42a21Sandrew.rutz@sun.com px_lib_iommu_detach(px_t *px_p)
56489b42a21Sandrew.rutz@sun.com {
56589b42a21Sandrew.rutz@sun.com 	return (DDI_SUCCESS);
56689b42a21Sandrew.rutz@sun.com }
56789b42a21Sandrew.rutz@sun.com 
56825cf1a30Sjl /*ARGSUSED*/
56925cf1a30Sjl uint64_t
px_get_rng_parent_hi_mask(px_t * px_p)570d3533785Sschwartz px_get_rng_parent_hi_mask(px_t *px_p)
57125cf1a30Sjl {
572d3533785Sschwartz 	return (PX_RANGE_PROP_MASK);
57325cf1a30Sjl }
5747c478bd9Sstevel@tonic-gate 
5757c478bd9Sstevel@tonic-gate /*
5767c478bd9Sstevel@tonic-gate  * Checks dma attributes against system bypass ranges
5777c478bd9Sstevel@tonic-gate  * A sun4v device must be capable of generating the entire 64-bit
5787c478bd9Sstevel@tonic-gate  * address in order to perform bypass DMA.
5797c478bd9Sstevel@tonic-gate  */
5807c478bd9Sstevel@tonic-gate /*ARGSUSED*/
5817c478bd9Sstevel@tonic-gate int
px_lib_dma_bypass_rngchk(dev_info_t * dip,ddi_dma_attr_t * attr_p,uint64_t * lo_p,uint64_t * hi_p)58225cf1a30Sjl px_lib_dma_bypass_rngchk(dev_info_t *dip, ddi_dma_attr_t *attr_p,
58325cf1a30Sjl     uint64_t *lo_p, uint64_t *hi_p)
5847c478bd9Sstevel@tonic-gate {
58544bb982bSgovinda 	if ((attr_p->dma_attr_addr_lo != 0ull) ||
58644bb982bSgovinda 	    (attr_p->dma_attr_addr_hi != UINT64_MAX)) {
5877c478bd9Sstevel@tonic-gate 
5887c478bd9Sstevel@tonic-gate 		return (DDI_DMA_BADATTR);
5897c478bd9Sstevel@tonic-gate 	}
5907c478bd9Sstevel@tonic-gate 
5917c478bd9Sstevel@tonic-gate 	*lo_p = 0ull;
5927c478bd9Sstevel@tonic-gate 	*hi_p = UINT64_MAX;
5937c478bd9Sstevel@tonic-gate 
5947c478bd9Sstevel@tonic-gate 	return (DDI_SUCCESS);
5957c478bd9Sstevel@tonic-gate }
5967c478bd9Sstevel@tonic-gate 
5977c478bd9Sstevel@tonic-gate 
5987c478bd9Sstevel@tonic-gate /*ARGSUSED*/
5997c478bd9Sstevel@tonic-gate int
px_lib_iommu_getbypass(dev_info_t * dip,r_addr_t ra,io_attributes_t attr,io_addr_t * io_addr_p)60044bb982bSgovinda px_lib_iommu_getbypass(dev_info_t *dip, r_addr_t ra, io_attributes_t attr,
60144bb982bSgovinda     io_addr_t *io_addr_p)
6027c478bd9Sstevel@tonic-gate {
6037c478bd9Sstevel@tonic-gate 	uint64_t	ret;
6047c478bd9Sstevel@tonic-gate 
6057c478bd9Sstevel@tonic-gate 	DBG(DBG_LIB_DMA, dip, "px_lib_iommu_getbypass: dip 0x%p ra 0x%llx "
606ef2504f2SDaniel Ice 	    "attr 0x%llx\n", dip, ra, attr);
6076142aa70Sandrew.rutz@sun.com 	/*
6083d78e6abSAlan Adamson, SD OSSD 	 * If HV VPCI version is 2.0 and higher, pass BDF, phantom function,
6096142aa70Sandrew.rutz@sun.com 	 * and relaxed ordering attributes. Otherwise, pass only read or write
6106142aa70Sandrew.rutz@sun.com 	 * attribute.
6116142aa70Sandrew.rutz@sun.com 	 */
6123d78e6abSAlan Adamson, SD OSSD 	if ((px_vpci_maj_ver == PX_HSVC_MAJOR_VER_1) &&
6133d78e6abSAlan Adamson, SD OSSD 	    (px_vpci_min_ver == PX_HSVC_MINOR_VER_0))
6146142aa70Sandrew.rutz@sun.com 		attr &= PCI_MAP_ATTR_READ | PCI_MAP_ATTR_WRITE;
6157c478bd9Sstevel@tonic-gate 
6167c478bd9Sstevel@tonic-gate 	if ((ret = hvio_iommu_getbypass(DIP_TO_HANDLE(dip), ra,
61744bb982bSgovinda 	    attr, io_addr_p)) != H_EOK) {
6187c478bd9Sstevel@tonic-gate 		DBG(DBG_LIB_DMA, dip,
6197c478bd9Sstevel@tonic-gate 		    "hvio_iommu_getbypass failed, ret 0x%lx\n", ret);
6207c478bd9Sstevel@tonic-gate 		return (ret == H_ENOTSUPPORTED ? DDI_ENOTSUP : DDI_FAILURE);
6217c478bd9Sstevel@tonic-gate 	}
6227c478bd9Sstevel@tonic-gate 
6237c478bd9Sstevel@tonic-gate 	DBG(DBG_LIB_DMA, dip, "px_lib_iommu_getbypass: io_addr 0x%llx\n",
6247c478bd9Sstevel@tonic-gate 	    *io_addr_p);
6257c478bd9Sstevel@tonic-gate 
6267c478bd9Sstevel@tonic-gate 	return (DDI_SUCCESS);
6277c478bd9Sstevel@tonic-gate }
6287c478bd9Sstevel@tonic-gate 
629a616a11eSLida.Horn /*
630a616a11eSLida.Horn  * Returns any needed IO address bit(s) for relaxed ordering in IOMMU
631a616a11eSLida.Horn  * bypass mode.
632a616a11eSLida.Horn  */
633a616a11eSLida.Horn /* ARGSUSED */
634a616a11eSLida.Horn uint64_t
px_lib_ro_bypass(dev_info_t * dip,io_attributes_t attr,uint64_t ioaddr)635a616a11eSLida.Horn px_lib_ro_bypass(dev_info_t *dip, io_attributes_t attr, uint64_t ioaddr)
636a616a11eSLida.Horn {
637a616a11eSLida.Horn 	return (ioaddr);
638a616a11eSLida.Horn }
639a616a11eSLida.Horn 
6407c478bd9Sstevel@tonic-gate /*ARGSUSED*/
6417c478bd9Sstevel@tonic-gate int
px_lib_dma_sync(dev_info_t * dip,dev_info_t * rdip,ddi_dma_handle_t handle,off_t off,size_t len,uint_t cache_flags)6427c478bd9Sstevel@tonic-gate px_lib_dma_sync(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle,
643*d5ebc493SDan Cross     off_t off, size_t len, uint_t cache_flags)
6447c478bd9Sstevel@tonic-gate {
6457c478bd9Sstevel@tonic-gate 	ddi_dma_impl_t *mp = (ddi_dma_impl_t *)handle;
6467c478bd9Sstevel@tonic-gate 	uint64_t sync_dir;
64722bbbd20Saa 	size_t bytes_synced;
64822bbbd20Saa 	int end, idx;
64922bbbd20Saa 	off_t pg_off;
65022bbbd20Saa 	devhandle_t hdl = DIP_TO_HANDLE(dip); /* need to cache hdl */
6517c478bd9Sstevel@tonic-gate 
6527c478bd9Sstevel@tonic-gate 	DBG(DBG_LIB_DMA, dip, "px_lib_dma_sync: dip 0x%p rdip 0x%p "
6537c478bd9Sstevel@tonic-gate 	    "handle 0x%llx off 0x%x len 0x%x flags 0x%x\n",
6547c478bd9Sstevel@tonic-gate 	    dip, rdip, handle, off, len, cache_flags);
6557c478bd9Sstevel@tonic-gate 
65636fe4a92Segillett 	if (!(mp->dmai_flags & PX_DMAI_FLAGS_INUSE)) {
657f8d2de6bSjchu 		cmn_err(CE_WARN, "%s%d: Unbound dma handle %p.",
658f8d2de6bSjchu 		    ddi_driver_name(rdip), ddi_get_instance(rdip), (void *)mp);
6597c478bd9Sstevel@tonic-gate 		return (DDI_FAILURE);
6607c478bd9Sstevel@tonic-gate 	}
6617c478bd9Sstevel@tonic-gate 
66236fe4a92Segillett 	if (mp->dmai_flags & PX_DMAI_FLAGS_NOSYNC)
6637c478bd9Sstevel@tonic-gate 		return (DDI_SUCCESS);
6647c478bd9Sstevel@tonic-gate 
6657c478bd9Sstevel@tonic-gate 	if (!len)
6667c478bd9Sstevel@tonic-gate 		len = mp->dmai_size;
6677c478bd9Sstevel@tonic-gate 
6687c478bd9Sstevel@tonic-gate 	if (mp->dmai_rflags & DDI_DMA_READ)
6697c478bd9Sstevel@tonic-gate 		sync_dir = HVIO_DMA_SYNC_DIR_FROM_DEV;
6707c478bd9Sstevel@tonic-gate 	else
6717c478bd9Sstevel@tonic-gate 		sync_dir = HVIO_DMA_SYNC_DIR_TO_DEV;
6727c478bd9Sstevel@tonic-gate 
67322bbbd20Saa 	off += mp->dmai_offset;
67422bbbd20Saa 	pg_off = off & MMU_PAGEOFFSET;
67522bbbd20Saa 
67622bbbd20Saa 	DBG(DBG_LIB_DMA, dip, "px_lib_dma_sync: page offset %x size %x\n",
67722bbbd20Saa 	    pg_off, len);
67822bbbd20Saa 
67922bbbd20Saa 	/* sync on page basis */
68022bbbd20Saa 	end = MMU_BTOPR(off + len - 1);
68122bbbd20Saa 	for (idx = MMU_BTOP(off); idx < end; idx++,
68222bbbd20Saa 	    len -= bytes_synced, pg_off = 0) {
6839d0d62adSJason Beloro 		size_t bytes_to_sync = bytes_to_sync =
6849d0d62adSJason Beloro 		    MIN(len, MMU_PAGESIZE - pg_off);
68522bbbd20Saa 
6869d0d62adSJason Beloro 		if (hvio_dma_sync(hdl, MMU_PTOB(PX_GET_MP_PFN(mp, idx)) +
6879d0d62adSJason Beloro 		    pg_off, bytes_to_sync, sync_dir, &bytes_synced) != H_EOK)
6889d0d62adSJason Beloro 			break;
68922bbbd20Saa 
69022bbbd20Saa 		DBG(DBG_LIB_DMA, dip, "px_lib_dma_sync: Called hvio_dma_sync "
69122bbbd20Saa 		    "ra = %p bytes to sync = %x bytes synced %x\n",
69222bbbd20Saa 		    MMU_PTOB(PX_GET_MP_PFN(mp, idx)) + pg_off, bytes_to_sync,
69322bbbd20Saa 		    bytes_synced);
69422bbbd20Saa 
69522bbbd20Saa 		if (bytes_to_sync != bytes_synced)
69622bbbd20Saa 			break;
6977c478bd9Sstevel@tonic-gate 	}
6987c478bd9Sstevel@tonic-gate 
69922bbbd20Saa 	return (len ? DDI_FAILURE : DDI_SUCCESS);
7007c478bd9Sstevel@tonic-gate }
7017c478bd9Sstevel@tonic-gate 
7027c478bd9Sstevel@tonic-gate 
7037c478bd9Sstevel@tonic-gate /*
7047c478bd9Sstevel@tonic-gate  * MSIQ Functions:
7057c478bd9Sstevel@tonic-gate  */
7067c478bd9Sstevel@tonic-gate 
7077c478bd9Sstevel@tonic-gate /*ARGSUSED*/
7087c478bd9Sstevel@tonic-gate int
px_lib_msiq_init(dev_info_t * dip)7097c478bd9Sstevel@tonic-gate px_lib_msiq_init(dev_info_t *dip)
7107c478bd9Sstevel@tonic-gate {
7117c478bd9Sstevel@tonic-gate 	px_t		*px_p = DIP_TO_STATE(dip);
7127c478bd9Sstevel@tonic-gate 	px_msiq_state_t	*msiq_state_p = &px_p->px_ib_p->ib_msiq_state;
71395003185Segillett 	r_addr_t	ra;
7147c478bd9Sstevel@tonic-gate 	size_t		msiq_size;
7157c478bd9Sstevel@tonic-gate 	uint_t		rec_cnt;
7167c478bd9Sstevel@tonic-gate 	int		i, err = DDI_SUCCESS;
7177c478bd9Sstevel@tonic-gate 	uint64_t	ret;
7187c478bd9Sstevel@tonic-gate 
7197c478bd9Sstevel@tonic-gate 	DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_init: dip 0x%p\n", dip);
7207c478bd9Sstevel@tonic-gate 
7217c478bd9Sstevel@tonic-gate 	msiq_size = msiq_state_p->msiq_rec_cnt * sizeof (msiq_rec_t);
7227c478bd9Sstevel@tonic-gate 
723348fdf9eSAlan Adamson, SD OSSD 	/* sun4v requires all EQ allocation to be on q size boundary */
724348fdf9eSAlan Adamson, SD OSSD 	if ((msiq_state_p->msiq_buf_p = contig_mem_alloc_align(
725348fdf9eSAlan Adamson, SD OSSD 	    msiq_state_p->msiq_cnt * msiq_size, msiq_size)) == NULL) {
726348fdf9eSAlan Adamson, SD OSSD 		DBG(DBG_LIB_MSIQ, dip,
727348fdf9eSAlan Adamson, SD OSSD 		    "px_lib_msiq_init: Contig alloc failed\n");
728348fdf9eSAlan Adamson, SD OSSD 
729348fdf9eSAlan Adamson, SD OSSD 		return (DDI_FAILURE);
730348fdf9eSAlan Adamson, SD OSSD 	}
731348fdf9eSAlan Adamson, SD OSSD 
7327c478bd9Sstevel@tonic-gate 	for (i = 0; i < msiq_state_p->msiq_cnt; i++) {
733348fdf9eSAlan Adamson, SD OSSD 		msiq_state_p->msiq_p[i].msiq_base_p = (msiqhead_t *)
734348fdf9eSAlan Adamson, SD OSSD 		    ((caddr_t)msiq_state_p->msiq_buf_p + (i * msiq_size));
735348fdf9eSAlan Adamson, SD OSSD 
73695003185Segillett 		ra = (r_addr_t)va_to_pa((caddr_t)msiq_state_p->msiq_buf_p +
73795003185Segillett 		    (i * msiq_size));
7387c478bd9Sstevel@tonic-gate 
7397c478bd9Sstevel@tonic-gate 		if ((ret = hvio_msiq_conf(DIP_TO_HANDLE(dip),
7407c478bd9Sstevel@tonic-gate 		    (i + msiq_state_p->msiq_1st_msiq_id),
7417c478bd9Sstevel@tonic-gate 		    ra, msiq_state_p->msiq_rec_cnt)) != H_EOK) {
7427c478bd9Sstevel@tonic-gate 			DBG(DBG_LIB_MSIQ, dip,
7437c478bd9Sstevel@tonic-gate 			    "hvio_msiq_conf failed, ret 0x%lx\n", ret);
7447c478bd9Sstevel@tonic-gate 			err = DDI_FAILURE;
7457c478bd9Sstevel@tonic-gate 			break;
7467c478bd9Sstevel@tonic-gate 		}
7477c478bd9Sstevel@tonic-gate 
7487c478bd9Sstevel@tonic-gate 		if ((err = px_lib_msiq_info(dip,
7497c478bd9Sstevel@tonic-gate 		    (i + msiq_state_p->msiq_1st_msiq_id),
7507c478bd9Sstevel@tonic-gate 		    &ra, &rec_cnt)) != DDI_SUCCESS) {
7517c478bd9Sstevel@tonic-gate 			DBG(DBG_LIB_MSIQ, dip,
7527c478bd9Sstevel@tonic-gate 			    "px_lib_msiq_info failed, ret 0x%x\n", err);
7537c478bd9Sstevel@tonic-gate 			err = DDI_FAILURE;
7547c478bd9Sstevel@tonic-gate 			break;
7557c478bd9Sstevel@tonic-gate 		}
7567c478bd9Sstevel@tonic-gate 
7577c478bd9Sstevel@tonic-gate 		DBG(DBG_LIB_MSIQ, dip,
7587c478bd9Sstevel@tonic-gate 		    "px_lib_msiq_init: ra 0x%p rec_cnt 0x%x\n", ra, rec_cnt);
7597c478bd9Sstevel@tonic-gate 	}
7607c478bd9Sstevel@tonic-gate 
7617c478bd9Sstevel@tonic-gate 	return (err);
7627c478bd9Sstevel@tonic-gate }
7637c478bd9Sstevel@tonic-gate 
7647c478bd9Sstevel@tonic-gate /*ARGSUSED*/
7657c478bd9Sstevel@tonic-gate int
px_lib_msiq_fini(dev_info_t * dip)7667c478bd9Sstevel@tonic-gate px_lib_msiq_fini(dev_info_t *dip)
7677c478bd9Sstevel@tonic-gate {
768348fdf9eSAlan Adamson, SD OSSD 	px_t		*px_p = DIP_TO_STATE(dip);
769348fdf9eSAlan Adamson, SD OSSD 	px_msiq_state_t	*msiq_state_p = &px_p->px_ib_p->ib_msiq_state;
770348fdf9eSAlan Adamson, SD OSSD 	size_t		msiq_size;
771348fdf9eSAlan Adamson, SD OSSD 
7727c478bd9Sstevel@tonic-gate 	DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_fini: dip 0x%p\n", dip);
773348fdf9eSAlan Adamson, SD OSSD 	msiq_size = msiq_state_p->msiq_rec_cnt * sizeof (msiq_rec_t);
774348fdf9eSAlan Adamson, SD OSSD 
775348fdf9eSAlan Adamson, SD OSSD 	if (msiq_state_p->msiq_buf_p != NULL)
776348fdf9eSAlan Adamson, SD OSSD 		contig_mem_free(msiq_state_p->msiq_buf_p,
777348fdf9eSAlan Adamson, SD OSSD 		    msiq_state_p->msiq_cnt * msiq_size);
7787c478bd9Sstevel@tonic-gate 
7797c478bd9Sstevel@tonic-gate 	return (DDI_SUCCESS);
7807c478bd9Sstevel@tonic-gate }
7817c478bd9Sstevel@tonic-gate 
7827c478bd9Sstevel@tonic-gate /*ARGSUSED*/
7837c478bd9Sstevel@tonic-gate int
px_lib_msiq_info(dev_info_t * dip,msiqid_t msiq_id,r_addr_t * ra_p,uint_t * msiq_rec_cnt_p)7847c478bd9Sstevel@tonic-gate px_lib_msiq_info(dev_info_t *dip, msiqid_t msiq_id, r_addr_t *ra_p,
7857c478bd9Sstevel@tonic-gate     uint_t *msiq_rec_cnt_p)
7867c478bd9Sstevel@tonic-gate {
7877c478bd9Sstevel@tonic-gate 	uint64_t	ret;
7887c478bd9Sstevel@tonic-gate 
7897c478bd9Sstevel@tonic-gate 	DBG(DBG_LIB_MSIQ, dip, "px_msiq_info: dip 0x%p msiq_id 0x%x\n",
7907c478bd9Sstevel@tonic-gate 	    dip, msiq_id);
7917c478bd9Sstevel@tonic-gate 
7927c478bd9Sstevel@tonic-gate 	if ((ret = hvio_msiq_info(DIP_TO_HANDLE(dip),
7937c478bd9Sstevel@tonic-gate 	    msiq_id, ra_p, msiq_rec_cnt_p)) != H_EOK) {
7947c478bd9Sstevel@tonic-gate 		DBG(DBG_LIB_MSIQ, dip,
7957c478bd9Sstevel@tonic-gate 		    "hvio_msiq_info failed, ret 0x%lx\n", ret);
7967c478bd9Sstevel@tonic-gate 		return (DDI_FAILURE);
7977c478bd9Sstevel@tonic-gate 	}
7987c478bd9Sstevel@tonic-gate 
7997c478bd9Sstevel@tonic-gate 	DBG(DBG_LIB_MSIQ, dip, "px_msiq_info: ra_p 0x%p msiq_rec_cnt 0x%x\n",
8007c478bd9Sstevel@tonic-gate 	    ra_p, *msiq_rec_cnt_p);
8017c478bd9Sstevel@tonic-gate 
8027c478bd9Sstevel@tonic-gate 	return (DDI_SUCCESS);
8037c478bd9Sstevel@tonic-gate }
8047c478bd9Sstevel@tonic-gate 
8057c478bd9Sstevel@tonic-gate /*ARGSUSED*/
8067c478bd9Sstevel@tonic-gate int
px_lib_msiq_getvalid(dev_info_t * dip,msiqid_t msiq_id,pci_msiq_valid_state_t * msiq_valid_state)8077c478bd9Sstevel@tonic-gate px_lib_msiq_getvalid(dev_info_t *dip, msiqid_t msiq_id,
8087c478bd9Sstevel@tonic-gate     pci_msiq_valid_state_t *msiq_valid_state)
8097c478bd9Sstevel@tonic-gate {
8107c478bd9Sstevel@tonic-gate 	uint64_t	ret;
8117c478bd9Sstevel@tonic-gate 
8127c478bd9Sstevel@tonic-gate 	DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_getvalid: dip 0x%p msiq_id 0x%x\n",
8137c478bd9Sstevel@tonic-gate 	    dip, msiq_id);
8147c478bd9Sstevel@tonic-gate 
8157c478bd9Sstevel@tonic-gate 	if ((ret = hvio_msiq_getvalid(DIP_TO_HANDLE(dip),
8167c478bd9Sstevel@tonic-gate 	    msiq_id, msiq_valid_state)) != H_EOK) {
8177c478bd9Sstevel@tonic-gate 		DBG(DBG_LIB_MSIQ, dip,
8187c478bd9Sstevel@tonic-gate 		    "hvio_msiq_getvalid failed, ret 0x%lx\n", ret);
8197c478bd9Sstevel@tonic-gate 		return (DDI_FAILURE);
8207c478bd9Sstevel@tonic-gate 	}
8217c478bd9Sstevel@tonic-gate 
8227c478bd9Sstevel@tonic-gate 	DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_getvalid: msiq_valid_state 0x%x\n",
8237c478bd9Sstevel@tonic-gate 	    *msiq_valid_state);
8247c478bd9Sstevel@tonic-gate 
8257c478bd9Sstevel@tonic-gate 	return (DDI_SUCCESS);
8267c478bd9Sstevel@tonic-gate }
8277c478bd9Sstevel@tonic-gate 
8287c478bd9Sstevel@tonic-gate /*ARGSUSED*/
8297c478bd9Sstevel@tonic-gate int
px_lib_msiq_setvalid(dev_info_t * dip,msiqid_t msiq_id,pci_msiq_valid_state_t msiq_valid_state)8307c478bd9Sstevel@tonic-gate px_lib_msiq_setvalid(dev_info_t *dip, msiqid_t msiq_id,
8317c478bd9Sstevel@tonic-gate     pci_msiq_valid_state_t msiq_valid_state)
8327c478bd9Sstevel@tonic-gate {
8337c478bd9Sstevel@tonic-gate 	uint64_t	ret;
8347c478bd9Sstevel@tonic-gate 
8357c478bd9Sstevel@tonic-gate 	DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_setvalid: dip 0x%p msiq_id 0x%x "
8367c478bd9Sstevel@tonic-gate 	    "msiq_valid_state 0x%x\n", dip, msiq_id, msiq_valid_state);
8377c478bd9Sstevel@tonic-gate 
8387c478bd9Sstevel@tonic-gate 	if ((ret = hvio_msiq_setvalid(DIP_TO_HANDLE(dip),
8397c478bd9Sstevel@tonic-gate 	    msiq_id, msiq_valid_state)) != H_EOK) {
8407c478bd9Sstevel@tonic-gate 		DBG(DBG_LIB_MSIQ, dip,
8417c478bd9Sstevel@tonic-gate 		    "hvio_msiq_setvalid failed, ret 0x%lx\n", ret);
8427c478bd9Sstevel@tonic-gate 		return (DDI_FAILURE);
8437c478bd9Sstevel@tonic-gate 	}
8447c478bd9Sstevel@tonic-gate 
8457c478bd9Sstevel@tonic-gate 	return (DDI_SUCCESS);
8467c478bd9Sstevel@tonic-gate }
8477c478bd9Sstevel@tonic-gate 
8487c478bd9Sstevel@tonic-gate /*ARGSUSED*/
8497c478bd9Sstevel@tonic-gate int
px_lib_msiq_getstate(dev_info_t * dip,msiqid_t msiq_id,pci_msiq_state_t * msiq_state)8507c478bd9Sstevel@tonic-gate px_lib_msiq_getstate(dev_info_t *dip, msiqid_t msiq_id,
8517c478bd9Sstevel@tonic-gate     pci_msiq_state_t *msiq_state)
8527c478bd9Sstevel@tonic-gate {
8537c478bd9Sstevel@tonic-gate 	uint64_t	ret;
8547c478bd9Sstevel@tonic-gate 
8557c478bd9Sstevel@tonic-gate 	DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_getstate: dip 0x%p msiq_id 0x%x\n",
8567c478bd9Sstevel@tonic-gate 	    dip, msiq_id);
8577c478bd9Sstevel@tonic-gate 
8587c478bd9Sstevel@tonic-gate 	if ((ret = hvio_msiq_getstate(DIP_TO_HANDLE(dip),
8597c478bd9Sstevel@tonic-gate 	    msiq_id, msiq_state)) != H_EOK) {
8607c478bd9Sstevel@tonic-gate 		DBG(DBG_LIB_MSIQ, dip,
8617c478bd9Sstevel@tonic-gate 		    "hvio_msiq_getstate failed, ret 0x%lx\n", ret);
8627c478bd9Sstevel@tonic-gate 		return (DDI_FAILURE);
8637c478bd9Sstevel@tonic-gate 	}
8647c478bd9Sstevel@tonic-gate 
8657c478bd9Sstevel@tonic-gate 	DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_getstate: msiq_state 0x%x\n",
8667c478bd9Sstevel@tonic-gate 	    *msiq_state);
8677c478bd9Sstevel@tonic-gate 
8687c478bd9Sstevel@tonic-gate 	return (DDI_SUCCESS);
8697c478bd9Sstevel@tonic-gate }
8707c478bd9Sstevel@tonic-gate 
8717c478bd9Sstevel@tonic-gate /*ARGSUSED*/
8727c478bd9Sstevel@tonic-gate int
px_lib_msiq_setstate(dev_info_t * dip,msiqid_t msiq_id,pci_msiq_state_t msiq_state)8737c478bd9Sstevel@tonic-gate px_lib_msiq_setstate(dev_info_t *dip, msiqid_t msiq_id,
8747c478bd9Sstevel@tonic-gate     pci_msiq_state_t msiq_state)
8757c478bd9Sstevel@tonic-gate {
8767c478bd9Sstevel@tonic-gate 	uint64_t	ret;
8777c478bd9Sstevel@tonic-gate 
8787c478bd9Sstevel@tonic-gate 	DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_setstate: dip 0x%p msiq_id 0x%x "
8797c478bd9Sstevel@tonic-gate 	    "msiq_state 0x%x\n", dip, msiq_id, msiq_state);
8807c478bd9Sstevel@tonic-gate 
8817c478bd9Sstevel@tonic-gate 	if ((ret = hvio_msiq_setstate(DIP_TO_HANDLE(dip),
8827c478bd9Sstevel@tonic-gate 	    msiq_id, msiq_state)) != H_EOK) {
8837c478bd9Sstevel@tonic-gate 		DBG(DBG_LIB_MSIQ, dip,
8847c478bd9Sstevel@tonic-gate 		    "hvio_msiq_setstate failed, ret 0x%lx\n", ret);
8857c478bd9Sstevel@tonic-gate 		return (DDI_FAILURE);
8867c478bd9Sstevel@tonic-gate 	}
8877c478bd9Sstevel@tonic-gate 
8887c478bd9Sstevel@tonic-gate 	return (DDI_SUCCESS);
8897c478bd9Sstevel@tonic-gate }
8907c478bd9Sstevel@tonic-gate 
8917c478bd9Sstevel@tonic-gate /*ARGSUSED*/
8927c478bd9Sstevel@tonic-gate int
px_lib_msiq_gethead(dev_info_t * dip,msiqid_t msiq_id,msiqhead_t * msiq_head_p)8937c478bd9Sstevel@tonic-gate px_lib_msiq_gethead(dev_info_t *dip, msiqid_t msiq_id,
8947c478bd9Sstevel@tonic-gate     msiqhead_t *msiq_head_p)
8957c478bd9Sstevel@tonic-gate {
8967c478bd9Sstevel@tonic-gate 	uint64_t	ret;
8977c478bd9Sstevel@tonic-gate 
8987c478bd9Sstevel@tonic-gate 	DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_gethead: dip 0x%p msiq_id 0x%x\n",
8997c478bd9Sstevel@tonic-gate 	    dip, msiq_id);
9007c478bd9Sstevel@tonic-gate 
9017c478bd9Sstevel@tonic-gate 	if ((ret = hvio_msiq_gethead(DIP_TO_HANDLE(dip),
9027c478bd9Sstevel@tonic-gate 	    msiq_id, msiq_head_p)) != H_EOK) {
9037c478bd9Sstevel@tonic-gate 		DBG(DBG_LIB_MSIQ, dip,
9047c478bd9Sstevel@tonic-gate 		    "hvio_msiq_gethead failed, ret 0x%lx\n", ret);
9057c478bd9Sstevel@tonic-gate 		return (DDI_FAILURE);
9067c478bd9Sstevel@tonic-gate 	}
9077c478bd9Sstevel@tonic-gate 
9087c478bd9Sstevel@tonic-gate 	*msiq_head_p =  (*msiq_head_p / sizeof (msiq_rec_t));
9097c478bd9Sstevel@tonic-gate 
9107c478bd9Sstevel@tonic-gate 	DBG(DBG_LIB_MSIQ, dip, "px_msiq_gethead: msiq_head 0x%x\n",
9117c478bd9Sstevel@tonic-gate 	    *msiq_head_p);
9127c478bd9Sstevel@tonic-gate 
9137c478bd9Sstevel@tonic-gate 	return (DDI_SUCCESS);
9147c478bd9Sstevel@tonic-gate }
9157c478bd9Sstevel@tonic-gate 
9167c478bd9Sstevel@tonic-gate /*ARGSUSED*/
9177c478bd9Sstevel@tonic-gate int
px_lib_msiq_sethead(dev_info_t * dip,msiqid_t msiq_id,msiqhead_t msiq_head)9187c478bd9Sstevel@tonic-gate px_lib_msiq_sethead(dev_info_t *dip, msiqid_t msiq_id,
9197c478bd9Sstevel@tonic-gate     msiqhead_t msiq_head)
9207c478bd9Sstevel@tonic-gate {
9217c478bd9Sstevel@tonic-gate 	uint64_t	ret;
9227c478bd9Sstevel@tonic-gate 
9237c478bd9Sstevel@tonic-gate 	DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_sethead: dip 0x%p msiq_id 0x%x "
9247c478bd9Sstevel@tonic-gate 	    "msiq_head 0x%x\n", dip, msiq_id, msiq_head);
9257c478bd9Sstevel@tonic-gate 
9267c478bd9Sstevel@tonic-gate 	if ((ret = hvio_msiq_sethead(DIP_TO_HANDLE(dip),
9277c478bd9Sstevel@tonic-gate 	    msiq_id, msiq_head * sizeof (msiq_rec_t))) != H_EOK) {
9287c478bd9Sstevel@tonic-gate 		DBG(DBG_LIB_MSIQ, dip,
9297c478bd9Sstevel@tonic-gate 		    "hvio_msiq_sethead failed, ret 0x%lx\n", ret);
9307c478bd9Sstevel@tonic-gate 		return (DDI_FAILURE);
9317c478bd9Sstevel@tonic-gate 	}
9327c478bd9Sstevel@tonic-gate 
9337c478bd9Sstevel@tonic-gate 	return (DDI_SUCCESS);
9347c478bd9Sstevel@tonic-gate }
9357c478bd9Sstevel@tonic-gate 
9367c478bd9Sstevel@tonic-gate /*ARGSUSED*/
9377c478bd9Sstevel@tonic-gate int
px_lib_msiq_gettail(dev_info_t * dip,msiqid_t msiq_id,msiqtail_t * msiq_tail_p)9387c478bd9Sstevel@tonic-gate px_lib_msiq_gettail(dev_info_t *dip, msiqid_t msiq_id,
9397c478bd9Sstevel@tonic-gate     msiqtail_t *msiq_tail_p)
9407c478bd9Sstevel@tonic-gate {
9417c478bd9Sstevel@tonic-gate 	uint64_t	ret;
9427c478bd9Sstevel@tonic-gate 
9437c478bd9Sstevel@tonic-gate 	DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_gettail: dip 0x%p msiq_id 0x%x\n",
9447c478bd9Sstevel@tonic-gate 	    dip, msiq_id);
9457c478bd9Sstevel@tonic-gate 
9467c478bd9Sstevel@tonic-gate 	if ((ret = hvio_msiq_gettail(DIP_TO_HANDLE(dip),
9477c478bd9Sstevel@tonic-gate 	    msiq_id, msiq_tail_p)) != H_EOK) {
9487c478bd9Sstevel@tonic-gate 		DBG(DBG_LIB_MSIQ, dip,
9497c478bd9Sstevel@tonic-gate 		    "hvio_msiq_gettail failed, ret 0x%lx\n", ret);
9507c478bd9Sstevel@tonic-gate 		return (DDI_FAILURE);
9517c478bd9Sstevel@tonic-gate 	}
9527c478bd9Sstevel@tonic-gate 
9537c478bd9Sstevel@tonic-gate 	*msiq_tail_p =  (*msiq_tail_p / sizeof (msiq_rec_t));
9547c478bd9Sstevel@tonic-gate 	DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_gettail: msiq_tail 0x%x\n",
9557c478bd9Sstevel@tonic-gate 	    *msiq_tail_p);
9567c478bd9Sstevel@tonic-gate 
9577c478bd9Sstevel@tonic-gate 	return (DDI_SUCCESS);
9587c478bd9Sstevel@tonic-gate }
9597c478bd9Sstevel@tonic-gate 
9607c478bd9Sstevel@tonic-gate /*ARGSUSED*/
9617c478bd9Sstevel@tonic-gate void
px_lib_get_msiq_rec(dev_info_t * dip,msiqhead_t * msiq_head_p,msiq_rec_t * msiq_rec_p)962023ccc1eSegillett px_lib_get_msiq_rec(dev_info_t *dip, msiqhead_t *msiq_head_p,
963023ccc1eSegillett     msiq_rec_t *msiq_rec_p)
9647c478bd9Sstevel@tonic-gate {
965023ccc1eSegillett 	msiq_rec_t	*curr_msiq_rec_p = (msiq_rec_t *)msiq_head_p;
9667c478bd9Sstevel@tonic-gate 
9677c478bd9Sstevel@tonic-gate 	DBG(DBG_LIB_MSIQ, dip, "px_lib_get_msiq_rec: dip 0x%p\n", dip);
9687c478bd9Sstevel@tonic-gate 
969b0fc0e77Sgovinda 	if (!curr_msiq_rec_p->msiq_rec_type) {
970b0fc0e77Sgovinda 		/* Set msiq_rec_type to zero */
971b0fc0e77Sgovinda 		msiq_rec_p->msiq_rec_type = 0;
972b0fc0e77Sgovinda 
9737c478bd9Sstevel@tonic-gate 		return;
974b0fc0e77Sgovinda 	}
9757c478bd9Sstevel@tonic-gate 
9767c478bd9Sstevel@tonic-gate 	*msiq_rec_p = *curr_msiq_rec_p;
977b0fc0e77Sgovinda }
978b0fc0e77Sgovinda 
979b0fc0e77Sgovinda /*ARGSUSED*/
980b0fc0e77Sgovinda void
px_lib_clr_msiq_rec(dev_info_t * dip,msiqhead_t * msiq_head_p)981b0fc0e77Sgovinda px_lib_clr_msiq_rec(dev_info_t *dip, msiqhead_t *msiq_head_p)
982b0fc0e77Sgovinda {
983b0fc0e77Sgovinda 	msiq_rec_t	*curr_msiq_rec_p = (msiq_rec_t *)msiq_head_p;
984b0fc0e77Sgovinda 
985b0fc0e77Sgovinda 	DBG(DBG_LIB_MSIQ, dip, "px_lib_clr_msiq_rec: dip 0x%p\n", dip);
9867c478bd9Sstevel@tonic-gate 
9873ee8f295Smg 	/* Zero out msiq_rec_type field */
9883ee8f295Smg 	curr_msiq_rec_p->msiq_rec_type  = 0;
9897c478bd9Sstevel@tonic-gate }
9907c478bd9Sstevel@tonic-gate 
9917c478bd9Sstevel@tonic-gate /*
9927c478bd9Sstevel@tonic-gate  * MSI Functions:
9937c478bd9Sstevel@tonic-gate  */
9947c478bd9Sstevel@tonic-gate 
9957c478bd9Sstevel@tonic-gate /*ARGSUSED*/
9967c478bd9Sstevel@tonic-gate int
px_lib_msi_init(dev_info_t * dip)9977c478bd9Sstevel@tonic-gate px_lib_msi_init(dev_info_t *dip)
9987c478bd9Sstevel@tonic-gate {
9997c478bd9Sstevel@tonic-gate 	DBG(DBG_LIB_MSI, dip, "px_lib_msi_init: dip 0x%p\n", dip);
10007c478bd9Sstevel@tonic-gate 
10017c478bd9Sstevel@tonic-gate 	/* Noop */
10027c478bd9Sstevel@tonic-gate 	return (DDI_SUCCESS);
10037c478bd9Sstevel@tonic-gate }
10047c478bd9Sstevel@tonic-gate 
10057c478bd9Sstevel@tonic-gate /*ARGSUSED*/
10067c478bd9Sstevel@tonic-gate int
px_lib_msi_getmsiq(dev_info_t * dip,msinum_t msi_num,msiqid_t * msiq_id)10077c478bd9Sstevel@tonic-gate px_lib_msi_getmsiq(dev_info_t *dip, msinum_t msi_num,
10087c478bd9Sstevel@tonic-gate     msiqid_t *msiq_id)
10097c478bd9Sstevel@tonic-gate {
10107c478bd9Sstevel@tonic-gate 	uint64_t	ret;
10117c478bd9Sstevel@tonic-gate 
10127c478bd9Sstevel@tonic-gate 	DBG(DBG_LIB_MSI, dip, "px_lib_msi_getmsiq: dip 0x%p msi_num 0x%x\n",
10137c478bd9Sstevel@tonic-gate 	    dip, msi_num);
10147c478bd9Sstevel@tonic-gate 
10157c478bd9Sstevel@tonic-gate 	if ((ret = hvio_msi_getmsiq(DIP_TO_HANDLE(dip),
10167c478bd9Sstevel@tonic-gate 	    msi_num, msiq_id)) != H_EOK) {
10177c478bd9Sstevel@tonic-gate 		DBG(DBG_LIB_MSI, dip,
10187c478bd9Sstevel@tonic-gate 		    "hvio_msi_getmsiq failed, ret 0x%lx\n", ret);
10197c478bd9Sstevel@tonic-gate 		return (DDI_FAILURE);
10207c478bd9Sstevel@tonic-gate 	}
10217c478bd9Sstevel@tonic-gate 
10227c478bd9Sstevel@tonic-gate 	DBG(DBG_LIB_MSI, dip, "px_lib_msi_getmsiq: msiq_id 0x%x\n",
10237c478bd9Sstevel@tonic-gate 	    *msiq_id);
10247c478bd9Sstevel@tonic-gate 
10257c478bd9Sstevel@tonic-gate 	return (DDI_SUCCESS);
10267c478bd9Sstevel@tonic-gate }
10277c478bd9Sstevel@tonic-gate 
10287c478bd9Sstevel@tonic-gate /*ARGSUSED*/
10297c478bd9Sstevel@tonic-gate int
px_lib_msi_setmsiq(dev_info_t * dip,msinum_t msi_num,msiqid_t msiq_id,msi_type_t msitype)10307c478bd9Sstevel@tonic-gate px_lib_msi_setmsiq(dev_info_t *dip, msinum_t msi_num,
10317c478bd9Sstevel@tonic-gate     msiqid_t msiq_id, msi_type_t msitype)
10327c478bd9Sstevel@tonic-gate {
10337c478bd9Sstevel@tonic-gate 	uint64_t	ret;
10347c478bd9Sstevel@tonic-gate 
10357c478bd9Sstevel@tonic-gate 	DBG(DBG_LIB_MSI, dip, "px_lib_msi_setmsiq: dip 0x%p msi_num 0x%x "
10367c478bd9Sstevel@tonic-gate 	    "msq_id 0x%x\n", dip, msi_num, msiq_id);
10377c478bd9Sstevel@tonic-gate 
10387c478bd9Sstevel@tonic-gate 	if ((ret = hvio_msi_setmsiq(DIP_TO_HANDLE(dip),
10397c478bd9Sstevel@tonic-gate 	    msi_num, msiq_id, msitype)) != H_EOK) {
10407c478bd9Sstevel@tonic-gate 		DBG(DBG_LIB_MSI, dip,
10417c478bd9Sstevel@tonic-gate 		    "hvio_msi_setmsiq failed, ret 0x%lx\n", ret);
10427c478bd9Sstevel@tonic-gate 		return (DDI_FAILURE);
10437c478bd9Sstevel@tonic-gate 	}
10447c478bd9Sstevel@tonic-gate 
10457c478bd9Sstevel@tonic-gate 	return (DDI_SUCCESS);
10467c478bd9Sstevel@tonic-gate }
10477c478bd9Sstevel@tonic-gate 
10487c478bd9Sstevel@tonic-gate /*ARGSUSED*/
10497c478bd9Sstevel@tonic-gate int
px_lib_msi_getvalid(dev_info_t * dip,msinum_t msi_num,pci_msi_valid_state_t * msi_valid_state)10507c478bd9Sstevel@tonic-gate px_lib_msi_getvalid(dev_info_t *dip, msinum_t msi_num,
10517c478bd9Sstevel@tonic-gate     pci_msi_valid_state_t *msi_valid_state)
10527c478bd9Sstevel@tonic-gate {
10537c478bd9Sstevel@tonic-gate 	uint64_t	ret;
10547c478bd9Sstevel@tonic-gate 
10557c478bd9Sstevel@tonic-gate 	DBG(DBG_LIB_MSI, dip, "px_lib_msi_getvalid: dip 0x%p msi_num 0x%x\n",
10567c478bd9Sstevel@tonic-gate 	    dip, msi_num);
10577c478bd9Sstevel@tonic-gate 
10587c478bd9Sstevel@tonic-gate 	if ((ret = hvio_msi_getvalid(DIP_TO_HANDLE(dip),
10597c478bd9Sstevel@tonic-gate 	    msi_num, msi_valid_state)) != H_EOK) {
10607c478bd9Sstevel@tonic-gate 		DBG(DBG_LIB_MSI, dip,
10617c478bd9Sstevel@tonic-gate 		    "hvio_msi_getvalid failed, ret 0x%lx\n", ret);
10627c478bd9Sstevel@tonic-gate 		return (DDI_FAILURE);
10637c478bd9Sstevel@tonic-gate 	}
10647c478bd9Sstevel@tonic-gate 
10657c478bd9Sstevel@tonic-gate 	DBG(DBG_LIB_MSI, dip, "px_lib_msi_getvalid: msiq_id 0x%x\n",
10667c478bd9Sstevel@tonic-gate 	    *msi_valid_state);
10677c478bd9Sstevel@tonic-gate 
10687c478bd9Sstevel@tonic-gate 	return (DDI_SUCCESS);
10697c478bd9Sstevel@tonic-gate }
10707c478bd9Sstevel@tonic-gate 
10717c478bd9Sstevel@tonic-gate /*ARGSUSED*/
10727c478bd9Sstevel@tonic-gate int
px_lib_msi_setvalid(dev_info_t * dip,msinum_t msi_num,pci_msi_valid_state_t msi_valid_state)10737c478bd9Sstevel@tonic-gate px_lib_msi_setvalid(dev_info_t *dip, msinum_t msi_num,
10747c478bd9Sstevel@tonic-gate     pci_msi_valid_state_t msi_valid_state)
10757c478bd9Sstevel@tonic-gate {
10767c478bd9Sstevel@tonic-gate 	uint64_t	ret;
10777c478bd9Sstevel@tonic-gate 
10787c478bd9Sstevel@tonic-gate 	DBG(DBG_LIB_MSI, dip, "px_lib_msi_setvalid: dip 0x%p msi_num 0x%x "
10797c478bd9Sstevel@tonic-gate 	    "msi_valid_state 0x%x\n", dip, msi_num, msi_valid_state);
10807c478bd9Sstevel@tonic-gate 
10817c478bd9Sstevel@tonic-gate 	if ((ret = hvio_msi_setvalid(DIP_TO_HANDLE(dip),
10827c478bd9Sstevel@tonic-gate 	    msi_num, msi_valid_state)) != H_EOK) {
10837c478bd9Sstevel@tonic-gate 		DBG(DBG_LIB_MSI, dip,
10847c478bd9Sstevel@tonic-gate 		    "hvio_msi_setvalid failed, ret 0x%lx\n", ret);
10857c478bd9Sstevel@tonic-gate 		return (DDI_FAILURE);
10867c478bd9Sstevel@tonic-gate 	}
10877c478bd9Sstevel@tonic-gate 
10887c478bd9Sstevel@tonic-gate 	return (DDI_SUCCESS);
10897c478bd9Sstevel@tonic-gate }
10907c478bd9Sstevel@tonic-gate 
10917c478bd9Sstevel@tonic-gate /*ARGSUSED*/
10927c478bd9Sstevel@tonic-gate int
px_lib_msi_getstate(dev_info_t * dip,msinum_t msi_num,pci_msi_state_t * msi_state)10937c478bd9Sstevel@tonic-gate px_lib_msi_getstate(dev_info_t *dip, msinum_t msi_num,
10947c478bd9Sstevel@tonic-gate     pci_msi_state_t *msi_state)
10957c478bd9Sstevel@tonic-gate {
10967c478bd9Sstevel@tonic-gate 	uint64_t	ret;
10977c478bd9Sstevel@tonic-gate 
10987c478bd9Sstevel@tonic-gate 	DBG(DBG_LIB_MSI, dip, "px_lib_msi_getstate: dip 0x%p msi_num 0x%x\n",
10997c478bd9Sstevel@tonic-gate 	    dip, msi_num);
11007c478bd9Sstevel@tonic-gate 
11017c478bd9Sstevel@tonic-gate 	if ((ret = hvio_msi_getstate(DIP_TO_HANDLE(dip),
11027c478bd9Sstevel@tonic-gate 	    msi_num, msi_state)) != H_EOK) {
11037c478bd9Sstevel@tonic-gate 		DBG(DBG_LIB_MSI, dip,
11047c478bd9Sstevel@tonic-gate 		    "hvio_msi_getstate failed, ret 0x%lx\n", ret);
11057c478bd9Sstevel@tonic-gate 		return (DDI_FAILURE);
11067c478bd9Sstevel@tonic-gate 	}
11077c478bd9Sstevel@tonic-gate 
11087c478bd9Sstevel@tonic-gate 	DBG(DBG_LIB_MSI, dip, "px_lib_msi_getstate: msi_state 0x%x\n",
11097c478bd9Sstevel@tonic-gate 	    *msi_state);
11107c478bd9Sstevel@tonic-gate 
11117c478bd9Sstevel@tonic-gate 	return (DDI_SUCCESS);
11127c478bd9Sstevel@tonic-gate }
11137c478bd9Sstevel@tonic-gate 
11147c478bd9Sstevel@tonic-gate /*ARGSUSED*/
11157c478bd9Sstevel@tonic-gate int
px_lib_msi_setstate(dev_info_t * dip,msinum_t msi_num,pci_msi_state_t msi_state)11167c478bd9Sstevel@tonic-gate px_lib_msi_setstate(dev_info_t *dip, msinum_t msi_num,
11177c478bd9Sstevel@tonic-gate     pci_msi_state_t msi_state)
11187c478bd9Sstevel@tonic-gate {
11197c478bd9Sstevel@tonic-gate 	uint64_t	ret;
11207c478bd9Sstevel@tonic-gate 
11217c478bd9Sstevel@tonic-gate 	DBG(DBG_LIB_MSI, dip, "px_lib_msi_setstate: dip 0x%p msi_num 0x%x "
11227c478bd9Sstevel@tonic-gate 	    "msi_state 0x%x\n", dip, msi_num, msi_state);
11237c478bd9Sstevel@tonic-gate 
11247c478bd9Sstevel@tonic-gate 	if ((ret = hvio_msi_setstate(DIP_TO_HANDLE(dip),
11257c478bd9Sstevel@tonic-gate 	    msi_num, msi_state)) != H_EOK) {
11267c478bd9Sstevel@tonic-gate 		DBG(DBG_LIB_MSI, dip,
11277c478bd9Sstevel@tonic-gate 		    "hvio_msi_setstate failed, ret 0x%lx\n", ret);
11287c478bd9Sstevel@tonic-gate 		return (DDI_FAILURE);
11297c478bd9Sstevel@tonic-gate 	}
11307c478bd9Sstevel@tonic-gate 
11317c478bd9Sstevel@tonic-gate 	return (DDI_SUCCESS);
11327c478bd9Sstevel@tonic-gate }
11337c478bd9Sstevel@tonic-gate 
11347c478bd9Sstevel@tonic-gate /*
11357c478bd9Sstevel@tonic-gate  * MSG Functions:
11367c478bd9Sstevel@tonic-gate  */
11377c478bd9Sstevel@tonic-gate 
11387c478bd9Sstevel@tonic-gate /*ARGSUSED*/
11397c478bd9Sstevel@tonic-gate int
px_lib_msg_getmsiq(dev_info_t * dip,pcie_msg_type_t msg_type,msiqid_t * msiq_id)11407c478bd9Sstevel@tonic-gate px_lib_msg_getmsiq(dev_info_t *dip, pcie_msg_type_t msg_type,
11417c478bd9Sstevel@tonic-gate     msiqid_t *msiq_id)
11427c478bd9Sstevel@tonic-gate {
11437c478bd9Sstevel@tonic-gate 	uint64_t	ret;
11447c478bd9Sstevel@tonic-gate 
11457c478bd9Sstevel@tonic-gate 	DBG(DBG_LIB_MSG, dip, "px_lib_msg_getmsiq: dip 0x%p msg_type 0x%x\n",
11467c478bd9Sstevel@tonic-gate 	    dip, msg_type);
11477c478bd9Sstevel@tonic-gate 
11487c478bd9Sstevel@tonic-gate 	if ((ret = hvio_msg_getmsiq(DIP_TO_HANDLE(dip),
11497c478bd9Sstevel@tonic-gate 	    msg_type, msiq_id)) != H_EOK) {
11507c478bd9Sstevel@tonic-gate 		DBG(DBG_LIB_MSG, dip,
11517c478bd9Sstevel@tonic-gate 		    "hvio_msg_getmsiq failed, ret 0x%lx\n", ret);
11527c478bd9Sstevel@tonic-gate 		return (DDI_FAILURE);
11537c478bd9Sstevel@tonic-gate 	}
11547c478bd9Sstevel@tonic-gate 
11557c478bd9Sstevel@tonic-gate 	DBG(DBG_LIB_MSI, dip, "px_lib_msg_getmsiq: msiq_id 0x%x\n",
11567c478bd9Sstevel@tonic-gate 	    *msiq_id);
11577c478bd9Sstevel@tonic-gate 
11587c478bd9Sstevel@tonic-gate 	return (DDI_SUCCESS);
11597c478bd9Sstevel@tonic-gate }
11607c478bd9Sstevel@tonic-gate 
11617c478bd9Sstevel@tonic-gate /*ARGSUSED*/
11627c478bd9Sstevel@tonic-gate int
px_lib_msg_setmsiq(dev_info_t * dip,pcie_msg_type_t msg_type,msiqid_t msiq_id)11637c478bd9Sstevel@tonic-gate px_lib_msg_setmsiq(dev_info_t *dip, pcie_msg_type_t msg_type,
11647c478bd9Sstevel@tonic-gate     msiqid_t msiq_id)
11657c478bd9Sstevel@tonic-gate {
11667c478bd9Sstevel@tonic-gate 	uint64_t	ret;
11677c478bd9Sstevel@tonic-gate 
11687c478bd9Sstevel@tonic-gate 	DBG(DBG_LIB_MSG, dip, "px_lib_msg_setmsiq: dip 0x%p msg_type 0x%x "
11697c478bd9Sstevel@tonic-gate 	    "msq_id 0x%x\n", dip, msg_type, msiq_id);
11707c478bd9Sstevel@tonic-gate 
11717c478bd9Sstevel@tonic-gate 	if ((ret = hvio_msg_setmsiq(DIP_TO_HANDLE(dip),
11727c478bd9Sstevel@tonic-gate 	    msg_type, msiq_id)) != H_EOK) {
11737c478bd9Sstevel@tonic-gate 		DBG(DBG_LIB_MSG, dip,
11747c478bd9Sstevel@tonic-gate 		    "hvio_msg_setmsiq failed, ret 0x%lx\n", ret);
11757c478bd9Sstevel@tonic-gate 		return (DDI_FAILURE);
11767c478bd9Sstevel@tonic-gate 	}
11777c478bd9Sstevel@tonic-gate 
11787c478bd9Sstevel@tonic-gate 	return (DDI_SUCCESS);
11797c478bd9Sstevel@tonic-gate }
11807c478bd9Sstevel@tonic-gate 
11817c478bd9Sstevel@tonic-gate /*ARGSUSED*/
11827c478bd9Sstevel@tonic-gate int
px_lib_msg_getvalid(dev_info_t * dip,pcie_msg_type_t msg_type,pcie_msg_valid_state_t * msg_valid_state)11837c478bd9Sstevel@tonic-gate px_lib_msg_getvalid(dev_info_t *dip, pcie_msg_type_t msg_type,
11847c478bd9Sstevel@tonic-gate     pcie_msg_valid_state_t *msg_valid_state)
11857c478bd9Sstevel@tonic-gate {
11867c478bd9Sstevel@tonic-gate 	uint64_t	ret;
11877c478bd9Sstevel@tonic-gate 
11887c478bd9Sstevel@tonic-gate 	DBG(DBG_LIB_MSG, dip, "px_lib_msg_getvalid: dip 0x%p msg_type 0x%x\n",
11897c478bd9Sstevel@tonic-gate 	    dip, msg_type);
11907c478bd9Sstevel@tonic-gate 
11917c478bd9Sstevel@tonic-gate 	if ((ret = hvio_msg_getvalid(DIP_TO_HANDLE(dip), msg_type,
11927c478bd9Sstevel@tonic-gate 	    msg_valid_state)) != H_EOK) {
11937c478bd9Sstevel@tonic-gate 		DBG(DBG_LIB_MSG, dip,
11947c478bd9Sstevel@tonic-gate 		    "hvio_msg_getvalid failed, ret 0x%lx\n", ret);
11957c478bd9Sstevel@tonic-gate 		return (DDI_FAILURE);
11967c478bd9Sstevel@tonic-gate 	}
11977c478bd9Sstevel@tonic-gate 
11987c478bd9Sstevel@tonic-gate 	DBG(DBG_LIB_MSI, dip, "px_lib_msg_getvalid: msg_valid_state 0x%x\n",
11997c478bd9Sstevel@tonic-gate 	    *msg_valid_state);
12007c478bd9Sstevel@tonic-gate 
12017c478bd9Sstevel@tonic-gate 	return (DDI_SUCCESS);
12027c478bd9Sstevel@tonic-gate }
12037c478bd9Sstevel@tonic-gate 
12047c478bd9Sstevel@tonic-gate /*ARGSUSED*/
12057c478bd9Sstevel@tonic-gate int
px_lib_msg_setvalid(dev_info_t * dip,pcie_msg_type_t msg_type,pcie_msg_valid_state_t msg_valid_state)12067c478bd9Sstevel@tonic-gate px_lib_msg_setvalid(dev_info_t *dip, pcie_msg_type_t msg_type,
12077c478bd9Sstevel@tonic-gate     pcie_msg_valid_state_t msg_valid_state)
12087c478bd9Sstevel@tonic-gate {
12097c478bd9Sstevel@tonic-gate 	uint64_t	ret;
12107c478bd9Sstevel@tonic-gate 
12117c478bd9Sstevel@tonic-gate 	DBG(DBG_LIB_MSG, dip, "px_lib_msg_setvalid: dip 0x%p msg_type 0x%x "
12127c478bd9Sstevel@tonic-gate 	    "msg_valid_state 0x%x\n", dip, msg_type, msg_valid_state);
12137c478bd9Sstevel@tonic-gate 
12147c478bd9Sstevel@tonic-gate 	if ((ret = hvio_msg_setvalid(DIP_TO_HANDLE(dip), msg_type,
12157c478bd9Sstevel@tonic-gate 	    msg_valid_state)) != H_EOK) {
12167c478bd9Sstevel@tonic-gate 		DBG(DBG_LIB_MSG, dip,
12177c478bd9Sstevel@tonic-gate 		    "hvio_msg_setvalid failed, ret 0x%lx\n", ret);
12187c478bd9Sstevel@tonic-gate 		return (DDI_FAILURE);
12197c478bd9Sstevel@tonic-gate 	}
12207c478bd9Sstevel@tonic-gate 
12217c478bd9Sstevel@tonic-gate 	return (DDI_SUCCESS);
12227c478bd9Sstevel@tonic-gate }
12237c478bd9Sstevel@tonic-gate 
12247c478bd9Sstevel@tonic-gate /*
12257c478bd9Sstevel@tonic-gate  * Suspend/Resume Functions:
12267c478bd9Sstevel@tonic-gate  * Currently unsupported by hypervisor and all functions are noops.
12277c478bd9Sstevel@tonic-gate  */
12287c478bd9Sstevel@tonic-gate /*ARGSUSED*/
12297c478bd9Sstevel@tonic-gate int
px_lib_suspend(dev_info_t * dip)12307c478bd9Sstevel@tonic-gate px_lib_suspend(dev_info_t *dip)
12317c478bd9Sstevel@tonic-gate {
12327c478bd9Sstevel@tonic-gate 	DBG(DBG_ATTACH, dip, "px_lib_suspend: Not supported\n");
12337c478bd9Sstevel@tonic-gate 
12347c478bd9Sstevel@tonic-gate 	/* Not supported */
12357c478bd9Sstevel@tonic-gate 	return (DDI_FAILURE);
12367c478bd9Sstevel@tonic-gate }
12377c478bd9Sstevel@tonic-gate 
12387c478bd9Sstevel@tonic-gate /*ARGSUSED*/
12397c478bd9Sstevel@tonic-gate void
px_lib_resume(dev_info_t * dip)12407c478bd9Sstevel@tonic-gate px_lib_resume(dev_info_t *dip)
12417c478bd9Sstevel@tonic-gate {
12427c478bd9Sstevel@tonic-gate 	DBG(DBG_ATTACH, dip, "px_lib_resume: Not supported\n");
12437c478bd9Sstevel@tonic-gate 
12447c478bd9Sstevel@tonic-gate 	/* Noop */
12457c478bd9Sstevel@tonic-gate }
12467c478bd9Sstevel@tonic-gate 
12477c478bd9Sstevel@tonic-gate /*
12487c478bd9Sstevel@tonic-gate  * Misc Functions:
12497c478bd9Sstevel@tonic-gate  * Currently unsupported by hypervisor and all functions are noops.
12507c478bd9Sstevel@tonic-gate  */
12517c478bd9Sstevel@tonic-gate /*ARGSUSED*/
12527c478bd9Sstevel@tonic-gate static int
px_lib_config_get(dev_info_t * dip,pci_device_t bdf,pci_config_offset_t off,uint8_t size,pci_cfg_data_t * data_p)12537c478bd9Sstevel@tonic-gate px_lib_config_get(dev_info_t *dip, pci_device_t bdf, pci_config_offset_t off,
12547c478bd9Sstevel@tonic-gate     uint8_t size, pci_cfg_data_t *data_p)
12557c478bd9Sstevel@tonic-gate {
12567c478bd9Sstevel@tonic-gate 	uint64_t	ret;
12577c478bd9Sstevel@tonic-gate 
12587c478bd9Sstevel@tonic-gate 	DBG(DBG_LIB_CFG, dip, "px_lib_config_get: dip 0x%p, bdf 0x%llx "
12597c478bd9Sstevel@tonic-gate 	    "off 0x%x size 0x%x\n", dip, bdf, off, size);
12607c478bd9Sstevel@tonic-gate 
12617c478bd9Sstevel@tonic-gate 	if ((ret = hvio_config_get(DIP_TO_HANDLE(dip), bdf, off,
12627c478bd9Sstevel@tonic-gate 	    size, data_p)) != H_EOK) {
12637c478bd9Sstevel@tonic-gate 		DBG(DBG_LIB_CFG, dip,
12647c478bd9Sstevel@tonic-gate 		    "hvio_config_get failed, ret 0x%lx\n", ret);
12657c478bd9Sstevel@tonic-gate 		return (DDI_FAILURE);
12667c478bd9Sstevel@tonic-gate 	}
12677c478bd9Sstevel@tonic-gate 	DBG(DBG_LIB_CFG, dip, "px_config_get: data 0x%x\n", data_p->dw);
12687c478bd9Sstevel@tonic-gate 
12697c478bd9Sstevel@tonic-gate 	return (DDI_SUCCESS);
12707c478bd9Sstevel@tonic-gate }
12717c478bd9Sstevel@tonic-gate 
12727c478bd9Sstevel@tonic-gate /*ARGSUSED*/
12737c478bd9Sstevel@tonic-gate static int
px_lib_config_put(dev_info_t * dip,pci_device_t bdf,pci_config_offset_t off,uint8_t size,pci_cfg_data_t data)12747c478bd9Sstevel@tonic-gate px_lib_config_put(dev_info_t *dip, pci_device_t bdf, pci_config_offset_t off,
12757c478bd9Sstevel@tonic-gate     uint8_t size, pci_cfg_data_t data)
12767c478bd9Sstevel@tonic-gate {
12777c478bd9Sstevel@tonic-gate 	uint64_t	ret;
12787c478bd9Sstevel@tonic-gate 
12797c478bd9Sstevel@tonic-gate 	DBG(DBG_LIB_CFG, dip, "px_lib_config_put: dip 0x%p, bdf 0x%llx "
12807c478bd9Sstevel@tonic-gate 	    "off 0x%x size 0x%x data 0x%llx\n", dip, bdf, off, size, data.qw);
12817c478bd9Sstevel@tonic-gate 
12827c478bd9Sstevel@tonic-gate 	if ((ret = hvio_config_put(DIP_TO_HANDLE(dip), bdf, off,
12837c478bd9Sstevel@tonic-gate 	    size, data)) != H_EOK) {
12847c478bd9Sstevel@tonic-gate 		DBG(DBG_LIB_CFG, dip,
12857c478bd9Sstevel@tonic-gate 		    "hvio_config_put failed, ret 0x%lx\n", ret);
12867c478bd9Sstevel@tonic-gate 		return (DDI_FAILURE);
12877c478bd9Sstevel@tonic-gate 	}
12887c478bd9Sstevel@tonic-gate 
12897c478bd9Sstevel@tonic-gate 	return (DDI_SUCCESS);
12907c478bd9Sstevel@tonic-gate }
12917c478bd9Sstevel@tonic-gate 
12927c478bd9Sstevel@tonic-gate static uint32_t
px_pci_config_get(ddi_acc_impl_t * handle,uint32_t * addr,int size)12937c478bd9Sstevel@tonic-gate px_pci_config_get(ddi_acc_impl_t *handle, uint32_t *addr, int size)
12947c478bd9Sstevel@tonic-gate {
1295eae2e508Skrishnae 	px_config_acc_pvt_t *px_pvt = (px_config_acc_pvt_t *)
1296eae2e508Skrishnae 	    handle->ahi_common.ah_bus_private;
1297fc256490SJason Beloro 	pcie_bus_t *busp = NULL;
1298fc256490SJason Beloro 	dev_info_t *cdip = NULL;
12997c478bd9Sstevel@tonic-gate 	uint32_t pci_dev_addr = px_pvt->raddr;
13007c478bd9Sstevel@tonic-gate 	uint32_t vaddr = px_pvt->vaddr;
1301b40cec45Skrishnae 	uint16_t off = (uint16_t)(uintptr_t)(addr - vaddr) & 0xfff;
1302abdf5d9aSShesha Sreenivasamurthy 	uint64_t rdata = 0;
13037c478bd9Sstevel@tonic-gate 
13047c478bd9Sstevel@tonic-gate 	if (px_lib_config_get(px_pvt->dip, pci_dev_addr, off,
1305eae2e508Skrishnae 	    size, (pci_cfg_data_t *)&rdata) != DDI_SUCCESS)
13067c478bd9Sstevel@tonic-gate 		/* XXX update error kstats */
13077c478bd9Sstevel@tonic-gate 		return (0xffffffff);
1308fc256490SJason Beloro 
1309fc256490SJason Beloro 	if (cdip = pcie_find_dip_by_bdf(px_pvt->dip, pci_dev_addr >> 8))
1310fc256490SJason Beloro 		busp = PCIE_DIP2BUS(cdip);
1311fc256490SJason Beloro 	/*
1312fc256490SJason Beloro 	 * This can be called early, before busp or busp->bus_dom has
1313fc256490SJason Beloro 	 * been initialized, so check both before invoking
1314fc256490SJason Beloro 	 * PCIE_IS_ASSIGNED.
1315fc256490SJason Beloro 	 */
1316fc256490SJason Beloro 	if (busp && PCIE_BUS2DOM(busp) && PCIE_IS_ASSIGNED(busp)) {
1317fc256490SJason Beloro 		if (off == PCI_CONF_VENID && size == 2)
1318fc256490SJason Beloro 			rdata = busp->bus_dev_ven_id & 0xffff;
1319fc256490SJason Beloro 		else if (off == PCI_CONF_DEVID && size == 2)
1320fc256490SJason Beloro 			rdata = busp->bus_dev_ven_id >> 16;
1321fc256490SJason Beloro 		else if (off == PCI_CONF_VENID && size == 4)
1322fc256490SJason Beloro 			rdata = busp->bus_dev_ven_id;
1323fc256490SJason Beloro 	}
1324abdf5d9aSShesha Sreenivasamurthy 	return ((uint32_t)rdata);
13257c478bd9Sstevel@tonic-gate }
13267c478bd9Sstevel@tonic-gate 
13277c478bd9Sstevel@tonic-gate static void
px_pci_config_put(ddi_acc_impl_t * handle,uint32_t * addr,int size,pci_cfg_data_t wdata)13287c478bd9Sstevel@tonic-gate px_pci_config_put(ddi_acc_impl_t *handle, uint32_t *addr,
1329*d5ebc493SDan Cross     int size, pci_cfg_data_t wdata)
13307c478bd9Sstevel@tonic-gate {
1331eae2e508Skrishnae 	px_config_acc_pvt_t *px_pvt = (px_config_acc_pvt_t *)
1332eae2e508Skrishnae 	    handle->ahi_common.ah_bus_private;
13337c478bd9Sstevel@tonic-gate 	uint32_t pci_dev_addr = px_pvt->raddr;
13347c478bd9Sstevel@tonic-gate 	uint32_t vaddr = px_pvt->vaddr;
1335b40cec45Skrishnae 	uint16_t off = (uint16_t)(uintptr_t)(addr - vaddr) & 0xfff;
13367c478bd9Sstevel@tonic-gate 
13377c478bd9Sstevel@tonic-gate 	if (px_lib_config_put(px_pvt->dip, pci_dev_addr, off,
1338eae2e508Skrishnae 	    size, wdata) != DDI_SUCCESS) {
13397c478bd9Sstevel@tonic-gate 		/*EMPTY*/
13407c478bd9Sstevel@tonic-gate 		/* XXX update error kstats */
13417c478bd9Sstevel@tonic-gate 	}
13427c478bd9Sstevel@tonic-gate }
13437c478bd9Sstevel@tonic-gate 
13447c478bd9Sstevel@tonic-gate static uint8_t
px_pci_config_get8(ddi_acc_impl_t * handle,uint8_t * addr)13457c478bd9Sstevel@tonic-gate px_pci_config_get8(ddi_acc_impl_t *handle, uint8_t *addr)
13467c478bd9Sstevel@tonic-gate {
13477c478bd9Sstevel@tonic-gate 	return ((uint8_t)px_pci_config_get(handle, (uint32_t *)addr, 1));
13487c478bd9Sstevel@tonic-gate }
13497c478bd9Sstevel@tonic-gate 
13507c478bd9Sstevel@tonic-gate static uint16_t
px_pci_config_get16(ddi_acc_impl_t * handle,uint16_t * addr)13517c478bd9Sstevel@tonic-gate px_pci_config_get16(ddi_acc_impl_t *handle, uint16_t *addr)
13527c478bd9Sstevel@tonic-gate {
13537c478bd9Sstevel@tonic-gate 	return ((uint16_t)px_pci_config_get(handle, (uint32_t *)addr, 2));
13547c478bd9Sstevel@tonic-gate }
13557c478bd9Sstevel@tonic-gate 
13567c478bd9Sstevel@tonic-gate static uint32_t
px_pci_config_get32(ddi_acc_impl_t * handle,uint32_t * addr)13577c478bd9Sstevel@tonic-gate px_pci_config_get32(ddi_acc_impl_t *handle, uint32_t *addr)
13587c478bd9Sstevel@tonic-gate {
13597c478bd9Sstevel@tonic-gate 	return ((uint32_t)px_pci_config_get(handle, (uint32_t *)addr, 4));
13607c478bd9Sstevel@tonic-gate }
13617c478bd9Sstevel@tonic-gate 
13627c478bd9Sstevel@tonic-gate static uint64_t
px_pci_config_get64(ddi_acc_impl_t * handle,uint64_t * addr)13637c478bd9Sstevel@tonic-gate px_pci_config_get64(ddi_acc_impl_t *handle, uint64_t *addr)
13647c478bd9Sstevel@tonic-gate {
13657c478bd9Sstevel@tonic-gate 	uint32_t rdatah, rdatal;
13667c478bd9Sstevel@tonic-gate 
13677c478bd9Sstevel@tonic-gate 	rdatal = (uint32_t)px_pci_config_get(handle, (uint32_t *)addr, 4);
13687c478bd9Sstevel@tonic-gate 	rdatah = (uint32_t)px_pci_config_get(handle,
1369eae2e508Skrishnae 	    (uint32_t *)((char *)addr+4), 4);
13707c478bd9Sstevel@tonic-gate 	return (((uint64_t)rdatah << 32) | rdatal);
13717c478bd9Sstevel@tonic-gate }
13727c478bd9Sstevel@tonic-gate 
13737c478bd9Sstevel@tonic-gate static void
px_pci_config_put8(ddi_acc_impl_t * handle,uint8_t * addr,uint8_t data)13747c478bd9Sstevel@tonic-gate px_pci_config_put8(ddi_acc_impl_t *handle, uint8_t *addr, uint8_t data)
13757c478bd9Sstevel@tonic-gate {
13767c478bd9Sstevel@tonic-gate 	pci_cfg_data_t wdata = { 0 };
13777c478bd9Sstevel@tonic-gate 
13787c478bd9Sstevel@tonic-gate 	wdata.qw = (uint8_t)data;
13797c478bd9Sstevel@tonic-gate 	px_pci_config_put(handle, (uint32_t *)addr, 1, wdata);
13807c478bd9Sstevel@tonic-gate }
13817c478bd9Sstevel@tonic-gate 
13827c478bd9Sstevel@tonic-gate static void
px_pci_config_put16(ddi_acc_impl_t * handle,uint16_t * addr,uint16_t data)13837c478bd9Sstevel@tonic-gate px_pci_config_put16(ddi_acc_impl_t *handle, uint16_t *addr, uint16_t data)
13847c478bd9Sstevel@tonic-gate {
13857c478bd9Sstevel@tonic-gate 	pci_cfg_data_t wdata = { 0 };
13867c478bd9Sstevel@tonic-gate 
13877c478bd9Sstevel@tonic-gate 	wdata.qw = (uint16_t)data;
13887c478bd9Sstevel@tonic-gate 	px_pci_config_put(handle, (uint32_t *)addr, 2, wdata);
13897c478bd9Sstevel@tonic-gate }
13907c478bd9Sstevel@tonic-gate 
13917c478bd9Sstevel@tonic-gate static void
px_pci_config_put32(ddi_acc_impl_t * handle,uint32_t * addr,uint32_t data)13927c478bd9Sstevel@tonic-gate px_pci_config_put32(ddi_acc_impl_t *handle, uint32_t *addr, uint32_t data)
13937c478bd9Sstevel@tonic-gate {
13947c478bd9Sstevel@tonic-gate 	pci_cfg_data_t wdata = { 0 };
13957c478bd9Sstevel@tonic-gate 
13967c478bd9Sstevel@tonic-gate 	wdata.qw = (uint32_t)data;
13977c478bd9Sstevel@tonic-gate 	px_pci_config_put(handle, (uint32_t *)addr, 4, wdata);
13987c478bd9Sstevel@tonic-gate }
13997c478bd9Sstevel@tonic-gate 
14007c478bd9Sstevel@tonic-gate static void
px_pci_config_put64(ddi_acc_impl_t * handle,uint64_t * addr,uint64_t data)14017c478bd9Sstevel@tonic-gate px_pci_config_put64(ddi_acc_impl_t *handle, uint64_t *addr, uint64_t data)
14027c478bd9Sstevel@tonic-gate {
14037c478bd9Sstevel@tonic-gate 	pci_cfg_data_t wdata = { 0 };
14047c478bd9Sstevel@tonic-gate 
14057c478bd9Sstevel@tonic-gate 	wdata.qw = (uint32_t)(data & 0xffffffff);
14067c478bd9Sstevel@tonic-gate 	px_pci_config_put(handle, (uint32_t *)addr, 4, wdata);
14077c478bd9Sstevel@tonic-gate 	wdata.qw = (uint32_t)((data >> 32) & 0xffffffff);
14087c478bd9Sstevel@tonic-gate 	px_pci_config_put(handle, (uint32_t *)((char *)addr+4), 4, wdata);
14097c478bd9Sstevel@tonic-gate }
14107c478bd9Sstevel@tonic-gate 
14117c478bd9Sstevel@tonic-gate static void
px_pci_config_rep_get8(ddi_acc_impl_t * handle,uint8_t * host_addr,uint8_t * dev_addr,size_t repcount,uint_t flags)14127c478bd9Sstevel@tonic-gate px_pci_config_rep_get8(ddi_acc_impl_t *handle, uint8_t *host_addr,
1413*d5ebc493SDan Cross     uint8_t *dev_addr, size_t repcount, uint_t flags)
14147c478bd9Sstevel@tonic-gate {
14157c478bd9Sstevel@tonic-gate 	if (flags == DDI_DEV_AUTOINCR)
14167c478bd9Sstevel@tonic-gate 		for (; repcount; repcount--)
14177c478bd9Sstevel@tonic-gate 			*host_addr++ = px_pci_config_get8(handle, dev_addr++);
14187c478bd9Sstevel@tonic-gate 	else
14197c478bd9Sstevel@tonic-gate 		for (; repcount; repcount--)
14207c478bd9Sstevel@tonic-gate 			*host_addr++ = px_pci_config_get8(handle, dev_addr);
14217c478bd9Sstevel@tonic-gate }
14227c478bd9Sstevel@tonic-gate 
14237c478bd9Sstevel@tonic-gate /*
14247c478bd9Sstevel@tonic-gate  * Function to rep read 16 bit data off the PCI configuration space behind
14257c478bd9Sstevel@tonic-gate  * the 21554's host interface.
14267c478bd9Sstevel@tonic-gate  */
14277c478bd9Sstevel@tonic-gate static void
px_pci_config_rep_get16(ddi_acc_impl_t * handle,uint16_t * host_addr,uint16_t * dev_addr,size_t repcount,uint_t flags)14287c478bd9Sstevel@tonic-gate px_pci_config_rep_get16(ddi_acc_impl_t *handle, uint16_t *host_addr,
1429*d5ebc493SDan Cross     uint16_t *dev_addr, size_t repcount, uint_t flags)
14307c478bd9Sstevel@tonic-gate {
14317c478bd9Sstevel@tonic-gate 	if (flags == DDI_DEV_AUTOINCR)
14327c478bd9Sstevel@tonic-gate 		for (; repcount; repcount--)
14337c478bd9Sstevel@tonic-gate 			*host_addr++ = px_pci_config_get16(handle, dev_addr++);
14347c478bd9Sstevel@tonic-gate 	else
14357c478bd9Sstevel@tonic-gate 		for (; repcount; repcount--)
14367c478bd9Sstevel@tonic-gate 			*host_addr++ = px_pci_config_get16(handle, dev_addr);
14377c478bd9Sstevel@tonic-gate }
14387c478bd9Sstevel@tonic-gate 
14397c478bd9Sstevel@tonic-gate /*
14407c478bd9Sstevel@tonic-gate  * Function to rep read 32 bit data off the PCI configuration space behind
14417c478bd9Sstevel@tonic-gate  * the 21554's host interface.
14427c478bd9Sstevel@tonic-gate  */
14437c478bd9Sstevel@tonic-gate static void
px_pci_config_rep_get32(ddi_acc_impl_t * handle,uint32_t * host_addr,uint32_t * dev_addr,size_t repcount,uint_t flags)14447c478bd9Sstevel@tonic-gate px_pci_config_rep_get32(ddi_acc_impl_t *handle, uint32_t *host_addr,
1445*d5ebc493SDan Cross     uint32_t *dev_addr, size_t repcount, uint_t flags)
14467c478bd9Sstevel@tonic-gate {
14477c478bd9Sstevel@tonic-gate 	if (flags == DDI_DEV_AUTOINCR)
14487c478bd9Sstevel@tonic-gate 		for (; repcount; repcount--)
14497c478bd9Sstevel@tonic-gate 			*host_addr++ = px_pci_config_get32(handle, dev_addr++);
14507c478bd9Sstevel@tonic-gate 	else
14517c478bd9Sstevel@tonic-gate 		for (; repcount; repcount--)
14527c478bd9Sstevel@tonic-gate 			*host_addr++ = px_pci_config_get32(handle, dev_addr);
14537c478bd9Sstevel@tonic-gate }
14547c478bd9Sstevel@tonic-gate 
14557c478bd9Sstevel@tonic-gate /*
14567c478bd9Sstevel@tonic-gate  * Function to rep read 64 bit data off the PCI configuration space behind
14577c478bd9Sstevel@tonic-gate  * the 21554's host interface.
14587c478bd9Sstevel@tonic-gate  */
14597c478bd9Sstevel@tonic-gate static void
px_pci_config_rep_get64(ddi_acc_impl_t * handle,uint64_t * host_addr,uint64_t * dev_addr,size_t repcount,uint_t flags)14607c478bd9Sstevel@tonic-gate px_pci_config_rep_get64(ddi_acc_impl_t *handle, uint64_t *host_addr,
1461*d5ebc493SDan Cross     uint64_t *dev_addr, size_t repcount, uint_t flags)
14627c478bd9Sstevel@tonic-gate {
14637c478bd9Sstevel@tonic-gate 	if (flags == DDI_DEV_AUTOINCR)
14647c478bd9Sstevel@tonic-gate 		for (; repcount; repcount--)
14657c478bd9Sstevel@tonic-gate 			*host_addr++ = px_pci_config_get64(handle, dev_addr++);
14667c478bd9Sstevel@tonic-gate 	else
14677c478bd9Sstevel@tonic-gate 		for (; repcount; repcount--)
14687c478bd9Sstevel@tonic-gate 			*host_addr++ = px_pci_config_get64(handle, dev_addr);
14697c478bd9Sstevel@tonic-gate }
14707c478bd9Sstevel@tonic-gate 
14717c478bd9Sstevel@tonic-gate /*
14727c478bd9Sstevel@tonic-gate  * Function to rep write 8 bit data into the PCI configuration space behind
14737c478bd9Sstevel@tonic-gate  * the 21554's host interface.
14747c478bd9Sstevel@tonic-gate  */
14757c478bd9Sstevel@tonic-gate static void
px_pci_config_rep_put8(ddi_acc_impl_t * handle,uint8_t * host_addr,uint8_t * dev_addr,size_t repcount,uint_t flags)14767c478bd9Sstevel@tonic-gate px_pci_config_rep_put8(ddi_acc_impl_t *handle, uint8_t *host_addr,
1477*d5ebc493SDan Cross     uint8_t *dev_addr, size_t repcount, uint_t flags)
14787c478bd9Sstevel@tonic-gate {
14797c478bd9Sstevel@tonic-gate 	if (flags == DDI_DEV_AUTOINCR)
14807c478bd9Sstevel@tonic-gate 		for (; repcount; repcount--)
14817c478bd9Sstevel@tonic-gate 			px_pci_config_put8(handle, dev_addr++, *host_addr++);
14827c478bd9Sstevel@tonic-gate 	else
14837c478bd9Sstevel@tonic-gate 		for (; repcount; repcount--)
14847c478bd9Sstevel@tonic-gate 			px_pci_config_put8(handle, dev_addr, *host_addr++);
14857c478bd9Sstevel@tonic-gate }
14867c478bd9Sstevel@tonic-gate 
14877c478bd9Sstevel@tonic-gate /*
14887c478bd9Sstevel@tonic-gate  * Function to rep write 16 bit data into the PCI configuration space behind
14897c478bd9Sstevel@tonic-gate  * the 21554's host interface.
14907c478bd9Sstevel@tonic-gate  */
14917c478bd9Sstevel@tonic-gate static void
px_pci_config_rep_put16(ddi_acc_impl_t * handle,uint16_t * host_addr,uint16_t * dev_addr,size_t repcount,uint_t flags)14927c478bd9Sstevel@tonic-gate px_pci_config_rep_put16(ddi_acc_impl_t *handle, uint16_t *host_addr,
1493*d5ebc493SDan Cross     uint16_t *dev_addr, size_t repcount, uint_t flags)
14947c478bd9Sstevel@tonic-gate {
14957c478bd9Sstevel@tonic-gate 	if (flags == DDI_DEV_AUTOINCR)
14967c478bd9Sstevel@tonic-gate 		for (; repcount; repcount--)
14977c478bd9Sstevel@tonic-gate 			px_pci_config_put16(handle, dev_addr++, *host_addr++);
14987c478bd9Sstevel@tonic-gate 	else
14997c478bd9Sstevel@tonic-gate 		for (; repcount; repcount--)
15007c478bd9Sstevel@tonic-gate 			px_pci_config_put16(handle, dev_addr, *host_addr++);
15017c478bd9Sstevel@tonic-gate }
15027c478bd9Sstevel@tonic-gate 
15037c478bd9Sstevel@tonic-gate /*
15047c478bd9Sstevel@tonic-gate  * Function to rep write 32 bit data into the PCI configuration space behind
15057c478bd9Sstevel@tonic-gate  * the 21554's host interface.
15067c478bd9Sstevel@tonic-gate  */
15077c478bd9Sstevel@tonic-gate static void
px_pci_config_rep_put32(ddi_acc_impl_t * handle,uint32_t * host_addr,uint32_t * dev_addr,size_t repcount,uint_t flags)15087c478bd9Sstevel@tonic-gate px_pci_config_rep_put32(ddi_acc_impl_t *handle, uint32_t *host_addr,
1509*d5ebc493SDan Cross     uint32_t *dev_addr, size_t repcount, uint_t flags)
15107c478bd9Sstevel@tonic-gate {
15117c478bd9Sstevel@tonic-gate 	if (flags == DDI_DEV_AUTOINCR)
15127c478bd9Sstevel@tonic-gate 		for (; repcount; repcount--)
15137c478bd9Sstevel@tonic-gate 			px_pci_config_put32(handle, dev_addr++, *host_addr++);
15147c478bd9Sstevel@tonic-gate 	else
15157c478bd9Sstevel@tonic-gate 		for (; repcount; repcount--)
15167c478bd9Sstevel@tonic-gate 			px_pci_config_put32(handle, dev_addr, *host_addr++);
15177c478bd9Sstevel@tonic-gate }
15187c478bd9Sstevel@tonic-gate 
15197c478bd9Sstevel@tonic-gate /*
15207c478bd9Sstevel@tonic-gate  * Function to rep write 64 bit data into the PCI configuration space behind
15217c478bd9Sstevel@tonic-gate  * the 21554's host interface.
15227c478bd9Sstevel@tonic-gate  */
15237c478bd9Sstevel@tonic-gate static void
px_pci_config_rep_put64(ddi_acc_impl_t * handle,uint64_t * host_addr,uint64_t * dev_addr,size_t repcount,uint_t flags)15247c478bd9Sstevel@tonic-gate px_pci_config_rep_put64(ddi_acc_impl_t *handle, uint64_t *host_addr,
1525*d5ebc493SDan Cross     uint64_t *dev_addr, size_t repcount, uint_t flags)
15267c478bd9Sstevel@tonic-gate {
15277c478bd9Sstevel@tonic-gate 	if (flags == DDI_DEV_AUTOINCR)
15287c478bd9Sstevel@tonic-gate 		for (; repcount; repcount--)
15297c478bd9Sstevel@tonic-gate 			px_pci_config_put64(handle, dev_addr++, *host_addr++);
15307c478bd9Sstevel@tonic-gate 	else
15317c478bd9Sstevel@tonic-gate 		for (; repcount; repcount--)
15327c478bd9Sstevel@tonic-gate 			px_pci_config_put64(handle, dev_addr, *host_addr++);
15337c478bd9Sstevel@tonic-gate }
15347c478bd9Sstevel@tonic-gate 
15357c478bd9Sstevel@tonic-gate /*
15367c478bd9Sstevel@tonic-gate  * Provide a private access handle to route config access calls to Hypervisor.
15377c478bd9Sstevel@tonic-gate  * Beware: Do all error checking for config space accesses before calling
15387c478bd9Sstevel@tonic-gate  * this function. ie. do error checking from the calling function.
15397c478bd9Sstevel@tonic-gate  * Due to a lack of meaningful error code in DDI, the gauranteed return of
15407c478bd9Sstevel@tonic-gate  * DDI_SUCCESS from here makes the code organization readable/easier from
15417c478bd9Sstevel@tonic-gate  * the generic code.
15427c478bd9Sstevel@tonic-gate  */
15437c478bd9Sstevel@tonic-gate /*ARGSUSED*/
15447c478bd9Sstevel@tonic-gate int
px_lib_map_vconfig(dev_info_t * dip,ddi_map_req_t * mp,pci_config_offset_t off,pci_regspec_t * rp,caddr_t * addrp)15457c478bd9Sstevel@tonic-gate px_lib_map_vconfig(dev_info_t *dip,
1546*d5ebc493SDan Cross     ddi_map_req_t *mp, pci_config_offset_t off,
1547*d5ebc493SDan Cross     pci_regspec_t *rp, caddr_t *addrp)
15487c478bd9Sstevel@tonic-gate {
1549eae2e508Skrishnae 	int fmcap;
1550eae2e508Skrishnae 	ndi_err_t *errp;
1551eae2e508Skrishnae 	on_trap_data_t *otp;
15527c478bd9Sstevel@tonic-gate 	ddi_acc_hdl_t *hp;
15537c478bd9Sstevel@tonic-gate 	ddi_acc_impl_t *ap;
15547c478bd9Sstevel@tonic-gate 	uchar_t busnum;	/* bus number */
15557c478bd9Sstevel@tonic-gate 	uchar_t devnum;	/* device number */
15567c478bd9Sstevel@tonic-gate 	uchar_t funcnum; /* function number */
15577c478bd9Sstevel@tonic-gate 	px_config_acc_pvt_t *px_pvt;
15587c478bd9Sstevel@tonic-gate 
15597c478bd9Sstevel@tonic-gate 	hp = (ddi_acc_hdl_t *)mp->map_handlep;
15607c478bd9Sstevel@tonic-gate 	ap = (ddi_acc_impl_t *)hp->ah_platform_private;
15617c478bd9Sstevel@tonic-gate 
15627c478bd9Sstevel@tonic-gate 	/* Check for mapping teardown operation */
15637c478bd9Sstevel@tonic-gate 	if ((mp->map_op == DDI_MO_UNMAP) ||
1564eae2e508Skrishnae 	    (mp->map_op == DDI_MO_UNLOCK)) {
15657c478bd9Sstevel@tonic-gate 		/* free up memory allocated for the private access handle. */
15667c478bd9Sstevel@tonic-gate 		px_pvt = (px_config_acc_pvt_t *)hp->ah_bus_private;
15677c478bd9Sstevel@tonic-gate 		kmem_free((void *)px_pvt, sizeof (px_config_acc_pvt_t));
15687c478bd9Sstevel@tonic-gate 
15697c478bd9Sstevel@tonic-gate 		/* unmap operation of PCI IO/config space. */
15707c478bd9Sstevel@tonic-gate 		return (DDI_SUCCESS);
15717c478bd9Sstevel@tonic-gate 	}
15727c478bd9Sstevel@tonic-gate 
1573eae2e508Skrishnae 	fmcap = ddi_fm_capable(dip);
1574eae2e508Skrishnae 	if (DDI_FM_ACC_ERR_CAP(fmcap)) {
1575eae2e508Skrishnae 		errp = ((ddi_acc_impl_t *)hp)->ahi_err;
1576eae2e508Skrishnae 		otp = (on_trap_data_t *)errp->err_ontrap;
1577eae2e508Skrishnae 		otp->ot_handle = (void *)(hp);
1578eae2e508Skrishnae 		otp->ot_prot = OT_DATA_ACCESS;
1579eae2e508Skrishnae 		errp->err_status = DDI_FM_OK;
1580eae2e508Skrishnae 		errp->err_expected = DDI_FM_ERR_UNEXPECTED;
1581eae2e508Skrishnae 		errp->err_cf = px_err_cfg_hdl_check;
1582eae2e508Skrishnae 	}
1583eae2e508Skrishnae 
15847c478bd9Sstevel@tonic-gate 	ap->ahi_get8 = px_pci_config_get8;
15857c478bd9Sstevel@tonic-gate 	ap->ahi_get16 = px_pci_config_get16;
15867c478bd9Sstevel@tonic-gate 	ap->ahi_get32 = px_pci_config_get32;
15877c478bd9Sstevel@tonic-gate 	ap->ahi_get64 = px_pci_config_get64;
15887c478bd9Sstevel@tonic-gate 	ap->ahi_put8 = px_pci_config_put8;
15897c478bd9Sstevel@tonic-gate 	ap->ahi_put16 = px_pci_config_put16;
15907c478bd9Sstevel@tonic-gate 	ap->ahi_put32 = px_pci_config_put32;
15917c478bd9Sstevel@tonic-gate 	ap->ahi_put64 = px_pci_config_put64;
15927c478bd9Sstevel@tonic-gate 	ap->ahi_rep_get8 = px_pci_config_rep_get8;
15937c478bd9Sstevel@tonic-gate 	ap->ahi_rep_get16 = px_pci_config_rep_get16;
15947c478bd9Sstevel@tonic-gate 	ap->ahi_rep_get32 = px_pci_config_rep_get32;
15957c478bd9Sstevel@tonic-gate 	ap->ahi_rep_get64 = px_pci_config_rep_get64;
15967c478bd9Sstevel@tonic-gate 	ap->ahi_rep_put8 = px_pci_config_rep_put8;
15977c478bd9Sstevel@tonic-gate 	ap->ahi_rep_put16 = px_pci_config_rep_put16;
15987c478bd9Sstevel@tonic-gate 	ap->ahi_rep_put32 = px_pci_config_rep_put32;
15997c478bd9Sstevel@tonic-gate 	ap->ahi_rep_put64 = px_pci_config_rep_put64;
16007c478bd9Sstevel@tonic-gate 
16017c478bd9Sstevel@tonic-gate 	/* Initialize to default check/notify functions */
16027c478bd9Sstevel@tonic-gate 	ap->ahi_fault = 0;
16037c478bd9Sstevel@tonic-gate 	ap->ahi_fault_check = i_ddi_acc_fault_check;
16047c478bd9Sstevel@tonic-gate 	ap->ahi_fault_notify = i_ddi_acc_fault_notify;
16057c478bd9Sstevel@tonic-gate 
16067c478bd9Sstevel@tonic-gate 	/* allocate memory for our private handle */
16077c478bd9Sstevel@tonic-gate 	px_pvt = (px_config_acc_pvt_t *)
1608eae2e508Skrishnae 	    kmem_zalloc(sizeof (px_config_acc_pvt_t), KM_SLEEP);
16097c478bd9Sstevel@tonic-gate 	hp->ah_bus_private = (void *)px_pvt;
16107c478bd9Sstevel@tonic-gate 
16117c478bd9Sstevel@tonic-gate 	busnum = PCI_REG_BUS_G(rp->pci_phys_hi);
16127c478bd9Sstevel@tonic-gate 	devnum = PCI_REG_DEV_G(rp->pci_phys_hi);
16137c478bd9Sstevel@tonic-gate 	funcnum = PCI_REG_FUNC_G(rp->pci_phys_hi);
16147c478bd9Sstevel@tonic-gate 
16157c478bd9Sstevel@tonic-gate 	/* set up private data for use during IO routines */
16167c478bd9Sstevel@tonic-gate 
16177c478bd9Sstevel@tonic-gate 	/* addr needed by the HV APIs */
16187c478bd9Sstevel@tonic-gate 	px_pvt->raddr = busnum << 16 | devnum << 11 | funcnum << 8;
16197c478bd9Sstevel@tonic-gate 	/*
16207c478bd9Sstevel@tonic-gate 	 * Address that specifies the actual offset into the 256MB
16217c478bd9Sstevel@tonic-gate 	 * memory mapped configuration space, 4K per device.
16227c478bd9Sstevel@tonic-gate 	 * First 12bits form the offset into 4K config space.
16237c478bd9Sstevel@tonic-gate 	 * This address is only used during the IO routines to calculate
16247c478bd9Sstevel@tonic-gate 	 * the offset at which the transaction must be performed.
16257c478bd9Sstevel@tonic-gate 	 * Drivers bypassing DDI functions to access PCI config space will
16267c478bd9Sstevel@tonic-gate 	 * panic the system since the following is a bogus virtual address.
16277c478bd9Sstevel@tonic-gate 	 */
16287c478bd9Sstevel@tonic-gate 	px_pvt->vaddr = busnum << 20 | devnum << 15 | funcnum << 12 | off;
16297c478bd9Sstevel@tonic-gate 	px_pvt->dip = dip;
16307c478bd9Sstevel@tonic-gate 
16317c478bd9Sstevel@tonic-gate 	DBG(DBG_LIB_CFG, dip, "px_config_setup: raddr 0x%x, vaddr 0x%x\n",
1632eae2e508Skrishnae 	    px_pvt->raddr, px_pvt->vaddr);
1633b40cec45Skrishnae 	*addrp = (caddr_t)(uintptr_t)px_pvt->vaddr;
16347c478bd9Sstevel@tonic-gate 	return (DDI_SUCCESS);
16357c478bd9Sstevel@tonic-gate }
16367c478bd9Sstevel@tonic-gate 
16374fbb58f6Sjchu /*ARGSUSED*/
16384fbb58f6Sjchu void
px_lib_map_attr_check(ddi_map_req_t * mp)16394fbb58f6Sjchu px_lib_map_attr_check(ddi_map_req_t *mp)
16404fbb58f6Sjchu {
16414fbb58f6Sjchu }
16424fbb58f6Sjchu 
1643f8d2de6bSjchu /*
1644f8d2de6bSjchu  * px_lib_log_safeacc_err:
1645f8d2de6bSjchu  * Imitate a cpu/mem trap call when a peek/poke fails.
1646f8d2de6bSjchu  * This will initiate something similar to px_fm_callback.
1647f8d2de6bSjchu  */
16487c478bd9Sstevel@tonic-gate static void
px_lib_log_safeacc_err(px_t * px_p,ddi_acc_handle_t handle,int fme_flag,r_addr_t addr)1649bf8fc234Set px_lib_log_safeacc_err(px_t *px_p, ddi_acc_handle_t handle, int fme_flag,
1650bf8fc234Set     r_addr_t addr)
16517c478bd9Sstevel@tonic-gate {
1652bf8fc234Set 	uint32_t	addr_high, addr_low;
1653c85864d8SKrishna Elango 	pcie_req_id_t	bdf = PCIE_INVALID_BDF;
165426947304SEvan Yan 	pci_ranges_t	*ranges_p;
1655bf8fc234Set 	int		range_len, i;
16567c478bd9Sstevel@tonic-gate 	ddi_acc_impl_t *hp = (ddi_acc_impl_t *)handle;
16577c478bd9Sstevel@tonic-gate 	ddi_fm_error_t derr;
16587c478bd9Sstevel@tonic-gate 
1659fc256490SJason Beloro 	if (px_fm_enter(px_p) != DDI_SUCCESS)
1660fc256490SJason Beloro 		return;
1661fc256490SJason Beloro 
16627c478bd9Sstevel@tonic-gate 	derr.fme_status = DDI_FM_NONFATAL;
16637c478bd9Sstevel@tonic-gate 	derr.fme_version = DDI_FME_VERSION;
16647c478bd9Sstevel@tonic-gate 	derr.fme_flag = fme_flag;
16657c478bd9Sstevel@tonic-gate 	derr.fme_ena = fm_ena_generate(0, FM_ENA_FMT1);
16667c478bd9Sstevel@tonic-gate 	derr.fme_acc_handle = handle;
16677c478bd9Sstevel@tonic-gate 	if (hp)
16687c478bd9Sstevel@tonic-gate 		hp->ahi_err->err_expected = DDI_FM_ERR_EXPECTED;
16697c478bd9Sstevel@tonic-gate 
1670bf8fc234Set 	addr_high = (uint32_t)(addr >> 32);
1671bf8fc234Set 	addr_low = (uint32_t)addr;
1672bf8fc234Set 
1673bf8fc234Set 	/*
1674bf8fc234Set 	 * Make sure this failed load came from this PCIe port.  Check by
1675bf8fc234Set 	 * matching the upper 32 bits of the address with the ranges property.
1676bf8fc234Set 	 */
167726947304SEvan Yan 	range_len = px_p->px_ranges_length / sizeof (pci_ranges_t);
1678bf8fc234Set 	i = 0;
1679bf8fc234Set 	for (ranges_p = px_p->px_ranges_p; i < range_len; i++, ranges_p++) {
1680bf8fc234Set 		if (ranges_p->parent_high == addr_high) {
1681bf8fc234Set 			switch (ranges_p->child_high & PCI_ADDR_MASK) {
1682bf8fc234Set 			case PCI_ADDR_CONFIG:
1683bf8fc234Set 				bdf = (pcie_req_id_t)(addr_low >> 12);
1684bf8fc234Set 				break;
1685bf8fc234Set 			default:
1686c85864d8SKrishna Elango 				bdf = PCIE_INVALID_BDF;
1687bf8fc234Set 				break;
1688bf8fc234Set 			}
1689bf8fc234Set 			break;
1690bf8fc234Set 		}
1691bf8fc234Set 	}
1692bf8fc234Set 
1693e214b19eSToomas Soome 	(void) px_rp_en_q(px_p, bdf, addr, 0);
1694fc256490SJason Beloro 	(void) px_scan_fabric(px_p, px_p->px_dip, &derr);
1695fc256490SJason Beloro 	px_fm_exit(px_p);
16967c478bd9Sstevel@tonic-gate }
16977c478bd9Sstevel@tonic-gate 
16987c478bd9Sstevel@tonic-gate 
16997c478bd9Sstevel@tonic-gate #ifdef  DEBUG
17007c478bd9Sstevel@tonic-gate int	px_peekfault_cnt = 0;
17017c478bd9Sstevel@tonic-gate int	px_pokefault_cnt = 0;
17027c478bd9Sstevel@tonic-gate #endif  /* DEBUG */
17037c478bd9Sstevel@tonic-gate 
17047c478bd9Sstevel@tonic-gate /*
17057c478bd9Sstevel@tonic-gate  * Do a safe write to a device.
17067c478bd9Sstevel@tonic-gate  *
17077c478bd9Sstevel@tonic-gate  * When this function is given a handle (cautious access), all errors are
17087c478bd9Sstevel@tonic-gate  * suppressed.
17097c478bd9Sstevel@tonic-gate  *
17107c478bd9Sstevel@tonic-gate  * When this function is not given a handle (poke), only Unsupported Request
17117c478bd9Sstevel@tonic-gate  * and Completer Abort errors are suppressed.
17127c478bd9Sstevel@tonic-gate  *
17137c478bd9Sstevel@tonic-gate  * In all cases, all errors are returned in the function return status.
17147c478bd9Sstevel@tonic-gate  */
17157c478bd9Sstevel@tonic-gate 
17167c478bd9Sstevel@tonic-gate int
px_lib_ctlops_poke(dev_info_t * dip,dev_info_t * rdip,peekpoke_ctlops_t * in_args)17177c478bd9Sstevel@tonic-gate px_lib_ctlops_poke(dev_info_t *dip, dev_info_t *rdip,
17187c478bd9Sstevel@tonic-gate     peekpoke_ctlops_t *in_args)
17197c478bd9Sstevel@tonic-gate {
17207c478bd9Sstevel@tonic-gate 	px_t *px_p = DIP_TO_STATE(dip);
17217c478bd9Sstevel@tonic-gate 	px_pec_t *pec_p = px_p->px_pec_p;
1722f8d2de6bSjchu 	ddi_acc_impl_t *hp = (ddi_acc_impl_t *)in_args->handle;
17237c478bd9Sstevel@tonic-gate 
17247c478bd9Sstevel@tonic-gate 	size_t repcount = in_args->repcount;
17257c478bd9Sstevel@tonic-gate 	size_t size = in_args->size;
17267c478bd9Sstevel@tonic-gate 	uintptr_t dev_addr = in_args->dev_addr;
17277c478bd9Sstevel@tonic-gate 	uintptr_t host_addr = in_args->host_addr;
17287c478bd9Sstevel@tonic-gate 
17297c478bd9Sstevel@tonic-gate 	int err	= DDI_SUCCESS;
17307c478bd9Sstevel@tonic-gate 	uint64_t hvio_poke_status;
17317c478bd9Sstevel@tonic-gate 	uint32_t wrt_stat;
17327c478bd9Sstevel@tonic-gate 
17337c478bd9Sstevel@tonic-gate 	r_addr_t ra;
17347c478bd9Sstevel@tonic-gate 	uint64_t pokeval;
1735939f5b68Saa 	pcie_req_id_t bdf;
1736f8d2de6bSjchu 
17377c478bd9Sstevel@tonic-gate 	ra = (r_addr_t)va_to_pa((void *)dev_addr);
17387c478bd9Sstevel@tonic-gate 	for (; repcount; repcount--) {
17397c478bd9Sstevel@tonic-gate 
17407c478bd9Sstevel@tonic-gate 		switch (size) {
17417c478bd9Sstevel@tonic-gate 		case sizeof (uint8_t):
17427c478bd9Sstevel@tonic-gate 			pokeval = *(uint8_t *)host_addr;
17437c478bd9Sstevel@tonic-gate 			break;
17447c478bd9Sstevel@tonic-gate 		case sizeof (uint16_t):
17457c478bd9Sstevel@tonic-gate 			pokeval = *(uint16_t *)host_addr;
17467c478bd9Sstevel@tonic-gate 			break;
17477c478bd9Sstevel@tonic-gate 		case sizeof (uint32_t):
17487c478bd9Sstevel@tonic-gate 			pokeval = *(uint32_t *)host_addr;
17497c478bd9Sstevel@tonic-gate 			break;
17507c478bd9Sstevel@tonic-gate 		case sizeof (uint64_t):
17517c478bd9Sstevel@tonic-gate 			pokeval = *(uint64_t *)host_addr;
17527c478bd9Sstevel@tonic-gate 			break;
17537c478bd9Sstevel@tonic-gate 		default:
17547c478bd9Sstevel@tonic-gate 			DBG(DBG_MAP, px_p->px_dip,
17557c478bd9Sstevel@tonic-gate 			    "poke: invalid size %d passed\n", size);
17567c478bd9Sstevel@tonic-gate 			err = DDI_FAILURE;
17577c478bd9Sstevel@tonic-gate 			goto done;
17587c478bd9Sstevel@tonic-gate 		}
17597c478bd9Sstevel@tonic-gate 
17607c478bd9Sstevel@tonic-gate 		/*
1761f8d2de6bSjchu 		 * Grab pokefault mutex since hypervisor does not guarantee
1762f8d2de6bSjchu 		 * poke serialization.
17637c478bd9Sstevel@tonic-gate 		 */
1764f8d2de6bSjchu 		if (hp) {
1765f8d2de6bSjchu 			i_ndi_busop_access_enter(hp->ahi_common.ah_dip,
1766f8d2de6bSjchu 			    (ddi_acc_handle_t)hp);
1767f8d2de6bSjchu 			pec_p->pec_safeacc_type = DDI_FM_ERR_EXPECTED;
1768f8d2de6bSjchu 		} else {
1769f8d2de6bSjchu 			mutex_enter(&pec_p->pec_pokefault_mutex);
1770f8d2de6bSjchu 			pec_p->pec_safeacc_type = DDI_FM_ERR_POKE;
1771f8d2de6bSjchu 		}
1772f8d2de6bSjchu 
1773939f5b68Saa 		if (pcie_get_bdf_from_dip(rdip, &bdf) != DDI_SUCCESS) {
1774f8d2de6bSjchu 			err = DDI_FAILURE;
1775939f5b68Saa 			goto done;
1776939f5b68Saa 		}
1777939f5b68Saa 
1778939f5b68Saa 		hvio_poke_status = hvio_poke(px_p->px_dev_hdl, ra, size,
1779939f5b68Saa 		    pokeval, bdf << 8, &wrt_stat);
17807c478bd9Sstevel@tonic-gate 
17817c478bd9Sstevel@tonic-gate 		if ((hvio_poke_status != H_EOK) || (wrt_stat != H_EOK)) {
17827c478bd9Sstevel@tonic-gate 			err = DDI_FAILURE;
17837c478bd9Sstevel@tonic-gate #ifdef  DEBUG
17847c478bd9Sstevel@tonic-gate 			px_pokefault_cnt++;
17857c478bd9Sstevel@tonic-gate #endif
17867c478bd9Sstevel@tonic-gate 			/*
17877c478bd9Sstevel@tonic-gate 			 * For CAUTIOUS and POKE access, notify FMA to
1788f8d2de6bSjchu 			 * cleanup.  Imitate a cpu/mem trap call like in sun4u.
17897c478bd9Sstevel@tonic-gate 			 */
1790f8d2de6bSjchu 			px_lib_log_safeacc_err(px_p, (ddi_acc_handle_t)hp,
1791f8d2de6bSjchu 			    (hp ? DDI_FM_ERR_EXPECTED :
1792bf8fc234Set 			    DDI_FM_ERR_POKE), ra);
17937c478bd9Sstevel@tonic-gate 
1794f8d2de6bSjchu 			pec_p->pec_ontrap_data = NULL;
1795f8d2de6bSjchu 			pec_p->pec_safeacc_type = DDI_FM_ERR_UNEXPECTED;
1796f8d2de6bSjchu 			if (hp) {
1797f8d2de6bSjchu 				i_ndi_busop_access_exit(hp->ahi_common.ah_dip,
1798f8d2de6bSjchu 				    (ddi_acc_handle_t)hp);
1799f8d2de6bSjchu 			} else {
1800f8d2de6bSjchu 				mutex_exit(&pec_p->pec_pokefault_mutex);
1801f8d2de6bSjchu 			}
18027c478bd9Sstevel@tonic-gate 			goto done;
18037c478bd9Sstevel@tonic-gate 		}
18047c478bd9Sstevel@tonic-gate 
1805f8d2de6bSjchu 		pec_p->pec_ontrap_data = NULL;
1806f8d2de6bSjchu 		pec_p->pec_safeacc_type = DDI_FM_ERR_UNEXPECTED;
1807f8d2de6bSjchu 		if (hp) {
1808f8d2de6bSjchu 			i_ndi_busop_access_exit(hp->ahi_common.ah_dip,
1809f8d2de6bSjchu 			    (ddi_acc_handle_t)hp);
1810f8d2de6bSjchu 		} else {
1811f8d2de6bSjchu 			mutex_exit(&pec_p->pec_pokefault_mutex);
1812f8d2de6bSjchu 		}
1813f8d2de6bSjchu 
18147c478bd9Sstevel@tonic-gate 		host_addr += size;
18157c478bd9Sstevel@tonic-gate 
18167c478bd9Sstevel@tonic-gate 		if (in_args->flags == DDI_DEV_AUTOINCR) {
18177c478bd9Sstevel@tonic-gate 			dev_addr += size;
18187c478bd9Sstevel@tonic-gate 			ra = (r_addr_t)va_to_pa((void *)dev_addr);
18197c478bd9Sstevel@tonic-gate 		}
18207c478bd9Sstevel@tonic-gate 	}
18217c478bd9Sstevel@tonic-gate 
18227c478bd9Sstevel@tonic-gate done:
18237c478bd9Sstevel@tonic-gate 	return (err);
18247c478bd9Sstevel@tonic-gate }
18257c478bd9Sstevel@tonic-gate 
18267c478bd9Sstevel@tonic-gate 
18277c478bd9Sstevel@tonic-gate /*ARGSUSED*/
18287c478bd9Sstevel@tonic-gate int
px_lib_ctlops_peek(dev_info_t * dip,dev_info_t * rdip,peekpoke_ctlops_t * in_args,void * result)18297c478bd9Sstevel@tonic-gate px_lib_ctlops_peek(dev_info_t *dip, dev_info_t *rdip,
18307c478bd9Sstevel@tonic-gate     peekpoke_ctlops_t *in_args, void *result)
18317c478bd9Sstevel@tonic-gate {
18327c478bd9Sstevel@tonic-gate 	px_t *px_p = DIP_TO_STATE(dip);
18337c478bd9Sstevel@tonic-gate 	px_pec_t *pec_p = px_p->px_pec_p;
1834f8d2de6bSjchu 	ddi_acc_impl_t *hp = (ddi_acc_impl_t *)in_args->handle;
18357c478bd9Sstevel@tonic-gate 
18367c478bd9Sstevel@tonic-gate 	size_t repcount = in_args->repcount;
18377c478bd9Sstevel@tonic-gate 	uintptr_t dev_addr = in_args->dev_addr;
18387c478bd9Sstevel@tonic-gate 	uintptr_t host_addr = in_args->host_addr;
18397c478bd9Sstevel@tonic-gate 
18407c478bd9Sstevel@tonic-gate 	r_addr_t ra;
18417c478bd9Sstevel@tonic-gate 	uint32_t read_status;
18427c478bd9Sstevel@tonic-gate 	uint64_t hvio_peek_status;
18437c478bd9Sstevel@tonic-gate 	uint64_t peekval;
18447c478bd9Sstevel@tonic-gate 	int err = DDI_SUCCESS;
18457c478bd9Sstevel@tonic-gate 
18467c478bd9Sstevel@tonic-gate 	result = (void *)in_args->host_addr;
18477c478bd9Sstevel@tonic-gate 
18487c478bd9Sstevel@tonic-gate 	ra = (r_addr_t)va_to_pa((void *)dev_addr);
18497c478bd9Sstevel@tonic-gate 	for (; repcount; repcount--) {
18507c478bd9Sstevel@tonic-gate 
18517c478bd9Sstevel@tonic-gate 		/* Lock pokefault mutex so read doesn't mask a poke fault. */
1852f8d2de6bSjchu 		if (hp) {
1853f8d2de6bSjchu 			i_ndi_busop_access_enter(hp->ahi_common.ah_dip,
1854f8d2de6bSjchu 			    (ddi_acc_handle_t)hp);
1855f8d2de6bSjchu 			pec_p->pec_safeacc_type = DDI_FM_ERR_EXPECTED;
1856f8d2de6bSjchu 		} else {
1857f8d2de6bSjchu 			mutex_enter(&pec_p->pec_pokefault_mutex);
1858f8d2de6bSjchu 			pec_p->pec_safeacc_type = DDI_FM_ERR_PEEK;
1859f8d2de6bSjchu 		}
18607c478bd9Sstevel@tonic-gate 
18617c478bd9Sstevel@tonic-gate 		hvio_peek_status = hvio_peek(px_p->px_dev_hdl, ra,
18627c478bd9Sstevel@tonic-gate 		    in_args->size, &read_status, &peekval);
18637c478bd9Sstevel@tonic-gate 
18647c478bd9Sstevel@tonic-gate 		if ((hvio_peek_status != H_EOK) || (read_status != H_EOK)) {
18657c478bd9Sstevel@tonic-gate 			err = DDI_FAILURE;
18667c478bd9Sstevel@tonic-gate 
18677c478bd9Sstevel@tonic-gate 			/*
18687c478bd9Sstevel@tonic-gate 			 * For CAUTIOUS and PEEK access, notify FMA to
1869f8d2de6bSjchu 			 * cleanup.  Imitate a cpu/mem trap call like in sun4u.
18707c478bd9Sstevel@tonic-gate 			 */
1871f8d2de6bSjchu 			px_lib_log_safeacc_err(px_p, (ddi_acc_handle_t)hp,
1872f8d2de6bSjchu 			    (hp ? DDI_FM_ERR_EXPECTED :
1873bf8fc234Set 			    DDI_FM_ERR_PEEK), ra);
18747c478bd9Sstevel@tonic-gate 
18757c478bd9Sstevel@tonic-gate 			/* Stuff FFs in host addr if peek. */
1876f8d2de6bSjchu 			if (hp == NULL) {
18777c478bd9Sstevel@tonic-gate 				int i;
18787c478bd9Sstevel@tonic-gate 				uint8_t *ff_addr = (uint8_t *)host_addr;
18797c478bd9Sstevel@tonic-gate 				for (i = 0; i < in_args->size; i++)
18807c478bd9Sstevel@tonic-gate 					*ff_addr++ = 0xff;
18817c478bd9Sstevel@tonic-gate 			}
18827c478bd9Sstevel@tonic-gate #ifdef  DEBUG
18837c478bd9Sstevel@tonic-gate 			px_peekfault_cnt++;
18847c478bd9Sstevel@tonic-gate #endif
1885f8d2de6bSjchu 			pec_p->pec_ontrap_data = NULL;
1886f8d2de6bSjchu 			pec_p->pec_safeacc_type = DDI_FM_ERR_UNEXPECTED;
1887f8d2de6bSjchu 			if (hp) {
1888f8d2de6bSjchu 				i_ndi_busop_access_exit(hp->ahi_common.ah_dip,
1889f8d2de6bSjchu 				    (ddi_acc_handle_t)hp);
1890f8d2de6bSjchu 			} else {
1891f8d2de6bSjchu 				mutex_exit(&pec_p->pec_pokefault_mutex);
1892f8d2de6bSjchu 			}
18937c478bd9Sstevel@tonic-gate 			goto done;
18947c478bd9Sstevel@tonic-gate 
1895f8d2de6bSjchu 		}
1896f8d2de6bSjchu 		pec_p->pec_ontrap_data = NULL;
1897f8d2de6bSjchu 		pec_p->pec_safeacc_type = DDI_FM_ERR_UNEXPECTED;
1898f8d2de6bSjchu 		if (hp) {
1899f8d2de6bSjchu 			i_ndi_busop_access_exit(hp->ahi_common.ah_dip,
1900f8d2de6bSjchu 			    (ddi_acc_handle_t)hp);
19017c478bd9Sstevel@tonic-gate 		} else {
1902f8d2de6bSjchu 			mutex_exit(&pec_p->pec_pokefault_mutex);
1903f8d2de6bSjchu 		}
19047c478bd9Sstevel@tonic-gate 
1905f8d2de6bSjchu 		switch (in_args->size) {
1906f8d2de6bSjchu 		case sizeof (uint8_t):
1907f8d2de6bSjchu 			*(uint8_t *)host_addr = (uint8_t)peekval;
1908f8d2de6bSjchu 			break;
1909f8d2de6bSjchu 		case sizeof (uint16_t):
1910f8d2de6bSjchu 			*(uint16_t *)host_addr = (uint16_t)peekval;
1911f8d2de6bSjchu 			break;
1912f8d2de6bSjchu 		case sizeof (uint32_t):
1913f8d2de6bSjchu 			*(uint32_t *)host_addr = (uint32_t)peekval;
1914f8d2de6bSjchu 			break;
1915f8d2de6bSjchu 		case sizeof (uint64_t):
1916f8d2de6bSjchu 			*(uint64_t *)host_addr = (uint64_t)peekval;
1917f8d2de6bSjchu 			break;
1918f8d2de6bSjchu 		default:
1919f8d2de6bSjchu 			DBG(DBG_MAP, px_p->px_dip,
1920f8d2de6bSjchu 			    "peek: invalid size %d passed\n",
1921f8d2de6bSjchu 			    in_args->size);
1922f8d2de6bSjchu 			err = DDI_FAILURE;
1923f8d2de6bSjchu 			goto done;
19247c478bd9Sstevel@tonic-gate 		}
19257c478bd9Sstevel@tonic-gate 
19267c478bd9Sstevel@tonic-gate 		host_addr += in_args->size;
19277c478bd9Sstevel@tonic-gate 
19287c478bd9Sstevel@tonic-gate 		if (in_args->flags == DDI_DEV_AUTOINCR) {
19297c478bd9Sstevel@tonic-gate 			dev_addr += in_args->size;
19307c478bd9Sstevel@tonic-gate 			ra = (r_addr_t)va_to_pa((void *)dev_addr);
19317c478bd9Sstevel@tonic-gate 		}
19327c478bd9Sstevel@tonic-gate 	}
19337c478bd9Sstevel@tonic-gate done:
19347c478bd9Sstevel@tonic-gate 	return (err);
19357c478bd9Sstevel@tonic-gate }
19367c478bd9Sstevel@tonic-gate 
1937f8d2de6bSjchu 
1938f8d2de6bSjchu /* add interrupt vector */
1939f8d2de6bSjchu int
px_err_add_intr(px_fault_t * px_fault_p)1940f8d2de6bSjchu px_err_add_intr(px_fault_t *px_fault_p)
1941f8d2de6bSjchu {
1942f8d2de6bSjchu 	px_t	*px_p = DIP_TO_STATE(px_fault_p->px_fh_dip);
1943f8d2de6bSjchu 
1944f8d2de6bSjchu 	DBG(DBG_LIB_INT, px_p->px_dip,
1945f8d2de6bSjchu 	    "px_err_add_intr: calling add_ivintr");
1946f8d2de6bSjchu 
1947b0fc0e77Sgovinda 	VERIFY(add_ivintr(px_fault_p->px_fh_sysino, PX_ERR_PIL,
1948b0fc0e77Sgovinda 	    (intrfunc)px_fault_p->px_err_func, (caddr_t)px_fault_p, NULL,
1949b0fc0e77Sgovinda 	    (caddr_t)&px_fault_p->px_intr_payload[0]) == 0);
1950f8d2de6bSjchu 
1951f8d2de6bSjchu 	DBG(DBG_LIB_INT, px_p->px_dip,
1952f8d2de6bSjchu 	    "px_err_add_intr: ib_intr_enable ");
1953f8d2de6bSjchu 
1954f8d2de6bSjchu 	px_ib_intr_enable(px_p, intr_dist_cpuid(), px_fault_p->px_intr_ino);
1955f8d2de6bSjchu 
1956b0fc0e77Sgovinda 	return (DDI_SUCCESS);
1957f8d2de6bSjchu }
1958f8d2de6bSjchu 
1959f8d2de6bSjchu /* remove interrupt vector */
1960f8d2de6bSjchu void
px_err_rem_intr(px_fault_t * px_fault_p)1961f8d2de6bSjchu px_err_rem_intr(px_fault_t *px_fault_p)
1962f8d2de6bSjchu {
1963f8d2de6bSjchu 	px_t	*px_p = DIP_TO_STATE(px_fault_p->px_fh_dip);
1964f8d2de6bSjchu 
1965f8d2de6bSjchu 	px_ib_intr_disable(px_p->px_ib_p, px_fault_p->px_intr_ino,
1966f8d2de6bSjchu 	    IB_INTR_WAIT);
19679c75c6bfSgovinda 
1968b0fc0e77Sgovinda 	VERIFY(rem_ivintr(px_fault_p->px_fh_sysino, PX_ERR_PIL) == 0);
1969f8d2de6bSjchu }
1970f8d2de6bSjchu 
1971a3c68edcSjchu void
px_cb_intr_redist(void * arg)1972a3c68edcSjchu px_cb_intr_redist(void *arg)
1973a3c68edcSjchu {
1974a3c68edcSjchu 	px_t	*px_p = (px_t *)arg;
1975a3c68edcSjchu 	px_ib_intr_dist_en(px_p->px_dip, intr_dist_cpuid(),
1976a3c68edcSjchu 	    px_p->px_inos[PX_INTR_XBC], B_FALSE);
1977a3c68edcSjchu }
1978a3c68edcSjchu 
197901689544Sjchu int
px_cb_add_intr(px_fault_t * f_p)198001689544Sjchu px_cb_add_intr(px_fault_t *f_p)
198101689544Sjchu {
1982a3c68edcSjchu 	px_t	*px_p = DIP_TO_STATE(f_p->px_fh_dip);
1983a3c68edcSjchu 
1984a3c68edcSjchu 	DBG(DBG_LIB_INT, px_p->px_dip,
1985a3c68edcSjchu 	    "px_err_add_intr: calling add_ivintr");
1986a3c68edcSjchu 
1987a3c68edcSjchu 	VERIFY(add_ivintr(f_p->px_fh_sysino, PX_ERR_PIL,
1988a3c68edcSjchu 	    (intrfunc)f_p->px_err_func, (caddr_t)f_p, NULL,
1989a3c68edcSjchu 	    (caddr_t)&f_p->px_intr_payload[0]) == 0);
1990a3c68edcSjchu 
1991a3c68edcSjchu 	intr_dist_add(px_cb_intr_redist, px_p);
1992a3c68edcSjchu 
1993a3c68edcSjchu 	DBG(DBG_LIB_INT, px_p->px_dip,
1994a3c68edcSjchu 	    "px_err_add_intr: ib_intr_enable ");
1995a3c68edcSjchu 
1996a3c68edcSjchu 	px_ib_intr_enable(px_p, intr_dist_cpuid(), f_p->px_intr_ino);
1997a3c68edcSjchu 
1998a3c68edcSjchu 	return (DDI_SUCCESS);
199901689544Sjchu }
200001689544Sjchu 
200101689544Sjchu void
px_cb_rem_intr(px_fault_t * f_p)200201689544Sjchu px_cb_rem_intr(px_fault_t *f_p)
200301689544Sjchu {
2004a3c68edcSjchu 	intr_dist_rem(px_cb_intr_redist, DIP_TO_STATE(f_p->px_fh_dip));
200501689544Sjchu 	px_err_rem_intr(f_p);
200601689544Sjchu }
200701689544Sjchu 
2008f8d2de6bSjchu #ifdef FMA
2009f8d2de6bSjchu void
px_fill_rc_status(px_fault_t * px_fault_p,pciex_rc_error_regs_t * rc_status)2010f8d2de6bSjchu px_fill_rc_status(px_fault_t *px_fault_p, pciex_rc_error_regs_t *rc_status)
2011f8d2de6bSjchu {
2012f8d2de6bSjchu 	px_pec_err_t	*err_pkt;
2013f8d2de6bSjchu 
2014f8d2de6bSjchu 	err_pkt = (px_pec_err_t *)px_fault_p->px_intr_payload;
2015f8d2de6bSjchu 
2016f8d2de6bSjchu 	/* initialise all the structure members */
2017f8d2de6bSjchu 	rc_status->status_valid = 0;
2018f8d2de6bSjchu 
2019f8d2de6bSjchu 	if (err_pkt->pec_descr.P) {
2020f8d2de6bSjchu 		/* PCI Status Register */
2021f8d2de6bSjchu 		rc_status->pci_err_status = err_pkt->pci_err_status;
2022f8d2de6bSjchu 		rc_status->status_valid |= PCI_ERR_STATUS_VALID;
2023f8d2de6bSjchu 	}
2024f8d2de6bSjchu 
2025f8d2de6bSjchu 	if (err_pkt->pec_descr.E) {
2026f8d2de6bSjchu 		/* PCIe Status Register */
2027f8d2de6bSjchu 		rc_status->pcie_err_status = err_pkt->pcie_err_status;
2028f8d2de6bSjchu 		rc_status->status_valid |= PCIE_ERR_STATUS_VALID;
2029f8d2de6bSjchu 	}
2030f8d2de6bSjchu 
2031f8d2de6bSjchu 	if (err_pkt->pec_descr.U) {
2032f8d2de6bSjchu 		rc_status->ue_status = err_pkt->ue_reg_status;
2033f8d2de6bSjchu 		rc_status->status_valid |= UE_STATUS_VALID;
2034f8d2de6bSjchu 	}
2035f8d2de6bSjchu 
2036f8d2de6bSjchu 	if (err_pkt->pec_descr.H) {
2037f8d2de6bSjchu 		rc_status->ue_hdr1 = err_pkt->hdr[0];
2038f8d2de6bSjchu 		rc_status->status_valid |= UE_HDR1_VALID;
2039f8d2de6bSjchu 	}
2040f8d2de6bSjchu 
2041f8d2de6bSjchu 	if (err_pkt->pec_descr.I) {
2042f8d2de6bSjchu 		rc_status->ue_hdr2 = err_pkt->hdr[1];
2043f8d2de6bSjchu 		rc_status->status_valid |= UE_HDR2_VALID;
2044f8d2de6bSjchu 	}
2045f8d2de6bSjchu 
2046f8d2de6bSjchu 	/* ue_fst_err_ptr - not available for sun4v?? */
2047f8d2de6bSjchu 
2048f8d2de6bSjchu 
2049f8d2de6bSjchu 	if (err_pkt->pec_descr.S) {
2050f8d2de6bSjchu 		rc_status->source_id = err_pkt->err_src_reg;
2051f8d2de6bSjchu 		rc_status->status_valid |= SOURCE_ID_VALID;
2052f8d2de6bSjchu 	}
2053f8d2de6bSjchu 
2054f8d2de6bSjchu 	if (err_pkt->pec_descr.R) {
2055f8d2de6bSjchu 		rc_status->root_err_status = err_pkt->root_err_status;
2056f8d2de6bSjchu 		rc_status->status_valid |= CE_STATUS_VALID;
2057f8d2de6bSjchu 	}
2058f8d2de6bSjchu }
2059f8d2de6bSjchu #endif
2060f8d2de6bSjchu 
20617c478bd9Sstevel@tonic-gate /*ARGSUSED*/
20627c478bd9Sstevel@tonic-gate int
px_lib_pmctl(int cmd,px_t * px_p)20637c478bd9Sstevel@tonic-gate px_lib_pmctl(int cmd, px_t *px_p)
20647c478bd9Sstevel@tonic-gate {
20657c478bd9Sstevel@tonic-gate 	return (DDI_FAILURE);
20667c478bd9Sstevel@tonic-gate }
20671a887b2eSjchu 
20681a887b2eSjchu /*ARGSUSED*/
20691a887b2eSjchu uint_t
px_pmeq_intr(caddr_t arg)20701a887b2eSjchu px_pmeq_intr(caddr_t arg)
20711a887b2eSjchu {
20721a887b2eSjchu 	return (DDI_INTR_CLAIMED);
20731a887b2eSjchu }
20748bc7d88aSet 
20758bc7d88aSet /*
2076c0da6274SZhi-Jun Robin Fu  * fetch the config space base addr of the root complex
2077c0da6274SZhi-Jun Robin Fu  * note this depends on px structure being initialized
20788bc7d88aSet  */
2079c0da6274SZhi-Jun Robin Fu uint64_t
px_lib_get_cfgacc_base(dev_info_t * dip)2080c0da6274SZhi-Jun Robin Fu px_lib_get_cfgacc_base(dev_info_t *dip)
2081c0da6274SZhi-Jun Robin Fu {
2082c0da6274SZhi-Jun Robin Fu 	int		instance = DIP_TO_INST(dip);
2083c0da6274SZhi-Jun Robin Fu 	px_t		*px_p = INST_TO_STATE(instance);
20848bc7d88aSet 
2085c0da6274SZhi-Jun Robin Fu 	return (px_p->px_dev_hdl);
20868bc7d88aSet }
2087817a6df8Sjchu 
2088fc256490SJason Beloro void
px_panic_domain(px_t * px_p,pcie_req_id_t bdf)2089fc256490SJason Beloro px_panic_domain(px_t *px_p, pcie_req_id_t bdf)
2090fc256490SJason Beloro {
2091fc256490SJason Beloro 	uint64_t	ret;
2092fc256490SJason Beloro 	dev_info_t	*dip = px_p->px_dip;
2093fc256490SJason Beloro 
2094fc256490SJason Beloro 	DBG(DBG_ERR_INTR, dip, "px_panic_domain: handle 0x%lx, ino %d, "
2095fc256490SJason Beloro 	    "bdf<<8 0x%lx\n",
2096fc256490SJason Beloro 	    (uint64_t)DIP_TO_HANDLE(dip), px_p->px_cb_fault.px_intr_ino,
2097fc256490SJason Beloro 	    (pci_device_t)bdf << 8);
2098fc256490SJason Beloro 	if ((ret = pci_error_send(DIP_TO_HANDLE(dip),
2099fc256490SJason Beloro 	    px_p->px_cb_fault.px_intr_ino, (pci_device_t)bdf << 8)) != H_EOK) {
2100fc256490SJason Beloro 		DBG(DBG_ERR_INTR, dip, "pci_error_send failed, ret 0x%lx\n",
2101fc256490SJason Beloro 		    ret);
2102fc256490SJason Beloro 	} else
2103fc256490SJason Beloro 		DBG(DBG_ERR_INTR, dip, "pci_error_send worked\n");
2104fc256490SJason Beloro }
2105fc256490SJason Beloro 
2106b65731f1Skini /*ARGSUSED*/
2107b65731f1Skini int
px_lib_hotplug_init(dev_info_t * dip,void * arg)2108b65731f1Skini px_lib_hotplug_init(dev_info_t *dip, void *arg)
2109b65731f1Skini {
2110b65731f1Skini 	return (DDI_ENOTSUP);
2111b65731f1Skini }
2112b65731f1Skini 
2113b65731f1Skini /*ARGSUSED*/
2114b65731f1Skini void
px_lib_hotplug_uninit(dev_info_t * dip)2115b65731f1Skini px_lib_hotplug_uninit(dev_info_t *dip)
2116b65731f1Skini {
2117b65731f1Skini }
2118b65731f1Skini 
2119ab4471cdSscarter /*ARGSUSED*/
2120ab4471cdSscarter void
px_hp_intr_redist(px_t * px_p)2121ab4471cdSscarter px_hp_intr_redist(px_t *px_p)
2122ab4471cdSscarter {
2123ab4471cdSscarter }
2124ab4471cdSscarter 
2125817a6df8Sjchu /* Dummy cpr add callback */
2126817a6df8Sjchu /*ARGSUSED*/
2127817a6df8Sjchu void
px_cpr_add_callb(px_t * px_p)2128817a6df8Sjchu px_cpr_add_callb(px_t *px_p)
2129817a6df8Sjchu {
2130817a6df8Sjchu }
2131817a6df8Sjchu 
2132817a6df8Sjchu /* Dummy cpr rem callback */
2133817a6df8Sjchu /*ARGSUSED*/
2134817a6df8Sjchu void
px_cpr_rem_callb(px_t * px_p)2135817a6df8Sjchu px_cpr_rem_callb(px_t *px_p)
2136817a6df8Sjchu {
2137817a6df8Sjchu }
2138d60bae31Sdwoods 
2139d60bae31Sdwoods /*ARGSUSED*/
2140d60bae31Sdwoods boolean_t
px_lib_is_in_drain_state(px_t * px_p)2141d60bae31Sdwoods px_lib_is_in_drain_state(px_t *px_p)
2142d60bae31Sdwoods {
2143d60bae31Sdwoods 	return (B_FALSE);
2144d60bae31Sdwoods }
21457ea9b230Set 
21467ea9b230Set /*
21477ea9b230Set  * There is no IOAPI to get the BDF of the pcie root port nexus at this moment.
21487ea9b230Set  * Assume it is 0x0000, until otherwise noted.  For now, all sun4v platforms
21497ea9b230Set  * have programmed the BDF to be 0x0000.
21507ea9b230Set  */
21517ea9b230Set /*ARGSUSED*/
21527ea9b230Set pcie_req_id_t
px_lib_get_bdf(px_t * px_p)21537ea9b230Set px_lib_get_bdf(px_t *px_p)
21547ea9b230Set {
21557ea9b230Set 	return (0x0000);
21567ea9b230Set }
21570114761dSAlan Adamson, SD OSSD 
21580114761dSAlan Adamson, SD OSSD int
px_lib_get_root_complex_mps(px_t * px_p,dev_info_t * dip,int * mps)21590114761dSAlan Adamson, SD OSSD px_lib_get_root_complex_mps(px_t *px_p, dev_info_t *dip, int *mps)
21600114761dSAlan Adamson, SD OSSD {
21610114761dSAlan Adamson, SD OSSD 	pci_device_t	bdf = px_lib_get_bdf(px_p);
21620114761dSAlan Adamson, SD OSSD 
21630114761dSAlan Adamson, SD OSSD 	if (hvio_get_rp_mps_cap(DIP_TO_HANDLE(dip), bdf, mps) == H_EOK)
21640114761dSAlan Adamson, SD OSSD 		return (DDI_SUCCESS);
21650114761dSAlan Adamson, SD OSSD 	else
21660114761dSAlan Adamson, SD OSSD 		return (DDI_FAILURE);
21670114761dSAlan Adamson, SD OSSD }
21680114761dSAlan Adamson, SD OSSD 
21690114761dSAlan Adamson, SD OSSD int
px_lib_set_root_complex_mps(px_t * px_p,dev_info_t * dip,int mps)21700114761dSAlan Adamson, SD OSSD px_lib_set_root_complex_mps(px_t *px_p,  dev_info_t *dip, int mps)
21710114761dSAlan Adamson, SD OSSD {
21720114761dSAlan Adamson, SD OSSD 	pci_device_t	bdf = px_lib_get_bdf(px_p);
21730114761dSAlan Adamson, SD OSSD 
21740114761dSAlan Adamson, SD OSSD 	if (hvio_set_rp_mps(DIP_TO_HANDLE(dip), bdf, mps) == H_EOK)
21750114761dSAlan Adamson, SD OSSD 		return (DDI_SUCCESS);
21760114761dSAlan Adamson, SD OSSD 	else
21770114761dSAlan Adamson, SD OSSD 		return (DDI_FAILURE);
21780114761dSAlan Adamson, SD OSSD }
2179fc256490SJason Beloro 
2180fc256490SJason Beloro static int
px_lib_do_count_waiting_dev(dev_info_t * dip,void * arg)2181fc256490SJason Beloro px_lib_do_count_waiting_dev(dev_info_t *dip, void *arg)
2182fc256490SJason Beloro {
2183fc256490SJason Beloro 	int *count = (int *)arg;
2184fc256490SJason Beloro 	dev_info_t *cdip = ddi_get_child(dip);
2185fc256490SJason Beloro 
2186fc256490SJason Beloro 	while (cdip != NULL) {
2187fc256490SJason Beloro 		/* check if this is an assigned device */
2188fc256490SJason Beloro 		if (ddi_prop_exists(DDI_DEV_T_NONE, cdip, DDI_PROP_DONTPASS,
2189fc256490SJason Beloro 		    "ddi-assigned")) {
2190fc256490SJason Beloro 			DBG(DBG_ATTACH, dip, "px_lib_do_count_waiting_dev: "
2191fc256490SJason Beloro 			    "Found an assigned dev %p, under bridge %p",
2192fc256490SJason Beloro 			    cdip, dip);
2193fc256490SJason Beloro 
2194fc256490SJason Beloro 			/*
2195fc256490SJason Beloro 			 * Mark this bridge as needing waiting for
2196fc256490SJason Beloro 			 * CHILD_LOANED will be removed after bridge reports
2197fc256490SJason Beloro 			 * its readyness back to px driver
2198fc256490SJason Beloro 			 */
2199fc256490SJason Beloro 			if (ddi_prop_update_int(DDI_DEV_T_NONE, dip,
2200fc256490SJason Beloro 			    CHILD_LOANED, 1) == DDI_PROP_SUCCESS)
2201fc256490SJason Beloro 				(*count)++;
2202fc256490SJason Beloro 			break;
2203fc256490SJason Beloro 		}
2204fc256490SJason Beloro 		cdip = ddi_get_next_sibling(cdip);
2205fc256490SJason Beloro 	}
2206fc256490SJason Beloro 
2207fc256490SJason Beloro 	return (DDI_WALK_CONTINUE);
2208fc256490SJason Beloro }
2209fc256490SJason Beloro 
2210fc256490SJason Beloro static int
px_lib_count_waiting_dev(dev_info_t * dip)2211fc256490SJason Beloro px_lib_count_waiting_dev(dev_info_t *dip)
2212fc256490SJason Beloro {
2213fc256490SJason Beloro 	int count = 0;
2214fc256490SJason Beloro 
2215fc256490SJason Beloro 	/* No need to continue if this system is not SDIO capable */
2216fc256490SJason Beloro 	if (px_sdio_users == 0)
2217fc256490SJason Beloro 		return (0);
2218fc256490SJason Beloro 
2219fc256490SJason Beloro 	/* see if px iteslf has assigned children */
2220fc256490SJason Beloro 	(void) px_lib_do_count_waiting_dev(dip, &count);
2221fc256490SJason Beloro 
2222fc256490SJason Beloro 	/* scan dev under this px */
22233fe80ca4SDan Cross 	ndi_devi_enter(dip);
2224fc256490SJason Beloro 	ddi_walk_devs(ddi_get_child(dip), px_lib_do_count_waiting_dev, &count);
22253fe80ca4SDan Cross 	ndi_devi_exit(dip);
2226fc256490SJason Beloro 	return (count);
2227fc256490SJason Beloro }
2228fc256490SJason Beloro 
2229fc256490SJason Beloro /* Called from px/bridge driver directly to report its readyness */
2230fc256490SJason Beloro int
px_lib_fabric_sync(dev_info_t * dip)2231fc256490SJason Beloro px_lib_fabric_sync(dev_info_t *dip)
2232fc256490SJason Beloro {
2233fc256490SJason Beloro 	px_t *px;
2234fc256490SJason Beloro 	dev_info_t *rcdip;
2235fc256490SJason Beloro 	int waitdev;
2236fc256490SJason Beloro 
2237fc256490SJason Beloro 	/* No need to continue if this system is not SDIO capable */
2238fc256490SJason Beloro 	if (px_sdio_users == 0)
2239fc256490SJason Beloro 		return (DDI_SUCCESS);
2240fc256490SJason Beloro 
2241fc256490SJason Beloro 	/* a valid bridge w/ assigned dev under it? */
2242fc256490SJason Beloro 	if (ddi_prop_remove(DDI_DEV_T_NONE, dip, CHILD_LOANED) !=
2243fc256490SJason Beloro 	    DDI_PROP_SUCCESS)
2244fc256490SJason Beloro 		return (DDI_FAILURE);
2245fc256490SJason Beloro 
2246fc256490SJason Beloro 	/* find out RC dip */
2247fc256490SJason Beloro 	for (rcdip = dip; rcdip != NULL; rcdip = ddi_get_parent(rcdip)) {
2248fc256490SJason Beloro 		if (PCIE_DIP2BUS(rcdip) && PCIE_IS_RC(PCIE_DIP2BUS(rcdip)))
2249fc256490SJason Beloro 			break;
2250fc256490SJason Beloro 	}
2251fc256490SJason Beloro 	if ((rcdip == NULL) || ((px = (px_t *)DIP_TO_STATE(rcdip)) == NULL))
2252fc256490SJason Beloro 		return (DDI_FAILURE);
2253fc256490SJason Beloro 
2254fc256490SJason Beloro 	/* are we ready? */
2255fc256490SJason Beloro 	waitdev = (int)(uintptr_t)px->px_plat_p;
2256fc256490SJason Beloro 	ASSERT(waitdev);
2257fc256490SJason Beloro 	DBG(DBG_CTLOPS, rcdip, "px_lib_fabric_sync: "
2258fc256490SJason Beloro 	    "Px/bridge %p is ready, %d left", rcdip, waitdev - 1);
2259fc256490SJason Beloro 	--waitdev;
2260fc256490SJason Beloro 	px->px_plat_p = (void *)(uintptr_t)waitdev;
2261fc256490SJason Beloro 	if (waitdev != 0)
2262fc256490SJason Beloro 		return (DDI_SUCCESS);
2263fc256490SJason Beloro 
2264fc256490SJason Beloro 	/* notify hpyervisor */
2265fc256490SJason Beloro 	DBG(DBG_CTLOPS, rcdip, "px_lib_fabric_sync: "
2266fc256490SJason Beloro 	    "Notifying HV that RC %p is ready users=%d", rcdip, px_sdio_users);
2267fc256490SJason Beloro 
2268fc256490SJason Beloro 	if (pci_iov_root_configured(px->px_dev_hdl) != H_EOK)
2269fc256490SJason Beloro 		return (DDI_FAILURE);
2270fc256490SJason Beloro 
2271fc256490SJason Beloro 	return (DDI_SUCCESS);
2272fc256490SJason Beloro }
2273