1f8d2de6bSjchu /* 2f8d2de6bSjchu * CDDL HEADER START 3f8d2de6bSjchu * 4f8d2de6bSjchu * The contents of this file are subject to the terms of the 501689544Sjchu * Common Development and Distribution License (the "License"). 601689544Sjchu * You may not use this file except in compliance with the License. 7f8d2de6bSjchu * 8f8d2de6bSjchu * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9f8d2de6bSjchu * or http://www.opensolaris.org/os/licensing. 10f8d2de6bSjchu * See the License for the specific language governing permissions 11f8d2de6bSjchu * and limitations under the License. 12f8d2de6bSjchu * 13f8d2de6bSjchu * When distributing Covered Code, include this CDDL HEADER in each 14f8d2de6bSjchu * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15f8d2de6bSjchu * If applicable, add the following below this CDDL HEADER, with the 16f8d2de6bSjchu * fields enclosed by brackets "[]" replaced with your own identifying 17f8d2de6bSjchu * information: Portions Copyright [yyyy] [name of copyright owner] 18f8d2de6bSjchu * 19f8d2de6bSjchu * CDDL HEADER END 20f8d2de6bSjchu */ 21f8d2de6bSjchu /* 22*c85864d8SKrishna Elango * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23f8d2de6bSjchu * Use is subject to license terms. 24f8d2de6bSjchu */ 25f8d2de6bSjchu 26f8d2de6bSjchu /* 27f8d2de6bSjchu * sun4v Fire Error Handling 28f8d2de6bSjchu */ 29f8d2de6bSjchu 30f8d2de6bSjchu #include <sys/types.h> 31f8d2de6bSjchu #include <sys/ddi.h> 32f8d2de6bSjchu #include <sys/sunddi.h> 33eae2e508Skrishnae #include <sys/sunndi.h> 34f8d2de6bSjchu #include <sys/fm/protocol.h> 35f8d2de6bSjchu #include <sys/fm/util.h> 36f8d2de6bSjchu #include <sys/membar.h> 37f8d2de6bSjchu #include "px_obj.h" 38f8d2de6bSjchu #include "px_err.h" 39f8d2de6bSjchu 40bf8fc234Set static void px_err_fill_pf_data(dev_info_t *dip, px_t *px_p, px_rc_err_t *epkt); 41bf8fc234Set static uint_t px_err_intr(px_fault_t *fault_p, px_rc_err_t *epkt); 42bf8fc234Set static int px_err_epkt_severity(px_t *px_p, ddi_fm_error_t *derr, 43f8d2de6bSjchu px_rc_err_t *epkt, int caller); 44f8d2de6bSjchu 45bf8fc234Set static void px_err_log_handle(dev_info_t *dip, px_rc_err_t *epkt, 46bf8fc234Set boolean_t is_block_pci, char *msg); 47eae2e508Skrishnae static void px_err_send_epkt_erpt(dev_info_t *dip, px_rc_err_t *epkt, 48eae2e508Skrishnae boolean_t is_block_pci, int err, ddi_fm_error_t *derr, 49eae2e508Skrishnae boolean_t is_valid_epkt); 50bf8fc234Set static int px_cb_epkt_severity(dev_info_t *dip, ddi_fm_error_t *derr, 51bf8fc234Set px_rc_err_t *epkt); 52bf8fc234Set static int px_mmu_epkt_severity(dev_info_t *dip, ddi_fm_error_t *derr, 53bf8fc234Set px_rc_err_t *epkt); 54bf8fc234Set static int px_intr_epkt_severity(dev_info_t *dip, ddi_fm_error_t *derr, 55bf8fc234Set px_rc_err_t *epkt); 56bf8fc234Set static int px_pcie_epkt_severity(dev_info_t *dip, ddi_fm_error_t *derr, 57bf8fc234Set px_rc_err_t *epkt); 58bf8fc234Set static int px_intr_handle_errors(dev_info_t *dip, ddi_fm_error_t *derr, 59bf8fc234Set px_rc_err_t *epkt); 60bf8fc234Set static void px_fix_legacy_epkt(dev_info_t *dip, ddi_fm_error_t *derr, 61bf8fc234Set px_rc_err_t *epkt); 62bf8fc234Set static int px_mmu_handle_lookup(dev_info_t *dip, ddi_fm_error_t *derr, 63bf8fc234Set px_rc_err_t *epkt); 64bf8fc234Set 65bf8fc234Set /* Include the code generated sun4v epkt checking code */ 66bf8fc234Set #include "px_err_gen.c" 67bf8fc234Set 68bf8fc234Set /* 69bf8fc234Set * This variable indicates if we have a hypervisor that could potentially send 70bf8fc234Set * incorrect epkts. We always set this to TRUE for now until we find a way to 71bf8fc234Set * tell if this HV bug has been fixed. 72bf8fc234Set */ 73bf8fc234Set boolean_t px_legacy_epkt = B_TRUE; 74f8d2de6bSjchu 75f8d2de6bSjchu /* 76f8d2de6bSjchu * px_err_cb_intr: 77f8d2de6bSjchu * Interrupt handler for the Host Bus Block. 78f8d2de6bSjchu */ 79f8d2de6bSjchu uint_t 80f8d2de6bSjchu px_err_cb_intr(caddr_t arg) 81f8d2de6bSjchu { 82f8d2de6bSjchu px_fault_t *fault_p = (px_fault_t *)arg; 83f8d2de6bSjchu px_rc_err_t *epkt = (px_rc_err_t *)fault_p->px_intr_payload; 84f8d2de6bSjchu 85f8d2de6bSjchu if (epkt != NULL) { 86bf8fc234Set return (px_err_intr(fault_p, epkt)); 87f8d2de6bSjchu } 88f8d2de6bSjchu 89f8d2de6bSjchu return (DDI_INTR_UNCLAIMED); 90f8d2de6bSjchu } 91f8d2de6bSjchu 92f8d2de6bSjchu /* 93f8d2de6bSjchu * px_err_dmc_pec_intr: 94f8d2de6bSjchu * Interrupt handler for the DMC/PEC block. 95f8d2de6bSjchu */ 96f8d2de6bSjchu uint_t 97f8d2de6bSjchu px_err_dmc_pec_intr(caddr_t arg) 98f8d2de6bSjchu { 99f8d2de6bSjchu px_fault_t *fault_p = (px_fault_t *)arg; 100f8d2de6bSjchu px_rc_err_t *epkt = (px_rc_err_t *)fault_p->px_intr_payload; 101f8d2de6bSjchu 102f8d2de6bSjchu if (epkt != NULL) { 103bf8fc234Set return (px_err_intr(fault_p, epkt)); 104f8d2de6bSjchu } 105f8d2de6bSjchu 106f8d2de6bSjchu return (DDI_INTR_UNCLAIMED); 107f8d2de6bSjchu } 108f8d2de6bSjchu 109f8d2de6bSjchu /* 110bf8fc234Set * px_err_cmn_intr: 111f8d2de6bSjchu * Common function called by trap, mondo and fabric intr. 112f8d2de6bSjchu * This function is more meaningful in sun4u implementation. Kept 113f8d2de6bSjchu * to mirror sun4u call stack. 114f8d2de6bSjchu * o check for safe access 115bf8fc234Set * o create and queue RC info for later use in fabric scan. 116bf8fc234Set * o RUC/WUC, PTLP, MMU Errors(CA), UR 117f8d2de6bSjchu * 118f8d2de6bSjchu * @param px_p leaf in which to check access 119f8d2de6bSjchu * @param derr fm err data structure to be updated 120f8d2de6bSjchu * @param caller PX_TRAP_CALL | PX_INTR_CALL 121f8d2de6bSjchu * @param chkjbc whether to handle hostbus registers (ignored) 122bf8fc234Set * @return err PX_NO_PANIC | PX_PROTECTED | 123bf8fc234Set * PX_PANIC | PX_HW_RESET | PX_EXPECTED 124f8d2de6bSjchu */ 125f8d2de6bSjchu /* ARGSUSED */ 126f8d2de6bSjchu int 127bf8fc234Set px_err_cmn_intr(px_t *px_p, ddi_fm_error_t *derr, int caller, int block) 128f8d2de6bSjchu { 129f8d2de6bSjchu px_err_safeacc_check(px_p, derr); 130e51949e6Sdduvall return (DDI_FM_OK); 1313d9c56a1Set } 1323d9c56a1Set 1333d9c56a1Set /* 134bf8fc234Set * fills RC specific fault data 135bf8fc234Set */ 136bf8fc234Set static void 137bf8fc234Set px_err_fill_pfd(dev_info_t *dip, px_t *px_p, px_rc_err_t *epkt) { 138eae2e508Skrishnae pf_pcie_adv_err_regs_t adv_reg; 139bf8fc234Set int sts = DDI_SUCCESS; 140*c85864d8SKrishna Elango pcie_req_id_t fault_bdf = PCIE_INVALID_BDF; 141eae2e508Skrishnae uint64_t fault_addr = 0; 142bf8fc234Set uint16_t s_status = 0; 143bf8fc234Set 144bf8fc234Set /* Add an PCIE PF_DATA Entry */ 145bf8fc234Set if (epkt->rc_descr.block == BLOCK_MMU) { 146bf8fc234Set /* Only PIO Fault Addresses are valid, this is DMA */ 147bf8fc234Set s_status = PCI_STAT_S_TARG_AB; 148bf8fc234Set fault_addr = NULL; 149bf8fc234Set 150bf8fc234Set if (epkt->rc_descr.H) 151bf8fc234Set fault_bdf = (pcie_req_id_t)(epkt->hdr[0] >> 16); 152bf8fc234Set else 153bf8fc234Set sts = DDI_FAILURE; 154bf8fc234Set } else { 155bf8fc234Set px_pec_err_t *pec_p = (px_pec_err_t *)epkt; 156bf8fc234Set uint32_t dir = pec_p->pec_descr.dir; 157bf8fc234Set 158eae2e508Skrishnae adv_reg.pcie_ue_hdr[0] = (uint32_t)(pec_p->hdr[0]); 159eae2e508Skrishnae adv_reg.pcie_ue_hdr[1] = (uint32_t)(pec_p->hdr[0] >> 32); 160eae2e508Skrishnae adv_reg.pcie_ue_hdr[2] = (uint32_t)(pec_p->hdr[1]); 161eae2e508Skrishnae adv_reg.pcie_ue_hdr[3] = (uint32_t)(pec_p->hdr[1] >> 32); 162bf8fc234Set 163bf8fc234Set /* translate RC UR/CA to legacy secondary errors */ 164bf8fc234Set if ((dir == DIR_READ || dir == DIR_WRITE) && 165bf8fc234Set pec_p->pec_descr.U) { 166bf8fc234Set if (pec_p->ue_reg_status & PCIE_AER_UCE_UR) 167bf8fc234Set s_status |= PCI_STAT_R_MAST_AB; 1681ff65112Segillett if (pec_p->ue_reg_status & PCIE_AER_UCE_CA) 169bf8fc234Set s_status |= PCI_STAT_R_TARG_AB; 170bf8fc234Set } 171bf8fc234Set 172bf8fc234Set if (pec_p->ue_reg_status & PCIE_AER_UCE_PTLP) 173bf8fc234Set s_status |= PCI_STAT_PERROR; 174bf8fc234Set 175bf8fc234Set if (pec_p->ue_reg_status & PCIE_AER_UCE_CA) 176bf8fc234Set s_status |= PCI_STAT_S_TARG_AB; 177bf8fc234Set 178eae2e508Skrishnae sts = pf_tlp_decode(PCIE_DIP2BUS(dip), &adv_reg); 179eae2e508Skrishnae fault_bdf = adv_reg.pcie_ue_tgt_bdf; 180*c85864d8SKrishna Elango fault_addr = adv_reg.pcie_ue_tgt_addr; 181bf8fc234Set } 182bf8fc234Set 183bf8fc234Set if (sts == DDI_SUCCESS) 184bf8fc234Set px_rp_en_q(px_p, fault_bdf, fault_addr, s_status); 185bf8fc234Set } 186bf8fc234Set 187bf8fc234Set /* 188bf8fc234Set * px_err_intr: 189f8d2de6bSjchu * Interrupt handler for the JBC/DMC/PEC block. 190f8d2de6bSjchu * o lock 191f8d2de6bSjchu * o create derr 192f8d2de6bSjchu * o check safe access 193bf8fc234Set * o px_err_check_severity(epkt) 194bf8fc234Set * o pcie_scan_fabric 195f8d2de6bSjchu * o Idle intr state 196f8d2de6bSjchu * o unlock 197f8d2de6bSjchu * o handle error: fatal? fm_panic() : return INTR_CLAIMED) 198f8d2de6bSjchu */ 199f8d2de6bSjchu static uint_t 200bf8fc234Set px_err_intr(px_fault_t *fault_p, px_rc_err_t *epkt) 201f8d2de6bSjchu { 202f8d2de6bSjchu px_t *px_p = DIP_TO_STATE(fault_p->px_fh_dip); 203f8d2de6bSjchu dev_info_t *rpdip = px_p->px_dip; 204eae2e508Skrishnae int rc_err, fab_err, msg; 205f8d2de6bSjchu ddi_fm_error_t derr; 206f8d2de6bSjchu 207eae2e508Skrishnae if (px_fm_enter(px_p) != DDI_SUCCESS) 208eae2e508Skrishnae goto done; 209f8d2de6bSjchu 210f8d2de6bSjchu /* Create the derr */ 211f8d2de6bSjchu bzero(&derr, sizeof (ddi_fm_error_t)); 212f8d2de6bSjchu derr.fme_version = DDI_FME_VERSION; 213f8d2de6bSjchu derr.fme_ena = fm_ena_generate(epkt->stick, FM_ENA_FMT1); 214f8d2de6bSjchu derr.fme_flag = DDI_FM_ERR_UNEXPECTED; 215f8d2de6bSjchu 216f8d2de6bSjchu /* Basically check for safe access */ 217bf8fc234Set (void) px_err_cmn_intr(px_p, &derr, PX_INTR_CALL, PX_FM_BLOCK_ALL); 218f8d2de6bSjchu 219f8d2de6bSjchu /* Check the severity of this error */ 220bf8fc234Set rc_err = px_err_epkt_severity(px_p, &derr, epkt, PX_INTR_CALL); 221f8d2de6bSjchu 222bf8fc234Set /* Scan the fabric if the root port is not in drain state. */ 223eae2e508Skrishnae fab_err = px_scan_fabric(px_p, rpdip, &derr); 224f8d2de6bSjchu 225f8d2de6bSjchu /* Set the intr state to idle for the leaf that received the mondo */ 226f8d2de6bSjchu if (px_lib_intr_setstate(rpdip, fault_p->px_fh_sysino, 2271ff65112Segillett INTR_IDLE_STATE) != DDI_SUCCESS) { 228eae2e508Skrishnae px_fm_exit(px_p); 229f8d2de6bSjchu return (DDI_INTR_UNCLAIMED); 230f8d2de6bSjchu } 231f8d2de6bSjchu 232bf8fc234Set switch (epkt->rc_descr.block) { 233bf8fc234Set case BLOCK_MMU: /* FALLTHROUGH */ 234bf8fc234Set case BLOCK_INTR: 235bf8fc234Set msg = PX_RC; 236bf8fc234Set break; 237bf8fc234Set case BLOCK_PCIE: 238bf8fc234Set msg = PX_RP; 239bf8fc234Set break; 240bf8fc234Set case BLOCK_HOSTBUS: /* FALLTHROUGH */ 241bf8fc234Set default: 242bf8fc234Set msg = PX_HB; 243bf8fc234Set break; 244bf8fc234Set } 245bf8fc234Set 246eae2e508Skrishnae px_err_panic(rc_err, msg, fab_err, B_TRUE); 247eae2e508Skrishnae px_fm_exit(px_p); 248eae2e508Skrishnae px_err_panic(rc_err, msg, fab_err, B_FALSE); 249f8d2de6bSjchu 250eae2e508Skrishnae done: 251f8d2de6bSjchu return (DDI_INTR_CLAIMED); 252f8d2de6bSjchu } 253f8d2de6bSjchu 254f8d2de6bSjchu /* 255bf8fc234Set * px_err_epkt_severity: 256f8d2de6bSjchu * Check the severity of the fire error based the epkt received 257f8d2de6bSjchu * 258f8d2de6bSjchu * @param px_p leaf in which to take the snap shot. 259f8d2de6bSjchu * @param derr fm err in which the ereport is to be based on 260f8d2de6bSjchu * @param epkt epkt recevied from HV 261f8d2de6bSjchu */ 262f8d2de6bSjchu static int 263bf8fc234Set px_err_epkt_severity(px_t *px_p, ddi_fm_error_t *derr, px_rc_err_t *epkt, 264f8d2de6bSjchu int caller) 265f8d2de6bSjchu { 266f8d2de6bSjchu px_pec_t *pec_p = px_p->px_pec_p; 267f8d2de6bSjchu dev_info_t *dip = px_p->px_dip; 268bf8fc234Set boolean_t is_safeacc = B_FALSE; 269bf8fc234Set boolean_t is_block_pci = B_FALSE; 270eae2e508Skrishnae boolean_t is_valid_epkt = B_FALSE; 271f8d2de6bSjchu int err = 0; 272f8d2de6bSjchu 273f8d2de6bSjchu /* Cautious access error handling */ 274bf8fc234Set switch (derr->fme_flag) { 275bf8fc234Set case DDI_FM_ERR_EXPECTED: 276f8d2de6bSjchu if (caller == PX_TRAP_CALL) { 277f8d2de6bSjchu /* 278f8d2de6bSjchu * for ddi_caut_get treat all events as nonfatal 279f8d2de6bSjchu * The trampoline will set err_ena = 0, 280f8d2de6bSjchu * err_status = NONFATAL. 281f8d2de6bSjchu */ 282f8d2de6bSjchu derr->fme_status = DDI_FM_NONFATAL; 283bf8fc234Set is_safeacc = B_TRUE; 284f8d2de6bSjchu } else { 285f8d2de6bSjchu /* 286f8d2de6bSjchu * For ddi_caut_put treat all events as nonfatal. Here 287f8d2de6bSjchu * we have the handle and can call ndi_fm_acc_err_set(). 288f8d2de6bSjchu */ 289f8d2de6bSjchu derr->fme_status = DDI_FM_NONFATAL; 290f8d2de6bSjchu ndi_fm_acc_err_set(pec_p->pec_acc_hdl, derr); 291bf8fc234Set is_safeacc = B_TRUE; 292f8d2de6bSjchu } 293bf8fc234Set break; 294bf8fc234Set case DDI_FM_ERR_PEEK: 295bf8fc234Set case DDI_FM_ERR_POKE: 296bf8fc234Set /* 297bf8fc234Set * For ddi_peek/poke treat all events as nonfatal. 298bf8fc234Set */ 299bf8fc234Set is_safeacc = B_TRUE; 300bf8fc234Set break; 301bf8fc234Set default: 302bf8fc234Set is_safeacc = B_FALSE; 303f8d2de6bSjchu } 304f8d2de6bSjchu 305bf8fc234Set /* 306bf8fc234Set * Older hypervisors in some cases send epkts with incorrect fields. 307bf8fc234Set * We have to handle these "special" epkts correctly. 308bf8fc234Set */ 309bf8fc234Set if (px_legacy_epkt) 310bf8fc234Set px_fix_legacy_epkt(dip, derr, epkt); 311bf8fc234Set 312f8d2de6bSjchu switch (epkt->rc_descr.block) { 313f8d2de6bSjchu case BLOCK_HOSTBUS: 314bf8fc234Set err = px_cb_epkt_severity(dip, derr, epkt); 315f8d2de6bSjchu break; 316f8d2de6bSjchu case BLOCK_MMU: 317bf8fc234Set err = px_mmu_epkt_severity(dip, derr, epkt); 318bf8fc234Set px_err_fill_pfd(dip, px_p, epkt); 319f8d2de6bSjchu break; 320f8d2de6bSjchu case BLOCK_INTR: 321bf8fc234Set err = px_intr_epkt_severity(dip, derr, epkt); 322f8d2de6bSjchu break; 323f8d2de6bSjchu case BLOCK_PCIE: 324bf8fc234Set is_block_pci = B_TRUE; 325bf8fc234Set err = px_pcie_epkt_severity(dip, derr, epkt); 326bf8fc234Set px_err_fill_pfd(dip, px_p, epkt); 327f8d2de6bSjchu break; 328f8d2de6bSjchu default: 329bf8fc234Set err = 0; 330f8d2de6bSjchu } 331f8d2de6bSjchu 332bf8fc234Set if ((err & PX_HW_RESET) || (err & PX_PANIC)) { 333bf8fc234Set if (px_log & PX_PANIC) 334bf8fc234Set px_err_log_handle(dip, epkt, is_block_pci, "PANIC"); 335eae2e508Skrishnae is_valid_epkt = B_TRUE; 336bf8fc234Set } else if (err & PX_PROTECTED) { 337bf8fc234Set if (px_log & PX_PROTECTED) 338bf8fc234Set px_err_log_handle(dip, epkt, is_block_pci, "PROTECTED"); 339eae2e508Skrishnae is_valid_epkt = B_TRUE; 340bf8fc234Set } else if (err & PX_NO_PANIC) { 341bf8fc234Set if (px_log & PX_NO_PANIC) 342bf8fc234Set px_err_log_handle(dip, epkt, is_block_pci, "NO PANIC"); 343eae2e508Skrishnae is_valid_epkt = B_TRUE; 344bf8fc234Set } else if (err & PX_NO_ERROR) { 345bf8fc234Set if (px_log & PX_NO_ERROR) 346bf8fc234Set px_err_log_handle(dip, epkt, is_block_pci, "NO ERROR"); 347eae2e508Skrishnae is_valid_epkt = B_TRUE; 348bf8fc234Set } else if (err == 0) { 349bf8fc234Set px_err_log_handle(dip, epkt, is_block_pci, "UNRECOGNIZED"); 350eae2e508Skrishnae is_valid_epkt = B_FALSE; 351bf8fc234Set 352eae2e508Skrishnae /* Panic on a unrecognized epkt */ 353bf8fc234Set err = PX_PANIC; 354bf8fc234Set } 355bf8fc234Set 356eae2e508Skrishnae px_err_send_epkt_erpt(dip, epkt, is_block_pci, err, derr, 357eae2e508Skrishnae is_valid_epkt); 358eae2e508Skrishnae 359bf8fc234Set /* Readjust the severity as a result of safe access */ 360bf8fc234Set if (is_safeacc && !(err & PX_PANIC) && !(px_die & PX_PROTECTED)) 361bf8fc234Set err = PX_NO_PANIC; 362bf8fc234Set 363f8d2de6bSjchu return (err); 364f8d2de6bSjchu } 365f8d2de6bSjchu 366eae2e508Skrishnae static void 367eae2e508Skrishnae px_err_send_epkt_erpt(dev_info_t *dip, px_rc_err_t *epkt, 368eae2e508Skrishnae boolean_t is_block_pci, int err, ddi_fm_error_t *derr, 369eae2e508Skrishnae boolean_t is_valid_epkt) 370eae2e508Skrishnae { 371eae2e508Skrishnae char buf[FM_MAX_CLASS], descr_buf[1024]; 372eae2e508Skrishnae 373eae2e508Skrishnae /* send ereport for debug purposes */ 374eae2e508Skrishnae (void) snprintf(buf, FM_MAX_CLASS, "%s", PX_FM_RC_UNRECOG); 375eae2e508Skrishnae 376eae2e508Skrishnae if (is_block_pci) { 377eae2e508Skrishnae px_pec_err_t *pec = (px_pec_err_t *)epkt; 378eae2e508Skrishnae (void) snprintf(descr_buf, sizeof (descr_buf), 379eae2e508Skrishnae "%s Epkt contents:\n" 380eae2e508Skrishnae "Block: 0x%x, Dir: 0x%x, Flags: Z=%d, S=%d, R=%d\n" 381eae2e508Skrishnae "I=%d, H=%d, C=%d, U=%d, E=%d, P=%d\n" 382eae2e508Skrishnae "PCI Err Status: 0x%x, PCIe Err Status: 0x%x\n" 383eae2e508Skrishnae "CE Status Reg: 0x%x, UE Status Reg: 0x%x\n" 384eae2e508Skrishnae "HDR1: 0x%lx, HDR2: 0x%lx\n" 385eae2e508Skrishnae "Err Src Reg: 0x%x, Root Err Status: 0x%x\n" 386eae2e508Skrishnae "Err Severity: 0x%x\n", 387eae2e508Skrishnae is_valid_epkt ? "Valid" : "Invalid", 388eae2e508Skrishnae pec->pec_descr.block, pec->pec_descr.dir, 389eae2e508Skrishnae pec->pec_descr.Z, pec->pec_descr.S, 390eae2e508Skrishnae pec->pec_descr.R, pec->pec_descr.I, 391eae2e508Skrishnae pec->pec_descr.H, pec->pec_descr.C, 392eae2e508Skrishnae pec->pec_descr.U, pec->pec_descr.E, 393eae2e508Skrishnae pec->pec_descr.P, pec->pci_err_status, 394eae2e508Skrishnae pec->pcie_err_status, pec->ce_reg_status, 395eae2e508Skrishnae pec->ue_reg_status, pec->hdr[0], 396eae2e508Skrishnae pec->hdr[1], pec->err_src_reg, 397eae2e508Skrishnae pec->root_err_status, err); 398eae2e508Skrishnae 399eae2e508Skrishnae ddi_fm_ereport_post(dip, buf, derr->fme_ena, 400eae2e508Skrishnae DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 401eae2e508Skrishnae EPKT_SYSINO, DATA_TYPE_UINT64, 402eae2e508Skrishnae is_valid_epkt ? pec->sysino : 0, 403eae2e508Skrishnae EPKT_EHDL, DATA_TYPE_UINT64, 404eae2e508Skrishnae is_valid_epkt ? pec->ehdl : 0, 405eae2e508Skrishnae EPKT_STICK, DATA_TYPE_UINT64, 406eae2e508Skrishnae is_valid_epkt ? pec->stick : 0, 407eae2e508Skrishnae EPKT_PEC_DESCR, DATA_TYPE_STRING, descr_buf); 408eae2e508Skrishnae } else { 409eae2e508Skrishnae (void) snprintf(descr_buf, sizeof (descr_buf), 410eae2e508Skrishnae "%s Epkt contents:\n" 411eae2e508Skrishnae "Block: 0x%x, Op: 0x%x, Phase: 0x%x, Cond: 0x%x\n" 412eae2e508Skrishnae "Dir: 0x%x, Flags: STOP=%d, H=%d, R=%d, D=%d\n" 413eae2e508Skrishnae "M=%d, S=%d, Size: 0x%x, Addr: 0x%lx\n" 414eae2e508Skrishnae "Hdr1: 0x%lx, Hdr2: 0x%lx, Res: 0x%lx\n" 415eae2e508Skrishnae "Err Severity: 0x%x\n", 416eae2e508Skrishnae is_valid_epkt ? "Valid" : "Invalid", 417eae2e508Skrishnae epkt->rc_descr.block, epkt->rc_descr.op, 418eae2e508Skrishnae epkt->rc_descr.phase, epkt->rc_descr.cond, 419eae2e508Skrishnae epkt->rc_descr.dir, epkt->rc_descr.STOP, 420eae2e508Skrishnae epkt->rc_descr.H, epkt->rc_descr.R, 421eae2e508Skrishnae epkt->rc_descr.D, epkt->rc_descr.M, 422eae2e508Skrishnae epkt->rc_descr.S, epkt->size, epkt->addr, 423eae2e508Skrishnae epkt->hdr[0], epkt->hdr[1], epkt->reserved, 424eae2e508Skrishnae err); 425eae2e508Skrishnae 426eae2e508Skrishnae ddi_fm_ereport_post(dip, buf, derr->fme_ena, 427eae2e508Skrishnae DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 428eae2e508Skrishnae EPKT_SYSINO, DATA_TYPE_UINT64, 429eae2e508Skrishnae is_valid_epkt ? epkt->sysino : 0, 430eae2e508Skrishnae EPKT_EHDL, DATA_TYPE_UINT64, 431eae2e508Skrishnae is_valid_epkt ? epkt->ehdl : 0, 432eae2e508Skrishnae EPKT_STICK, DATA_TYPE_UINT64, 433eae2e508Skrishnae is_valid_epkt ? epkt->stick : 0, 434eae2e508Skrishnae EPKT_RC_DESCR, DATA_TYPE_STRING, descr_buf); 435eae2e508Skrishnae } 436eae2e508Skrishnae } 437eae2e508Skrishnae 438bf8fc234Set static void 439bf8fc234Set px_err_log_handle(dev_info_t *dip, px_rc_err_t *epkt, boolean_t is_block_pci, 440bf8fc234Set char *msg) 441bf8fc234Set { 442bf8fc234Set if (is_block_pci) { 443bf8fc234Set px_pec_err_t *pec = (px_pec_err_t *)epkt; 444bf8fc234Set DBG(DBG_ERR_INTR, dip, 445bf8fc234Set "A PCIe root port error has occured with a severity" 446bf8fc234Set " \"%s\"\n" 447bf8fc234Set "\tBlock: 0x%x, Dir: 0x%x, Flags: Z=%d, S=%d, R=%d, I=%d\n" 448bf8fc234Set "\tH=%d, C=%d, U=%d, E=%d, P=%d\n" 449bf8fc234Set "\tpci_err: 0x%x, pcie_err=0x%x, ce_reg: 0x%x\n" 450bf8fc234Set "\tue_reg: 0x%x, Hdr1: 0x%p, Hdr2: 0x%p\n" 451bf8fc234Set "\terr_src: 0x%x, root_err: 0x%x\n", 452bf8fc234Set msg, pec->pec_descr.block, pec->pec_descr.dir, 453bf8fc234Set pec->pec_descr.Z, pec->pec_descr.S, pec->pec_descr.R, 454bf8fc234Set pec->pec_descr.I, pec->pec_descr.H, pec->pec_descr.C, 455bf8fc234Set pec->pec_descr.U, pec->pec_descr.E, pec->pec_descr.P, 456bf8fc234Set pec->pci_err_status, pec->pcie_err_status, 457bf8fc234Set pec->ce_reg_status, pec->ue_reg_status, pec->hdr[0], 458bf8fc234Set pec->hdr[1], pec->err_src_reg, pec->root_err_status); 459bf8fc234Set } else { 460bf8fc234Set DBG(DBG_ERR_INTR, dip, 461bf8fc234Set "A PCIe root complex error has occured with a severity" 462bf8fc234Set " \"%s\"\n" 463bf8fc234Set "\tBlock: 0x%x, Op: 0x%x, Phase: 0x%x, Cond: 0x%x\n" 464bf8fc234Set "\tDir: 0x%x, Flags: STOP=%d, H=%d, R=%d, D=%d, M=%d\n" 465bf8fc234Set "\tS=%d, Size: 0x%x, Addr: 0x%p\n" 466bf8fc234Set "\tHdr1: 0x%p, Hdr2: 0x%p, Res: 0x%p\n", 467bf8fc234Set msg, epkt->rc_descr.block, epkt->rc_descr.op, 468bf8fc234Set epkt->rc_descr.phase, epkt->rc_descr.cond, 469bf8fc234Set epkt->rc_descr.dir, epkt->rc_descr.STOP, epkt->rc_descr.H, 470bf8fc234Set epkt->rc_descr.R, epkt->rc_descr.D, epkt->rc_descr.M, 471bf8fc234Set epkt->rc_descr.S, epkt->size, epkt->addr, epkt->hdr[0], 472bf8fc234Set epkt->hdr[1], epkt->reserved); 473bf8fc234Set } 474bf8fc234Set } 475bf8fc234Set 476f8d2de6bSjchu /* ARGSUSED */ 477bf8fc234Set static void 478bf8fc234Set px_fix_legacy_epkt(dev_info_t *dip, ddi_fm_error_t *derr, px_rc_err_t *epkt) 479f8d2de6bSjchu { 480bf8fc234Set /* 481bf8fc234Set * We don't have a default case for any of the below switch statements 482bf8fc234Set * since we are ok with the code falling through. 483bf8fc234Set */ 484bf8fc234Set switch (epkt->rc_descr.block) { 485bf8fc234Set case BLOCK_HOSTBUS: 486bf8fc234Set switch (epkt->rc_descr.op) { 487bf8fc234Set case OP_DMA: 488bf8fc234Set switch (epkt->rc_descr.phase) { 489bf8fc234Set case PH_UNKNOWN: 490bf8fc234Set switch (epkt->rc_descr.cond) { 491bf8fc234Set case CND_UNKNOWN: 492bf8fc234Set switch (epkt->rc_descr.dir) { 493bf8fc234Set case DIR_RESERVED: 494bf8fc234Set epkt->rc_descr.dir = DIR_READ; 495bf8fc234Set break; 496bf8fc234Set } /* DIR */ 497bf8fc234Set } /* CND */ 498bf8fc234Set } /* PH */ 499bf8fc234Set } /* OP */ 500f8d2de6bSjchu break; 501bf8fc234Set case BLOCK_MMU: 502bf8fc234Set switch (epkt->rc_descr.op) { 503bf8fc234Set case OP_XLAT: 504bf8fc234Set switch (epkt->rc_descr.phase) { 505bf8fc234Set case PH_DATA: 506bf8fc234Set switch (epkt->rc_descr.cond) { 507bf8fc234Set case CND_PROT: 508bf8fc234Set switch (epkt->rc_descr.dir) { 509bf8fc234Set case DIR_UNKNOWN: 510bf8fc234Set epkt->rc_descr.dir = DIR_WRITE; 511bf8fc234Set break; 512bf8fc234Set } /* DIR */ 513bf8fc234Set } /* CND */ 5143d9c56a1Set break; 515bf8fc234Set case PH_IRR: 516bf8fc234Set switch (epkt->rc_descr.cond) { 517bf8fc234Set case CND_RESERVED: 518bf8fc234Set switch (epkt->rc_descr.dir) { 519bf8fc234Set case DIR_IRR: 520bf8fc234Set epkt->rc_descr.phase = PH_ADDR; 521bf8fc234Set epkt->rc_descr.cond = CND_IRR; 522bf8fc234Set } /* DIR */ 523bf8fc234Set } /* CND */ 524bf8fc234Set } /* PH */ 525bf8fc234Set } /* OP */ 526e51949e6Sdduvall break; 527bf8fc234Set case BLOCK_INTR: 528bf8fc234Set switch (epkt->rc_descr.op) { 529bf8fc234Set case OP_MSIQ: 530bf8fc234Set switch (epkt->rc_descr.phase) { 531bf8fc234Set case PH_UNKNOWN: 532bf8fc234Set switch (epkt->rc_descr.cond) { 533bf8fc234Set case CND_ILL: 534bf8fc234Set switch (epkt->rc_descr.dir) { 535bf8fc234Set case DIR_RESERVED: 536bf8fc234Set epkt->rc_descr.dir = DIR_IRR; 537bf8fc234Set break; 538bf8fc234Set } /* DIR */ 539bf8fc234Set break; 540bf8fc234Set case CND_IRR: 541bf8fc234Set switch (epkt->rc_descr.dir) { 542bf8fc234Set case DIR_IRR: 543bf8fc234Set epkt->rc_descr.cond = CND_OV; 544bf8fc234Set break; 545bf8fc234Set } /* DIR */ 546bf8fc234Set } /* CND */ 547bf8fc234Set } /* PH */ 548bf8fc234Set break; 549bf8fc234Set case OP_RESERVED: 550bf8fc234Set switch (epkt->rc_descr.phase) { 551bf8fc234Set case PH_UNKNOWN: 552bf8fc234Set switch (epkt->rc_descr.cond) { 553bf8fc234Set case CND_ILL: 554bf8fc234Set switch (epkt->rc_descr.dir) { 555bf8fc234Set case DIR_IRR: 556bf8fc234Set epkt->rc_descr.op = OP_MSI32; 557bf8fc234Set epkt->rc_descr.phase = PH_DATA; 558bf8fc234Set break; 559bf8fc234Set } /* DIR */ 560bf8fc234Set } /* CND */ 561bf8fc234Set break; 562bf8fc234Set case PH_DATA: 563bf8fc234Set switch (epkt->rc_descr.cond) { 564bf8fc234Set case CND_INT: 565bf8fc234Set switch (epkt->rc_descr.dir) { 566bf8fc234Set case DIR_UNKNOWN: 567bf8fc234Set epkt->rc_descr.op = OP_MSI32; 568bf8fc234Set break; 569bf8fc234Set } /* DIR */ 570bf8fc234Set } /* CND */ 571bf8fc234Set } /* PH */ 572bf8fc234Set } /* OP */ 573bf8fc234Set } /* BLOCK */ 574bf8fc234Set } 5753d9c56a1Set 576bf8fc234Set /* ARGSUSED */ 577bf8fc234Set static int 578bf8fc234Set px_intr_handle_errors(dev_info_t *dip, ddi_fm_error_t *derr, px_rc_err_t *epkt) 579bf8fc234Set { 580bf8fc234Set return (px_err_check_eq(dip)); 581bf8fc234Set } 582bf8fc234Set 583bf8fc234Set /* ARGSUSED */ 584bf8fc234Set static int 585bf8fc234Set px_pcie_epkt_severity(dev_info_t *dip, ddi_fm_error_t *derr, px_rc_err_t *epkt) 586bf8fc234Set { 587eae2e508Skrishnae px_pec_err_t *pec_p = (px_pec_err_t *)epkt; 588bf8fc234Set px_err_pcie_t *pcie = (px_err_pcie_t *)epkt; 589eae2e508Skrishnae pf_pcie_adv_err_regs_t adv_reg; 590eae2e508Skrishnae int sts; 591bf8fc234Set uint32_t temp; 592f8d2de6bSjchu 593f8d2de6bSjchu /* 594bf8fc234Set * Check for failed PIO Read/Writes, which are errors that are not 595bf8fc234Set * defined in the PCIe spec. 596f8d2de6bSjchu */ 597bf8fc234Set temp = PCIE_AER_UCE_UR | PCIE_AER_UCE_CA; 598eae2e508Skrishnae if (((pec_p->pec_descr.dir == DIR_READ) || 599eae2e508Skrishnae (pec_p->pec_descr.dir == DIR_WRITE)) && 600eae2e508Skrishnae pec_p->pec_descr.U && (pec_p->ue_reg_status & temp)) { 601eae2e508Skrishnae adv_reg.pcie_ue_hdr[0] = (uint32_t)(pec_p->hdr[0]); 602eae2e508Skrishnae adv_reg.pcie_ue_hdr[1] = (uint32_t)(pec_p->hdr[0] >> 32); 603eae2e508Skrishnae adv_reg.pcie_ue_hdr[2] = (uint32_t)(pec_p->hdr[1]); 604eae2e508Skrishnae adv_reg.pcie_ue_hdr[3] = (uint32_t)(pec_p->hdr[1] >> 32); 605eae2e508Skrishnae 606eae2e508Skrishnae sts = pf_tlp_decode(PCIE_DIP2BUS(dip), &adv_reg); 607eae2e508Skrishnae 608eae2e508Skrishnae if (sts == DDI_SUCCESS && 609eae2e508Skrishnae pf_hdl_lookup(dip, derr->fme_ena, 610eae2e508Skrishnae adv_reg.pcie_ue_tgt_trans, 611eae2e508Skrishnae adv_reg.pcie_ue_tgt_addr, 612eae2e508Skrishnae adv_reg.pcie_ue_tgt_bdf) == PF_HDL_FOUND) 613bf8fc234Set return (PX_NO_PANIC); 614f8d2de6bSjchu else 615bf8fc234Set return (PX_PANIC); 616f8d2de6bSjchu } 617f8d2de6bSjchu 618eae2e508Skrishnae if (!pec_p->pec_descr.C) 619eae2e508Skrishnae pec_p->ce_reg_status = 0; 620eae2e508Skrishnae if (!pec_p->pec_descr.U) 621eae2e508Skrishnae pec_p->ue_reg_status = 0; 622eae2e508Skrishnae if (!pec_p->pec_descr.H) 623eae2e508Skrishnae pec_p->hdr[0] = 0; 624eae2e508Skrishnae if (!pec_p->pec_descr.I) 625eae2e508Skrishnae pec_p->hdr[1] = 0; 626f8d2de6bSjchu 627bf8fc234Set /* 628bf8fc234Set * According to the PCIe spec, there is a first error pointer. If there 629bf8fc234Set * are header logs recorded and there are more than one error, the log 630bf8fc234Set * will belong to the error that the first error pointer points to. 631bf8fc234Set * 632bf8fc234Set * The regs.primary_ue expects a bit number, go through the ue register 633bf8fc234Set * and find the first error that occured. Because the sun4v epkt spec 634bf8fc234Set * does not define this value, the algorithm below gives the lower bit 635bf8fc234Set * priority. 636bf8fc234Set */ 637bf8fc234Set temp = pcie->ue_reg; 638bf8fc234Set if (temp) { 639eae2e508Skrishnae int x; 640bf8fc234Set for (x = 0; !(temp & 0x1); x++) { 641bf8fc234Set temp = temp >> 1; 642bf8fc234Set } 643bf8fc234Set pcie->primary_ue = 1 << x; 644bf8fc234Set } else { 645bf8fc234Set pcie->primary_ue = 0; 6463d9c56a1Set } 647f8d2de6bSjchu 648bf8fc234Set /* Sun4v doesn't log the TX hdr except for CTOs */ 649bf8fc234Set if (pcie->primary_ue == PCIE_AER_UCE_TO) { 650bf8fc234Set pcie->tx_hdr1 = pcie->rx_hdr1; 651bf8fc234Set pcie->tx_hdr2 = pcie->rx_hdr2; 652bf8fc234Set pcie->tx_hdr3 = pcie->rx_hdr3; 653bf8fc234Set pcie->tx_hdr4 = pcie->rx_hdr4; 654bf8fc234Set pcie->rx_hdr1 = 0; 655bf8fc234Set pcie->rx_hdr2 = 0; 656bf8fc234Set pcie->rx_hdr3 = 0; 657bf8fc234Set pcie->rx_hdr4 = 0; 658bf8fc234Set } else { 659bf8fc234Set pcie->tx_hdr1 = 0; 660bf8fc234Set pcie->tx_hdr2 = 0; 661bf8fc234Set pcie->tx_hdr3 = 0; 662bf8fc234Set pcie->tx_hdr4 = 0; 663bf8fc234Set } 664e51949e6Sdduvall 665bf8fc234Set return (px_err_check_pcie(dip, derr, pcie)); 666f8d2de6bSjchu } 667f8d2de6bSjchu 668f8d2de6bSjchu static int 669bf8fc234Set px_mmu_handle_lookup(dev_info_t *dip, ddi_fm_error_t *derr, px_rc_err_t *epkt) 670f8d2de6bSjchu { 671eae2e508Skrishnae uint64_t addr = (uint64_t)epkt->addr; 672*c85864d8SKrishna Elango pcie_req_id_t bdf = PCIE_INVALID_BDF; 673f8d2de6bSjchu 674bf8fc234Set if (epkt->rc_descr.H) { 675bf8fc234Set bdf = (uint32_t)((epkt->hdr[0] >> 16) && 0xFFFF); 676f8d2de6bSjchu } 677f8d2de6bSjchu 678eae2e508Skrishnae return (pf_hdl_lookup(dip, derr->fme_ena, PF_ADDR_DMA, addr, 6791ff65112Segillett bdf)); 680f8d2de6bSjchu } 681