1f8d2de6bSjchu /* 2f8d2de6bSjchu * CDDL HEADER START 3f8d2de6bSjchu * 4f8d2de6bSjchu * The contents of this file are subject to the terms of the 501689544Sjchu * Common Development and Distribution License (the "License"). 601689544Sjchu * You may not use this file except in compliance with the License. 7f8d2de6bSjchu * 8f8d2de6bSjchu * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9f8d2de6bSjchu * or http://www.opensolaris.org/os/licensing. 10f8d2de6bSjchu * See the License for the specific language governing permissions 11f8d2de6bSjchu * and limitations under the License. 12f8d2de6bSjchu * 13f8d2de6bSjchu * When distributing Covered Code, include this CDDL HEADER in each 14f8d2de6bSjchu * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15f8d2de6bSjchu * If applicable, add the following below this CDDL HEADER, with the 16f8d2de6bSjchu * fields enclosed by brackets "[]" replaced with your own identifying 17f8d2de6bSjchu * information: Portions Copyright [yyyy] [name of copyright owner] 18f8d2de6bSjchu * 19f8d2de6bSjchu * CDDL HEADER END 20f8d2de6bSjchu */ 21f8d2de6bSjchu /* 22c85864d8SKrishna Elango * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23f8d2de6bSjchu * Use is subject to license terms. 24f8d2de6bSjchu */ 25f8d2de6bSjchu 26f8d2de6bSjchu /* 27f8d2de6bSjchu * sun4v Fire Error Handling 28f8d2de6bSjchu */ 29f8d2de6bSjchu 30f8d2de6bSjchu #include <sys/types.h> 31f8d2de6bSjchu #include <sys/ddi.h> 32f8d2de6bSjchu #include <sys/sunddi.h> 33eae2e508Skrishnae #include <sys/sunndi.h> 34f8d2de6bSjchu #include <sys/fm/protocol.h> 35f8d2de6bSjchu #include <sys/fm/util.h> 36f8d2de6bSjchu #include <sys/membar.h> 37f8d2de6bSjchu #include "px_obj.h" 38f8d2de6bSjchu #include "px_err.h" 39f8d2de6bSjchu 40bf8fc234Set static void px_err_fill_pf_data(dev_info_t *dip, px_t *px_p, px_rc_err_t *epkt); 41bf8fc234Set static uint_t px_err_intr(px_fault_t *fault_p, px_rc_err_t *epkt); 42bf8fc234Set static int px_err_epkt_severity(px_t *px_p, ddi_fm_error_t *derr, 43f8d2de6bSjchu px_rc_err_t *epkt, int caller); 44f8d2de6bSjchu 45bf8fc234Set static void px_err_log_handle(dev_info_t *dip, px_rc_err_t *epkt, 46bf8fc234Set boolean_t is_block_pci, char *msg); 47eae2e508Skrishnae static void px_err_send_epkt_erpt(dev_info_t *dip, px_rc_err_t *epkt, 48eae2e508Skrishnae boolean_t is_block_pci, int err, ddi_fm_error_t *derr, 49eae2e508Skrishnae boolean_t is_valid_epkt); 50bf8fc234Set static int px_cb_epkt_severity(dev_info_t *dip, ddi_fm_error_t *derr, 51bf8fc234Set px_rc_err_t *epkt); 52bf8fc234Set static int px_mmu_epkt_severity(dev_info_t *dip, ddi_fm_error_t *derr, 53bf8fc234Set px_rc_err_t *epkt); 54bf8fc234Set static int px_intr_epkt_severity(dev_info_t *dip, ddi_fm_error_t *derr, 55bf8fc234Set px_rc_err_t *epkt); 56*4df55fdeSJanie Lu static int px_port_epkt_severity(dev_info_t *dip, ddi_fm_error_t *derr, 57*4df55fdeSJanie Lu px_rc_err_t *epkt); 58bf8fc234Set static int px_pcie_epkt_severity(dev_info_t *dip, ddi_fm_error_t *derr, 59bf8fc234Set px_rc_err_t *epkt); 60bf8fc234Set static int px_intr_handle_errors(dev_info_t *dip, ddi_fm_error_t *derr, 61bf8fc234Set px_rc_err_t *epkt); 62*4df55fdeSJanie Lu static int px_port_handle_errors(dev_info_t *dip, ddi_fm_error_t *derr, 63*4df55fdeSJanie Lu px_rc_err_t *epkt); 64bf8fc234Set static void px_fix_legacy_epkt(dev_info_t *dip, ddi_fm_error_t *derr, 65bf8fc234Set px_rc_err_t *epkt); 66bf8fc234Set static int px_mmu_handle_lookup(dev_info_t *dip, ddi_fm_error_t *derr, 67bf8fc234Set px_rc_err_t *epkt); 68bf8fc234Set 69bf8fc234Set /* Include the code generated sun4v epkt checking code */ 70bf8fc234Set #include "px_err_gen.c" 71bf8fc234Set 72bf8fc234Set /* 73bf8fc234Set * This variable indicates if we have a hypervisor that could potentially send 74bf8fc234Set * incorrect epkts. We always set this to TRUE for now until we find a way to 75bf8fc234Set * tell if this HV bug has been fixed. 76bf8fc234Set */ 77bf8fc234Set boolean_t px_legacy_epkt = B_TRUE; 78f8d2de6bSjchu 79f8d2de6bSjchu /* 80f8d2de6bSjchu * px_err_cb_intr: 81f8d2de6bSjchu * Interrupt handler for the Host Bus Block. 82f8d2de6bSjchu */ 83f8d2de6bSjchu uint_t 84f8d2de6bSjchu px_err_cb_intr(caddr_t arg) 85f8d2de6bSjchu { 86f8d2de6bSjchu px_fault_t *fault_p = (px_fault_t *)arg; 87f8d2de6bSjchu px_rc_err_t *epkt = (px_rc_err_t *)fault_p->px_intr_payload; 88f8d2de6bSjchu 89f8d2de6bSjchu if (epkt != NULL) { 90bf8fc234Set return (px_err_intr(fault_p, epkt)); 91f8d2de6bSjchu } 92f8d2de6bSjchu 93f8d2de6bSjchu return (DDI_INTR_UNCLAIMED); 94f8d2de6bSjchu } 95f8d2de6bSjchu 96f8d2de6bSjchu /* 97f8d2de6bSjchu * px_err_dmc_pec_intr: 98f8d2de6bSjchu * Interrupt handler for the DMC/PEC block. 99f8d2de6bSjchu */ 100f8d2de6bSjchu uint_t 101f8d2de6bSjchu px_err_dmc_pec_intr(caddr_t arg) 102f8d2de6bSjchu { 103f8d2de6bSjchu px_fault_t *fault_p = (px_fault_t *)arg; 104f8d2de6bSjchu px_rc_err_t *epkt = (px_rc_err_t *)fault_p->px_intr_payload; 105f8d2de6bSjchu 106f8d2de6bSjchu if (epkt != NULL) { 107bf8fc234Set return (px_err_intr(fault_p, epkt)); 108f8d2de6bSjchu } 109f8d2de6bSjchu 110f8d2de6bSjchu return (DDI_INTR_UNCLAIMED); 111f8d2de6bSjchu } 112f8d2de6bSjchu 113f8d2de6bSjchu /* 114bf8fc234Set * px_err_cmn_intr: 115f8d2de6bSjchu * Common function called by trap, mondo and fabric intr. 116f8d2de6bSjchu * This function is more meaningful in sun4u implementation. Kept 117f8d2de6bSjchu * to mirror sun4u call stack. 118f8d2de6bSjchu * o check for safe access 119bf8fc234Set * o create and queue RC info for later use in fabric scan. 120bf8fc234Set * o RUC/WUC, PTLP, MMU Errors(CA), UR 121f8d2de6bSjchu * 122f8d2de6bSjchu * @param px_p leaf in which to check access 123f8d2de6bSjchu * @param derr fm err data structure to be updated 124f8d2de6bSjchu * @param caller PX_TRAP_CALL | PX_INTR_CALL 125f8d2de6bSjchu * @param chkjbc whether to handle hostbus registers (ignored) 126bf8fc234Set * @return err PX_NO_PANIC | PX_PROTECTED | 127bf8fc234Set * PX_PANIC | PX_HW_RESET | PX_EXPECTED 128f8d2de6bSjchu */ 129f8d2de6bSjchu /* ARGSUSED */ 130f8d2de6bSjchu int 131bf8fc234Set px_err_cmn_intr(px_t *px_p, ddi_fm_error_t *derr, int caller, int block) 132f8d2de6bSjchu { 133f8d2de6bSjchu px_err_safeacc_check(px_p, derr); 134e51949e6Sdduvall return (DDI_FM_OK); 1353d9c56a1Set } 1363d9c56a1Set 1373d9c56a1Set /* 138bf8fc234Set * fills RC specific fault data 139bf8fc234Set */ 140bf8fc234Set static void 141bf8fc234Set px_err_fill_pfd(dev_info_t *dip, px_t *px_p, px_rc_err_t *epkt) { 142eae2e508Skrishnae pf_pcie_adv_err_regs_t adv_reg; 143bf8fc234Set int sts = DDI_SUCCESS; 144c85864d8SKrishna Elango pcie_req_id_t fault_bdf = PCIE_INVALID_BDF; 145eae2e508Skrishnae uint64_t fault_addr = 0; 146bf8fc234Set uint16_t s_status = 0; 147bf8fc234Set 148bf8fc234Set /* Add an PCIE PF_DATA Entry */ 149bf8fc234Set if (epkt->rc_descr.block == BLOCK_MMU) { 150bf8fc234Set /* Only PIO Fault Addresses are valid, this is DMA */ 151bf8fc234Set s_status = PCI_STAT_S_TARG_AB; 152bf8fc234Set fault_addr = NULL; 153bf8fc234Set 154bf8fc234Set if (epkt->rc_descr.H) 155bf8fc234Set fault_bdf = (pcie_req_id_t)(epkt->hdr[0] >> 16); 156bf8fc234Set else 157bf8fc234Set sts = DDI_FAILURE; 158bf8fc234Set } else { 159bf8fc234Set px_pec_err_t *pec_p = (px_pec_err_t *)epkt; 160bf8fc234Set uint32_t dir = pec_p->pec_descr.dir; 161bf8fc234Set 162eae2e508Skrishnae adv_reg.pcie_ue_hdr[0] = (uint32_t)(pec_p->hdr[0]); 163eae2e508Skrishnae adv_reg.pcie_ue_hdr[1] = (uint32_t)(pec_p->hdr[0] >> 32); 164eae2e508Skrishnae adv_reg.pcie_ue_hdr[2] = (uint32_t)(pec_p->hdr[1]); 165eae2e508Skrishnae adv_reg.pcie_ue_hdr[3] = (uint32_t)(pec_p->hdr[1] >> 32); 166bf8fc234Set 167bf8fc234Set /* translate RC UR/CA to legacy secondary errors */ 168bf8fc234Set if ((dir == DIR_READ || dir == DIR_WRITE) && 169bf8fc234Set pec_p->pec_descr.U) { 170bf8fc234Set if (pec_p->ue_reg_status & PCIE_AER_UCE_UR) 171bf8fc234Set s_status |= PCI_STAT_R_MAST_AB; 1721ff65112Segillett if (pec_p->ue_reg_status & PCIE_AER_UCE_CA) 173bf8fc234Set s_status |= PCI_STAT_R_TARG_AB; 174bf8fc234Set } 175bf8fc234Set 176bf8fc234Set if (pec_p->ue_reg_status & PCIE_AER_UCE_PTLP) 177bf8fc234Set s_status |= PCI_STAT_PERROR; 178bf8fc234Set 179bf8fc234Set if (pec_p->ue_reg_status & PCIE_AER_UCE_CA) 180bf8fc234Set s_status |= PCI_STAT_S_TARG_AB; 181bf8fc234Set 182eae2e508Skrishnae sts = pf_tlp_decode(PCIE_DIP2BUS(dip), &adv_reg); 183eae2e508Skrishnae fault_bdf = adv_reg.pcie_ue_tgt_bdf; 184c85864d8SKrishna Elango fault_addr = adv_reg.pcie_ue_tgt_addr; 185bf8fc234Set } 186bf8fc234Set 187bf8fc234Set if (sts == DDI_SUCCESS) 188bf8fc234Set px_rp_en_q(px_p, fault_bdf, fault_addr, s_status); 189bf8fc234Set } 190bf8fc234Set 191bf8fc234Set /* 192bf8fc234Set * px_err_intr: 193f8d2de6bSjchu * Interrupt handler for the JBC/DMC/PEC block. 194f8d2de6bSjchu * o lock 195f8d2de6bSjchu * o create derr 196f8d2de6bSjchu * o check safe access 197bf8fc234Set * o px_err_check_severity(epkt) 198bf8fc234Set * o pcie_scan_fabric 199f8d2de6bSjchu * o Idle intr state 200f8d2de6bSjchu * o unlock 201f8d2de6bSjchu * o handle error: fatal? fm_panic() : return INTR_CLAIMED) 202f8d2de6bSjchu */ 203f8d2de6bSjchu static uint_t 204bf8fc234Set px_err_intr(px_fault_t *fault_p, px_rc_err_t *epkt) 205f8d2de6bSjchu { 206f8d2de6bSjchu px_t *px_p = DIP_TO_STATE(fault_p->px_fh_dip); 207f8d2de6bSjchu dev_info_t *rpdip = px_p->px_dip; 208eae2e508Skrishnae int rc_err, fab_err, msg; 209f8d2de6bSjchu ddi_fm_error_t derr; 210f8d2de6bSjchu 211eae2e508Skrishnae if (px_fm_enter(px_p) != DDI_SUCCESS) 212eae2e508Skrishnae goto done; 213f8d2de6bSjchu 214f8d2de6bSjchu /* Create the derr */ 215f8d2de6bSjchu bzero(&derr, sizeof (ddi_fm_error_t)); 216f8d2de6bSjchu derr.fme_version = DDI_FME_VERSION; 217f8d2de6bSjchu derr.fme_ena = fm_ena_generate(epkt->stick, FM_ENA_FMT1); 218f8d2de6bSjchu derr.fme_flag = DDI_FM_ERR_UNEXPECTED; 219f8d2de6bSjchu 220f8d2de6bSjchu /* Basically check for safe access */ 221bf8fc234Set (void) px_err_cmn_intr(px_p, &derr, PX_INTR_CALL, PX_FM_BLOCK_ALL); 222f8d2de6bSjchu 223f8d2de6bSjchu /* Check the severity of this error */ 224bf8fc234Set rc_err = px_err_epkt_severity(px_p, &derr, epkt, PX_INTR_CALL); 225f8d2de6bSjchu 226bf8fc234Set /* Scan the fabric if the root port is not in drain state. */ 227eae2e508Skrishnae fab_err = px_scan_fabric(px_p, rpdip, &derr); 228f8d2de6bSjchu 229f8d2de6bSjchu /* Set the intr state to idle for the leaf that received the mondo */ 230f8d2de6bSjchu if (px_lib_intr_setstate(rpdip, fault_p->px_fh_sysino, 2311ff65112Segillett INTR_IDLE_STATE) != DDI_SUCCESS) { 232eae2e508Skrishnae px_fm_exit(px_p); 233f8d2de6bSjchu return (DDI_INTR_UNCLAIMED); 234f8d2de6bSjchu } 235f8d2de6bSjchu 236bf8fc234Set switch (epkt->rc_descr.block) { 237bf8fc234Set case BLOCK_MMU: /* FALLTHROUGH */ 238bf8fc234Set case BLOCK_INTR: 239bf8fc234Set msg = PX_RC; 240bf8fc234Set break; 241bf8fc234Set case BLOCK_PCIE: 242bf8fc234Set msg = PX_RP; 243bf8fc234Set break; 244bf8fc234Set case BLOCK_HOSTBUS: /* FALLTHROUGH */ 245bf8fc234Set default: 246bf8fc234Set msg = PX_HB; 247bf8fc234Set break; 248bf8fc234Set } 249bf8fc234Set 250eae2e508Skrishnae px_err_panic(rc_err, msg, fab_err, B_TRUE); 251eae2e508Skrishnae px_fm_exit(px_p); 252eae2e508Skrishnae px_err_panic(rc_err, msg, fab_err, B_FALSE); 253f8d2de6bSjchu 254eae2e508Skrishnae done: 255f8d2de6bSjchu return (DDI_INTR_CLAIMED); 256f8d2de6bSjchu } 257f8d2de6bSjchu 258f8d2de6bSjchu /* 259bf8fc234Set * px_err_epkt_severity: 260f8d2de6bSjchu * Check the severity of the fire error based the epkt received 261f8d2de6bSjchu * 262f8d2de6bSjchu * @param px_p leaf in which to take the snap shot. 263f8d2de6bSjchu * @param derr fm err in which the ereport is to be based on 264f8d2de6bSjchu * @param epkt epkt recevied from HV 265f8d2de6bSjchu */ 266f8d2de6bSjchu static int 267bf8fc234Set px_err_epkt_severity(px_t *px_p, ddi_fm_error_t *derr, px_rc_err_t *epkt, 268f8d2de6bSjchu int caller) 269f8d2de6bSjchu { 270f8d2de6bSjchu px_pec_t *pec_p = px_p->px_pec_p; 271f8d2de6bSjchu dev_info_t *dip = px_p->px_dip; 272bf8fc234Set boolean_t is_safeacc = B_FALSE; 273bf8fc234Set boolean_t is_block_pci = B_FALSE; 274eae2e508Skrishnae boolean_t is_valid_epkt = B_FALSE; 275f8d2de6bSjchu int err = 0; 276f8d2de6bSjchu 277f8d2de6bSjchu /* Cautious access error handling */ 278bf8fc234Set switch (derr->fme_flag) { 279bf8fc234Set case DDI_FM_ERR_EXPECTED: 280f8d2de6bSjchu if (caller == PX_TRAP_CALL) { 281f8d2de6bSjchu /* 282f8d2de6bSjchu * for ddi_caut_get treat all events as nonfatal 283f8d2de6bSjchu * The trampoline will set err_ena = 0, 284f8d2de6bSjchu * err_status = NONFATAL. 285f8d2de6bSjchu */ 286f8d2de6bSjchu derr->fme_status = DDI_FM_NONFATAL; 287bf8fc234Set is_safeacc = B_TRUE; 288f8d2de6bSjchu } else { 289f8d2de6bSjchu /* 290f8d2de6bSjchu * For ddi_caut_put treat all events as nonfatal. Here 291f8d2de6bSjchu * we have the handle and can call ndi_fm_acc_err_set(). 292f8d2de6bSjchu */ 293f8d2de6bSjchu derr->fme_status = DDI_FM_NONFATAL; 294f8d2de6bSjchu ndi_fm_acc_err_set(pec_p->pec_acc_hdl, derr); 295bf8fc234Set is_safeacc = B_TRUE; 296f8d2de6bSjchu } 297bf8fc234Set break; 298bf8fc234Set case DDI_FM_ERR_PEEK: 299bf8fc234Set case DDI_FM_ERR_POKE: 300bf8fc234Set /* 301bf8fc234Set * For ddi_peek/poke treat all events as nonfatal. 302bf8fc234Set */ 303bf8fc234Set is_safeacc = B_TRUE; 304bf8fc234Set break; 305bf8fc234Set default: 306bf8fc234Set is_safeacc = B_FALSE; 307f8d2de6bSjchu } 308f8d2de6bSjchu 309bf8fc234Set /* 310bf8fc234Set * Older hypervisors in some cases send epkts with incorrect fields. 311bf8fc234Set * We have to handle these "special" epkts correctly. 312bf8fc234Set */ 313bf8fc234Set if (px_legacy_epkt) 314bf8fc234Set px_fix_legacy_epkt(dip, derr, epkt); 315bf8fc234Set 316f8d2de6bSjchu switch (epkt->rc_descr.block) { 317f8d2de6bSjchu case BLOCK_HOSTBUS: 318bf8fc234Set err = px_cb_epkt_severity(dip, derr, epkt); 319f8d2de6bSjchu break; 320f8d2de6bSjchu case BLOCK_MMU: 321bf8fc234Set err = px_mmu_epkt_severity(dip, derr, epkt); 322bf8fc234Set px_err_fill_pfd(dip, px_p, epkt); 323f8d2de6bSjchu break; 324f8d2de6bSjchu case BLOCK_INTR: 325bf8fc234Set err = px_intr_epkt_severity(dip, derr, epkt); 326f8d2de6bSjchu break; 327*4df55fdeSJanie Lu case BLOCK_PORT: 328*4df55fdeSJanie Lu err = px_port_epkt_severity(dip, derr, epkt); 329*4df55fdeSJanie Lu break; 330f8d2de6bSjchu case BLOCK_PCIE: 331bf8fc234Set is_block_pci = B_TRUE; 332bf8fc234Set err = px_pcie_epkt_severity(dip, derr, epkt); 333bf8fc234Set px_err_fill_pfd(dip, px_p, epkt); 334f8d2de6bSjchu break; 335f8d2de6bSjchu default: 336bf8fc234Set err = 0; 337f8d2de6bSjchu } 338f8d2de6bSjchu 339bf8fc234Set if ((err & PX_HW_RESET) || (err & PX_PANIC)) { 340bf8fc234Set if (px_log & PX_PANIC) 341bf8fc234Set px_err_log_handle(dip, epkt, is_block_pci, "PANIC"); 342eae2e508Skrishnae is_valid_epkt = B_TRUE; 343bf8fc234Set } else if (err & PX_PROTECTED) { 344bf8fc234Set if (px_log & PX_PROTECTED) 345bf8fc234Set px_err_log_handle(dip, epkt, is_block_pci, "PROTECTED"); 346eae2e508Skrishnae is_valid_epkt = B_TRUE; 347bf8fc234Set } else if (err & PX_NO_PANIC) { 348bf8fc234Set if (px_log & PX_NO_PANIC) 349bf8fc234Set px_err_log_handle(dip, epkt, is_block_pci, "NO PANIC"); 350eae2e508Skrishnae is_valid_epkt = B_TRUE; 351bf8fc234Set } else if (err & PX_NO_ERROR) { 352bf8fc234Set if (px_log & PX_NO_ERROR) 353bf8fc234Set px_err_log_handle(dip, epkt, is_block_pci, "NO ERROR"); 354eae2e508Skrishnae is_valid_epkt = B_TRUE; 355bf8fc234Set } else if (err == 0) { 356bf8fc234Set px_err_log_handle(dip, epkt, is_block_pci, "UNRECOGNIZED"); 357eae2e508Skrishnae is_valid_epkt = B_FALSE; 358bf8fc234Set 359eae2e508Skrishnae /* Panic on a unrecognized epkt */ 360bf8fc234Set err = PX_PANIC; 361bf8fc234Set } 362bf8fc234Set 363eae2e508Skrishnae px_err_send_epkt_erpt(dip, epkt, is_block_pci, err, derr, 364eae2e508Skrishnae is_valid_epkt); 365eae2e508Skrishnae 366bf8fc234Set /* Readjust the severity as a result of safe access */ 367bf8fc234Set if (is_safeacc && !(err & PX_PANIC) && !(px_die & PX_PROTECTED)) 368bf8fc234Set err = PX_NO_PANIC; 369bf8fc234Set 370f8d2de6bSjchu return (err); 371f8d2de6bSjchu } 372f8d2de6bSjchu 373eae2e508Skrishnae static void 374eae2e508Skrishnae px_err_send_epkt_erpt(dev_info_t *dip, px_rc_err_t *epkt, 375eae2e508Skrishnae boolean_t is_block_pci, int err, ddi_fm_error_t *derr, 376eae2e508Skrishnae boolean_t is_valid_epkt) 377eae2e508Skrishnae { 378eae2e508Skrishnae char buf[FM_MAX_CLASS], descr_buf[1024]; 379eae2e508Skrishnae 380eae2e508Skrishnae /* send ereport for debug purposes */ 381eae2e508Skrishnae (void) snprintf(buf, FM_MAX_CLASS, "%s", PX_FM_RC_UNRECOG); 382eae2e508Skrishnae 383eae2e508Skrishnae if (is_block_pci) { 384eae2e508Skrishnae px_pec_err_t *pec = (px_pec_err_t *)epkt; 385eae2e508Skrishnae (void) snprintf(descr_buf, sizeof (descr_buf), 386eae2e508Skrishnae "%s Epkt contents:\n" 387eae2e508Skrishnae "Block: 0x%x, Dir: 0x%x, Flags: Z=%d, S=%d, R=%d\n" 388eae2e508Skrishnae "I=%d, H=%d, C=%d, U=%d, E=%d, P=%d\n" 389eae2e508Skrishnae "PCI Err Status: 0x%x, PCIe Err Status: 0x%x\n" 390eae2e508Skrishnae "CE Status Reg: 0x%x, UE Status Reg: 0x%x\n" 391eae2e508Skrishnae "HDR1: 0x%lx, HDR2: 0x%lx\n" 392eae2e508Skrishnae "Err Src Reg: 0x%x, Root Err Status: 0x%x\n" 393eae2e508Skrishnae "Err Severity: 0x%x\n", 394eae2e508Skrishnae is_valid_epkt ? "Valid" : "Invalid", 395eae2e508Skrishnae pec->pec_descr.block, pec->pec_descr.dir, 396eae2e508Skrishnae pec->pec_descr.Z, pec->pec_descr.S, 397eae2e508Skrishnae pec->pec_descr.R, pec->pec_descr.I, 398eae2e508Skrishnae pec->pec_descr.H, pec->pec_descr.C, 399eae2e508Skrishnae pec->pec_descr.U, pec->pec_descr.E, 400eae2e508Skrishnae pec->pec_descr.P, pec->pci_err_status, 401eae2e508Skrishnae pec->pcie_err_status, pec->ce_reg_status, 402eae2e508Skrishnae pec->ue_reg_status, pec->hdr[0], 403eae2e508Skrishnae pec->hdr[1], pec->err_src_reg, 404eae2e508Skrishnae pec->root_err_status, err); 405eae2e508Skrishnae 406eae2e508Skrishnae ddi_fm_ereport_post(dip, buf, derr->fme_ena, 407eae2e508Skrishnae DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 408eae2e508Skrishnae EPKT_SYSINO, DATA_TYPE_UINT64, 409eae2e508Skrishnae is_valid_epkt ? pec->sysino : 0, 410eae2e508Skrishnae EPKT_EHDL, DATA_TYPE_UINT64, 411eae2e508Skrishnae is_valid_epkt ? pec->ehdl : 0, 412eae2e508Skrishnae EPKT_STICK, DATA_TYPE_UINT64, 413eae2e508Skrishnae is_valid_epkt ? pec->stick : 0, 414*4df55fdeSJanie Lu EPKT_DW0, DATA_TYPE_UINT64, ((uint64_t *)pec)[3], 415*4df55fdeSJanie Lu EPKT_DW1, DATA_TYPE_UINT64, ((uint64_t *)pec)[4], 416*4df55fdeSJanie Lu EPKT_DW2, DATA_TYPE_UINT64, ((uint64_t *)pec)[5], 417*4df55fdeSJanie Lu EPKT_DW3, DATA_TYPE_UINT64, ((uint64_t *)pec)[6], 418*4df55fdeSJanie Lu EPKT_DW4, DATA_TYPE_UINT64, ((uint64_t *)pec)[7], 419eae2e508Skrishnae EPKT_PEC_DESCR, DATA_TYPE_STRING, descr_buf); 420eae2e508Skrishnae } else { 421eae2e508Skrishnae (void) snprintf(descr_buf, sizeof (descr_buf), 422eae2e508Skrishnae "%s Epkt contents:\n" 423eae2e508Skrishnae "Block: 0x%x, Op: 0x%x, Phase: 0x%x, Cond: 0x%x\n" 424eae2e508Skrishnae "Dir: 0x%x, Flags: STOP=%d, H=%d, R=%d, D=%d\n" 425eae2e508Skrishnae "M=%d, S=%d, Size: 0x%x, Addr: 0x%lx\n" 426eae2e508Skrishnae "Hdr1: 0x%lx, Hdr2: 0x%lx, Res: 0x%lx\n" 427eae2e508Skrishnae "Err Severity: 0x%x\n", 428eae2e508Skrishnae is_valid_epkt ? "Valid" : "Invalid", 429eae2e508Skrishnae epkt->rc_descr.block, epkt->rc_descr.op, 430eae2e508Skrishnae epkt->rc_descr.phase, epkt->rc_descr.cond, 431eae2e508Skrishnae epkt->rc_descr.dir, epkt->rc_descr.STOP, 432eae2e508Skrishnae epkt->rc_descr.H, epkt->rc_descr.R, 433eae2e508Skrishnae epkt->rc_descr.D, epkt->rc_descr.M, 434eae2e508Skrishnae epkt->rc_descr.S, epkt->size, epkt->addr, 435eae2e508Skrishnae epkt->hdr[0], epkt->hdr[1], epkt->reserved, 436eae2e508Skrishnae err); 437eae2e508Skrishnae 438eae2e508Skrishnae ddi_fm_ereport_post(dip, buf, derr->fme_ena, 439eae2e508Skrishnae DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 440eae2e508Skrishnae EPKT_SYSINO, DATA_TYPE_UINT64, 441eae2e508Skrishnae is_valid_epkt ? epkt->sysino : 0, 442eae2e508Skrishnae EPKT_EHDL, DATA_TYPE_UINT64, 443eae2e508Skrishnae is_valid_epkt ? epkt->ehdl : 0, 444eae2e508Skrishnae EPKT_STICK, DATA_TYPE_UINT64, 445eae2e508Skrishnae is_valid_epkt ? epkt->stick : 0, 446*4df55fdeSJanie Lu EPKT_DW0, DATA_TYPE_UINT64, ((uint64_t *)epkt)[3], 447*4df55fdeSJanie Lu EPKT_DW1, DATA_TYPE_UINT64, ((uint64_t *)epkt)[4], 448*4df55fdeSJanie Lu EPKT_DW2, DATA_TYPE_UINT64, ((uint64_t *)epkt)[5], 449*4df55fdeSJanie Lu EPKT_DW3, DATA_TYPE_UINT64, ((uint64_t *)epkt)[6], 450*4df55fdeSJanie Lu EPKT_DW4, DATA_TYPE_UINT64, ((uint64_t *)epkt)[7], 451eae2e508Skrishnae EPKT_RC_DESCR, DATA_TYPE_STRING, descr_buf); 452eae2e508Skrishnae } 453eae2e508Skrishnae } 454eae2e508Skrishnae 455bf8fc234Set static void 456bf8fc234Set px_err_log_handle(dev_info_t *dip, px_rc_err_t *epkt, boolean_t is_block_pci, 457bf8fc234Set char *msg) 458bf8fc234Set { 459bf8fc234Set if (is_block_pci) { 460bf8fc234Set px_pec_err_t *pec = (px_pec_err_t *)epkt; 461bf8fc234Set DBG(DBG_ERR_INTR, dip, 462bf8fc234Set "A PCIe root port error has occured with a severity" 463bf8fc234Set " \"%s\"\n" 464bf8fc234Set "\tBlock: 0x%x, Dir: 0x%x, Flags: Z=%d, S=%d, R=%d, I=%d\n" 465bf8fc234Set "\tH=%d, C=%d, U=%d, E=%d, P=%d\n" 466bf8fc234Set "\tpci_err: 0x%x, pcie_err=0x%x, ce_reg: 0x%x\n" 467bf8fc234Set "\tue_reg: 0x%x, Hdr1: 0x%p, Hdr2: 0x%p\n" 468bf8fc234Set "\terr_src: 0x%x, root_err: 0x%x\n", 469bf8fc234Set msg, pec->pec_descr.block, pec->pec_descr.dir, 470bf8fc234Set pec->pec_descr.Z, pec->pec_descr.S, pec->pec_descr.R, 471bf8fc234Set pec->pec_descr.I, pec->pec_descr.H, pec->pec_descr.C, 472bf8fc234Set pec->pec_descr.U, pec->pec_descr.E, pec->pec_descr.P, 473bf8fc234Set pec->pci_err_status, pec->pcie_err_status, 474bf8fc234Set pec->ce_reg_status, pec->ue_reg_status, pec->hdr[0], 475bf8fc234Set pec->hdr[1], pec->err_src_reg, pec->root_err_status); 476bf8fc234Set } else { 477bf8fc234Set DBG(DBG_ERR_INTR, dip, 478bf8fc234Set "A PCIe root complex error has occured with a severity" 479bf8fc234Set " \"%s\"\n" 480bf8fc234Set "\tBlock: 0x%x, Op: 0x%x, Phase: 0x%x, Cond: 0x%x\n" 481bf8fc234Set "\tDir: 0x%x, Flags: STOP=%d, H=%d, R=%d, D=%d, M=%d\n" 482bf8fc234Set "\tS=%d, Size: 0x%x, Addr: 0x%p\n" 483bf8fc234Set "\tHdr1: 0x%p, Hdr2: 0x%p, Res: 0x%p\n", 484bf8fc234Set msg, epkt->rc_descr.block, epkt->rc_descr.op, 485bf8fc234Set epkt->rc_descr.phase, epkt->rc_descr.cond, 486bf8fc234Set epkt->rc_descr.dir, epkt->rc_descr.STOP, epkt->rc_descr.H, 487bf8fc234Set epkt->rc_descr.R, epkt->rc_descr.D, epkt->rc_descr.M, 488bf8fc234Set epkt->rc_descr.S, epkt->size, epkt->addr, epkt->hdr[0], 489bf8fc234Set epkt->hdr[1], epkt->reserved); 490bf8fc234Set } 491bf8fc234Set } 492bf8fc234Set 493f8d2de6bSjchu /* ARGSUSED */ 494bf8fc234Set static void 495bf8fc234Set px_fix_legacy_epkt(dev_info_t *dip, ddi_fm_error_t *derr, px_rc_err_t *epkt) 496f8d2de6bSjchu { 497bf8fc234Set /* 498bf8fc234Set * We don't have a default case for any of the below switch statements 499bf8fc234Set * since we are ok with the code falling through. 500bf8fc234Set */ 501bf8fc234Set switch (epkt->rc_descr.block) { 502bf8fc234Set case BLOCK_HOSTBUS: 503bf8fc234Set switch (epkt->rc_descr.op) { 504bf8fc234Set case OP_DMA: 505bf8fc234Set switch (epkt->rc_descr.phase) { 506bf8fc234Set case PH_UNKNOWN: 507bf8fc234Set switch (epkt->rc_descr.cond) { 508bf8fc234Set case CND_UNKNOWN: 509bf8fc234Set switch (epkt->rc_descr.dir) { 510bf8fc234Set case DIR_RESERVED: 511bf8fc234Set epkt->rc_descr.dir = DIR_READ; 512bf8fc234Set break; 513bf8fc234Set } /* DIR */ 514bf8fc234Set } /* CND */ 515bf8fc234Set } /* PH */ 516bf8fc234Set } /* OP */ 517f8d2de6bSjchu break; 518bf8fc234Set case BLOCK_MMU: 519bf8fc234Set switch (epkt->rc_descr.op) { 520bf8fc234Set case OP_XLAT: 521bf8fc234Set switch (epkt->rc_descr.phase) { 522bf8fc234Set case PH_DATA: 523bf8fc234Set switch (epkt->rc_descr.cond) { 524bf8fc234Set case CND_PROT: 525bf8fc234Set switch (epkt->rc_descr.dir) { 526bf8fc234Set case DIR_UNKNOWN: 527bf8fc234Set epkt->rc_descr.dir = DIR_WRITE; 528bf8fc234Set break; 529bf8fc234Set } /* DIR */ 530bf8fc234Set } /* CND */ 5313d9c56a1Set break; 532bf8fc234Set case PH_IRR: 533bf8fc234Set switch (epkt->rc_descr.cond) { 534bf8fc234Set case CND_RESERVED: 535bf8fc234Set switch (epkt->rc_descr.dir) { 536bf8fc234Set case DIR_IRR: 537bf8fc234Set epkt->rc_descr.phase = PH_ADDR; 538bf8fc234Set epkt->rc_descr.cond = CND_IRR; 539bf8fc234Set } /* DIR */ 540bf8fc234Set } /* CND */ 541bf8fc234Set } /* PH */ 542bf8fc234Set } /* OP */ 543e51949e6Sdduvall break; 544bf8fc234Set case BLOCK_INTR: 545bf8fc234Set switch (epkt->rc_descr.op) { 546bf8fc234Set case OP_MSIQ: 547bf8fc234Set switch (epkt->rc_descr.phase) { 548bf8fc234Set case PH_UNKNOWN: 549bf8fc234Set switch (epkt->rc_descr.cond) { 550bf8fc234Set case CND_ILL: 551bf8fc234Set switch (epkt->rc_descr.dir) { 552bf8fc234Set case DIR_RESERVED: 553bf8fc234Set epkt->rc_descr.dir = DIR_IRR; 554bf8fc234Set break; 555bf8fc234Set } /* DIR */ 556bf8fc234Set break; 557bf8fc234Set case CND_IRR: 558bf8fc234Set switch (epkt->rc_descr.dir) { 559bf8fc234Set case DIR_IRR: 560bf8fc234Set epkt->rc_descr.cond = CND_OV; 561bf8fc234Set break; 562bf8fc234Set } /* DIR */ 563bf8fc234Set } /* CND */ 564bf8fc234Set } /* PH */ 565bf8fc234Set break; 566bf8fc234Set case OP_RESERVED: 567bf8fc234Set switch (epkt->rc_descr.phase) { 568bf8fc234Set case PH_UNKNOWN: 569bf8fc234Set switch (epkt->rc_descr.cond) { 570bf8fc234Set case CND_ILL: 571bf8fc234Set switch (epkt->rc_descr.dir) { 572bf8fc234Set case DIR_IRR: 573bf8fc234Set epkt->rc_descr.op = OP_MSI32; 574bf8fc234Set epkt->rc_descr.phase = PH_DATA; 575bf8fc234Set break; 576bf8fc234Set } /* DIR */ 577bf8fc234Set } /* CND */ 578bf8fc234Set break; 579bf8fc234Set case PH_DATA: 580bf8fc234Set switch (epkt->rc_descr.cond) { 581bf8fc234Set case CND_INT: 582bf8fc234Set switch (epkt->rc_descr.dir) { 583bf8fc234Set case DIR_UNKNOWN: 584bf8fc234Set epkt->rc_descr.op = OP_MSI32; 585bf8fc234Set break; 586bf8fc234Set } /* DIR */ 587bf8fc234Set } /* CND */ 588bf8fc234Set } /* PH */ 589bf8fc234Set } /* OP */ 590bf8fc234Set } /* BLOCK */ 591bf8fc234Set } 5923d9c56a1Set 593bf8fc234Set /* ARGSUSED */ 594bf8fc234Set static int 595bf8fc234Set px_intr_handle_errors(dev_info_t *dip, ddi_fm_error_t *derr, px_rc_err_t *epkt) 596bf8fc234Set { 597bf8fc234Set return (px_err_check_eq(dip)); 598bf8fc234Set } 599bf8fc234Set 600*4df55fdeSJanie Lu /* ARGSUSED */ 601*4df55fdeSJanie Lu static int 602*4df55fdeSJanie Lu px_port_handle_errors(dev_info_t *dip, ddi_fm_error_t *derr, px_rc_err_t *epkt) 603*4df55fdeSJanie Lu { 604*4df55fdeSJanie Lu pf_pcie_adv_err_regs_t adv_reg; 605*4df55fdeSJanie Lu uint16_t s_status; 606*4df55fdeSJanie Lu int sts = PX_PANIC; 607*4df55fdeSJanie Lu 608*4df55fdeSJanie Lu /* 609*4df55fdeSJanie Lu * Check for failed non-posted writes, which are errors that are not 610*4df55fdeSJanie Lu * defined in the PCIe spec. If not return panic. 611*4df55fdeSJanie Lu */ 612*4df55fdeSJanie Lu if (!((epkt->rc_descr.op == OP_PIO) && 613*4df55fdeSJanie Lu (epkt->rc_descr.phase == PH_IRR))) { 614*4df55fdeSJanie Lu sts = (PX_PANIC); 615*4df55fdeSJanie Lu goto done; 616*4df55fdeSJanie Lu } 617*4df55fdeSJanie Lu 618*4df55fdeSJanie Lu /* 619*4df55fdeSJanie Lu * Gather the error logs, if they do not exist just return with no panic 620*4df55fdeSJanie Lu * and let the fabric message take care of the error. 621*4df55fdeSJanie Lu */ 622*4df55fdeSJanie Lu if (!epkt->rc_descr.H) { 623*4df55fdeSJanie Lu sts = (PX_NO_PANIC); 624*4df55fdeSJanie Lu goto done; 625*4df55fdeSJanie Lu } 626*4df55fdeSJanie Lu 627*4df55fdeSJanie Lu adv_reg.pcie_ue_hdr[0] = (uint32_t)(epkt->hdr[0]); 628*4df55fdeSJanie Lu adv_reg.pcie_ue_hdr[1] = (uint32_t)(epkt->hdr[0] >> 32); 629*4df55fdeSJanie Lu adv_reg.pcie_ue_hdr[2] = (uint32_t)(epkt->hdr[1]); 630*4df55fdeSJanie Lu adv_reg.pcie_ue_hdr[3] = (uint32_t)(epkt->hdr[1] >> 32); 631*4df55fdeSJanie Lu 632*4df55fdeSJanie Lu sts = pf_tlp_decode(PCIE_DIP2BUS(dip), &adv_reg); 633*4df55fdeSJanie Lu 634*4df55fdeSJanie Lu if (epkt->rc_descr.M) 635*4df55fdeSJanie Lu adv_reg.pcie_ue_tgt_addr = epkt->addr; 636*4df55fdeSJanie Lu 637*4df55fdeSJanie Lu if (!((sts == DDI_SUCCESS) || (epkt->rc_descr.M))) { 638*4df55fdeSJanie Lu /* Let the fabric message take care of error */ 639*4df55fdeSJanie Lu sts = PX_NO_PANIC; 640*4df55fdeSJanie Lu goto done; 641*4df55fdeSJanie Lu } 642*4df55fdeSJanie Lu 643*4df55fdeSJanie Lu /* See if the failed transaction belonged to a hardened driver */ 644*4df55fdeSJanie Lu if (pf_hdl_lookup(dip, derr->fme_ena, 645*4df55fdeSJanie Lu adv_reg.pcie_ue_tgt_trans, adv_reg.pcie_ue_tgt_addr, 646*4df55fdeSJanie Lu adv_reg.pcie_ue_tgt_bdf) == PF_HDL_FOUND) 647*4df55fdeSJanie Lu sts = (PX_NO_PANIC); 648*4df55fdeSJanie Lu else 649*4df55fdeSJanie Lu sts = (PX_PANIC); 650*4df55fdeSJanie Lu 651*4df55fdeSJanie Lu /* Add pfd to cause a fabric scan */ 652*4df55fdeSJanie Lu switch (epkt->rc_descr.cond) { 653*4df55fdeSJanie Lu case CND_RCA: 654*4df55fdeSJanie Lu s_status = PCI_STAT_R_TARG_AB; 655*4df55fdeSJanie Lu break; 656*4df55fdeSJanie Lu case CND_RUR: 657*4df55fdeSJanie Lu s_status = PCI_STAT_R_MAST_AB; 658*4df55fdeSJanie Lu break; 659*4df55fdeSJanie Lu } 660*4df55fdeSJanie Lu px_rp_en_q(DIP_TO_STATE(dip), adv_reg.pcie_ue_tgt_bdf, 661*4df55fdeSJanie Lu adv_reg.pcie_ue_tgt_addr, s_status); 662*4df55fdeSJanie Lu 663*4df55fdeSJanie Lu done: 664*4df55fdeSJanie Lu return (sts); 665*4df55fdeSJanie Lu } 666*4df55fdeSJanie Lu 667bf8fc234Set /* ARGSUSED */ 668bf8fc234Set static int 669bf8fc234Set px_pcie_epkt_severity(dev_info_t *dip, ddi_fm_error_t *derr, px_rc_err_t *epkt) 670bf8fc234Set { 671eae2e508Skrishnae px_pec_err_t *pec_p = (px_pec_err_t *)epkt; 672bf8fc234Set px_err_pcie_t *pcie = (px_err_pcie_t *)epkt; 673eae2e508Skrishnae pf_pcie_adv_err_regs_t adv_reg; 674eae2e508Skrishnae int sts; 675bf8fc234Set uint32_t temp; 676f8d2de6bSjchu 677f8d2de6bSjchu /* 678bf8fc234Set * Check for failed PIO Read/Writes, which are errors that are not 679bf8fc234Set * defined in the PCIe spec. 680f8d2de6bSjchu */ 681bf8fc234Set temp = PCIE_AER_UCE_UR | PCIE_AER_UCE_CA; 682eae2e508Skrishnae if (((pec_p->pec_descr.dir == DIR_READ) || 683eae2e508Skrishnae (pec_p->pec_descr.dir == DIR_WRITE)) && 684eae2e508Skrishnae pec_p->pec_descr.U && (pec_p->ue_reg_status & temp)) { 685eae2e508Skrishnae adv_reg.pcie_ue_hdr[0] = (uint32_t)(pec_p->hdr[0]); 686eae2e508Skrishnae adv_reg.pcie_ue_hdr[1] = (uint32_t)(pec_p->hdr[0] >> 32); 687eae2e508Skrishnae adv_reg.pcie_ue_hdr[2] = (uint32_t)(pec_p->hdr[1]); 688eae2e508Skrishnae adv_reg.pcie_ue_hdr[3] = (uint32_t)(pec_p->hdr[1] >> 32); 689eae2e508Skrishnae 690eae2e508Skrishnae sts = pf_tlp_decode(PCIE_DIP2BUS(dip), &adv_reg); 691eae2e508Skrishnae 692eae2e508Skrishnae if (sts == DDI_SUCCESS && 693eae2e508Skrishnae pf_hdl_lookup(dip, derr->fme_ena, 694eae2e508Skrishnae adv_reg.pcie_ue_tgt_trans, 695eae2e508Skrishnae adv_reg.pcie_ue_tgt_addr, 696eae2e508Skrishnae adv_reg.pcie_ue_tgt_bdf) == PF_HDL_FOUND) 697bf8fc234Set return (PX_NO_PANIC); 698f8d2de6bSjchu else 699bf8fc234Set return (PX_PANIC); 700f8d2de6bSjchu } 701f8d2de6bSjchu 702eae2e508Skrishnae if (!pec_p->pec_descr.C) 703eae2e508Skrishnae pec_p->ce_reg_status = 0; 704eae2e508Skrishnae if (!pec_p->pec_descr.U) 705eae2e508Skrishnae pec_p->ue_reg_status = 0; 706eae2e508Skrishnae if (!pec_p->pec_descr.H) 707eae2e508Skrishnae pec_p->hdr[0] = 0; 708eae2e508Skrishnae if (!pec_p->pec_descr.I) 709eae2e508Skrishnae pec_p->hdr[1] = 0; 710f8d2de6bSjchu 711bf8fc234Set /* 712bf8fc234Set * According to the PCIe spec, there is a first error pointer. If there 713bf8fc234Set * are header logs recorded and there are more than one error, the log 714bf8fc234Set * will belong to the error that the first error pointer points to. 715bf8fc234Set * 716bf8fc234Set * The regs.primary_ue expects a bit number, go through the ue register 717bf8fc234Set * and find the first error that occured. Because the sun4v epkt spec 718bf8fc234Set * does not define this value, the algorithm below gives the lower bit 719bf8fc234Set * priority. 720bf8fc234Set */ 721bf8fc234Set temp = pcie->ue_reg; 722bf8fc234Set if (temp) { 723eae2e508Skrishnae int x; 724bf8fc234Set for (x = 0; !(temp & 0x1); x++) { 725bf8fc234Set temp = temp >> 1; 726bf8fc234Set } 727bf8fc234Set pcie->primary_ue = 1 << x; 728bf8fc234Set } else { 729bf8fc234Set pcie->primary_ue = 0; 7303d9c56a1Set } 731f8d2de6bSjchu 732bf8fc234Set /* Sun4v doesn't log the TX hdr except for CTOs */ 733bf8fc234Set if (pcie->primary_ue == PCIE_AER_UCE_TO) { 734bf8fc234Set pcie->tx_hdr1 = pcie->rx_hdr1; 735bf8fc234Set pcie->tx_hdr2 = pcie->rx_hdr2; 736bf8fc234Set pcie->tx_hdr3 = pcie->rx_hdr3; 737bf8fc234Set pcie->tx_hdr4 = pcie->rx_hdr4; 738bf8fc234Set pcie->rx_hdr1 = 0; 739bf8fc234Set pcie->rx_hdr2 = 0; 740bf8fc234Set pcie->rx_hdr3 = 0; 741bf8fc234Set pcie->rx_hdr4 = 0; 742bf8fc234Set } else { 743bf8fc234Set pcie->tx_hdr1 = 0; 744bf8fc234Set pcie->tx_hdr2 = 0; 745bf8fc234Set pcie->tx_hdr3 = 0; 746bf8fc234Set pcie->tx_hdr4 = 0; 747bf8fc234Set } 748e51949e6Sdduvall 749bf8fc234Set return (px_err_check_pcie(dip, derr, pcie)); 750f8d2de6bSjchu } 751f8d2de6bSjchu 752f8d2de6bSjchu static int 753bf8fc234Set px_mmu_handle_lookup(dev_info_t *dip, ddi_fm_error_t *derr, px_rc_err_t *epkt) 754f8d2de6bSjchu { 755eae2e508Skrishnae uint64_t addr = (uint64_t)epkt->addr; 756c85864d8SKrishna Elango pcie_req_id_t bdf = PCIE_INVALID_BDF; 757f8d2de6bSjchu 758bf8fc234Set if (epkt->rc_descr.H) { 759bf8fc234Set bdf = (uint32_t)((epkt->hdr[0] >> 16) && 0xFFFF); 760f8d2de6bSjchu } 761f8d2de6bSjchu 762eae2e508Skrishnae return (pf_hdl_lookup(dip, derr->fme_ena, PF_ADDR_DMA, addr, 7631ff65112Segillett bdf)); 764f8d2de6bSjchu } 765