xref: /illumos-gate/usr/src/uts/sun4v/io/niumx/niumx_var.h (revision 44961713)
1*44961713Sgirish /*
2*44961713Sgirish  * CDDL HEADER START
3*44961713Sgirish  *
4*44961713Sgirish  * The contents of this file are subject to the terms of the
5*44961713Sgirish  * Common Development and Distribution License (the "License").
6*44961713Sgirish  * You may not use this file except in compliance with the License.
7*44961713Sgirish  *
8*44961713Sgirish  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9*44961713Sgirish  * or http://www.opensolaris.org/os/licensing.
10*44961713Sgirish  * See the License for the specific language governing permissions
11*44961713Sgirish  * and limitations under the License.
12*44961713Sgirish  *
13*44961713Sgirish  * When distributing Covered Code, include this CDDL HEADER in each
14*44961713Sgirish  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15*44961713Sgirish  * If applicable, add the following below this CDDL HEADER, with the
16*44961713Sgirish  * fields enclosed by brackets "[]" replaced with your own identifying
17*44961713Sgirish  * information: Portions Copyright [yyyy] [name of copyright owner]
18*44961713Sgirish  *
19*44961713Sgirish  * CDDL HEADER END
20*44961713Sgirish  */
21*44961713Sgirish /*
22*44961713Sgirish  * Copyright 2006 Sun Microsystems, Inc.  All rights reserved.
23*44961713Sgirish  * Use is subject to license terms.
24*44961713Sgirish  */
25*44961713Sgirish 
26*44961713Sgirish #ifndef	_SYS_NMX_H
27*44961713Sgirish #define	_SYS_NMX_H
28*44961713Sgirish 
29*44961713Sgirish #pragma ident	"%Z%%M%	%I%	%E% SMI"
30*44961713Sgirish 
31*44961713Sgirish #ifdef	__cplusplus
32*44961713Sgirish extern "C" {
33*44961713Sgirish #endif
34*44961713Sgirish 
35*44961713Sgirish typedef enum {	/* same sequence as niumx_debug_sym[] */
36*44961713Sgirish 	/*  0 */ DBG_ATTACH,
37*44961713Sgirish 	/*  1 */ DBG_MAP,
38*44961713Sgirish 	/*  2 */ DBG_CTLOPS,
39*44961713Sgirish 	/*  3 */ DBG_INTROPS,
40*44961713Sgirish 	/*  4 */ DBG_A_INTX,
41*44961713Sgirish 	/*  5 */ DBG_R_INTX,
42*44961713Sgirish 	/*  6 */ DBG_INTR,
43*44961713Sgirish 	/*  7 */ DBG_DMA_ALLOCH,
44*44961713Sgirish 	/*  8 */ DBG_DMA_BINDH,
45*44961713Sgirish 	/*  9 */ DBG_DMA_UNBINDH,
46*44961713Sgirish 	/* 10 */ DBG_CHK_MOD
47*44961713Sgirish } niumx_debug_bit_t;
48*44961713Sgirish 
49*44961713Sgirish #if defined(DEBUG)
50*44961713Sgirish #define	DBG niumx_dbg
51*44961713Sgirish extern void niumx_dbg(niumx_debug_bit_t bit, dev_info_t *dip, char *fmt, ...);
52*44961713Sgirish #else
53*44961713Sgirish #define	DBG 0 &&
54*44961713Sgirish #endif	/* DEBUG */
55*44961713Sgirish 
56*44961713Sgirish typedef uint64_t devhandle_t;
57*44961713Sgirish #define	NIUMX_DEVHDLE_MASK	0xFFFFFFF
58*44961713Sgirish typedef uint32_t cpuid_t;
59*44961713Sgirish typedef uint32_t devino_t;
60*44961713Sgirish typedef	uint64_t sysino_t;
61*44961713Sgirish 
62*44961713Sgirish /*
63*44961713Sgirish  * The following structure represents an interrupt handler control block for
64*44961713Sgirish  * each interrupt added via ddi_intr_add_handler().
65*44961713Sgirish  */
66*44961713Sgirish typedef struct niumx_ih {
67*44961713Sgirish 	dev_info_t	*ih_dip;	/* devinfo structure */
68*44961713Sgirish 	uint32_t	ih_inum;	/* interrupt index, from leaf */
69*44961713Sgirish 	devino_t	ih_ino;		/* INO number, from "interrupts" prop */
70*44961713Sgirish 	sysino_t	ih_sysino;	/* System virtual inumber, from HV */
71*44961713Sgirish 	cpuid_t		ih_cpuid;	/* cpu that ino is targeting */
72*44961713Sgirish 	uint_t		(*ih_hdlr)();	/* interrupt handler */
73*44961713Sgirish 	caddr_t		ih_arg1;	/* interrupt handler argument #1 */
74*44961713Sgirish 	caddr_t		ih_arg2;	/* interrupt handler argument #2 */
75*44961713Sgirish 	struct niumx_ih	*ih_next;	/* next in the chain */
76*44961713Sgirish } niumx_ih_t;
77*44961713Sgirish 
78*44961713Sgirish typedef struct niumx_devstate {
79*44961713Sgirish 	dev_info_t *dip;
80*44961713Sgirish 	devhandle_t	niumx_dev_hdl;	/* device handle */
81*44961713Sgirish 	kmutex_t niumx_mutex;
82*44961713Sgirish } niumx_devstate_t;
83*44961713Sgirish 
84*44961713Sgirish #define	NIUMX_FUNC_NUM_MASK	1
85*44961713Sgirish #define	NIUMX_MAX_INTRS	64
86*44961713Sgirish 
87*44961713Sgirish /* currently Error Interrupt handler slot is hardcoded */
88*44961713Sgirish #define	NIUMX_EI_IH 52
89*44961713Sgirish 
90*44961713Sgirish /*
91*44961713Sgirish  * flags for overloading dmai_inuse field of the dma request structure:
92*44961713Sgirish  */
93*44961713Sgirish #define	dmai_pfnlst		dmai_iopte
94*44961713Sgirish #define	dmai_pfn0		dmai_sbi
95*44961713Sgirish #define	dmai_roffset		dmai_pool
96*44961713Sgirish 
97*44961713Sgirish #define	NIUMX_PAGE_SHIFT		13
98*44961713Sgirish #define	NIUMX_PAGE_SIZE		(1 << NIUMX_PAGE_SHIFT)
99*44961713Sgirish #define	NIUMX_PAGE_MASK		~(NIUMX_PAGE_SIZE - 1)
100*44961713Sgirish #define	NIUMX_PAGE_OFFSET		(NIUMX_PAGE_SIZE - 1)
101*44961713Sgirish #define	NIUMX_PTOB(x)		(((uint64_t)(x)) << NIUMX_PAGE_SHIFT)
102*44961713Sgirish 
103*44961713Sgirish /* for "ranges" property */
104*44961713Sgirish typedef struct niumx_ranges {
105*44961713Sgirish 	uint32_t child_hi;
106*44961713Sgirish 	uint32_t child_lo;
107*44961713Sgirish 	uint32_t parent_hi;
108*44961713Sgirish 	uint32_t parent_lo;
109*44961713Sgirish 	uint32_t size_hi;
110*44961713Sgirish 	uint32_t size_lo;
111*44961713Sgirish } niumx_ranges_t;
112*44961713Sgirish 
113*44961713Sgirish /* IPL of 6 for networking devices */
114*44961713Sgirish #define	NIUMX_DEFAULT_PIL	6
115*44961713Sgirish 
116*44961713Sgirish typedef struct {
117*44961713Sgirish 	uint32_t addr_high;
118*44961713Sgirish 	uint32_t addr_low;
119*44961713Sgirish 	uint32_t size_high;
120*44961713Sgirish 	uint32_t size_low;
121*44961713Sgirish } niu_regspec_t;
122*44961713Sgirish 
123*44961713Sgirish /*
124*44961713Sgirish  * HV VPCI & INTR  API versioning.
125*44961713Sgirish  *
126*44961713Sgirish  * Currently NIU nexus driver supports VPCI API version 1.0
127*44961713Sgirish  */
128*44961713Sgirish #define	NIUMX_VPCI_MAJOR_VER_1	0x1ull
129*44961713Sgirish #define	NIUMX_VPCI_MAJOR_VER	NIUMX_VPCI_MAJOR_VER_1
130*44961713Sgirish 
131*44961713Sgirish #define	NIUMX_VPCI_MINOR_VER_0	0x0ull
132*44961713Sgirish #define	NIUMX_VPCI_MINOR_VER	NIUMX_VPCI_MINOR_VER_0
133*44961713Sgirish 
134*44961713Sgirish #define	NIUMX_INTR_MAJOR_VER_1	0x1ull
135*44961713Sgirish #define	NIUMX_INTR_MAJOR_VER	NIUMX_INTR_MAJOR_VER_1
136*44961713Sgirish 
137*44961713Sgirish #define	NIUMX_INTR_MINOR_VER_0	0x0ull
138*44961713Sgirish #define	NIUMX_INTR_MINOR_VER	NIUMX_INTR_MINOR_VER_0
139*44961713Sgirish 
140*44961713Sgirish #define	NAMEINST(dip)   ddi_driver_name(dip), ddi_get_instance(dip)
141*44961713Sgirish #define	DIP_TO_HANDLE(dip) \
142*44961713Sgirish 		((niumx_devstate_t *)DIP_TO_STATE(dip))->niumx_dev_hdl
143*44961713Sgirish #define	DIP_TO_INST(dip)	ddi_get_instance(dip)
144*44961713Sgirish #define	INST_TO_STATE(inst)	ddi_get_soft_state(niumx_state, inst)
145*44961713Sgirish #define	DIP_TO_STATE(dip)	INST_TO_STATE(DIP_TO_INST(dip))
146*44961713Sgirish 
147*44961713Sgirish #ifdef	__cplusplus
148*44961713Sgirish }
149*44961713Sgirish #endif
150*44961713Sgirish 
151*44961713Sgirish #endif	/* _SYS_NMX_H */
152