144961713Sgirish /* 244961713Sgirish * CDDL HEADER START 344961713Sgirish * 444961713Sgirish * The contents of this file are subject to the terms of the 544961713Sgirish * Common Development and Distribution License (the "License"). 644961713Sgirish * You may not use this file except in compliance with the License. 744961713Sgirish * 844961713Sgirish * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 944961713Sgirish * or http://www.opensolaris.org/os/licensing. 1044961713Sgirish * See the License for the specific language governing permissions 1144961713Sgirish * and limitations under the License. 1244961713Sgirish * 1344961713Sgirish * When distributing Covered Code, include this CDDL HEADER in each 1444961713Sgirish * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 1544961713Sgirish * If applicable, add the following below this CDDL HEADER, with the 1644961713Sgirish * fields enclosed by brackets "[]" replaced with your own identifying 1744961713Sgirish * information: Portions Copyright [yyyy] [name of copyright owner] 1844961713Sgirish * 1944961713Sgirish * CDDL HEADER END 2044961713Sgirish */ 2144961713Sgirish /* 228fca0570Sjf * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 2344961713Sgirish * Use is subject to license terms. 2444961713Sgirish */ 2544961713Sgirish 2644961713Sgirish #pragma ident "%Z%%M% %I% %E% SMI" 2744961713Sgirish 2844961713Sgirish /* 2944961713Sgirish * Niagara2 Network Interface Unit (NIU) Nexus Driver 3044961713Sgirish */ 3144961713Sgirish 3244961713Sgirish #include <sys/conf.h> 3344961713Sgirish #include <sys/modctl.h> 3444961713Sgirish #include <sys/ddi_impldefs.h> 3544961713Sgirish #include <sys/ddi_subrdefs.h> 3644961713Sgirish #include <sys/ddi.h> 3744961713Sgirish #include <sys/sunndi.h> 3844961713Sgirish #include <sys/sunddi.h> 3944961713Sgirish #include <sys/open.h> 4044961713Sgirish #include <sys/stat.h> 4144961713Sgirish #include <sys/file.h> 4244961713Sgirish #include <sys/machsystm.h> 4344961713Sgirish #include <sys/hsvc.h> 4444961713Sgirish #include <sys/sdt.h> 4544961713Sgirish #include <sys/hypervisor_api.h> 4644961713Sgirish #include "niumx_var.h" 4744961713Sgirish 488fca0570Sjf static int niumx_fm_init_child(dev_info_t *, dev_info_t *, int, 498fca0570Sjf ddi_iblock_cookie_t *); 5044961713Sgirish static int niumx_intr_ops(dev_info_t *dip, dev_info_t *rdip, 5144961713Sgirish ddi_intr_op_t intr_op, ddi_intr_handle_impl_t *hdlp, void *result); 5244961713Sgirish static int niumx_attach(dev_info_t *devi, ddi_attach_cmd_t cmd); 5344961713Sgirish static int niumx_detach(dev_info_t *devi, ddi_detach_cmd_t cmd); 5444961713Sgirish static int niumx_set_intr(dev_info_t *dip, dev_info_t *rdip, 5544961713Sgirish ddi_intr_handle_impl_t *hdlp, int valid); 5644961713Sgirish static int niumx_add_intr(dev_info_t *dip, dev_info_t *rdip, 5744961713Sgirish ddi_intr_handle_impl_t *hdlp); 5844961713Sgirish static int niumx_rem_intr(dev_info_t *dip, dev_info_t *rdip, 5944961713Sgirish ddi_intr_handle_impl_t *hdlp); 6044961713Sgirish static uint_t niumx_intr_hdlr(void *arg); 6144961713Sgirish static int niumx_map(dev_info_t *dip, dev_info_t *rdip, ddi_map_req_t *mp, 6244961713Sgirish off_t offset, off_t len, caddr_t *addrp); 6344961713Sgirish static int niumx_dma_allochdl(dev_info_t *dip, dev_info_t *rdip, 6444961713Sgirish ddi_dma_attr_t *attrp, 6544961713Sgirish int (*waitfp)(caddr_t), caddr_t arg, ddi_dma_handle_t *handlep); 6644961713Sgirish static int niumx_dma_freehdl(dev_info_t *dip, dev_info_t *rdip, 6744961713Sgirish ddi_dma_handle_t handlep); 6844961713Sgirish static int niumx_dma_bindhdl(dev_info_t *dip, dev_info_t *rdip, 6944961713Sgirish ddi_dma_handle_t handle, ddi_dma_req_t *dmareq, 7044961713Sgirish ddi_dma_cookie_t *cookiep, uint_t *ccountp); 7144961713Sgirish static int niumx_dma_unbindhdl(dev_info_t *dip, dev_info_t *rdip, 7244961713Sgirish ddi_dma_handle_t handle); 7344961713Sgirish static int niumx_ctlops(dev_info_t *dip, dev_info_t *rdip, 7444961713Sgirish ddi_ctl_enum_t op, void *arg, void *result); 7544961713Sgirish 7644961713Sgirish static struct bus_ops niumx_bus_ops = { 7744961713Sgirish BUSO_REV, 7844961713Sgirish niumx_map, 7944961713Sgirish 0, 8044961713Sgirish 0, 8144961713Sgirish 0, 8244961713Sgirish i_ddi_map_fault, 8344961713Sgirish 0, 8444961713Sgirish niumx_dma_allochdl, 8544961713Sgirish niumx_dma_freehdl, 8644961713Sgirish niumx_dma_bindhdl, 8744961713Sgirish niumx_dma_unbindhdl, 8844961713Sgirish 0, 8944961713Sgirish 0, 9044961713Sgirish 0, 9144961713Sgirish niumx_ctlops, 9244961713Sgirish ddi_bus_prop_op, 9344961713Sgirish 0, /* (*bus_get_eventcookie)(); */ 9444961713Sgirish 0, /* (*bus_add_eventcall)(); */ 9544961713Sgirish 0, /* (*bus_remove_eventcall)(); */ 9644961713Sgirish 0, /* (*bus_post_event)(); */ 9744961713Sgirish 0, /* (*bus_intr_ctl)(); */ 9844961713Sgirish 0, /* (*bus_config)(); */ 9944961713Sgirish 0, /* (*bus_unconfig)(); */ 1008fca0570Sjf niumx_fm_init_child, /* (*bus_fm_init)(); */ 10144961713Sgirish 0, /* (*bus_fm_fini)(); */ 10244961713Sgirish 0, /* (*bus_enter)() */ 10344961713Sgirish 0, /* (*bus_exit)() */ 10444961713Sgirish 0, /* (*bus_power)() */ 10544961713Sgirish niumx_intr_ops /* (*bus_intr_op)(); */ 10644961713Sgirish }; 10744961713Sgirish 10844961713Sgirish static struct dev_ops niumx_ops = { 10944961713Sgirish DEVO_REV, /* devo_rev */ 11044961713Sgirish 0, /* refcnt */ 11144961713Sgirish ddi_no_info, /* info */ 11244961713Sgirish nulldev, /* identify */ 11344961713Sgirish 0, /* probe */ 11444961713Sgirish niumx_attach, /* attach */ 11544961713Sgirish niumx_detach, /* detach */ 11644961713Sgirish nulldev, /* reset */ 11744961713Sgirish (struct cb_ops *)0, /* driver operations */ 11844961713Sgirish &niumx_bus_ops, /* bus operations */ 11944961713Sgirish 0 12044961713Sgirish }; 12144961713Sgirish 12244961713Sgirish /* Module linkage information for the kernel. */ 12344961713Sgirish static struct modldrv modldrv = { 12444961713Sgirish &mod_driverops, /* Type of module */ 12544961713Sgirish "NIU Nexus Driver %I%", 12644961713Sgirish &niumx_ops, /* driver ops */ 12744961713Sgirish }; 12844961713Sgirish 12944961713Sgirish static struct modlinkage modlinkage = { 13044961713Sgirish MODREV_1, 13144961713Sgirish (void *)&modldrv, 13244961713Sgirish NULL 13344961713Sgirish }; 13444961713Sgirish 13544961713Sgirish static void *niumx_state; 13644961713Sgirish static niumx_ih_t niumx_ihtable[NIUMX_MAX_INTRS]; 13744961713Sgirish 13844961713Sgirish /* 13944961713Sgirish * forward function declarations: 14044961713Sgirish */ 14144961713Sgirish static void niumx_removechild(dev_info_t *); 14244961713Sgirish static int niumx_initchild(dev_info_t *child); 14344961713Sgirish 14444961713Sgirish int 14544961713Sgirish _init(void) 14644961713Sgirish { 14744961713Sgirish int e; 14844961713Sgirish if ((e = ddi_soft_state_init(&niumx_state, sizeof (niumx_devstate_t), 14944961713Sgirish 1)) == 0 && (e = mod_install(&modlinkage)) != 0) 15044961713Sgirish ddi_soft_state_fini(&niumx_state); 15144961713Sgirish return (e); 15244961713Sgirish } 15344961713Sgirish 15444961713Sgirish int 15544961713Sgirish _fini(void) 15644961713Sgirish { 15744961713Sgirish int e; 15844961713Sgirish if ((e = mod_remove(&modlinkage)) == 0) 15944961713Sgirish ddi_soft_state_fini(&niumx_state); 16044961713Sgirish return (e); 16144961713Sgirish } 16244961713Sgirish 16344961713Sgirish int 16444961713Sgirish _info(struct modinfo *modinfop) 16544961713Sgirish { 16644961713Sgirish return (mod_info(&modlinkage, modinfop)); 16744961713Sgirish } 16844961713Sgirish 169*c165966dSjf 170*c165966dSjf hrtime_t niumx_intr_timeout = 2ull * NANOSEC; /* 2 seconds in nanoseconds */ 171*c165966dSjf 1723266dff7Sjf void 1733266dff7Sjf niumx_intr_dist(void *arg) 1743266dff7Sjf { 1753266dff7Sjf kmutex_t *lock_p = (kmutex_t *)arg; 1763266dff7Sjf int i = NIUMX_RSVD_INTRS; 1773266dff7Sjf niumx_ih_t *ih_p = niumx_ihtable + i; 1783266dff7Sjf 1793266dff7Sjf DBG(DBG_A_INTX, NULL, "niumx_intr_dist entered\n"); 1803266dff7Sjf mutex_enter(lock_p); 1813266dff7Sjf for (; i < NIUMX_MAX_INTRS; i++, ih_p++) { 1823266dff7Sjf sysino_t sysino = ih_p->ih_sysino; 1833266dff7Sjf cpuid_t cpuid; 184*c165966dSjf int intr_state, state; 185*c165966dSjf hrtime_t start; 186*c165966dSjf dev_info_t *dip = ih_p->ih_dip; 1873266dff7Sjf if (!sysino || /* sequence is significant */ 1883266dff7Sjf (hvio_intr_getvalid(sysino, &intr_state) != H_EOK) || 1893266dff7Sjf (intr_state == HV_INTR_NOTVALID) || 1903266dff7Sjf (cpuid = intr_dist_cpuid()) == ih_p->ih_cpuid) 1913266dff7Sjf continue; 1923266dff7Sjf 1933266dff7Sjf (void) hvio_intr_setvalid(sysino, HV_INTR_NOTVALID); 194*c165966dSjf 195*c165966dSjf /* check for pending interrupts, busy wait if so */ 196*c165966dSjf for (start = gethrtime(); !panicstr && 197*c165966dSjf (hvio_intr_getstate(sysino, &state) == H_EOK) && 198*c165966dSjf (state == HV_INTR_DELIVERED_STATE); /* */) { 199*c165966dSjf if (gethrtime() - start > niumx_intr_timeout) { 200*c165966dSjf cmn_err(CE_WARN, "%s%d: niumx_intr_dist: " 201*c165966dSjf "pending interrupt (%x,%lx) timedout\n", 202*c165966dSjf ddi_driver_name(dip), ddi_get_instance(dip), 203*c165966dSjf ih_p->ih_inum, sysino); 204*c165966dSjf (void) hvio_intr_setstate(sysino, 205*c165966dSjf HV_INTR_IDLE_STATE); 206*c165966dSjf break; 207*c165966dSjf } 208*c165966dSjf } 2093266dff7Sjf (void) hvio_intr_settarget(sysino, cpuid); 2103266dff7Sjf (void) hvio_intr_setvalid(sysino, HV_INTR_VALID); 2113266dff7Sjf ih_p->ih_cpuid = cpuid; 2123266dff7Sjf } 2133266dff7Sjf mutex_exit(lock_p); 2143266dff7Sjf } 21544961713Sgirish 21644961713Sgirish /* 2173266dff7Sjf * Hypervisor INTR services information for the NIU nexus driver. 21844961713Sgirish */ 2193266dff7Sjf static uint64_t niumx_intr_min_ver; /* Neg. API minor version */ 22044961713Sgirish static hsvc_info_t niumx_hv_intr = { 22144961713Sgirish HSVC_REV_1, NULL, HSVC_GROUP_INTR, NIUMX_INTR_MAJOR_VER, 22244961713Sgirish NIUMX_INTR_MINOR_VER, "NIUMX" 22344961713Sgirish }; 22444961713Sgirish 22544961713Sgirish static int 22644961713Sgirish niumx_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 22744961713Sgirish { 22844961713Sgirish int instance = ddi_get_instance(dip); 22944961713Sgirish niumx_devstate_t *niumxds_p; /* devstate pointer */ 23044961713Sgirish niu_regspec_t *reg_p; 23144961713Sgirish uint_t reglen; 23244961713Sgirish int ret = DDI_SUCCESS; 23344961713Sgirish 23444961713Sgirish switch (cmd) { 23544961713Sgirish case DDI_ATTACH: 23644961713Sgirish if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 23744961713Sgirish DDI_PROP_DONTPASS, "reg", (int **)®_p, ®len) 23844961713Sgirish != DDI_PROP_SUCCESS) { 23944961713Sgirish DBG(DBG_ATTACH, dip, "reg lookup failed\n"); 24044961713Sgirish ret = DDI_FAILURE; 24144961713Sgirish goto done; 24244961713Sgirish } 24344961713Sgirish 24444961713Sgirish /* 24544961713Sgirish * Allocate and get soft state structure. 24644961713Sgirish */ 24744961713Sgirish if (ddi_soft_state_zalloc(niumx_state, instance) 24844961713Sgirish != DDI_SUCCESS) { 24944961713Sgirish ret = DDI_FAILURE; 25044961713Sgirish goto prop_free; 25144961713Sgirish } 25244961713Sgirish niumxds_p = (niumx_devstate_t *)ddi_get_soft_state(niumx_state, 25344961713Sgirish instance); 25444961713Sgirish niumxds_p->dip = dip; 25544961713Sgirish mutex_init(&niumxds_p->niumx_mutex, NULL, MUTEX_DRIVER, NULL); 25644961713Sgirish 25744961713Sgirish DBG(DBG_ATTACH, dip, "soft state alloc'd instance = %d, " 25844961713Sgirish "niumxds_p = %p\n", instance, niumxds_p); 25944961713Sgirish 26044961713Sgirish /* 2613266dff7Sjf * Negotiate the API version for HV INTR services. 26244961713Sgirish */ 26344961713Sgirish if ((ret = hsvc_register(&niumx_hv_intr, &niumx_intr_min_ver)) 26444961713Sgirish != H_EOK) { 26544961713Sgirish cmn_err(CE_WARN, "%s: cannot negotiate hypervisor services " 26644961713Sgirish "group: 0x%lx major: 0x%lx minor: 0x%lx errno: %d\n", 26744961713Sgirish niumx_hv_intr.hsvc_modname, niumx_hv_intr.hsvc_group, 26844961713Sgirish niumx_hv_intr.hsvc_major, niumx_hv_intr.hsvc_minor, ret); 26944961713Sgirish ret = DDI_FAILURE; 2703266dff7Sjf goto cleanup; 27144961713Sgirish } 27244961713Sgirish 27344961713Sgirish DBG(DBG_ATTACH, dip, "neg. HV API major 0x%lx minor 0x%lx\n", 2743266dff7Sjf niumx_hv_intr.hsvc_major, niumx_intr_min_ver); 27544961713Sgirish 27644961713Sgirish /* hv devhdl: low 28-bit of 1st "reg" entry's addr.hi */ 27744961713Sgirish niumxds_p->niumx_dev_hdl = (devhandle_t)(reg_p->addr_high & 27844961713Sgirish NIUMX_DEVHDLE_MASK); 27944961713Sgirish 2803266dff7Sjf /* add interrupt redistribution callback */ 2813266dff7Sjf intr_dist_add(niumx_intr_dist, &niumxds_p->niumx_mutex); 2823266dff7Sjf 2838fca0570Sjf niumxds_p->niumx_fm_cap = DDI_FM_EREPORT_CAPABLE; 28414ea4bb7Ssd 28514ea4bb7Ssd ddi_fm_init(niumxds_p->dip, &niumxds_p->niumx_fm_cap, 28614ea4bb7Ssd &niumxds_p->niumx_fm_ibc); 28714ea4bb7Ssd 28844961713Sgirish ret = DDI_SUCCESS; 28944961713Sgirish goto prop_free; 29044961713Sgirish cleanup: 29144961713Sgirish mutex_destroy(&niumxds_p->niumx_mutex); 29244961713Sgirish ddi_soft_state_free(niumx_state, ddi_get_instance(dip)); 29344961713Sgirish prop_free: 29444961713Sgirish ddi_prop_free(reg_p); 29544961713Sgirish done: 29644961713Sgirish return (ret); 29744961713Sgirish 29844961713Sgirish case DDI_RESUME: 29944961713Sgirish default: 30044961713Sgirish break; 30144961713Sgirish } 30244961713Sgirish return (ret); 30344961713Sgirish } 30444961713Sgirish 30544961713Sgirish static int 30644961713Sgirish niumx_detach(dev_info_t *dip, ddi_detach_cmd_t cmd) 30744961713Sgirish { 30844961713Sgirish niumx_devstate_t *niumxds_p; 30944961713Sgirish 31044961713Sgirish switch (cmd) { 31144961713Sgirish case DDI_DETACH: 31244961713Sgirish (void) hsvc_unregister(&niumx_hv_intr); 31344961713Sgirish 31444961713Sgirish niumxds_p = (niumx_devstate_t *) 31544961713Sgirish ddi_get_soft_state(niumx_state, ddi_get_instance(dip)); 31644961713Sgirish 3173266dff7Sjf intr_dist_rem(niumx_intr_dist, &niumxds_p->niumx_mutex); 31814ea4bb7Ssd ddi_fm_fini(dip); 31944961713Sgirish mutex_destroy(&niumxds_p->niumx_mutex); 32044961713Sgirish ddi_soft_state_free(niumx_state, ddi_get_instance(dip)); 32144961713Sgirish return (DDI_SUCCESS); 32244961713Sgirish 32344961713Sgirish case DDI_SUSPEND: 32444961713Sgirish default: 32544961713Sgirish break; 32644961713Sgirish } 32744961713Sgirish return (DDI_FAILURE); 32844961713Sgirish } 32944961713Sgirish 3308fca0570Sjf 3318fca0570Sjf /* 3328fca0570Sjf * Function used to initialize FMA for our children nodes. Called 3338fca0570Sjf * through pci busops when child node calls ddi_fm_init. 3348fca0570Sjf */ 3358fca0570Sjf /*ARGSUSED*/ 3368fca0570Sjf int 3378fca0570Sjf niumx_fm_init_child(dev_info_t *dip, dev_info_t *cdip, int cap, 3388fca0570Sjf ddi_iblock_cookie_t *ibc_p) 3398fca0570Sjf { 3408fca0570Sjf niumx_devstate_t *niumxds_p = DIP_TO_STATE(dip); 3418fca0570Sjf 3428fca0570Sjf ASSERT(ibc_p != NULL); 3438fca0570Sjf *ibc_p = niumxds_p->niumx_fm_ibc; 3448fca0570Sjf 3458fca0570Sjf return (niumxds_p->niumx_fm_cap); 3468fca0570Sjf } 3478fca0570Sjf 3488fca0570Sjf 34944961713Sgirish /*ARGSUSED*/ 35044961713Sgirish int 35144961713Sgirish niumx_map(dev_info_t *dip, dev_info_t *rdip, ddi_map_req_t *mp, 35244961713Sgirish off_t offset, off_t len, caddr_t *vaddrp) 35344961713Sgirish { 35444961713Sgirish struct regspec p_regspec; 35544961713Sgirish ddi_map_req_t p_mapreq; 35644961713Sgirish niu_regspec_t *reg_p; 35744961713Sgirish int i, rn = mp->map_obj.rnumber, reglen, rnglen, rngnum, ret; 35844961713Sgirish niumx_ranges_t *rng_p; 35944961713Sgirish 36044961713Sgirish uint32_t reg_begin, rng_begin; 36144961713Sgirish 36244961713Sgirish DBG(DBG_MAP, dip, "%s%d: mapping %s%d reg %d\n", NAMEINST(dip), 36344961713Sgirish NAMEINST(rdip), rn); 36444961713Sgirish 36544961713Sgirish if (ddi_getlongprop(DDI_DEV_T_ANY, rdip, DDI_PROP_DONTPASS, 36644961713Sgirish "reg", (caddr_t)®_p, ®len) != DDI_SUCCESS) 36744961713Sgirish return (DDI_FAILURE); 36844961713Sgirish 36944961713Sgirish if (rn < 0 || (rn >= reglen / sizeof (niu_regspec_t))) { 37044961713Sgirish DBG(DBG_MAP, dip, "rnumber out of range: %d\n", rn); 37144961713Sgirish kmem_free(reg_p, reglen); 37244961713Sgirish return (DDI_ME_RNUMBER_RANGE); 37344961713Sgirish } 37444961713Sgirish 37544961713Sgirish /* build regspec up for parent */ 37644961713Sgirish p_mapreq = *mp; /* dup the whole structure */ 37744961713Sgirish p_mapreq.map_type = DDI_MT_REGSPEC; 37844961713Sgirish p_mapreq.map_obj.rp = &p_regspec; 37944961713Sgirish 38044961713Sgirish if (ddi_getlongprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, "ranges", 38144961713Sgirish (caddr_t)&rng_p, &rnglen) != DDI_SUCCESS) { 38244961713Sgirish DBG(DBG_MAP, dip, "%s%d: no ranges property\n", 38344961713Sgirish ddi_driver_name(dip), ddi_get_instance(dip)); 38444961713Sgirish kmem_free(reg_p, reglen); 38544961713Sgirish return (DDI_FAILURE); 38644961713Sgirish } 38744961713Sgirish 38844961713Sgirish /* locate matching ranges record */ 38944961713Sgirish rngnum = rnglen / sizeof (niumx_ranges_t); 39044961713Sgirish for (i = 0, reg_p += rn; i < rngnum; rng_p++, i++) { 39144961713Sgirish if (reg_p->addr_high == rng_p->child_hi) 39244961713Sgirish break; 39344961713Sgirish } 39444961713Sgirish 39544961713Sgirish if (i >= rngnum) { 39644961713Sgirish DBG(DBG_MAP, dip, "ranges record for reg[%d] not found.\n", rn); 39744961713Sgirish ret = DDI_ME_REGSPEC_RANGE; 39844961713Sgirish goto err; 39944961713Sgirish } 40044961713Sgirish 40144961713Sgirish /* 40244961713Sgirish * validate request has matching bus type and within 4G 40344961713Sgirish * limit by comparing addr.hi of "ranges" and child "reg". 40444961713Sgirish */ 40544961713Sgirish 40644961713Sgirish ASSERT(reg_p->size_high == 0); 40744961713Sgirish 40844961713Sgirish rng_begin = rng_p->child_lo; 40944961713Sgirish reg_begin = reg_p->addr_low; 41044961713Sgirish /* check to verify reg bounds are within rng bounds */ 41144961713Sgirish if (reg_begin < rng_begin || (reg_begin + (reg_p->size_low - 1)) > 41244961713Sgirish (rng_begin + (rng_p->size_lo - 1))) { 41344961713Sgirish DBG(DBG_MAP, dip, "size out of range for reg[%d].\n", rn); 41444961713Sgirish ret = DDI_ME_REGSPEC_RANGE; 41544961713Sgirish goto err; 41644961713Sgirish } 41744961713Sgirish 41844961713Sgirish p_regspec.regspec_bustype = rng_p->parent_hi; 41944961713Sgirish p_regspec.regspec_addr = reg_begin - rng_begin + rng_p->parent_lo; 42044961713Sgirish p_regspec.regspec_size = reg_p->size_low; 42144961713Sgirish DBG(DBG_MAP, dip, "regspec:bus,addr,size = (%x,%x,%x)\n", 42244961713Sgirish p_regspec.regspec_bustype, p_regspec.regspec_addr, 42344961713Sgirish p_regspec.regspec_size); 42444961713Sgirish ret = ddi_map(dip, &p_mapreq, 0, 0, vaddrp); 42544961713Sgirish DBG(DBG_MAP, dip, "niumx_map: ret %d.\n", ret); 42644961713Sgirish err: 42744961713Sgirish kmem_free(rng_p - i, rnglen); 42844961713Sgirish kmem_free(reg_p - rn, reglen); 42944961713Sgirish return (ret); 43044961713Sgirish } 43144961713Sgirish 43244961713Sgirish /* 43344961713Sgirish * niumx_ctlops 43444961713Sgirish */ 43544961713Sgirish int 43644961713Sgirish niumx_ctlops(dev_info_t *dip, dev_info_t *rdip, 43744961713Sgirish ddi_ctl_enum_t ctlop, void *arg, void *result) 43844961713Sgirish { 43944961713Sgirish niu_regspec_t *reg_p; 44044961713Sgirish int reglen, totreg; 44144961713Sgirish 44244961713Sgirish DBG(DBG_CTLOPS, dip, "niumx_ctlops ctlop=%d.\n", ctlop); 44344961713Sgirish if (rdip == (dev_info_t *)0) 44444961713Sgirish return (DDI_FAILURE); 44544961713Sgirish 44644961713Sgirish switch (ctlop) { 44744961713Sgirish case DDI_CTLOPS_REPORTDEV: 44844961713Sgirish cmn_err(CE_NOTE, "device: %s@%s, %s%d\n", 44944961713Sgirish ddi_node_name(rdip), ddi_get_name_addr(rdip), 45044961713Sgirish NAMEINST(rdip)); 45144961713Sgirish return (DDI_SUCCESS); 45244961713Sgirish 45344961713Sgirish case DDI_CTLOPS_INITCHILD: 45444961713Sgirish return (niumx_initchild((dev_info_t *)arg)); 45544961713Sgirish 45644961713Sgirish case DDI_CTLOPS_UNINITCHILD: 45744961713Sgirish niumx_removechild((dev_info_t *)arg); 45844961713Sgirish return (DDI_SUCCESS); 45944961713Sgirish 46044961713Sgirish case DDI_CTLOPS_REGSIZE: 46144961713Sgirish case DDI_CTLOPS_NREGS: 46244961713Sgirish /* fall through */ 46344961713Sgirish break; 46444961713Sgirish default: 46544961713Sgirish DBG(DBG_CTLOPS, dip, "just pass to ddi_cltops.\n"); 46644961713Sgirish return (ddi_ctlops(dip, rdip, ctlop, arg, result)); 46744961713Sgirish } 46844961713Sgirish 46944961713Sgirish /* REGSIZE/NREGS */ 47044961713Sgirish 47144961713Sgirish *(int *)result = 0; 47244961713Sgirish 47344961713Sgirish if (ddi_getlongprop(DDI_DEV_T_NONE, rdip, DDI_PROP_DONTPASS | 47444961713Sgirish DDI_PROP_CANSLEEP, "reg", (caddr_t)®_p, ®len) 47544961713Sgirish != DDI_SUCCESS) 47644961713Sgirish return (DDI_FAILURE); 47744961713Sgirish 47844961713Sgirish totreg = reglen / sizeof (niu_regspec_t); 47944961713Sgirish if (ctlop == DDI_CTLOPS_NREGS) { 48044961713Sgirish DBG(DBG_CTLOPS, (dev_info_t *)dip, "niumx_ctlops NREGS=%d.\n", 48144961713Sgirish totreg); 48244961713Sgirish *(int *)result = totreg; 48344961713Sgirish } else if (ctlop == DDI_CTLOPS_REGSIZE) { 48444961713Sgirish int rn; 48544961713Sgirish rn = *(int *)arg; 48644961713Sgirish if (rn >= totreg) { 48744961713Sgirish kmem_free(reg_p, reglen); 48844961713Sgirish return (DDI_FAILURE); 48944961713Sgirish } 49044961713Sgirish *(off_t *)result = (reg_p + rn)->size_low; 49144961713Sgirish DBG(DBG_CTLOPS, (dev_info_t *)dip, "rn = %d, REGSIZE=%x.\n", 49244961713Sgirish rn, *(off_t *)result); 49344961713Sgirish } 49444961713Sgirish 49544961713Sgirish kmem_free(reg_p, reglen); 49644961713Sgirish return (DDI_SUCCESS); 49744961713Sgirish } 49844961713Sgirish 49944961713Sgirish static int 50044961713Sgirish niumx_initchild(dev_info_t *child) 50144961713Sgirish { 50244961713Sgirish char name[MAXNAMELEN]; 50344961713Sgirish niu_regspec_t *r; 50444961713Sgirish uint_t n; 50544961713Sgirish 50644961713Sgirish if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, child, DDI_PROP_DONTPASS, 50744961713Sgirish "reg", (int **)&r, &n) != DDI_SUCCESS) { 50844961713Sgirish return (DDI_FAILURE); 50944961713Sgirish } 51044961713Sgirish (void) snprintf(name, MAXNAMELEN, "%x", (r[0].addr_high & 51144961713Sgirish NIUMX_FUNC_NUM_MASK)); 51244961713Sgirish ddi_prop_free(r); 51344961713Sgirish ddi_set_name_addr(child, name); 51444961713Sgirish return (DDI_SUCCESS); 51544961713Sgirish } 51644961713Sgirish 51744961713Sgirish static void 51844961713Sgirish niumx_removechild(dev_info_t *dip) 51944961713Sgirish { 52044961713Sgirish ddi_set_name_addr(dip, NULL); 52144961713Sgirish ddi_remove_minor_node(dip, NULL); 52244961713Sgirish impl_rem_dev_props(dip); 52344961713Sgirish } 52444961713Sgirish 52544961713Sgirish 52644961713Sgirish 52744961713Sgirish /* 52844961713Sgirish * bus dma alloc handle entry point: 52944961713Sgirish */ 53044961713Sgirish /*ARGSUSED*/ 53144961713Sgirish int 53244961713Sgirish niumx_dma_allochdl(dev_info_t *dip, dev_info_t *rdip, ddi_dma_attr_t *attrp, 53344961713Sgirish int (*waitfp)(caddr_t), caddr_t arg, ddi_dma_handle_t *handlep) 53444961713Sgirish { 53544961713Sgirish ddi_dma_impl_t *mp; 53644961713Sgirish int sleep = (waitfp == DDI_DMA_SLEEP) ? KM_SLEEP : KM_NOSLEEP; 53744961713Sgirish 53844961713Sgirish DBG(DBG_DMA_ALLOCH, dip, "rdip=%s%d\n", NAMEINST(rdip)); 53944961713Sgirish 54044961713Sgirish if (attrp->dma_attr_version != DMA_ATTR_V0) { 54144961713Sgirish DBG(DBG_DMA_ALLOCH, (dev_info_t *)dip, "DDI_DMA_BADATTR\n"); 54244961713Sgirish return (DDI_DMA_BADATTR); 54344961713Sgirish } 54444961713Sgirish 54544961713Sgirish /* Caution: we don't use zalloc to enhance performance! */ 54644961713Sgirish if ((mp = kmem_alloc(sizeof (ddi_dma_impl_t), sleep)) == 0) { 54744961713Sgirish DBG(DBG_DMA_ALLOCH, dip, "can't alloc ddi_dma_impl_t\n"); 54844961713Sgirish return (DDI_FAILURE); 54944961713Sgirish } 55044961713Sgirish mp->dmai_rdip = rdip; 55144961713Sgirish mp->dmai_pfnlst = NULL; 55244961713Sgirish mp->dmai_cookie = NULL; 55344961713Sgirish mp->dmai_fault = 0; 55444961713Sgirish mp->dmai_fault_check = NULL; 55544961713Sgirish mp->dmai_fault_notify = NULL; 55644961713Sgirish 55744961713Sgirish mp->dmai_attr = *attrp; /* set requestors attr info */ 55844961713Sgirish 55944961713Sgirish DBG(DBG_DMA_ALLOCH, dip, "mp=%p\n", mp); 56044961713Sgirish 56144961713Sgirish *handlep = (ddi_dma_handle_t)mp; 56244961713Sgirish return (DDI_SUCCESS); 56344961713Sgirish } 56444961713Sgirish 56544961713Sgirish 56644961713Sgirish /* 56744961713Sgirish * bus dma free handle entry point: 56844961713Sgirish */ 56944961713Sgirish /*ARGSUSED*/ 57044961713Sgirish int 57144961713Sgirish niumx_dma_freehdl(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle) 57244961713Sgirish { 57344961713Sgirish ddi_dma_impl_t *mp = (ddi_dma_impl_t *)handle; 57444961713Sgirish 57544961713Sgirish if (mp->dmai_cookie) 57644961713Sgirish kmem_free(mp->dmai_cookie, sizeof (ddi_dma_cookie_t)); 57744961713Sgirish kmem_free(mp, sizeof (ddi_dma_impl_t)); 57844961713Sgirish 57944961713Sgirish return (DDI_SUCCESS); 58044961713Sgirish } 58144961713Sgirish 58244961713Sgirish 58344961713Sgirish /* 58444961713Sgirish * bus dma bind handle entry point: 58544961713Sgirish * 58644961713Sgirish * check/enforce DMA type, setup pfn0 and some other key pieces 58744961713Sgirish * of this dma request. 58844961713Sgirish * Note: this only works with DMA_OTYP_VADDR, and makes use of the known 58944961713Sgirish * fact that only contiguous memory blocks will be passed in. 59044961713Sgirish * Therefore only one cookie will ever be returned. 59144961713Sgirish * 59244961713Sgirish * return values: 59344961713Sgirish * DDI_DMA_NOMAPPING - can't get valid pfn0, or bad dma type 59444961713Sgirish * DDI_DMA_NORESOURCES 59544961713Sgirish * DDI_SUCCESS 59644961713Sgirish * 59744961713Sgirish * dma handle members affected (set on exit): 59844961713Sgirish * mp->dmai_object - dmareq->dmar_object 59944961713Sgirish * mp->dmai_rflags - dmareq->dmar_flags 60044961713Sgirish * mp->dmai_pfn0 - 1st page pfn (if va/size pair and not shadow) 60144961713Sgirish * mp->dmai_roffset - initialized to starting page offset 60244961713Sgirish * mp->dmai_size - # of total pages of entire object 60344961713Sgirish * mp->dmai_cookie - new cookie alloc'd 60444961713Sgirish */ 60544961713Sgirish /*ARGSUSED*/ 60644961713Sgirish int 60744961713Sgirish niumx_dma_bindhdl(dev_info_t *dip, dev_info_t *rdip, 60844961713Sgirish ddi_dma_handle_t handle, ddi_dma_req_t *dmareq, 60944961713Sgirish ddi_dma_cookie_t *cookiep, uint_t *ccountp) 61044961713Sgirish { 61144961713Sgirish int (*waitfp)(caddr_t) = dmareq->dmar_fp; 61244961713Sgirish ddi_dma_impl_t *mp = (ddi_dma_impl_t *)handle; 61344961713Sgirish ddi_dma_obj_t *dobj_p = &dmareq->dmar_object; 61444961713Sgirish uint32_t offset; 61544961713Sgirish pfn_t pfn0; 61644961713Sgirish int ret; 61744961713Sgirish 61844961713Sgirish DBG(DBG_DMA_BINDH, dip, "rdip=%s%d mp=%p dmareq=%p\n", NAMEINST(rdip), 61944961713Sgirish mp, dmareq); 62044961713Sgirish 62144961713Sgirish /* first check dma type */ 62244961713Sgirish mp->dmai_rflags = dmareq->dmar_flags & DMP_DDIFLAGS | DMP_NOSYNC; 62344961713Sgirish switch (dobj_p->dmao_type) { 62444961713Sgirish case DMA_OTYP_VADDR: { 62544961713Sgirish caddr_t vaddr = dobj_p->dmao_obj.virt_obj.v_addr; 62644961713Sgirish struct as *as_p = dobj_p->dmao_obj.virt_obj.v_as; 62744961713Sgirish struct hat *hat_p = as_p ? as_p->a_hat : kas.a_hat; 62844961713Sgirish offset = (ulong_t)vaddr & NIUMX_PAGE_OFFSET; 62944961713Sgirish pfn0 = hat_getpfnum(hat_p, vaddr); 63044961713Sgirish } 63144961713Sgirish break; 63244961713Sgirish 63344961713Sgirish case DMA_OTYP_BUFVADDR: 63444961713Sgirish case DMA_OTYP_PAGES: 63544961713Sgirish case DMA_OTYP_PADDR: 63644961713Sgirish default: 63744961713Sgirish cmn_err(CE_WARN, "%s%d requested unsupported dma type %x", 63844961713Sgirish NAMEINST(mp->dmai_rdip), dobj_p->dmao_type); 63944961713Sgirish ret = DDI_DMA_NOMAPPING; 64044961713Sgirish goto err; 64144961713Sgirish } 64244961713Sgirish if (pfn0 == PFN_INVALID) { 64344961713Sgirish cmn_err(CE_WARN, "%s%d: invalid pfn0 for DMA object %p", 64444961713Sgirish NAMEINST(dip), (void *)dobj_p); 64544961713Sgirish ret = DDI_DMA_NOMAPPING; 64644961713Sgirish goto err; 64744961713Sgirish } 64844961713Sgirish mp->dmai_object = *dobj_p; /* whole object */ 64944961713Sgirish mp->dmai_pfn0 = (void *)pfn0; /* cache pfn0 */ 65044961713Sgirish mp->dmai_roffset = offset; /* pg0 offset */ 65144961713Sgirish mp->dmai_mapping = mp->dmai_roffset | NIUMX_PTOB(pfn0); 65244961713Sgirish mp->dmai_size = mp->dmai_object.dmao_size; 65344961713Sgirish 65444961713Sgirish DBG(DBG_DMA_BINDH, dip, "check pfn: mp=%p pfn0=%x\n", 65544961713Sgirish mp, mp->dmai_pfn0); 65644961713Sgirish if (!(mp->dmai_cookie = kmem_zalloc(sizeof (ddi_dma_cookie_t), 65744961713Sgirish waitfp == DDI_DMA_SLEEP ? KM_SLEEP : KM_NOSLEEP))) { 65844961713Sgirish ret = DDI_DMA_NORESOURCES; 65944961713Sgirish goto err; 66044961713Sgirish } 66144961713Sgirish mp->dmai_cookie->dmac_laddress = mp->dmai_mapping; 66244961713Sgirish mp->dmai_cookie->dmac_size = mp->dmai_size; 66344961713Sgirish *ccountp = 1; 66444961713Sgirish *cookiep = *mp->dmai_cookie; 66544961713Sgirish DBG(DBG_DMA_BINDH, dip, "cookie %" PRIx64 "+%x, count=%d\n", 66644961713Sgirish cookiep->dmac_address, cookiep->dmac_size, *ccountp); 66744961713Sgirish return (DDI_DMA_MAPPED); 66844961713Sgirish 66944961713Sgirish err: 67044961713Sgirish DBG(DBG_DMA_BINDH, (dev_info_t *)dip, 67144961713Sgirish "niumx_dma_bindhdl error ret=%d\n", ret); 67244961713Sgirish return (ret); 67344961713Sgirish } 67444961713Sgirish 67544961713Sgirish /* 67644961713Sgirish * bus dma unbind handle entry point: 67744961713Sgirish */ 67844961713Sgirish /*ARGSUSED*/ 67944961713Sgirish int 68044961713Sgirish niumx_dma_unbindhdl(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle) 68144961713Sgirish { 68244961713Sgirish ddi_dma_impl_t *mp = (ddi_dma_impl_t *)handle; 68344961713Sgirish 68444961713Sgirish DBG(DBG_DMA_UNBINDH, dip, "rdip=%s%d, mp=%p\n", 68544961713Sgirish ddi_driver_name(rdip), ddi_get_instance(rdip), handle); 68644961713Sgirish if (mp->dmai_cookie) { 68744961713Sgirish kmem_free(mp->dmai_cookie, sizeof (ddi_dma_cookie_t)); 68844961713Sgirish mp->dmai_cookie = NULL; 68944961713Sgirish } 69044961713Sgirish 69144961713Sgirish return (DDI_SUCCESS); 69244961713Sgirish } 69344961713Sgirish 69444961713Sgirish /*ARGSUSED*/ 69544961713Sgirish int 69644961713Sgirish niumx_intr_ops(dev_info_t *dip, dev_info_t *rdip, ddi_intr_op_t intr_op, 69744961713Sgirish ddi_intr_handle_impl_t *hdlp, void *result) 69844961713Sgirish { 69944961713Sgirish 70044961713Sgirish int ret = DDI_SUCCESS; 70144961713Sgirish 70244961713Sgirish DBG(DBG_INTROPS, dip, "niumx_intr_ops: dip=%p rdip=%p intr_op=%x " 70344961713Sgirish "handle=%p\n", dip, rdip, intr_op, hdlp); 70444961713Sgirish 70544961713Sgirish switch (intr_op) { 70644961713Sgirish 70744961713Sgirish case DDI_INTROP_SUPPORTED_TYPES: 70844961713Sgirish *(int *)result = DDI_INTR_TYPE_FIXED; 70944961713Sgirish break; 71044961713Sgirish case DDI_INTROP_GETCAP: 71144961713Sgirish *(int *)result = DDI_INTR_FLAG_LEVEL; 71244961713Sgirish break; 71344961713Sgirish case DDI_INTROP_SETCAP: 71444961713Sgirish ret = DDI_ENOTSUP; 71544961713Sgirish break; 71644961713Sgirish case DDI_INTROP_ALLOC: 71744961713Sgirish /* scratch1 = count, # of intrs from DDI framework */ 71844961713Sgirish *(int *)result = hdlp->ih_scratch1; 71944961713Sgirish break; 72044961713Sgirish case DDI_INTROP_FREE: 72144961713Sgirish /* Do we need to do anything here? */ 72244961713Sgirish break; 72344961713Sgirish case DDI_INTROP_GETPRI: 72444961713Sgirish *(int *)result = NIUMX_DEFAULT_PIL; 72544961713Sgirish break; 72644961713Sgirish case DDI_INTROP_SETPRI: 72744961713Sgirish ret = DDI_ENOTSUP; 72844961713Sgirish break; 72944961713Sgirish case DDI_INTROP_ADDISR: 73044961713Sgirish ret = niumx_add_intr(dip, rdip, hdlp); 73144961713Sgirish break; 73244961713Sgirish case DDI_INTROP_REMISR: 73344961713Sgirish ret = niumx_rem_intr(dip, rdip, hdlp); 73444961713Sgirish break; 73544961713Sgirish case DDI_INTROP_ENABLE: 73644961713Sgirish ret = niumx_set_intr(dip, rdip, hdlp, HV_INTR_VALID); 73744961713Sgirish break; 73844961713Sgirish case DDI_INTROP_DISABLE: 73944961713Sgirish ret = niumx_set_intr(dip, rdip, hdlp, HV_INTR_NOTVALID); 74044961713Sgirish break; 74144961713Sgirish case DDI_INTROP_SETMASK: 74244961713Sgirish ret = DDI_ENOTSUP; 74344961713Sgirish break; 74444961713Sgirish case DDI_INTROP_CLRMASK: 74544961713Sgirish ret = DDI_ENOTSUP; 74644961713Sgirish break; 74744961713Sgirish case DDI_INTROP_GETPENDING: 74844961713Sgirish ret = DDI_ENOTSUP; 74944961713Sgirish break; 75044961713Sgirish case DDI_INTROP_NINTRS: 75144961713Sgirish case DDI_INTROP_NAVAIL: { 75244961713Sgirish devino_t *inos_p; 75344961713Sgirish int inoslen; 75444961713Sgirish if (ddi_getlongprop(DDI_DEV_T_ANY, rdip, DDI_PROP_DONTPASS, 75544961713Sgirish "interrupts", (caddr_t)&inos_p, &inoslen) 75644961713Sgirish != DDI_SUCCESS) { 75744961713Sgirish ret = DDI_FAILURE; 75844961713Sgirish break; 75944961713Sgirish } 76044961713Sgirish *(int *)result = inoslen / sizeof (uint32_t); 76144961713Sgirish kmem_free(inos_p, inoslen); 76244961713Sgirish } 76344961713Sgirish break; 76444961713Sgirish default: 76544961713Sgirish ret = DDI_ENOTSUP; 76644961713Sgirish break; 76744961713Sgirish } 76844961713Sgirish 76944961713Sgirish DBG(DBG_INTROPS, dip, "niumx_intr_ops: ret=%d\n", ret); 77044961713Sgirish return (ret); 77144961713Sgirish } 77244961713Sgirish 77344961713Sgirish int 77444961713Sgirish niumx_set_intr(dev_info_t *dip, dev_info_t *rdip, 77544961713Sgirish ddi_intr_handle_impl_t *hdlp, int valid) 77644961713Sgirish { 77744961713Sgirish niumx_ih_t *ih_p; 77844961713Sgirish devino_t *inos_p; 77944961713Sgirish int inoslen, ret = DDI_SUCCESS; 78044961713Sgirish uint64_t hvret; 78144961713Sgirish 78244961713Sgirish ASSERT(hdlp->ih_inum < NIUMX_MAX_INTRS); 78344961713Sgirish 78444961713Sgirish /* find the appropriate slot from the fixed table */ 78544961713Sgirish if (ddi_getlongprop(DDI_DEV_T_ANY, rdip, DDI_PROP_DONTPASS, 78644961713Sgirish "interrupts", (caddr_t)&inos_p, &inoslen) != DDI_SUCCESS) { 78744961713Sgirish ret = DDI_FAILURE; 78844961713Sgirish goto fail; 78944961713Sgirish } 79044961713Sgirish ih_p = niumx_ihtable + inos_p[hdlp->ih_inum]; 7918fca0570Sjf DBG(DBG_A_INTX, dip, "niumx_set_intr: rdip=%s%d, valid=%d %s (%x,%x)\n", 7928fca0570Sjf NAMEINST(rdip), valid, valid ? "enabling" : "disabling", 7938fca0570Sjf ih_p->ih_inum, ih_p->ih_sysino); 79444961713Sgirish 795cb343a2eSspeer if (valid == HV_INTR_VALID) 796cb343a2eSspeer (void) hvio_intr_setstate(ih_p->ih_sysino, HV_INTR_IDLE_STATE); 79744961713Sgirish if ((hvret = hvio_intr_setvalid(ih_p->ih_sysino, valid)) 79844961713Sgirish != H_EOK) { 79944961713Sgirish DBG(DBG_A_INTX, dip, "hvio_intr_setvalid failed, ret 0x%x\n", 80044961713Sgirish hvret); 80144961713Sgirish ret = DDI_FAILURE; 80244961713Sgirish } 80344961713Sgirish kmem_free(inos_p, inoslen); 80444961713Sgirish fail: 80544961713Sgirish return (ret); 80644961713Sgirish } 80744961713Sgirish 80844961713Sgirish 80944961713Sgirish 81044961713Sgirish /* 81144961713Sgirish * niumx_add_intr: 81244961713Sgirish * 81344961713Sgirish * This is the leaf/nexus/HV mapping, now read from "interrupts": 81444961713Sgirish * 81544961713Sgirish * we have a range of 64 to work with: 81644961713Sgirish * [0-15] - reserved 81744961713Sgirish * [16] - mac0 81844961713Sgirish * [17] - MIF 81944961713Sgirish * [18] - SYSERR 82044961713Sgirish * [19-26] - func0 Rx (qty. 8) 82144961713Sgirish * [27-34] - func0 Tx (qty. 8) 82244961713Sgirish * [35] - mac1 82344961713Sgirish * [36-43] - func1 Rx (qty. 8) 82444961713Sgirish * [44-51] - func1 Tx (qty. 8) 82544961713Sgirish */ 82644961713Sgirish int 82744961713Sgirish niumx_add_intr(dev_info_t *dip, dev_info_t *rdip, 82844961713Sgirish ddi_intr_handle_impl_t *hdlp) 82944961713Sgirish { 83044961713Sgirish niumx_ih_t *ih_p; 83144961713Sgirish int inoslen, ret = DDI_SUCCESS; 83244961713Sgirish uint64_t hvret; 8338fca0570Sjf devino_t *inos_p, ino; /* INO numbers, from "interrupts" prop */ 83444961713Sgirish sysino_t sysino; 83544961713Sgirish 83644961713Sgirish /* get new ino */ 83744961713Sgirish if (hdlp->ih_inum >= NIUMX_MAX_INTRS) { 83844961713Sgirish DBG(DBG_INTR, dip, "error: inum %d out of range\n", 83944961713Sgirish hdlp->ih_inum); 84044961713Sgirish ret = DDI_FAILURE; 84144961713Sgirish goto done; 84244961713Sgirish } 84344961713Sgirish if (ddi_getlongprop(DDI_DEV_T_ANY, rdip, DDI_PROP_DONTPASS, 84444961713Sgirish "interrupts", (caddr_t)&inos_p, &inoslen) != DDI_SUCCESS) { 84544961713Sgirish ret = DDI_FAILURE; 84644961713Sgirish goto done; 84744961713Sgirish } 84844961713Sgirish ih_p = niumx_ihtable + inos_p[hdlp->ih_inum]; 8498fca0570Sjf ino = inos_p[hdlp->ih_inum]; 85044961713Sgirish kmem_free(inos_p, inoslen); 8518fca0570Sjf if ((hvret = hvio_intr_devino_to_sysino(DIP_TO_HANDLE(dip), ino, 8528fca0570Sjf &sysino)) != H_EOK) { 85344961713Sgirish DBG(DBG_INTR, dip, "hvio_intr_devino_to_sysino failed, " 85444961713Sgirish "ret 0x%x\n", hvret); 85544961713Sgirish ret = DDI_FAILURE; 85644961713Sgirish goto done; 85744961713Sgirish } 85844961713Sgirish ih_p->ih_sysino = sysino; 85944961713Sgirish ih_p->ih_dip = dip; 86044961713Sgirish ih_p->ih_inum = hdlp->ih_inum; 86144961713Sgirish ih_p->ih_hdlr = hdlp->ih_cb_func; 86244961713Sgirish ih_p->ih_arg1 = hdlp->ih_cb_arg1; 86344961713Sgirish ih_p->ih_arg2 = hdlp->ih_cb_arg2; 86444961713Sgirish 86544961713Sgirish DBG(DBG_A_INTX, dip, "niumx_add_intr: rdip=%s%d inum=0x%x " 86644961713Sgirish "handler=%p arg1=%p arg2=%p, new ih_p = %p\n", NAMEINST(rdip), 86744961713Sgirish hdlp->ih_inum, hdlp->ih_cb_func, hdlp->ih_cb_arg1, 86844961713Sgirish hdlp->ih_cb_arg2, ih_p); 86944961713Sgirish 87044961713Sgirish if (hdlp->ih_pri == 0) 87144961713Sgirish hdlp->ih_pri = NIUMX_DEFAULT_PIL; 87244961713Sgirish 87344961713Sgirish /* Save sysino value in hdlp */ 87444961713Sgirish hdlp->ih_vector = ih_p->ih_sysino; 87544961713Sgirish 87644961713Sgirish /* swap in our handler & arg */ 87744961713Sgirish DDI_INTR_ASSIGN_HDLR_N_ARGS(hdlp, (ddi_intr_handler_t *)niumx_intr_hdlr, 87844961713Sgirish (void *)ih_p, NULL); 87944961713Sgirish 8808fca0570Sjf DBG(DBG_A_INTX, dip, "for ino %x adding (%x,%x)\n", ino, ih_p->ih_inum, 8818fca0570Sjf ih_p->ih_sysino); 88244961713Sgirish ret = i_ddi_add_ivintr(hdlp); 88344961713Sgirish 88444961713Sgirish /* Restore orig. interrupt handler & args in handle. */ 88544961713Sgirish DDI_INTR_ASSIGN_HDLR_N_ARGS(hdlp, ih_p->ih_hdlr, ih_p->ih_arg1, 88644961713Sgirish ih_p->ih_arg2); 88744961713Sgirish 88844961713Sgirish if (ret != DDI_SUCCESS) { 88944961713Sgirish DBG(DBG_A_INTX, dip, "i_ddi_add_ivintr error ret=%x\n", ret); 89044961713Sgirish goto done; 89144961713Sgirish } 89244961713Sgirish 89344961713Sgirish /* select cpu, saving it for removal */ 89444961713Sgirish ih_p->ih_cpuid = intr_dist_cpuid(); 89544961713Sgirish 89644961713Sgirish if ((hvret = hvio_intr_settarget(ih_p->ih_sysino, ih_p->ih_cpuid)) 89744961713Sgirish != H_EOK) { 89844961713Sgirish DBG(DBG_A_INTX, dip, "hvio_intr_settarget failed, ret 0x%x\n", 89944961713Sgirish hvret); 90044961713Sgirish ret = DDI_FAILURE; 90144961713Sgirish } 90244961713Sgirish done: 90344961713Sgirish DBG(DBG_A_INTX, dip, "done, ret = %d, ih_p 0x%p, hdlp 0x%p\n", ih_p, 90444961713Sgirish hdlp, ret); 90544961713Sgirish return (ret); 90644961713Sgirish } 90744961713Sgirish 90844961713Sgirish /* 90944961713Sgirish * niumx_rem_intr: 91044961713Sgirish * 91144961713Sgirish * This function is called to unregister interrupts. 91244961713Sgirish */ 91344961713Sgirish int 91444961713Sgirish niumx_rem_intr(dev_info_t *dip, dev_info_t *rdip, 91544961713Sgirish ddi_intr_handle_impl_t *hdlp) 91644961713Sgirish { 91744961713Sgirish niumx_ih_t *ih_p; 91844961713Sgirish devino_t *inos_p; 919*c165966dSjf int inoslen, ret = DDI_SUCCESS, state; 920*c165966dSjf hrtime_t start; 921*c165966dSjf sysino_t sysino; 92244961713Sgirish 92344961713Sgirish ASSERT(hdlp->ih_inum < NIUMX_MAX_INTRS); 92444961713Sgirish 92544961713Sgirish /* find the appropriate slot from the fixed table */ 92644961713Sgirish if (ddi_getlongprop(DDI_DEV_T_ANY, rdip, DDI_PROP_DONTPASS, 92744961713Sgirish "interrupts", (caddr_t)&inos_p, &inoslen) != DDI_SUCCESS) { 92844961713Sgirish ret = DDI_FAILURE; 92944961713Sgirish goto fail1; 93044961713Sgirish } 93144961713Sgirish ih_p = niumx_ihtable + inos_p[hdlp->ih_inum]; 932*c165966dSjf sysino = ih_p->ih_sysino; 933*c165966dSjf DBG(DBG_R_INTX, dip, "removing (%x,%x)\n", ih_p->ih_inum, sysino); 934*c165966dSjf 935*c165966dSjf (void) hvio_intr_setvalid(sysino, HV_INTR_NOTVALID); 936*c165966dSjf 937*c165966dSjf /* check for pending interrupts, busy wait if so */ 938*c165966dSjf for (start = gethrtime(); !panicstr && 939*c165966dSjf (hvio_intr_getstate(sysino, &state) == H_EOK) && 940*c165966dSjf (state == HV_INTR_DELIVERED_STATE); /* */) { 941*c165966dSjf if (gethrtime() - start > niumx_intr_timeout) { 942*c165966dSjf cmn_err(CE_WARN, "%s%d: niumx_intr_dist: " 943*c165966dSjf "pending interrupt (%x,%lx) timedout\n", 944*c165966dSjf ddi_driver_name(dip), ddi_get_instance(dip), 945*c165966dSjf ih_p->ih_inum, sysino); 946*c165966dSjf ret = DDI_FAILURE; 947*c165966dSjf goto fail2; 948*c165966dSjf } 94944961713Sgirish } 95044961713Sgirish 951*c165966dSjf hdlp->ih_vector = (uint32_t)sysino; 95244961713Sgirish if (hdlp->ih_vector != NULL) i_ddi_rem_ivintr(hdlp); 95344961713Sgirish 95444961713Sgirish fail2: 95544961713Sgirish kmem_free(inos_p, inoslen); 95644961713Sgirish fail1: 95744961713Sgirish return (ret); 95844961713Sgirish } 95944961713Sgirish 96044961713Sgirish /* 96144961713Sgirish * niumx_intr_hdlr (our interrupt handler) 96244961713Sgirish */ 96344961713Sgirish uint_t 96444961713Sgirish niumx_intr_hdlr(void *arg) 96544961713Sgirish { 96644961713Sgirish niumx_ih_t *ih_p = (niumx_ih_t *)arg; 96744961713Sgirish uint_t r; 96844961713Sgirish 96944961713Sgirish DTRACE_PROBE4(interrupt__start, dev_info_t, ih_p->ih_dip, void *, 97044961713Sgirish ih_p->ih_hdlr, caddr_t, ih_p->ih_arg1, caddr_t, ih_p->ih_arg2); 97144961713Sgirish 97244961713Sgirish r = (*ih_p->ih_hdlr)(ih_p->ih_arg1, ih_p->ih_arg2); 97344961713Sgirish 97444961713Sgirish DTRACE_PROBE4(interrupt__complete, dev_info_t, ih_p->ih_dip, void *, 97544961713Sgirish ih_p->ih_hdlr, caddr_t, ih_p->ih_arg1, int, r); 976cb343a2eSspeer 977cb343a2eSspeer (void) hvio_intr_setstate(ih_p->ih_sysino, HV_INTR_IDLE_STATE); 97844961713Sgirish return (r); 97944961713Sgirish } 98044961713Sgirish 98144961713Sgirish #ifdef DEBUG 98244961713Sgirish uint64_t niumx_debug_flags = 0; 98344961713Sgirish 98444961713Sgirish static char *niumx_debug_sym [] = { /* same sequence as niumx_debug_bit */ 98544961713Sgirish /* 0 */ "attach", 98644961713Sgirish /* 1 */ "map", 98744961713Sgirish /* 2 */ "nex-ctlops", 98844961713Sgirish /* 3 */ "introps", 98944961713Sgirish /* 4 */ "intr-add", 99044961713Sgirish /* 5 */ "intr-rem", 99144961713Sgirish /* 6 */ "intr", 99244961713Sgirish /* 7 */ "dma-alloc", 99344961713Sgirish /* 8 */ "dma-bind", 99444961713Sgirish /* 9 */ "dma-unbind", 99544961713Sgirish /* 10 */ "chk-dma-mode" 99644961713Sgirish }; 99744961713Sgirish 99844961713Sgirish /*ARGSUSED*/ 99944961713Sgirish void 100044961713Sgirish niumx_dbg(niumx_debug_bit_t bit, dev_info_t *dip, char *fmt, ...) 100144961713Sgirish { 100244961713Sgirish va_list ap; 100344961713Sgirish char msgbuf[1024]; 100444961713Sgirish 100544961713Sgirish if (!(1ull << bit & niumx_debug_flags)) 100644961713Sgirish return; 100744961713Sgirish va_start(ap, fmt); 100844961713Sgirish (void) vsprintf(msgbuf, fmt, ap); 100944961713Sgirish va_end(ap); 101044961713Sgirish cmn_err(CE_NOTE, "%s: %s", niumx_debug_sym[bit], msgbuf); 101144961713Sgirish } 101244961713Sgirish 101344961713Sgirish #endif /* DEBUG */ 1014