17c478bd9Sstevel@tonic-gate /* 27c478bd9Sstevel@tonic-gate * CDDL HEADER START 37c478bd9Sstevel@tonic-gate * 47c478bd9Sstevel@tonic-gate * The contents of this file are subject to the terms of the 5*49f91442Ssuha * Common Development and Distribution License (the "License"). 6*49f91442Ssuha * You may not use this file except in compliance with the License. 77c478bd9Sstevel@tonic-gate * 87c478bd9Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 97c478bd9Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 107c478bd9Sstevel@tonic-gate * See the License for the specific language governing permissions 117c478bd9Sstevel@tonic-gate * and limitations under the License. 127c478bd9Sstevel@tonic-gate * 137c478bd9Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 147c478bd9Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 157c478bd9Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 167c478bd9Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 177c478bd9Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 187c478bd9Sstevel@tonic-gate * 197c478bd9Sstevel@tonic-gate * CDDL HEADER END 207c478bd9Sstevel@tonic-gate */ 217c478bd9Sstevel@tonic-gate /* 22*49f91442Ssuha * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 237c478bd9Sstevel@tonic-gate * Use is subject to license terms. 247c478bd9Sstevel@tonic-gate */ 257c478bd9Sstevel@tonic-gate 267c478bd9Sstevel@tonic-gate #ifndef _SYS_PCIPSY_H 277c478bd9Sstevel@tonic-gate #define _SYS_PCIPSY_H 287c478bd9Sstevel@tonic-gate 297c478bd9Sstevel@tonic-gate #pragma ident "%Z%%M% %I% %E% SMI" 307c478bd9Sstevel@tonic-gate 317c478bd9Sstevel@tonic-gate #ifdef __cplusplus 327c478bd9Sstevel@tonic-gate extern "C" { 337c478bd9Sstevel@tonic-gate #endif 347c478bd9Sstevel@tonic-gate 357c478bd9Sstevel@tonic-gate /* 367c478bd9Sstevel@tonic-gate * Performance counters information. 377c478bd9Sstevel@tonic-gate */ 387c478bd9Sstevel@tonic-gate #define PSYCHO_SHIFT_PIC0 8 397c478bd9Sstevel@tonic-gate #define PSYCHO_SHIFT_PIC1 0 407c478bd9Sstevel@tonic-gate 417c478bd9Sstevel@tonic-gate /* 427c478bd9Sstevel@tonic-gate * Psycho-specific register offsets & bit field positions. 437c478bd9Sstevel@tonic-gate */ 447c478bd9Sstevel@tonic-gate 457c478bd9Sstevel@tonic-gate /* 467c478bd9Sstevel@tonic-gate * Offsets of global registers: 477c478bd9Sstevel@tonic-gate */ 487c478bd9Sstevel@tonic-gate #define PSYCHO_CB_DEVICE_ID_REG_OFFSET 0x00000000 497c478bd9Sstevel@tonic-gate #define PSYCHO_CB_CONTROL_STATUS_REG_OFFSET 0x00000010 507c478bd9Sstevel@tonic-gate 517c478bd9Sstevel@tonic-gate /* 527c478bd9Sstevel@tonic-gate * psycho performance counters offsets. 537c478bd9Sstevel@tonic-gate */ 547c478bd9Sstevel@tonic-gate #define PSYCHO_PERF_PCR_OFFSET 0x00000100 557c478bd9Sstevel@tonic-gate #define PSYCHO_PERF_PIC_OFFSET 0x00000108 567c478bd9Sstevel@tonic-gate 577c478bd9Sstevel@tonic-gate /* 587c478bd9Sstevel@tonic-gate * Offsets of registers in the interrupt block: 597c478bd9Sstevel@tonic-gate */ 607c478bd9Sstevel@tonic-gate #define PSYCHO_IB_SLOT_INTR_MAP_REG_OFFSET 0x00000C00 617c478bd9Sstevel@tonic-gate #define PSYCHO_IB_OBIO_INTR_MAP_REG_OFFSET 0x00001000 627c478bd9Sstevel@tonic-gate #define PSYCHO_IB_OBIO_CLEAR_INTR_REG_OFFSET 0x00001800 637c478bd9Sstevel@tonic-gate 647c478bd9Sstevel@tonic-gate /* 657c478bd9Sstevel@tonic-gate * Offsets of registers in the PBM block: 667c478bd9Sstevel@tonic-gate */ 677c478bd9Sstevel@tonic-gate #define PSYCHO_PCI_PBM_REG_BASE 0x00002000 687c478bd9Sstevel@tonic-gate #define PSYCHO_PCI_CTRL_REG_OFFSET 0x00000000 697c478bd9Sstevel@tonic-gate #define PSYCHO_PCI_ASYNC_FLT_STATUS_REG_OFFSET 0x00000010 707c478bd9Sstevel@tonic-gate #define PSYCHO_PCI_ASYNC_FLT_ADDR_REG_OFFSET 0x00000018 717c478bd9Sstevel@tonic-gate #define PSYCHO_PCI_DIAG_REG_OFFSET 0x00000020 727c478bd9Sstevel@tonic-gate 737c478bd9Sstevel@tonic-gate /* 747c478bd9Sstevel@tonic-gate * Offsets of registers in the streaming cache block: 757c478bd9Sstevel@tonic-gate */ 767c478bd9Sstevel@tonic-gate #define PSYCHO_SC_CTRL_REG_OFFSET 0x00000800 777c478bd9Sstevel@tonic-gate #define PSYCHO_SC_INVL_REG_OFFSET 0x00000808 787c478bd9Sstevel@tonic-gate #define PSYCHO_SC_SYNC_REG_OFFSET 0x00000810 797c478bd9Sstevel@tonic-gate #define PSYCHO_SC_A_DATA_DIAG_OFFSET 0x0000b000 807c478bd9Sstevel@tonic-gate #define PSYCHO_SC_A_TAG_DIAG_OFFSET 0x0000b800 817c478bd9Sstevel@tonic-gate #define PSYCHO_SC_A_LTAG_DIAG_OFFSET 0x0000b900 827c478bd9Sstevel@tonic-gate #define PSYCHO_SC_B_DATA_DIAG_OFFSET 0x0000c000 837c478bd9Sstevel@tonic-gate #define PSYCHO_SC_B_TAG_DIAG_OFFSET 0x0000c800 847c478bd9Sstevel@tonic-gate #define PSYCHO_SC_B_LTAG_DIAG_OFFSET 0x0000c900 857c478bd9Sstevel@tonic-gate 867c478bd9Sstevel@tonic-gate /* 877c478bd9Sstevel@tonic-gate * Address space offsets and sizes: 887c478bd9Sstevel@tonic-gate */ 897c478bd9Sstevel@tonic-gate #define PSYCHO_PCI_CONFIG 0x001000000ull 907c478bd9Sstevel@tonic-gate #define PSYCHO_PCI_A_IO 0x002000000ull 917c478bd9Sstevel@tonic-gate #define PSYCHO_PCI_B_IO 0x002010000ull 927c478bd9Sstevel@tonic-gate #define PSYCHO_PCI_A_MEMORY 0x100000000ull 937c478bd9Sstevel@tonic-gate #define PSYCHO_PCI_B_MEMORY 0x180000000ull 947c478bd9Sstevel@tonic-gate #define PSYCHO_PCI_IO_SIZE 0x000010000ull 957c478bd9Sstevel@tonic-gate #define PSYCHO_PCI_MEM_SIZE 0x080000000ull 967c478bd9Sstevel@tonic-gate 977c478bd9Sstevel@tonic-gate /* 987c478bd9Sstevel@tonic-gate * psycho control register bit definitions: 997c478bd9Sstevel@tonic-gate */ 1007c478bd9Sstevel@tonic-gate #define PSYCHO_CB_CONTROL_STATUS_MODE 0x0000000000000001ull 1017c478bd9Sstevel@tonic-gate #define PSYCHO_CB_CONTROL_STATUS_IMPL 0xf000000000000000ull 1027c478bd9Sstevel@tonic-gate #define PSYCHO_CB_CONTROL_STATUS_IMPL_SHIFT 60 1037c478bd9Sstevel@tonic-gate #define PSYCHO_CB_CONTROL_STATUS_VER 0x0f00000000000000ull 1047c478bd9Sstevel@tonic-gate #define PSYCHO_CB_CONTROL_STATUS_VER_SHIFT 56 1057c478bd9Sstevel@tonic-gate 1067c478bd9Sstevel@tonic-gate /* 1077c478bd9Sstevel@tonic-gate * psycho ECC UE AFSR bit definitions: 1087c478bd9Sstevel@tonic-gate */ 1097c478bd9Sstevel@tonic-gate #define PSYCHO_ECC_UE_AFSR_BYTEMASK 0x0000ffff00000000ull 1107c478bd9Sstevel@tonic-gate #define PSYCHO_ECC_UE_AFSR_BYTEMASK_SHIFT 32 1117c478bd9Sstevel@tonic-gate #define PSYCHO_ECC_UE_AFSR_DW_OFFSET 0x00000000e0000000ull 1127c478bd9Sstevel@tonic-gate #define PSYCHO_ECC_UE_AFSR_DW_OFFSET_SHIFT 29 1137c478bd9Sstevel@tonic-gate #define PSYCHO_ECC_UE_AFSR_ID 0x000000001f000000ull 1147c478bd9Sstevel@tonic-gate #define PSYCHO_ECC_UE_AFSR_ID_SHIFT 24 1157c478bd9Sstevel@tonic-gate #define PSYCHO_ECC_UE_AFSR_BLK 0x0000000000800000ull 1167c478bd9Sstevel@tonic-gate 1177c478bd9Sstevel@tonic-gate /* 1187c478bd9Sstevel@tonic-gate * psycho ECC CE AFSR bit definitions: 1197c478bd9Sstevel@tonic-gate */ 1207c478bd9Sstevel@tonic-gate #define PSYCHO_ECC_CE_AFSR_SYND 0x00ff000000000000ull 1217c478bd9Sstevel@tonic-gate #define PSYCHO_ECC_CE_AFSR_SYND_SHIFT 48 1227c478bd9Sstevel@tonic-gate #define PSYCHO_ECC_CE_AFSR_BYTEMASK 0x0000ffff00000000ull 1237c478bd9Sstevel@tonic-gate #define PSYCHO_ECC_CE_AFSR_BYTEMASK_SHIFT 32 1247c478bd9Sstevel@tonic-gate #define PSYCHO_ECC_CE_AFSR_DW_OFFSET 0x00000000e0000000ull 1257c478bd9Sstevel@tonic-gate #define PSYCHO_ECC_CE_AFSR_DW_OFFSET_SHIFT 29 1267c478bd9Sstevel@tonic-gate #define PSYCHO_ECC_CE_AFSR_UPA_MID 0x000000001f000000ull 1277c478bd9Sstevel@tonic-gate #define PSYCHO_ECC_CE_AFSR_UPA_MID_SHIFT 24 1287c478bd9Sstevel@tonic-gate #define PSYCHO_ECC_CE_AFSR_BLK 0x0000000000800000ull 1297c478bd9Sstevel@tonic-gate 1307c478bd9Sstevel@tonic-gate /* 1317c478bd9Sstevel@tonic-gate * psycho pci control register bits: 1327c478bd9Sstevel@tonic-gate */ 1337c478bd9Sstevel@tonic-gate #define PSYCHO_PCI_CTRL_ARB_PARK 0x0000000000200000ull 1347c478bd9Sstevel@tonic-gate #define PSYCHO_PCI_CTRL_SBH_INT_EN 0x0000000000000400ull 1357c478bd9Sstevel@tonic-gate #define PSYCHO_PCI_CTRL_WAKEUP_EN 0x0000000000000200ull 1367c478bd9Sstevel@tonic-gate #define PSYCHO_PCI_CTRL_ERR_INT_EN 0x0000000000000100ull 1377c478bd9Sstevel@tonic-gate #define PSYCHO_PCI_CTRL_ARB_EN_MASK 0x000000000000000full 1387c478bd9Sstevel@tonic-gate 1397c478bd9Sstevel@tonic-gate /* 1407c478bd9Sstevel@tonic-gate * psycho PCI asynchronous fault status register bit definitions: 1417c478bd9Sstevel@tonic-gate */ 1427c478bd9Sstevel@tonic-gate #define PSYCHO_PCI_AFSR_PE_SHIFT 60 1437c478bd9Sstevel@tonic-gate #define PSYCHO_PCI_AFSR_SE_SHIFT 56 1447c478bd9Sstevel@tonic-gate #define PSYCHO_PCI_AFSR_E_MA 0x0000000000000008ull 1457c478bd9Sstevel@tonic-gate #define PSYCHO_PCI_AFSR_E_TA 0x0000000000000004ull 1467c478bd9Sstevel@tonic-gate #define PSYCHO_PCI_AFSR_E_RTRY 0x0000000000000002ull 1477c478bd9Sstevel@tonic-gate #define PSYCHO_PCI_AFSR_E_PERR 0x0000000000000001ull 1487c478bd9Sstevel@tonic-gate #define PSYCHO_PCI_AFSR_E_MASK 0x000000000000000full 1497c478bd9Sstevel@tonic-gate #define PSYCHO_PCI_AFSR_BYTEMASK 0x0000ffff00000000ull 1507c478bd9Sstevel@tonic-gate #define PSYCHO_PCI_AFSR_BYTEMASK_SHIFT 32 1517c478bd9Sstevel@tonic-gate #define PSYCHO_PCI_AFSR_BLK 0x0000000080000000ull 1527c478bd9Sstevel@tonic-gate #define PSYCHO_PCI_AFSR_MID 0x000000003e000000ull 1537c478bd9Sstevel@tonic-gate #define PSYCHO_PCI_AFSR_MID_SHIFT 25 1547c478bd9Sstevel@tonic-gate 1557c478bd9Sstevel@tonic-gate /* 1567c478bd9Sstevel@tonic-gate * psycho PCI diagnostic register bit definitions: 1577c478bd9Sstevel@tonic-gate */ 1587c478bd9Sstevel@tonic-gate #define PSYCHO_PCI_DIAG_DIS_DWSYNC 0x0000000000000010ull 1597c478bd9Sstevel@tonic-gate 1607c478bd9Sstevel@tonic-gate #define PBM_AFSR_TO_PRIERR(afsr) \ 1617c478bd9Sstevel@tonic-gate (afsr >> PSYCHO_PCI_AFSR_PE_SHIFT & PSYCHO_PCI_AFSR_E_MASK) 1627c478bd9Sstevel@tonic-gate #define PBM_AFSR_TO_SECERR(afsr) \ 1637c478bd9Sstevel@tonic-gate (afsr >> PSYCHO_PCI_AFSR_SE_SHIFT & PSYCHO_PCI_AFSR_E_MASK) 1647c478bd9Sstevel@tonic-gate #define PBM_AFSR_TO_BYTEMASK(afsr) \ 1657c478bd9Sstevel@tonic-gate ((afsr & PSYCHO_PCI_AFSR_BYTEMASK) >> PSYCHO_PCI_AFSR_BYTEMASK_SHIFT) 1667c478bd9Sstevel@tonic-gate 1677c478bd9Sstevel@tonic-gate #define PCI_BRIDGE_TYPE(cmn_p) PCI_PSYCHO 1687c478bd9Sstevel@tonic-gate /* 1697c478bd9Sstevel@tonic-gate * for sabre 1707c478bd9Sstevel@tonic-gate */ 1717c478bd9Sstevel@tonic-gate #define DMA_WRITE_SYNC_REG 0x1C20 1727c478bd9Sstevel@tonic-gate 1737c478bd9Sstevel@tonic-gate extern uint_t cb_thermal_intr(caddr_t a); 1747c478bd9Sstevel@tonic-gate 1757c478bd9Sstevel@tonic-gate #define PCI_ID_TO_IGN(pci_id) ((pci_ign_t)UPAID_TO_IGN(pci_id)) 176*49f91442Ssuha 177*49f91442Ssuha /* 178*49f91442Ssuha * The following macro defines the 40-bit bus width support for UPA bus 179*49f91442Ssuha * in DVMA and iommu bypass transfers: 180*49f91442Ssuha */ 181*49f91442Ssuha 182*49f91442Ssuha #define UPA_IOMMU_BYPASS_END 0xFFFC00FFFFFFFFFFull 183*49f91442Ssuha 1847c478bd9Sstevel@tonic-gate #ifdef __cplusplus 1857c478bd9Sstevel@tonic-gate } 1867c478bd9Sstevel@tonic-gate #endif 1877c478bd9Sstevel@tonic-gate 1887c478bd9Sstevel@tonic-gate #endif /* _SYS_PCIPSY_H */ 189