xref: /illumos-gate/usr/src/uts/sun4u/sys/pci/pci_ib.h (revision 825808ce)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2006 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 
26 #ifndef	_SYS_PCI_IB_H
27 #define	_SYS_PCI_IB_H
28 
29 #pragma ident	"%Z%%M%	%I%	%E% SMI"
30 
31 #ifdef	__cplusplus
32 extern "C" {
33 #endif
34 
35 #include <sys/ddi_subrdefs.h>
36 #include <sys/pci_tools.h>
37 
38 typedef uint8_t ib_ino_t;
39 typedef uint16_t ib_mondo_t;
40 typedef struct ib_ino_info ib_ino_info_t;
41 typedef struct ib_ino_pil ib_ino_pil_t;
42 typedef uint8_t device_num_t;
43 typedef uint8_t interrupt_t;
44 
45 /*
46  * interrupt block soft state structure:
47  *
48  * Each pci node may share an interrupt block structure with its peer
49  * node or have its own private interrupt block structure.
50  */
51 typedef struct ib ib_t;
52 struct ib {
53 
54 	pci_t *ib_pci_p;	/* link back to pci soft state */
55 	pci_ign_t ib_ign;	/* interrupt group # */
56 
57 	/*
58 	 * PCI slot and onboard I/O interrupt mapping register blocks addresses:
59 	 */
60 	uintptr_t ib_slot_intr_map_regs;
61 #define	ib_intr_map_regs	ib_slot_intr_map_regs
62 	uintptr_t ib_obio_intr_map_regs;
63 
64 	/*
65 	 * PCI slot and onboard I/O clear interrupt register block addresses:
66 	 */
67 	uintptr_t ib_slot_clear_intr_regs;
68 	uintptr_t ib_obio_clear_intr_regs;
69 
70 	/*
71 	 * UPA expansion slot interrupt mapping register addresses:
72 	 */
73 	volatile uint64_t *ib_upa_imr[2];
74 	uint64_t ib_upa_imr_state[2];
75 
76 	/*
77 	 * Interrupt retry register address:
78 	 */
79 	volatile uint64_t *ib_intr_retry_timer_reg;
80 
81 	/*
82 	 * PCI slot and onboard I/O interrupt state diag register addresses:
83 	 */
84 	volatile uint64_t *ib_slot_intr_state_diag_reg;
85 	volatile uint64_t *ib_obio_intr_state_diag_reg;
86 
87 	uint_t ib_max_ino;			/* largest supported INO */
88 	ib_ino_info_t *ib_ino_lst;		/* ino link list */
89 	kmutex_t ib_ino_lst_mutex;		/* mutex for ino link list */
90 	kmutex_t ib_intr_lock;			/* lock for internal intr  */
91 	uint16_t ib_map_reg_counters[8];	/* counters for shared map */
92 						/* registers */
93 };
94 
95 #define	PCI_PULSE_INO	0x80000000
96 #define	PSYCHO_MAX_INO	0x3f
97 #define	SCHIZO_MAX_INO	0x37
98 #define	PCI_INO_BITS	6			/* INO#s are 6 bits long */
99 #define	PCI_IGN_BITS	5			/* IGN#s are 5 bits long */
100 
101 /*
102  * ih structure: one per every consumer of each ino and pil pair with interrupt
103  * registered.
104  */
105 typedef struct ih {
106 	dev_info_t *ih_dip;		/* devinfo structure */
107 	uint32_t ih_inum;		/* interrupt number for this device */
108 	uint_t	ih_intr_state;		/* Only used for fixed interrupts */
109 	uint_t (*ih_handler)();		/* interrupt handler */
110 	caddr_t ih_handler_arg1;	/* interrupt handler argument #1 */
111 	caddr_t ih_handler_arg2;	/* interrupt handler argument #2 */
112 	ddi_acc_handle_t ih_config_handle; /* config space reg map handle */
113 	struct ih *ih_next;		/* next entry in list */
114 	uint64_t ih_ticks;		/* ticks spent in this handler */
115 	uint64_t ih_nsec;		/* nsec spent in this handler */
116 	kstat_t *ih_ksp;		/* pointer to kstat information */
117 	ib_ino_pil_t *ih_ipil_p;	/* only for use by kstat */
118 } ih_t;
119 
120 /* Only used for fixed or legacy interrupts */
121 #define	PCI_INTR_STATE_DISABLE	0	/* disabled */
122 #define	PCI_INTR_STATE_ENABLE	1	/* enabled */
123 
124 /*
125  * ino_pil structure: one per each ino and pil pair with interrupt registered
126  */
127 struct ib_ino_pil {
128 	ushort_t ipil_pil;		/* PIL for this ino */
129 	ushort_t ipil_ih_size;		/* size of ih_t list */
130 	ih_t *ipil_ih_head;		/* ih_t list head */
131 	ih_t *ipil_ih_tail;		/* ih_t list tail */
132 	ih_t *ipil_ih_start;		/* starting point in ih_t list  */
133 	ib_ino_info_t *ipil_ino_p;	/* pointer to ib_ino_info_t */
134 	ib_ino_pil_t *ipil_next_p;	/* pointer to next ib_ino_pil_t */
135 };
136 
137 /*
138  * ino structure: one per each ino with interrupt registered
139  */
140 struct ib_ino_info {
141 	ib_ino_t ino_ino;		/* INO number - 8 bit */
142 	uint64_t ino_mondo;		/* store mondo number */
143 	uint8_t ino_slot_no;		/* PCI slot number 0-8 */
144 	ib_t *ino_ib_p;			/* link back to interrupt block state */
145 	volatile uint64_t *ino_clr_reg;	/* ino interrupt clear register */
146 	volatile uint64_t *ino_map_reg;	/* ino interrupt mapping register */
147 	uint64_t ino_map_reg_save;	/* = *ino_map_reg if saved */
148 	volatile uint_t ino_unclaimed_intrs; /* number of unclaimed intrs */
149 	clock_t ino_spurintr_begin;	/* begin time of spurious intr series */
150 	int ino_established;		/* ino has been associated with a cpu */
151 	uint32_t ino_cpuid;		/* cpu that ino is targeting */
152 	int32_t ino_intr_weight;	/* intr weight of devices sharing ino */
153 	ushort_t ino_ipil_size;		/* number of ib_ino_pil_t sharing ino */
154 	ushort_t ino_lopil;		/* lowest PIL sharing ino */
155 	ushort_t ino_claimed;		/* pil bit masks, who claimed intr */
156 	ib_ino_pil_t *ino_ipil_p;	/* pointer to first ib_ino_pil_t */
157 	ib_ino_info_t *ino_next_p;	/* pointer to next ib_ino_info_t */
158 };
159 
160 #define	IB_INTR_WAIT	1		/* wait for interrupt completion */
161 #define	IB_INTR_NOWAIT	0		/* already handling intr, no wait */
162 
163 #define	IB2CB(ib_p)	((ib_p)->ib_pci_p->pci_cb_p)
164 
165 #define	IB_MONDO_TO_INO(mondo)		((ib_ino_t)((mondo) & 0x3f))
166 #define	IB_INO_INTR_ON(reg_p)		*(reg_p) |= COMMON_INTR_MAP_REG_VALID
167 #define	IB_INO_INTR_OFF(reg_p)		*(reg_p) &= ~COMMON_INTR_MAP_REG_VALID
168 #define	IB_INO_INTR_RESET(reg_p)	*(reg_p) = 0ull
169 #define	IB_INO_INTR_STATE_REG(ib_p, ino) ((ino) & 0x20 ? \
170 	ib_p->ib_obio_intr_state_diag_reg : ib_p->ib_slot_intr_state_diag_reg)
171 #define	IB_INO_INTR_PENDING(reg_p, ino) \
172 	(((*(reg_p) >> (((ino) & 0x1f) << 1)) & COMMON_CLEAR_INTR_REG_MASK) == \
173 	COMMON_CLEAR_INTR_REG_PENDING)
174 #define	IB_INO_INTR_CLEAR(reg_p)	*(reg_p) = COMMON_CLEAR_INTR_REG_IDLE
175 #define	IB_INO_INTR_TRIG(reg_p)	*(reg_p) = COMMON_CLEAR_INTR_REG_RECEIVED
176 #define	IB_INO_INTR_PEND(reg_p)		*(reg_p) = COMMON_CLEAR_INTR_REG_PENDING
177 #define	IB_INO_INTR_ISON(imr)		((imr) >> 31)
178 #define	IB_IMR2MONDO(imr) \
179 	((imr) & (COMMON_INTR_MAP_REG_IGN | COMMON_INTR_MAP_REG_INO))
180 
181 #define	IB_IS_OBIO_INO(ino) (ino & 0x20)
182 
183 #ifdef _STARFIRE
184 /*
185  * returns a uniq ino per interrupt mapping register
186  * For on board devices, inos are not shared. But for plugin devices,
187  * return the 1st ino of the 4 that are sharing the same mapping register.
188  */
189 #define	IB_GET_MAPREG_INO(ino)	\
190 	((volatile uint64_t *)(uintptr_t)((ino & 0x20) ? \
191 	    ino : ((ino >> 2) << 2)))
192 #endif /* _STARFIRE */
193 
194 #define	IB_IGN_TO_MONDO(ign, ino)	(((ign) << PCI_INO_BITS) | (ino))
195 #define	IB_INO_TO_MONDO(ib_p, ino)	IB_IGN_TO_MONDO((ib_p)->ib_ign, ino)
196 
197 extern void ib_create(pci_t *pci_p);
198 extern void ib_destroy(pci_t *pci_p);
199 extern void ib_configure(ib_t *ib_p);
200 extern uint64_t ib_get_map_reg(ib_mondo_t mondo, uint32_t cpu_id);
201 extern void ib_intr_enable(pci_t *pci_p, ib_ino_t ino);
202 extern void ib_intr_disable(ib_t *ib_p, ib_ino_t ino, int wait);
203 extern void ib_nintr_clear(ib_t *ib_p, ib_ino_t ino);
204 extern void ib_suspend(ib_t *ib_p);
205 extern void ib_resume(ib_t *ib_p);
206 
207 extern ib_ino_info_t *ib_locate_ino(ib_t *ib_p, ib_ino_t ino_num);
208 extern ib_ino_pil_t *ib_new_ino_pil(ib_t *ib_p, ib_ino_t ino_num, uint_t pil,
209     ih_t *ih_p);
210 extern void ib_delete_ino_pil(ib_t *ib_p, ib_ino_pil_t *ipil_p);
211 extern void ib_free_ino_all(ib_t *ib_p);
212 extern ib_ino_pil_t *ib_ino_locate_ipil(ib_ino_info_t *ino_p, uint_t pil);
213 extern void ib_ino_add_intr(pci_t *pci_p, ib_ino_pil_t *ipil_p, ih_t *ih_p);
214 extern void ib_ino_rem_intr(pci_t *pci_p, ib_ino_pil_t *ipil_p, ih_t *ih_p);
215 extern ih_t *ib_intr_locate_ih(ib_ino_pil_t *ipil_p, dev_info_t *dip,
216     uint32_t inum);
217 extern ih_t *ib_alloc_ih(dev_info_t *dip, uint32_t inum,
218     uint_t (*int_handler)(caddr_t int_handler_arg1, caddr_t int_handler_arg2),
219     caddr_t int_handler_arg1, caddr_t int_handler_arg2);
220 extern void ib_free_ih(ih_t *ih_p);
221 extern int ib_update_intr_state(pci_t *pci_p, dev_info_t *rdip,
222     ddi_intr_handle_impl_t *hdlp, uint_t new_intr_state);
223 extern void ib_ino_map_reg_share(ib_t *ib_p, ib_ino_t ino,
224     ib_ino_info_t *ino_p);
225 extern int ib_ino_map_reg_unshare(ib_t *ib_p, ib_ino_t ino,
226     ib_ino_info_t *ino_p);
227 extern uint32_t ib_register_intr(ib_t *ib_p, ib_mondo_t mondo, uint_t pil,
228     uint_t (*handler)(caddr_t arg), caddr_t arg);
229 extern void ib_unregister_intr(ib_mondo_t mondo);
230 extern void ib_intr_dist_nintr(ib_t *ib_p, ib_ino_t ino,
231     volatile uint64_t *imr_p);
232 extern void ib_intr_dist_all(void *arg, int32_t max_weight, int32_t weight);
233 extern void ib_cpu_ticks_to_ih_nsec(ib_t *ib_p, ih_t *ih_p, uint32_t cpu_id);
234 extern uint8_t ib_get_ino_devs(ib_t *ib_p, uint32_t ino, uint8_t *devs_ret,
235     pcitool_intr_dev_t *devs);
236 extern void ib_log_new_cpu(ib_t *ib_p, uint32_t old_cpu_id, uint32_t new_cpu_id,
237     uint32_t ino);
238 
239 extern int pci_pil[];
240 
241 #ifdef	__cplusplus
242 }
243 #endif
244 
245 #endif	/* _SYS_PCI_IB_H */
246