1*7c478bd9Sstevel@tonic-gate /* 2*7c478bd9Sstevel@tonic-gate * CDDL HEADER START 3*7c478bd9Sstevel@tonic-gate * 4*7c478bd9Sstevel@tonic-gate * The contents of this file are subject to the terms of the 5*7c478bd9Sstevel@tonic-gate * Common Development and Distribution License, Version 1.0 only 6*7c478bd9Sstevel@tonic-gate * (the "License"). You may not use this file except in compliance 7*7c478bd9Sstevel@tonic-gate * with the License. 8*7c478bd9Sstevel@tonic-gate * 9*7c478bd9Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10*7c478bd9Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 11*7c478bd9Sstevel@tonic-gate * See the License for the specific language governing permissions 12*7c478bd9Sstevel@tonic-gate * and limitations under the License. 13*7c478bd9Sstevel@tonic-gate * 14*7c478bd9Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 15*7c478bd9Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16*7c478bd9Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 17*7c478bd9Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 18*7c478bd9Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 19*7c478bd9Sstevel@tonic-gate * 20*7c478bd9Sstevel@tonic-gate * CDDL HEADER END 21*7c478bd9Sstevel@tonic-gate */ 22*7c478bd9Sstevel@tonic-gate /* 23*7c478bd9Sstevel@tonic-gate * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24*7c478bd9Sstevel@tonic-gate * Use is subject to license terms. 25*7c478bd9Sstevel@tonic-gate */ 26*7c478bd9Sstevel@tonic-gate 27*7c478bd9Sstevel@tonic-gate #ifndef _SYS_PCI_IB_H 28*7c478bd9Sstevel@tonic-gate #define _SYS_PCI_IB_H 29*7c478bd9Sstevel@tonic-gate 30*7c478bd9Sstevel@tonic-gate #pragma ident "%Z%%M% %I% %E% SMI" 31*7c478bd9Sstevel@tonic-gate 32*7c478bd9Sstevel@tonic-gate #ifdef __cplusplus 33*7c478bd9Sstevel@tonic-gate extern "C" { 34*7c478bd9Sstevel@tonic-gate #endif 35*7c478bd9Sstevel@tonic-gate 36*7c478bd9Sstevel@tonic-gate #include <sys/ddi_subrdefs.h> 37*7c478bd9Sstevel@tonic-gate 38*7c478bd9Sstevel@tonic-gate typedef uint8_t ib_ino_t; 39*7c478bd9Sstevel@tonic-gate typedef uint16_t ib_mondo_t; 40*7c478bd9Sstevel@tonic-gate typedef struct ib_ino_info ib_ino_info_t; 41*7c478bd9Sstevel@tonic-gate typedef uint8_t device_num_t; 42*7c478bd9Sstevel@tonic-gate typedef uint8_t interrupt_t; 43*7c478bd9Sstevel@tonic-gate 44*7c478bd9Sstevel@tonic-gate /* 45*7c478bd9Sstevel@tonic-gate * interrupt block soft state structure: 46*7c478bd9Sstevel@tonic-gate * 47*7c478bd9Sstevel@tonic-gate * Each pci node may share an interrupt block structure with its peer 48*7c478bd9Sstevel@tonic-gate * node or have its own private interrupt block structure. 49*7c478bd9Sstevel@tonic-gate */ 50*7c478bd9Sstevel@tonic-gate typedef struct ib ib_t; 51*7c478bd9Sstevel@tonic-gate struct ib { 52*7c478bd9Sstevel@tonic-gate 53*7c478bd9Sstevel@tonic-gate pci_t *ib_pci_p; /* link back to pci soft state */ 54*7c478bd9Sstevel@tonic-gate pci_ign_t ib_ign; /* interrupt group # */ 55*7c478bd9Sstevel@tonic-gate 56*7c478bd9Sstevel@tonic-gate /* 57*7c478bd9Sstevel@tonic-gate * PCI slot and onboard I/O interrupt mapping register blocks addresses: 58*7c478bd9Sstevel@tonic-gate */ 59*7c478bd9Sstevel@tonic-gate uintptr_t ib_slot_intr_map_regs; 60*7c478bd9Sstevel@tonic-gate #define ib_intr_map_regs ib_slot_intr_map_regs 61*7c478bd9Sstevel@tonic-gate uintptr_t ib_obio_intr_map_regs; 62*7c478bd9Sstevel@tonic-gate 63*7c478bd9Sstevel@tonic-gate /* 64*7c478bd9Sstevel@tonic-gate * PCI slot and onboard I/O clear interrupt register block addresses: 65*7c478bd9Sstevel@tonic-gate */ 66*7c478bd9Sstevel@tonic-gate uintptr_t ib_slot_clear_intr_regs; 67*7c478bd9Sstevel@tonic-gate uintptr_t ib_obio_clear_intr_regs; 68*7c478bd9Sstevel@tonic-gate 69*7c478bd9Sstevel@tonic-gate /* 70*7c478bd9Sstevel@tonic-gate * UPA expansion slot interrupt mapping register addresses: 71*7c478bd9Sstevel@tonic-gate */ 72*7c478bd9Sstevel@tonic-gate volatile uint64_t *ib_upa_imr[2]; 73*7c478bd9Sstevel@tonic-gate uint64_t ib_upa_imr_state[2]; 74*7c478bd9Sstevel@tonic-gate 75*7c478bd9Sstevel@tonic-gate /* 76*7c478bd9Sstevel@tonic-gate * Interrupt retry register address: 77*7c478bd9Sstevel@tonic-gate */ 78*7c478bd9Sstevel@tonic-gate volatile uint64_t *ib_intr_retry_timer_reg; 79*7c478bd9Sstevel@tonic-gate 80*7c478bd9Sstevel@tonic-gate /* 81*7c478bd9Sstevel@tonic-gate * PCI slot and onboard I/O interrupt state diag register addresses: 82*7c478bd9Sstevel@tonic-gate */ 83*7c478bd9Sstevel@tonic-gate volatile uint64_t *ib_slot_intr_state_diag_reg; 84*7c478bd9Sstevel@tonic-gate volatile uint64_t *ib_obio_intr_state_diag_reg; 85*7c478bd9Sstevel@tonic-gate 86*7c478bd9Sstevel@tonic-gate uint_t ib_max_ino; /* largest supported INO */ 87*7c478bd9Sstevel@tonic-gate ib_ino_info_t *ib_ino_lst; /* ino link list */ 88*7c478bd9Sstevel@tonic-gate kmutex_t ib_ino_lst_mutex; /* mutex for ino link list */ 89*7c478bd9Sstevel@tonic-gate kmutex_t ib_intr_lock; /* lock for internal intr */ 90*7c478bd9Sstevel@tonic-gate uint16_t ib_map_reg_counters[8]; /* counters for shared map */ 91*7c478bd9Sstevel@tonic-gate /* registers */ 92*7c478bd9Sstevel@tonic-gate }; 93*7c478bd9Sstevel@tonic-gate 94*7c478bd9Sstevel@tonic-gate #define PCI_PULSE_INO 0x80000000 95*7c478bd9Sstevel@tonic-gate #define PSYCHO_MAX_INO 0x3f 96*7c478bd9Sstevel@tonic-gate #define SCHIZO_MAX_INO 0x37 97*7c478bd9Sstevel@tonic-gate #define PCI_INO_BITS 6 /* INO#s are 6 bits long */ 98*7c478bd9Sstevel@tonic-gate #define PCI_IGN_BITS 5 /* IGN#s are 5 bits long */ 99*7c478bd9Sstevel@tonic-gate 100*7c478bd9Sstevel@tonic-gate /* 101*7c478bd9Sstevel@tonic-gate * The following structure represents an interrupt entry for an INO. 102*7c478bd9Sstevel@tonic-gate */ 103*7c478bd9Sstevel@tonic-gate typedef struct ih { 104*7c478bd9Sstevel@tonic-gate dev_info_t *ih_dip; /* devinfo structure */ 105*7c478bd9Sstevel@tonic-gate uint32_t ih_inum; /* interrupt number for this device */ 106*7c478bd9Sstevel@tonic-gate uint_t ih_intr_state; /* Only used for fixed interrupts */ 107*7c478bd9Sstevel@tonic-gate uint_t (*ih_handler)(); /* interrupt handler */ 108*7c478bd9Sstevel@tonic-gate caddr_t ih_handler_arg1; /* interrupt handler argument #1 */ 109*7c478bd9Sstevel@tonic-gate caddr_t ih_handler_arg2; /* interrupt handler argument #2 */ 110*7c478bd9Sstevel@tonic-gate ddi_acc_handle_t ih_config_handle; /* config space reg map handle */ 111*7c478bd9Sstevel@tonic-gate struct ih *ih_next; /* next entry in list */ 112*7c478bd9Sstevel@tonic-gate uint64_t ih_ticks; /* ticks spent in this handler */ 113*7c478bd9Sstevel@tonic-gate uint64_t ih_nsec; /* nsec spent in this handler */ 114*7c478bd9Sstevel@tonic-gate kstat_t *ih_ksp; 115*7c478bd9Sstevel@tonic-gate struct ib_ino_info *ih_ino_p; /* only for use by kstat */ 116*7c478bd9Sstevel@tonic-gate } ih_t; 117*7c478bd9Sstevel@tonic-gate 118*7c478bd9Sstevel@tonic-gate /* Only used for fixed or legacy interrupts */ 119*7c478bd9Sstevel@tonic-gate #define PCI_INTR_STATE_DISABLE 0 /* disabled */ 120*7c478bd9Sstevel@tonic-gate #define PCI_INTR_STATE_ENABLE 1 /* enabled */ 121*7c478bd9Sstevel@tonic-gate 122*7c478bd9Sstevel@tonic-gate /* 123*7c478bd9Sstevel@tonic-gate * ino structure : one per each psycho slot ino with interrupt registered 124*7c478bd9Sstevel@tonic-gate */ 125*7c478bd9Sstevel@tonic-gate struct ib_ino_info { 126*7c478bd9Sstevel@tonic-gate ib_ino_t ino_ino; /* INO number - 8 bit */ 127*7c478bd9Sstevel@tonic-gate uint8_t ino_slot_no; /* PCI slot number 0-8 */ 128*7c478bd9Sstevel@tonic-gate uint16_t ino_ih_size; /* size of the pci intrspec list */ 129*7c478bd9Sstevel@tonic-gate struct ib_ino_info *ino_next; 130*7c478bd9Sstevel@tonic-gate ih_t *ino_ih_head; /* intr spec (part of ppd) list head */ 131*7c478bd9Sstevel@tonic-gate ih_t *ino_ih_tail; /* intr spec (part of ppd) list tail */ 132*7c478bd9Sstevel@tonic-gate ih_t *ino_ih_start; /* starting point in intr spec list */ 133*7c478bd9Sstevel@tonic-gate ib_t *ino_ib_p; /* link back to interrupt block state */ 134*7c478bd9Sstevel@tonic-gate volatile uint64_t *ino_clr_reg; /* ino interrupt clear register */ 135*7c478bd9Sstevel@tonic-gate volatile uint64_t *ino_map_reg; /* ino interrupt mapping register */ 136*7c478bd9Sstevel@tonic-gate uint64_t ino_map_reg_save; /* = *ino_map_reg if saved */ 137*7c478bd9Sstevel@tonic-gate uint32_t ino_pil; /* PIL for this ino */ 138*7c478bd9Sstevel@tonic-gate volatile uint_t ino_unclaimed; /* number of unclaimed interrupts */ 139*7c478bd9Sstevel@tonic-gate clock_t ino_spurintr_begin; /* begin time of spurious intr series */ 140*7c478bd9Sstevel@tonic-gate int ino_established; /* ino has been associated with a cpu */ 141*7c478bd9Sstevel@tonic-gate uint32_t ino_cpuid; /* cpu that ino is targeting */ 142*7c478bd9Sstevel@tonic-gate int32_t ino_intr_weight; /* intr weight of devices sharing ino */ 143*7c478bd9Sstevel@tonic-gate }; 144*7c478bd9Sstevel@tonic-gate 145*7c478bd9Sstevel@tonic-gate #define IB_INTR_WAIT 1 /* wait for interrupt completion */ 146*7c478bd9Sstevel@tonic-gate #define IB_INTR_NOWAIT 0 /* already handling intr, no wait */ 147*7c478bd9Sstevel@tonic-gate 148*7c478bd9Sstevel@tonic-gate #define IB2CB(ib_p) ((ib_p)->ib_pci_p->pci_cb_p) 149*7c478bd9Sstevel@tonic-gate 150*7c478bd9Sstevel@tonic-gate #define IB_MONDO_TO_INO(mondo) ((ib_ino_t)((mondo) & 0x3f)) 151*7c478bd9Sstevel@tonic-gate #define IB_INO_INTR_ON(reg_p) *(reg_p) |= COMMON_INTR_MAP_REG_VALID 152*7c478bd9Sstevel@tonic-gate #define IB_INO_INTR_OFF(reg_p) *(reg_p) &= ~COMMON_INTR_MAP_REG_VALID 153*7c478bd9Sstevel@tonic-gate #define IB_INO_INTR_RESET(reg_p) *(reg_p) = 0ull 154*7c478bd9Sstevel@tonic-gate #define IB_INO_INTR_STATE_REG(ib_p, ino) ((ino) & 0x20 ? \ 155*7c478bd9Sstevel@tonic-gate ib_p->ib_obio_intr_state_diag_reg : ib_p->ib_slot_intr_state_diag_reg) 156*7c478bd9Sstevel@tonic-gate #define IB_INO_INTR_PENDING(reg_p, ino) \ 157*7c478bd9Sstevel@tonic-gate (((*(reg_p) >> (((ino) & 0x1f) << 1)) & COMMON_CLEAR_INTR_REG_MASK) == \ 158*7c478bd9Sstevel@tonic-gate COMMON_CLEAR_INTR_REG_PENDING) 159*7c478bd9Sstevel@tonic-gate #define IB_INO_INTR_CLEAR(reg_p) *(reg_p) = COMMON_CLEAR_INTR_REG_IDLE 160*7c478bd9Sstevel@tonic-gate #define IB_INO_INTR_TRIG(reg_p) *(reg_p) = COMMON_CLEAR_INTR_REG_RECEIVED 161*7c478bd9Sstevel@tonic-gate #define IB_INO_INTR_PEND(reg_p) *(reg_p) = COMMON_CLEAR_INTR_REG_PENDING 162*7c478bd9Sstevel@tonic-gate #define IB_INO_INTR_ISON(imr) ((imr) >> 31) 163*7c478bd9Sstevel@tonic-gate #define IB_IMR2MONDO(imr) \ 164*7c478bd9Sstevel@tonic-gate ((imr) & (COMMON_INTR_MAP_REG_IGN | COMMON_INTR_MAP_REG_INO)) 165*7c478bd9Sstevel@tonic-gate 166*7c478bd9Sstevel@tonic-gate #define IB_IS_OBIO_INO(ino) (ino & 0x20) 167*7c478bd9Sstevel@tonic-gate 168*7c478bd9Sstevel@tonic-gate #ifdef _STARFIRE 169*7c478bd9Sstevel@tonic-gate /* 170*7c478bd9Sstevel@tonic-gate * returns a uniq ino per interrupt mapping register 171*7c478bd9Sstevel@tonic-gate * For on board devices, inos are not shared. But for plugin devices, 172*7c478bd9Sstevel@tonic-gate * return the 1st ino of the 4 that are sharing the same mapping register. 173*7c478bd9Sstevel@tonic-gate */ 174*7c478bd9Sstevel@tonic-gate #define IB_GET_MAPREG_INO(ino) \ 175*7c478bd9Sstevel@tonic-gate ((volatile uint64_t *)((ino & 0x20) ? ino : ((ino >> 2) << 2))) 176*7c478bd9Sstevel@tonic-gate #endif /* _STARFIRE */ 177*7c478bd9Sstevel@tonic-gate 178*7c478bd9Sstevel@tonic-gate #define IB_IGN_TO_MONDO(ign, ino) (((ign) << PCI_INO_BITS) | (ino)) 179*7c478bd9Sstevel@tonic-gate #define IB_INO_TO_MONDO(ib_p, ino) IB_IGN_TO_MONDO((ib_p)->ib_ign, ino) 180*7c478bd9Sstevel@tonic-gate 181*7c478bd9Sstevel@tonic-gate extern void ib_create(pci_t *pci_p); 182*7c478bd9Sstevel@tonic-gate extern void ib_destroy(pci_t *pci_p); 183*7c478bd9Sstevel@tonic-gate extern void ib_configure(ib_t *ib_p); 184*7c478bd9Sstevel@tonic-gate extern uint64_t ib_get_map_reg(ib_mondo_t mondo, uint32_t cpu_id); 185*7c478bd9Sstevel@tonic-gate extern void ib_intr_enable(pci_t *pci_p, ib_ino_t ino); 186*7c478bd9Sstevel@tonic-gate extern void ib_intr_disable(ib_t *ib_p, ib_ino_t ino, int wait); 187*7c478bd9Sstevel@tonic-gate extern void ib_nintr_clear(ib_t *ib_p, ib_ino_t ino); 188*7c478bd9Sstevel@tonic-gate extern void ib_suspend(ib_t *ib_p); 189*7c478bd9Sstevel@tonic-gate extern void ib_resume(ib_t *ib_p); 190*7c478bd9Sstevel@tonic-gate 191*7c478bd9Sstevel@tonic-gate extern ib_ino_info_t *ib_locate_ino(ib_t *ib_p, ib_ino_t ino_num); 192*7c478bd9Sstevel@tonic-gate extern ib_ino_info_t *ib_new_ino(ib_t *ib_p, ib_ino_t ino_num, ih_t *ih_p); 193*7c478bd9Sstevel@tonic-gate extern void ib_delete_ino(ib_t *ib_p, ib_ino_info_t *ino_p); 194*7c478bd9Sstevel@tonic-gate extern void ib_free_ino_all(ib_t *ib_p); 195*7c478bd9Sstevel@tonic-gate extern int ib_update_intr_state(pci_t *pci_p, dev_info_t *rdip, 196*7c478bd9Sstevel@tonic-gate ddi_intr_handle_impl_t *hdlp, uint_t new_intr_state); 197*7c478bd9Sstevel@tonic-gate extern void ib_ino_add_intr(pci_t *pci_p, ib_ino_info_t *ino_p, ih_t *ih_p); 198*7c478bd9Sstevel@tonic-gate extern void ib_ino_rem_intr(pci_t *pci_p, ib_ino_info_t *ino_p, ih_t *ih_p); 199*7c478bd9Sstevel@tonic-gate extern ih_t *ib_ino_locate_intr(ib_ino_info_t *ino_p, dev_info_t *dip, 200*7c478bd9Sstevel@tonic-gate uint32_t inum); 201*7c478bd9Sstevel@tonic-gate extern ih_t *ib_alloc_ih(dev_info_t *dip, uint32_t inum, 202*7c478bd9Sstevel@tonic-gate uint_t (*int_handler)(caddr_t int_handler_arg1, caddr_t int_handler_arg2), 203*7c478bd9Sstevel@tonic-gate caddr_t int_handler_arg1, caddr_t int_handler_arg2); 204*7c478bd9Sstevel@tonic-gate extern void ib_free_ih(ih_t *ih_p); 205*7c478bd9Sstevel@tonic-gate extern void ib_ino_map_reg_share(ib_t *ib_p, ib_ino_t ino, 206*7c478bd9Sstevel@tonic-gate ib_ino_info_t *ino_p); 207*7c478bd9Sstevel@tonic-gate extern int ib_ino_map_reg_unshare(ib_t *ib_p, ib_ino_t ino, 208*7c478bd9Sstevel@tonic-gate ib_ino_info_t *ino_p); 209*7c478bd9Sstevel@tonic-gate extern uint32_t ib_register_intr(ib_t *ib_p, ib_mondo_t mondo, uint_t pil, 210*7c478bd9Sstevel@tonic-gate uint_t (*handler)(caddr_t arg), caddr_t arg); 211*7c478bd9Sstevel@tonic-gate extern void ib_unregister_intr(ib_mondo_t mondo); 212*7c478bd9Sstevel@tonic-gate extern void ib_intr_dist_nintr(ib_t *ib_p, ib_ino_t ino, 213*7c478bd9Sstevel@tonic-gate volatile uint64_t *imr_p); 214*7c478bd9Sstevel@tonic-gate extern void ib_intr_dist_all(void *arg, int32_t max_weight, int32_t weight); 215*7c478bd9Sstevel@tonic-gate 216*7c478bd9Sstevel@tonic-gate extern int pci_pil[]; 217*7c478bd9Sstevel@tonic-gate 218*7c478bd9Sstevel@tonic-gate #ifdef __cplusplus 219*7c478bd9Sstevel@tonic-gate } 220*7c478bd9Sstevel@tonic-gate #endif 221*7c478bd9Sstevel@tonic-gate 222*7c478bd9Sstevel@tonic-gate #endif /* _SYS_PCI_IB_H */ 223