17c478bd9Sstevel@tonic-gate /* 27c478bd9Sstevel@tonic-gate * CDDL HEADER START 37c478bd9Sstevel@tonic-gate * 47c478bd9Sstevel@tonic-gate * The contents of this file are subject to the terms of the 57c478bd9Sstevel@tonic-gate * Common Development and Distribution License, Version 1.0 only 67c478bd9Sstevel@tonic-gate * (the "License"). You may not use this file except in compliance 77c478bd9Sstevel@tonic-gate * with the License. 87c478bd9Sstevel@tonic-gate * 97c478bd9Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 107c478bd9Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 117c478bd9Sstevel@tonic-gate * See the License for the specific language governing permissions 127c478bd9Sstevel@tonic-gate * and limitations under the License. 137c478bd9Sstevel@tonic-gate * 147c478bd9Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 157c478bd9Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 167c478bd9Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 177c478bd9Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 187c478bd9Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 197c478bd9Sstevel@tonic-gate * 207c478bd9Sstevel@tonic-gate * CDDL HEADER END 217c478bd9Sstevel@tonic-gate */ 227c478bd9Sstevel@tonic-gate /* 237c478bd9Sstevel@tonic-gate * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 247c478bd9Sstevel@tonic-gate * Use is subject to license terms. 257c478bd9Sstevel@tonic-gate */ 26*2a1fd0ffSPeter Tribble /* 27*2a1fd0ffSPeter Tribble * Copyright 2019 Peter Tribble. 28*2a1fd0ffSPeter Tribble */ 297c478bd9Sstevel@tonic-gate 307c478bd9Sstevel@tonic-gate #ifndef _SYS_MACHINTREG_H 317c478bd9Sstevel@tonic-gate #define _SYS_MACHINTREG_H 327c478bd9Sstevel@tonic-gate 337c478bd9Sstevel@tonic-gate #ifdef __cplusplus 347c478bd9Sstevel@tonic-gate extern "C" { 357c478bd9Sstevel@tonic-gate #endif 367c478bd9Sstevel@tonic-gate 377c478bd9Sstevel@tonic-gate /* 387c478bd9Sstevel@tonic-gate * Interrupt Receive Data Registers 397c478bd9Sstevel@tonic-gate * ASI_SDB_INTR_R or ASI_INTR_RECEIVE; ASI 0x7F; VA 0x40, 0x50, 0x60 407c478bd9Sstevel@tonic-gate */ 417c478bd9Sstevel@tonic-gate #define IRDR_0 0x40 427c478bd9Sstevel@tonic-gate #define IRDR_1 0x50 437c478bd9Sstevel@tonic-gate #define IRDR_2 0x60 447c478bd9Sstevel@tonic-gate 457c478bd9Sstevel@tonic-gate #define UIII_IRDR_0 0x40 467c478bd9Sstevel@tonic-gate #define UIII_IRDR_1 0x48 477c478bd9Sstevel@tonic-gate #define UIII_IRDR_2 0x50 487c478bd9Sstevel@tonic-gate #define UIII_IRDR_3 0x58 497c478bd9Sstevel@tonic-gate #define UIII_IRDR_4 0x60 507c478bd9Sstevel@tonic-gate #define UIII_IRDR_5 0x68 517c478bd9Sstevel@tonic-gate #define UIII_IRDR_6 0x80 527c478bd9Sstevel@tonic-gate #define UIII_IRDR_7 0x88 537c478bd9Sstevel@tonic-gate 547c478bd9Sstevel@tonic-gate /* 557c478bd9Sstevel@tonic-gate * Interrupt Receive Status Register 567c478bd9Sstevel@tonic-gate * ASI_INTR_RECEIVE_STATUS; ASI 0x49; VA 0x0 577c478bd9Sstevel@tonic-gate * 587c478bd9Sstevel@tonic-gate * |---------------------------------------------------| 597c478bd9Sstevel@tonic-gate * | RESERVED (Read as 0) | BUSY | PORTID | 607c478bd9Sstevel@tonic-gate * |--------------------------------|------|-----------| 617c478bd9Sstevel@tonic-gate * 63 6 5 4 0 627c478bd9Sstevel@tonic-gate * 637c478bd9Sstevel@tonic-gate */ 647c478bd9Sstevel@tonic-gate #define IRSR_BUSY 0x20 /* set when there's a vector received */ 657c478bd9Sstevel@tonic-gate #define IRSR_PID_MASK 0x1F /* PORTID bit mask <4:0> */ 667c478bd9Sstevel@tonic-gate 677c478bd9Sstevel@tonic-gate /* 687c478bd9Sstevel@tonic-gate * Interrupt Dispatch Data Register 697c478bd9Sstevel@tonic-gate * ASI_SDB_INTR_W or ASI_INTR_DISPATCH; ASI 0x77; VA 0x40, 0x50, 0x60 707c478bd9Sstevel@tonic-gate */ 717c478bd9Sstevel@tonic-gate #define IDDR_0 0x40 727c478bd9Sstevel@tonic-gate #define IDDR_1 0x50 737c478bd9Sstevel@tonic-gate #define IDDR_2 0x60 747c478bd9Sstevel@tonic-gate 757c478bd9Sstevel@tonic-gate #define UIII_IDDR_0 0x40 767c478bd9Sstevel@tonic-gate #define UIII_IDDR_1 0x48 777c478bd9Sstevel@tonic-gate #define UIII_IDDR_2 0x50 787c478bd9Sstevel@tonic-gate #define UIII_IDDR_3 0x58 797c478bd9Sstevel@tonic-gate #define UIII_IDDR_4 0x60 807c478bd9Sstevel@tonic-gate #define UIII_IDDR_5 0x68 817c478bd9Sstevel@tonic-gate #define UIII_IDDR_6 0x80 827c478bd9Sstevel@tonic-gate #define UIII_IDDR_7 0x88 837c478bd9Sstevel@tonic-gate 847c478bd9Sstevel@tonic-gate #if defined(JALAPENO) || defined(SERRANO) 857c478bd9Sstevel@tonic-gate /* 867c478bd9Sstevel@tonic-gate * Interrupt Dispatch Command Register 877c478bd9Sstevel@tonic-gate * ASI_INTR_DISPATCH or ASI_SDB_INTR_W; ASI 0x77; VA = PORTID<<14|0x70 887c478bd9Sstevel@tonic-gate * 897c478bd9Sstevel@tonic-gate * |------------------------------------------------| 907c478bd9Sstevel@tonic-gate * | 0 | PORTID & BUSY/NACK | 0x70 | 917c478bd9Sstevel@tonic-gate * |---------|-----------------------|--------------| 927c478bd9Sstevel@tonic-gate * 63 19 18 14 13 0 937c478bd9Sstevel@tonic-gate */ 947c478bd9Sstevel@tonic-gate #define IDCR_OFFSET 0x70 /* IDCR VA<13:0> */ 957c478bd9Sstevel@tonic-gate #define IDCR_PID_SHIFT 14 967c478bd9Sstevel@tonic-gate #define IDCR_BN_SHIFT 14 /* JBUS only */ 977c478bd9Sstevel@tonic-gate #define IDCR_BN_MASK 0x3 /* JBUS only */ 987c478bd9Sstevel@tonic-gate #else /* (JALAPENO || SERRANO) */ 997c478bd9Sstevel@tonic-gate /* 1007c478bd9Sstevel@tonic-gate * Interrupt Dispatch Command Register 1017c478bd9Sstevel@tonic-gate * ASI_INTR_DISPATCH or ASI_SDB_INTR_W; ASI 0x77; VA = PORTID<<14|0x70 1027c478bd9Sstevel@tonic-gate * 1037c478bd9Sstevel@tonic-gate * |------------------------------------------------| 1047c478bd9Sstevel@tonic-gate * | 0 | BUSY/NACK | PORTID | 0x70 | 1057c478bd9Sstevel@tonic-gate * |---------|-----------|-----------|--------------| 1067c478bd9Sstevel@tonic-gate * 63 29 28 24 23 14 13 0 1077c478bd9Sstevel@tonic-gate */ 1087c478bd9Sstevel@tonic-gate #define IDCR_OFFSET 0x70 /* IDCR VA<13:0> */ 1097c478bd9Sstevel@tonic-gate #define IDCR_PID_SHIFT 14 1107c478bd9Sstevel@tonic-gate #define IDCR_BN_SHIFT 24 /* safari only */ 1117c478bd9Sstevel@tonic-gate #endif /* (JALAPENO || SERRANO) */ 1127c478bd9Sstevel@tonic-gate 1137c478bd9Sstevel@tonic-gate /* 1147c478bd9Sstevel@tonic-gate * Interrupt Dispatch Status Register 1157c478bd9Sstevel@tonic-gate * ASI_INTR_DISPATCH_STATUS; ASI 0x48; VA 0x0 1167c478bd9Sstevel@tonic-gate * 1177c478bd9Sstevel@tonic-gate * |---------------------------------------------------| 1187c478bd9Sstevel@tonic-gate * | RESERVED (Read as 0) | NACK | BUSY | 1197c478bd9Sstevel@tonic-gate * |-----------------------------------|-------|-------| 1207c478bd9Sstevel@tonic-gate * 63 2 1 0 | 1217c478bd9Sstevel@tonic-gate */ 1227c478bd9Sstevel@tonic-gate #define IDSR_NACK 0x2 /* set if interrupt dispatch failed */ 1237c478bd9Sstevel@tonic-gate #define IDSR_BUSY 0x1 /* set when there's a dispatch */ 1247c478bd9Sstevel@tonic-gate 1257c478bd9Sstevel@tonic-gate /* 1267c478bd9Sstevel@tonic-gate * Safari systems define IDSR as 32 busy/nack pairs 1277c478bd9Sstevel@tonic-gate */ 1287c478bd9Sstevel@tonic-gate #if defined(JALAPENO) || defined(SERRANO) 1297c478bd9Sstevel@tonic-gate #define IDSR_BN_SETS 4 1307c478bd9Sstevel@tonic-gate #define CPUID_TO_BN_PAIR(x) ((x) & (IDSR_BN_SETS-1)) 1317c478bd9Sstevel@tonic-gate #else /* (JALAPENO || SERRANO) */ 1327c478bd9Sstevel@tonic-gate #define IDSR_BN_SETS 32 1337c478bd9Sstevel@tonic-gate #endif /* (JALAPENO || SERRANO) */ 1347c478bd9Sstevel@tonic-gate #define IDSR_NACK_BIT(i) ((uint64_t)IDSR_NACK << (2 * (i))) 1357c478bd9Sstevel@tonic-gate #define IDSR_BUSY_BIT(i) ((uint64_t)IDSR_BUSY << (2 * (i))) 1367c478bd9Sstevel@tonic-gate #define IDSR_NACK_TO_BUSY(n) ((n) >> 1) 1377c478bd9Sstevel@tonic-gate #define IDSR_BUSY_TO_NACK(n) ((n) << 1) 1387c478bd9Sstevel@tonic-gate #define IDSR_NACK_IDX(bit) (((bit) - 1) / 2) 1397c478bd9Sstevel@tonic-gate #define IDSR_BUSY_IDX(bit) ((bit) / 2) 1407c478bd9Sstevel@tonic-gate 1417c478bd9Sstevel@tonic-gate /* 1427c478bd9Sstevel@tonic-gate * Interrupt Number Register 1437c478bd9Sstevel@tonic-gate * Every interrupt source has a register associated with it 1447c478bd9Sstevel@tonic-gate * 1457c478bd9Sstevel@tonic-gate * |---------------------------------------------------| 1467c478bd9Sstevel@tonic-gate * |INT_EN | PORTID |RESERVED (Read as 0)| INT_NUMBER| 1477c478bd9Sstevel@tonic-gate * | | | | IGN | INO | 1487c478bd9Sstevel@tonic-gate * |-------|----------|--------------------|-----|-----| 1497c478bd9Sstevel@tonic-gate * | 31 30 26 25 11 10 6 5 0 1507c478bd9Sstevel@tonic-gate */ 1517c478bd9Sstevel@tonic-gate #define INR_EN_SHIFT 31 1527c478bd9Sstevel@tonic-gate #define INR_PID_SHIFT 26 1537c478bd9Sstevel@tonic-gate #define INR_PID_MASK (IRSR_PID_MASK << (INR_PID_SHIFT)) 1547c478bd9Sstevel@tonic-gate /* 1557c478bd9Sstevel@tonic-gate * IGN_SIZE can be defined in a platform's makefile. If it is not defined, 1567c478bd9Sstevel@tonic-gate * use a default of 5. 1577c478bd9Sstevel@tonic-gate */ 1587c478bd9Sstevel@tonic-gate #ifndef IGN_SIZE 1597c478bd9Sstevel@tonic-gate #define IGN_SIZE 5 /* Interrupt Group Number bit size */ 1607c478bd9Sstevel@tonic-gate #endif 1617c478bd9Sstevel@tonic-gate #define UPAID_TO_IGN(upaid) (upaid) 1627c478bd9Sstevel@tonic-gate 1637c478bd9Sstevel@tonic-gate #define IR_CPU_CLEAR 0x4 /* clear pending register for cpu */ 1647c478bd9Sstevel@tonic-gate #define IR_MASK_OFFSET 0x4 1657c478bd9Sstevel@tonic-gate #define IR_SET_ITR 0x10 1667c478bd9Sstevel@tonic-gate #define IR_SOFT_INT(n) (0x000010000 << (n)) 1677c478bd9Sstevel@tonic-gate #define IR_SOFT_INT4 IR_SOFT_INT(4) /* r/w - software level 4 interrupt */ 1687c478bd9Sstevel@tonic-gate #define IR_CPU_SOFTINT 0x8 /* set soft interrupt for cpu */ 1697c478bd9Sstevel@tonic-gate #define IR_CLEAR_OFFSET 0x8 1707c478bd9Sstevel@tonic-gate 1717c478bd9Sstevel@tonic-gate 1727c478bd9Sstevel@tonic-gate #ifdef __cplusplus 1737c478bd9Sstevel@tonic-gate } 1747c478bd9Sstevel@tonic-gate #endif 1757c478bd9Sstevel@tonic-gate 1767c478bd9Sstevel@tonic-gate #endif /* _SYS_MACHINTREG_H */ 177