xref: /illumos-gate/usr/src/uts/sun4u/sys/cpudrv_mach.h (revision 0e751525)
15cff7825Smh /*
25cff7825Smh  * CDDL HEADER START
35cff7825Smh  *
45cff7825Smh  * The contents of this file are subject to the terms of the
55cff7825Smh  * Common Development and Distribution License (the "License").
65cff7825Smh  * You may not use this file except in compliance with the License.
75cff7825Smh  *
85cff7825Smh  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
95cff7825Smh  * or http://www.opensolaris.org/os/licensing.
105cff7825Smh  * See the License for the specific language governing permissions
115cff7825Smh  * and limitations under the License.
125cff7825Smh  *
135cff7825Smh  * When distributing Covered Code, include this CDDL HEADER in each
145cff7825Smh  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
155cff7825Smh  * If applicable, add the following below this CDDL HEADER, with the
165cff7825Smh  * fields enclosed by brackets "[]" replaced with your own identifying
175cff7825Smh  * information: Portions Copyright [yyyy] [name of copyright owner]
185cff7825Smh  *
195cff7825Smh  * CDDL HEADER END
205cff7825Smh  */
215cff7825Smh /*
22*0e751525SEric Saxe  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
235cff7825Smh  * Use is subject to license terms.
245cff7825Smh  */
255cff7825Smh 
267f606aceSMark Haywood #ifndef _SYS_CPUDRV_MACH_H
277f606aceSMark Haywood #define	_SYS_CPUDRV_MACH_H
285cff7825Smh 
295cff7825Smh #include <sys/cpu_module.h>
307f606aceSMark Haywood #include <sys/cpudrv.h>
315cff7825Smh 
325cff7825Smh #ifdef  __cplusplus
335cff7825Smh extern "C" {
345cff7825Smh #endif
355cff7825Smh 
365cff7825Smh /*
375cff7825Smh  * We currently refuse to power manage if the CPU in not ready to
385cff7825Smh  * take cross calls (cross calls fail silently if CPU is not ready
395cff7825Smh  * for it).
405cff7825Smh  */
41*0e751525SEric Saxe #define	CPUDRV_XCALL_IS_READY(cpuid) (CPU_XCALL_READY(cpuid))
425cff7825Smh 
435cff7825Smh /*
447f606aceSMark Haywood  * Currently, there is no governor on sun4u,
455cff7825Smh  */
46*0e751525SEric Saxe #define	CPUDRV_RESET_GOVERNOR_THREAD(cpupm)
475cff7825Smh 
485cff7825Smh /*
497f606aceSMark Haywood  * Currently, there is no need for a handler on sun4u.
505cff7825Smh  */
51*0e751525SEric Saxe #define	CPUDRV_INSTALL_MAX_CHANGE_HANDLER(cpuid)
525cff7825Smh 
5317353130SMark Haywood /*
5417353130SMark Haywood  * Topspeed is always the head speed.
5517353130SMark Haywood  */
56*0e751525SEric Saxe #define	CPUDRV_TOPSPEED(cpupm)	(cpupm)->head_spd
5717353130SMark Haywood 
585cff7825Smh /*
597f606aceSMark Haywood  * There is no notion of changing topspeed on sun4u.
605cff7825Smh  */
61*0e751525SEric Saxe #define	CPUDRV_REDEFINE_TOPSPEED(dip)
625cff7825Smh 
635cff7825Smh /*
647f606aceSMark Haywood  * There are no PPM callbacks for sun4u.
655cff7825Smh  */
66*0e751525SEric Saxe #define	CPUDRV_SET_PPM_CALLBACKS()
675cff7825Smh 
685cff7825Smh /*
695cff7825Smh  * clock-divisors property tells the supported speeds
705cff7825Smh  * as divisors of the normal speed. Divisors are in increasing
715cff7825Smh  * order starting with 1 (for normal speed). For example, a
725cff7825Smh  * property value of "1, 2, 32" represents full, 1/2 and 1/32
735cff7825Smh  * speeds.
745cff7825Smh  */
75*0e751525SEric Saxe #define	CPUDRV_GET_SPEEDS(cpudsp, speeds, nspeeds) { \
765cff7825Smh 	if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, cpudsp->dip, \
775cff7825Smh 	    DDI_PROP_DONTPASS, "clock-divisors", &speeds, \
785cff7825Smh 	    &nspeeds) != DDI_PROP_SUCCESS) { \
79*0e751525SEric Saxe 		nspeeds = 0; \
80*0e751525SEric Saxe 		DPRINTF(D_PM_INIT, ("cpudrv_init: instance %d: " \
815cff7825Smh 		    "clock-divisors property not defined\n", \
82*0e751525SEric Saxe 		    ddi_get_instance(cpudsp->dip))); \
835cff7825Smh 	} \
845cff7825Smh }
85*0e751525SEric Saxe #define	CPUDRV_FREE_SPEEDS(speeds, nspeeds) { \
86*0e751525SEric Saxe 	if (nspeeds > 0) \
87*0e751525SEric Saxe 		ddi_prop_free(speeds); \
88*0e751525SEric Saxe }
895cff7825Smh 
905cff7825Smh /*
915cff7825Smh  * Convert speed to Hz.
925cff7825Smh  */
93*0e751525SEric Saxe #define	CPUDRV_SPEED_HZ(mhz, divisor) (((uint64_t)mhz * 1000000) / divisor)
945cff7825Smh 
955cff7825Smh /*
965cff7825Smh  * Compute the idle cnt percentage for a given speed.
975cff7825Smh  */
98*0e751525SEric Saxe #define	CPUDRV_IDLE_CNT_PERCENT(hwm, speeds, i) \
995cff7825Smh 	(100 - ((100 - hwm) * speeds[i]))
1005cff7825Smh 
1015cff7825Smh /*
1025cff7825Smh  * Compute the user cnt percentage for a given speed.
1035cff7825Smh  */
104*0e751525SEric Saxe #define	CPUDRV_USER_CNT_PERCENT(hwm, speeds, i) \
1055cff7825Smh 	((hwm * speeds[i - 1]) / speeds[i])
1065cff7825Smh 
1075cff7825Smh /*
1087f606aceSMark Haywood  * pm-components property defintions for sun4u.
1095cff7825Smh  *
1105cff7825Smh  * Fully constructed pm-components property should be an array of
1115cff7825Smh  * strings that look something like:
1125cff7825Smh  *
1135cff7825Smh  * pmc[0] = "NAME=CPU Speed"
1145cff7825Smh  * pmc[1] = "1=1/32 of Normal"
1155cff7825Smh  * pmc[2] = "2=1/2 of Normal"
1165cff7825Smh  * pmc[3] = "3=Normal"
1175cff7825Smh  *
1185cff7825Smh  * The amount of memory needed for each string is:
1195cff7825Smh  *      digits for power level + '=' + '1/' + digits for speed +
1205cff7825Smh  *      description text + '\0'
1215cff7825Smh  */
122*0e751525SEric Saxe #define	CPUDRV_COMP_NORMAL "Normal"
123*0e751525SEric Saxe #define	CPUDRV_COMP_OTHER " of Normal"
124*0e751525SEric Saxe #define	CPUDRV_COMP_SIZE() \
125*0e751525SEric Saxe 	(CPUDRV_COMP_MAX_DIG + 1 + 2 + CPUDRV_COMP_MAX_DIG + \
126*0e751525SEric Saxe 	    sizeof (CPUDRV_COMP_OTHER) + 1);
127*0e751525SEric Saxe #define	CPUDRV_COMP_SPEED(cpupm, cur_spd) \
1285cff7825Smh 	((cur_spd == cpupm->head_spd) ? cur_spd->pm_level : cur_spd->speed)
129*0e751525SEric Saxe #define	CPUDRV_COMP_SPRINT(pmc, cpupm, cur_spd, comp_spd) { \
1305cff7825Smh 	if (cur_spd == cpupm->head_spd) \
131*0e751525SEric Saxe 		(void) sprintf(pmc, "%d=%s", comp_spd, CPUDRV_COMP_NORMAL);\
1325cff7825Smh 	else \
1335cff7825Smh 		(void) sprintf(pmc, "%d=1/%d%s", cur_spd->pm_level, \
134*0e751525SEric Saxe 		    comp_spd, CPUDRV_COMP_OTHER); \
1355cff7825Smh }
1365cff7825Smh 
1375cff7825Smh #ifdef  __cplusplus
1385cff7825Smh }
1395cff7825Smh #endif
1405cff7825Smh 
1417f606aceSMark Haywood #endif /* _SYS_CPUDRV_MACH_H */
142