xref: /illumos-gate/usr/src/uts/sun4u/sys/cheetahregs.h (revision 7bebe46c)
17c478bd9Sstevel@tonic-gate /*
27c478bd9Sstevel@tonic-gate  * CDDL HEADER START
37c478bd9Sstevel@tonic-gate  *
47c478bd9Sstevel@tonic-gate  * The contents of this file are subject to the terms of the
525cf1a30Sjl  * Common Development and Distribution License (the "License").
625cf1a30Sjl  * You may not use this file except in compliance with the License.
77c478bd9Sstevel@tonic-gate  *
87c478bd9Sstevel@tonic-gate  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
97c478bd9Sstevel@tonic-gate  * or http://www.opensolaris.org/os/licensing.
107c478bd9Sstevel@tonic-gate  * See the License for the specific language governing permissions
117c478bd9Sstevel@tonic-gate  * and limitations under the License.
127c478bd9Sstevel@tonic-gate  *
137c478bd9Sstevel@tonic-gate  * When distributing Covered Code, include this CDDL HEADER in each
147c478bd9Sstevel@tonic-gate  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
157c478bd9Sstevel@tonic-gate  * If applicable, add the following below this CDDL HEADER, with the
167c478bd9Sstevel@tonic-gate  * fields enclosed by brackets "[]" replaced with your own identifying
177c478bd9Sstevel@tonic-gate  * information: Portions Copyright [yyyy] [name of copyright owner]
187c478bd9Sstevel@tonic-gate  *
197c478bd9Sstevel@tonic-gate  * CDDL HEADER END
207c478bd9Sstevel@tonic-gate  */
217c478bd9Sstevel@tonic-gate /*
22a4673f2eSss  * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
237c478bd9Sstevel@tonic-gate  * Use is subject to license terms.
247c478bd9Sstevel@tonic-gate  */
257c478bd9Sstevel@tonic-gate 
267c478bd9Sstevel@tonic-gate #ifndef _SYS_CHEETAHREGS_H
277c478bd9Sstevel@tonic-gate #define	_SYS_CHEETAHREGS_H
287c478bd9Sstevel@tonic-gate 
297c478bd9Sstevel@tonic-gate #pragma ident	"%Z%%M%	%I%	%E% SMI"
307c478bd9Sstevel@tonic-gate 
317c478bd9Sstevel@tonic-gate #include <sys/machasi.h>
3225cf1a30Sjl #include <sys/cpu_impl.h>
337c478bd9Sstevel@tonic-gate #ifdef _KERNEL
347c478bd9Sstevel@tonic-gate #include <sys/fpras.h>
357c478bd9Sstevel@tonic-gate #endif /* _KERNEL */
367c478bd9Sstevel@tonic-gate 
377c478bd9Sstevel@tonic-gate /*
387c478bd9Sstevel@tonic-gate  * This file is cpu dependent.
397c478bd9Sstevel@tonic-gate  */
407c478bd9Sstevel@tonic-gate 
417c478bd9Sstevel@tonic-gate #ifdef	__cplusplus
427c478bd9Sstevel@tonic-gate extern "C" {
437c478bd9Sstevel@tonic-gate #endif
447c478bd9Sstevel@tonic-gate 
457c478bd9Sstevel@tonic-gate /*
467c478bd9Sstevel@tonic-gate  * Cheetah includes the process info in its mask to make things
477c478bd9Sstevel@tonic-gate  * more difficult.  The process is the low bit of the major mask,
487c478bd9Sstevel@tonic-gate  * so to convert to the netlist major:
497c478bd9Sstevel@tonic-gate  * netlist_major = ((mask_major >> 1) + 1)
507c478bd9Sstevel@tonic-gate  */
517c478bd9Sstevel@tonic-gate #define	REMAP_CHEETAH_MASK(x)	(((((x) >> 1) + 0x10) & 0xf0) | ((x) & 0xf))
527c478bd9Sstevel@tonic-gate 
537c478bd9Sstevel@tonic-gate #ifdef _ASM
547c478bd9Sstevel@tonic-gate /*
557c478bd9Sstevel@tonic-gate  * assembler doesn't understand the 'ull' suffix for C constants so
567c478bd9Sstevel@tonic-gate  * use the inttypes.h macros and undefine them here for assembly code
577c478bd9Sstevel@tonic-gate  */
587c478bd9Sstevel@tonic-gate #undef INT64_C
597c478bd9Sstevel@tonic-gate #undef UINT64_C
607c478bd9Sstevel@tonic-gate #define	INT64_C(x)	(x)
617c478bd9Sstevel@tonic-gate #define	UINT64_C(x)	(x)
627c478bd9Sstevel@tonic-gate #endif	/* _ASM */
637c478bd9Sstevel@tonic-gate 
647c478bd9Sstevel@tonic-gate /*
657c478bd9Sstevel@tonic-gate  * DCU Control Register
667c478bd9Sstevel@tonic-gate  *
677c478bd9Sstevel@tonic-gate  * +------+----+----+----+----+----+-----+-----+----+----+----+
687c478bd9Sstevel@tonic-gate  * | Resv | CP | CV | ME | RE | PE | HPE | SPE | SL | WE | PM |
697c478bd9Sstevel@tonic-gate  * +------+----+----+----+----+----+-----+-----+----+----+----+
707c478bd9Sstevel@tonic-gate  *  63:50   49   48   47   46	45    44    43   42   41 40:33
717c478bd9Sstevel@tonic-gate  *
727c478bd9Sstevel@tonic-gate  * +----+----+----+----+----+----------+-----+----+----+----+---+
737c478bd9Sstevel@tonic-gate  * | VM | PR | PW | VR | VW | Reserved | WIH | DM | IM | DC | IC|
747c478bd9Sstevel@tonic-gate  * +----+----+----+----+----+----------+-----+----+----+----+---+
757c478bd9Sstevel@tonic-gate  * 32:25  24   23   22   21      20:5     4     3    2    1   0
767c478bd9Sstevel@tonic-gate  */
777c478bd9Sstevel@tonic-gate 
787c478bd9Sstevel@tonic-gate #define	ASI_DCU	ASI_LSU			    /* same as spitfire ASI_LSU 0x45 */
797c478bd9Sstevel@tonic-gate #define	DCU_IC	INT64_C(0x0000000000000001) /* icache enable		*/
807c478bd9Sstevel@tonic-gate #define	DCU_DC	INT64_C(0x0000000000000002) /* dcache enable		*/
817c478bd9Sstevel@tonic-gate #define	DCU_IM	INT64_C(0x0000000000000004) /* immu enable		*/
827c478bd9Sstevel@tonic-gate #define	DCU_DM	INT64_C(0x0000000000000008) /* dmmu enable		*/
837c478bd9Sstevel@tonic-gate #define	DCU_WIH	INT64_C(0x0000000000000010) /* Jaguar only - W$ hash index */
847c478bd9Sstevel@tonic-gate #define	DCU_VW	INT64_C(0x0000000000200000) /* virt watchpoint write enable  */
857c478bd9Sstevel@tonic-gate #define	DCU_VR	INT64_C(0x0000000000400000) /* virt watchpoint read enable   */
867c478bd9Sstevel@tonic-gate #define	DCU_PW	INT64_C(0x0000000000800000) /* phys watchpoint write enable  */
877c478bd9Sstevel@tonic-gate #define	DCU_PR	INT64_C(0x0000000001000000) /* phys watchpoint read enable   */
887c478bd9Sstevel@tonic-gate #define	DCU_VM	INT64_C(0x00000001FE000000) /* virtual watchpoint write mask */
897c478bd9Sstevel@tonic-gate #define	DCU_PM	INT64_C(0x000001FE00000000) /* phys watchpoint write mask    */
907c478bd9Sstevel@tonic-gate #define	DCU_WE	INT64_C(0x0000020000000000) /* write cache enable	*/
917c478bd9Sstevel@tonic-gate #define	DCU_SL	INT64_C(0x0000040000000000) /* second load control	*/
927c478bd9Sstevel@tonic-gate #define	DCU_SPE	INT64_C(0x0000080000000000) /* software prefetch enable */
937c478bd9Sstevel@tonic-gate #define	DCU_HPE	INT64_C(0x0000100000000000) /* hardware prefetch enable */
947c478bd9Sstevel@tonic-gate #define	DCU_PE	INT64_C(0x0000200000000000) /* prefetch enable		*/
957c478bd9Sstevel@tonic-gate #define	DCU_RE	INT64_C(0x0000400000000000) /* RAW bypass enable	*/
967c478bd9Sstevel@tonic-gate #define	DCU_ME	INT64_C(0x0000800000000000) /* noncache store merging enable */
977c478bd9Sstevel@tonic-gate #define	DCU_CV	INT64_C(0x0001000000000000) /* virt cacheability when DM=0   */
987c478bd9Sstevel@tonic-gate #define	DCU_CP	INT64_C(0x0002000000000000) /* phys cacheable when DM,IM=0   */
997c478bd9Sstevel@tonic-gate #define	DCU_CACHE (DCU_IC|DCU_DC|DCU_WE|DCU_SPE|DCU_HPE|DCU_PE)
100*7bebe46cSjc #define	DCU_IPS_MASK	INT64_C(0x0030000000000000)
1017c478bd9Sstevel@tonic-gate 
1027c478bd9Sstevel@tonic-gate /*
1037c478bd9Sstevel@tonic-gate  * bit shifts for the prefetch enable bit
1047c478bd9Sstevel@tonic-gate  */
1057c478bd9Sstevel@tonic-gate #define	DCU_PE_SHIFT	45
1067c478bd9Sstevel@tonic-gate 
1077c478bd9Sstevel@tonic-gate /*
1087c478bd9Sstevel@tonic-gate  * Safari Configuration Register
1097c478bd9Sstevel@tonic-gate  */
1107c478bd9Sstevel@tonic-gate #define	ASI_SAFARI_CONFIG	ASI_UPA_CONFIG /* Safari Config Reg, 0x4A */
1117c478bd9Sstevel@tonic-gate #define	SAFARI_CONFIG_ECLK_1	INT64_C(0x0000000000000000) /* 1/1 clock */
1127c478bd9Sstevel@tonic-gate #define	SAFARI_CONFIG_ECLK_1_DIV	1	/* clock divisor: 1 */
1137c478bd9Sstevel@tonic-gate #define	SAFARI_CONFIG_ECLK_2	INT64_C(0x0000000040000000) /* 1/2 clock */
1147c478bd9Sstevel@tonic-gate #define	SAFARI_CONFIG_ECLK_2_DIV	2	/* clock divisor: 2 */
1157c478bd9Sstevel@tonic-gate #define	SAFARI_CONFIG_ECLK_32	INT64_C(0x0000000080000000) /* 1/32 clock */
1167c478bd9Sstevel@tonic-gate #define	SAFARI_CONFIG_ECLK_32_DIV	32	/* clock divisor: 32 */
1177c478bd9Sstevel@tonic-gate #define	SAFARI_CONFIG_ECLK_MASK	(SAFARI_CONFIG_ECLK_32 | SAFARI_CONFIG_ECLK_2)
1187c478bd9Sstevel@tonic-gate 
1197c478bd9Sstevel@tonic-gate #if defined(JALAPENO) || defined(SERRANO)
1207c478bd9Sstevel@tonic-gate /*
1217c478bd9Sstevel@tonic-gate  * JBUS Configuration Register
1227c478bd9Sstevel@tonic-gate  */
1237c478bd9Sstevel@tonic-gate #define	ASI_JBUS_CONFIG		ASI_UPA_CONFIG /* JBUS Config Reg, 0x4A */
1247c478bd9Sstevel@tonic-gate #define	JBUS_CONFIG_ECLK_1	INT64_C(0x0000000000000000) /* 1/1 clock */
1257c478bd9Sstevel@tonic-gate #define	JBUS_CONFIG_ECLK_1_DIV	1	/* clock divisor: 1 */
1267c478bd9Sstevel@tonic-gate #define	JBUS_CONFIG_ECLK_2	INT64_C(0x0000000000002000) /* 1/2 clock */
1277c478bd9Sstevel@tonic-gate #define	JBUS_CONFIG_ECLK_2_DIV	2	/* clock divisor: 2 */
1287c478bd9Sstevel@tonic-gate #define	JBUS_CONFIG_ECLK_32	INT64_C(0x0000000000004000) /* 1/32 clock */
1297c478bd9Sstevel@tonic-gate #define	JBUS_CONFIG_ECLK_32_DIV	32	/* clock divisor: 32 */
1307c478bd9Sstevel@tonic-gate #define	JBUS_CONFIG_ECLK_MASK	(JBUS_CONFIG_ECLK_32 | JBUS_CONFIG_ECLK_2)
1317c478bd9Sstevel@tonic-gate #define	JBUS_CONFIG_ECLK_SHIFT	13
1327c478bd9Sstevel@tonic-gate 
1337c478bd9Sstevel@tonic-gate /*
1347c478bd9Sstevel@tonic-gate  * Jalapeno/Serrano MCU control registers and ASI
1357c478bd9Sstevel@tonic-gate  */
1367c478bd9Sstevel@tonic-gate #define	ASI_MCU_CTRL		0x72		/* MCU Control Reg ASI */
1377c478bd9Sstevel@tonic-gate #define	JP_MCU_FSM_MASK		INT64_C(0x0000000006000000) /* 26..25 */
1387c478bd9Sstevel@tonic-gate #define	JP_MCU_FSM_SHIFT	25
1397c478bd9Sstevel@tonic-gate #endif /* JALAPENO || SERRANO */
1407c478bd9Sstevel@tonic-gate 
1417c478bd9Sstevel@tonic-gate #if defined(SERRANO)
1427c478bd9Sstevel@tonic-gate #define	ASI_MCU_AFAR2_VA	0x18	/* captures FRC/FRU addr */
1437c478bd9Sstevel@tonic-gate #endif	/* SERRANO */
1447c478bd9Sstevel@tonic-gate 
1457c478bd9Sstevel@tonic-gate #if defined(JALAPENO) && defined(JALAPENO_ERRATA_85)
1467c478bd9Sstevel@tonic-gate /*
1477c478bd9Sstevel@tonic-gate  * Tomatillo Estar control registers (for JP Errataum 85)
1487c478bd9Sstevel@tonic-gate  */
1497c478bd9Sstevel@tonic-gate #define	JBUS_SLAVE_T_PORT_BIT	48
1507c478bd9Sstevel@tonic-gate #define	TOM_HIGH_PA		0x400		/* Hi 32 bit of Tom reg PA */
1517c478bd9Sstevel@tonic-gate #define	M_T_ESTAR_CTRL_PA	0x0f410050	/* M T estar PA */
1527c478bd9Sstevel@tonic-gate #define	S_T_ESTAR_CTRL_PA	0x0e410050	/* S T estar PA */
1537c478bd9Sstevel@tonic-gate #define	M_T_J_CHNG_INIT_PA	0x0f410058	/* Master T estar PA */
1547c478bd9Sstevel@tonic-gate #define	TOM_ESTAR_ELCK_MASK	0x23		/* bit 5,1,0 */
1557c478bd9Sstevel@tonic-gate #define	TOM_FULL_SPEED		0x1
1567c478bd9Sstevel@tonic-gate #define	TOM_HALF_SPEED		0x2
1577c478bd9Sstevel@tonic-gate #define	TOM_SLOW_SPEED		0x20
1587c478bd9Sstevel@tonic-gate #define	TOM_TRIGGER_MASK	0x18
1597c478bd9Sstevel@tonic-gate #define	TOM_TRIGGER		0x10
1607c478bd9Sstevel@tonic-gate 
1617c478bd9Sstevel@tonic-gate #endif /* JALAPENO && JALAPENO_ERRATA_85 */
1627c478bd9Sstevel@tonic-gate 
1637c478bd9Sstevel@tonic-gate 
1647c478bd9Sstevel@tonic-gate /*
1657c478bd9Sstevel@tonic-gate  * Miscellaneous ASI definitions not in machasi.h
1667c478bd9Sstevel@tonic-gate  */
1677c478bd9Sstevel@tonic-gate #define	ASI_DC_UTAG		0x43	/* Dcache Microtag Fields */
1687c478bd9Sstevel@tonic-gate #define	ASI_DC_SNP_TAG		0x44	/* Dcache Snoop Tag Fields */
1697c478bd9Sstevel@tonic-gate #define	ASI_IC_SNP_TAG		0x68	/* Icache Snoop Tag Fields */
1707c478bd9Sstevel@tonic-gate #define	ASI_IPB_DATA		0x69	/* Instruction Prefetch Buffer Data */
1717c478bd9Sstevel@tonic-gate #define	ASI_IPB_TAG		0x6A	/* Instruction Prefetch Buffer Tag */
1727c478bd9Sstevel@tonic-gate #define	ASI_MC_DECODE		0x72	/* Memory Address Decoding Registers */
1737c478bd9Sstevel@tonic-gate #define	ASI_EC_CFG_TIMING	0x73	/* Jaguar shared Ecache Control Reg */
1747c478bd9Sstevel@tonic-gate #define	ASI_EC_DATA		0x74	/* Ecache Data Staging Registers */
1757c478bd9Sstevel@tonic-gate #define	ASI_EC_CTRL		0x75	/* Ecache Control Register */
1767c478bd9Sstevel@tonic-gate #define	ASI_PC_STATUS_DATA	0x30	/* Pcache Status Data Access */
1777c478bd9Sstevel@tonic-gate #define	ASI_PC_DATA		0x31	/* Pcache Diagnostic Data Register */
1787c478bd9Sstevel@tonic-gate #define	ASI_PC_TAG		0x32	/* Pcache Virtual Tag/Valid Field */
1797c478bd9Sstevel@tonic-gate #define	ASI_PC_SNP_TAG		0x33	/* Pcache Snoop Tag Register */
1807c478bd9Sstevel@tonic-gate #define	ASI_L2_DATA		0x6B	/* L2 cache Data Diagnostic Access */
1817c478bd9Sstevel@tonic-gate #define	ASI_L2_TAG		0x6C	/* L2 cache Tag Diagnostic Access */
182a4673f2eSss #define	ASI_L2CACHE_CTRL	0x6D	/* L2 cache Control Register */
1837c478bd9Sstevel@tonic-gate 
1847c478bd9Sstevel@tonic-gate /*
1857c478bd9Sstevel@tonic-gate  * Bits of Cheetah Asynchronous Fault Status Register
1867c478bd9Sstevel@tonic-gate  *
1877c478bd9Sstevel@tonic-gate  * +---+--+----+----+----+----+---+---+---+---+--+----
1887c478bd9Sstevel@tonic-gate  * |rsv|ME|PRIV|PERR|IERR|ISAP|EMC|EMU|IVC|IVU|TO|BERR
1897c478bd9Sstevel@tonic-gate  * +---+--+----+----+----+----+---+---+---+---+--+----
1907c478bd9Sstevel@tonic-gate  * 63:54 53 52   51   50   49   48  47  46  45 44  43
1917c478bd9Sstevel@tonic-gate  * +---+---+---+---+---+---+---+---+--+--+---+------+---+-------+
1927c478bd9Sstevel@tonic-gate  * |UCC|UCU|CPC|CPU|WDC|WDU|EDC|EDU|UE|CE|rsv|M_SYND|rsv||E_SYND|
1937c478bd9Sstevel@tonic-gate  * +---+---+---+---+---+---+---+---+--+--+---+------+---+-------+
1947c478bd9Sstevel@tonic-gate  *   42  41  40  39  38  37  36  35 34 33 32:20 19:16 15:9 8:0
1957c478bd9Sstevel@tonic-gate  *
1967c478bd9Sstevel@tonic-gate  */
1977c478bd9Sstevel@tonic-gate #if defined(CHEETAH_PLUS)
1987c478bd9Sstevel@tonic-gate /*
1997c478bd9Sstevel@tonic-gate  * Bits of Cheetah+ Asynchronous Fault Status Register
2007c478bd9Sstevel@tonic-gate  *
2017c478bd9Sstevel@tonic-gate  * +------------------+----------------------------
2027c478bd9Sstevel@tonic-gate  * |rsv|TUE_SH|IMC|IMU|DTO|DBERR|THCE|TSCE|TUE|DUE|
2037c478bd9Sstevel@tonic-gate  * +------------------+---------------------------- . . .
2047c478bd9Sstevel@tonic-gate  *   63    62   61  60  59    58   57   56  55  54
2057c478bd9Sstevel@tonic-gate  *
2067c478bd9Sstevel@tonic-gate  * Note that bits 60-62 are only implemented in Panther (reserved
2077c478bd9Sstevel@tonic-gate  * in Cheetah+ and Jaguar. Also, bit 56 is reserved in Panther instead
2087c478bd9Sstevel@tonic-gate  * of TSCE since those errors are HW corrected in Panther.
2097c478bd9Sstevel@tonic-gate  */
2107c478bd9Sstevel@tonic-gate #define	C_AFSR_TUE_SH INT64_C(0x4000000000000000) /* uncorrectable tag UE  */
2117c478bd9Sstevel@tonic-gate #define	C_AFSR_IMC  INT64_C(0x2000000000000000)	/* intr vector MTAG ECC */
2127c478bd9Sstevel@tonic-gate #define	C_AFSR_IMU  INT64_C(0x1000000000000000)	/* intr vector MTAG ECC */
2137c478bd9Sstevel@tonic-gate #define	C_AFSR_DTO  INT64_C(0x0800000000000000)	/* disrupting TO error */
2147c478bd9Sstevel@tonic-gate #define	C_AFSR_DBERR INT64_C(0x0400000000000000) /* disrupting BERR error */
2157c478bd9Sstevel@tonic-gate #define	C_AFSR_THCE INT64_C(0x0200000000000000)	/* h/w correctable E$ tag err */
2167c478bd9Sstevel@tonic-gate #define	C_AFSR_TSCE INT64_C(0x0100000000000000)	/* s/w correctable E$ tag err */
2177c478bd9Sstevel@tonic-gate #define	C_AFSR_TUE  INT64_C(0x0080000000000000)	/* uncorrectable E$ tag error */
2187c478bd9Sstevel@tonic-gate #define	C_AFSR_DUE  INT64_C(0x0040000000000000)	/* disrupting UE error */
2197c478bd9Sstevel@tonic-gate #endif	/* CHEETAH_PLUS */
2207c478bd9Sstevel@tonic-gate #define	C_AFSR_ME   INT64_C(0x0020000000000000)	/* errors > 1, same type!=CE */
2217c478bd9Sstevel@tonic-gate #define	C_AFSR_PRIV INT64_C(0x0010000000000000)	/* priv code access error    */
2227c478bd9Sstevel@tonic-gate #define	C_AFSR_PERR INT64_C(0x0008000000000000)	/* system interface protocol */
2237c478bd9Sstevel@tonic-gate #define	C_AFSR_IERR INT64_C(0x0004000000000000)	/* internal system interface */
2247c478bd9Sstevel@tonic-gate #define	C_AFSR_ISAP INT64_C(0x0002000000000000)	/* system request parity err */
2257c478bd9Sstevel@tonic-gate #define	C_AFSR_EMC  INT64_C(0x0001000000000000)	/* mtag   with   CE   error  */
2267c478bd9Sstevel@tonic-gate #define	C_AFSR_EMU  INT64_C(0x0000800000000000)	/* mtag   with   UE   error  */
2277c478bd9Sstevel@tonic-gate #define	C_AFSR_IVC  INT64_C(0x0000400000000000)	/* intr vector with CE error */
2287c478bd9Sstevel@tonic-gate #define	C_AFSR_IVU  INT64_C(0x0000200000000000)	/* intr vector with UE error */
2297c478bd9Sstevel@tonic-gate #define	C_AFSR_TO   INT64_C(0x0000100000000000)	/* bus timeout from sys bus  */
2307c478bd9Sstevel@tonic-gate #define	C_AFSR_BERR INT64_C(0x0000080000000000)	/* bus error from system bus */
2317c478bd9Sstevel@tonic-gate #define	C_AFSR_UCC  INT64_C(0x0000040000000000)	/* E$ with software CE error */
2327c478bd9Sstevel@tonic-gate #define	C_AFSR_UCU  INT64_C(0x0000020000000000)	/* E$ with software UE error */
2337c478bd9Sstevel@tonic-gate #define	C_AFSR_CPC  INT64_C(0x0000010000000000) /* copyout  with  CE  error  */
2347c478bd9Sstevel@tonic-gate #define	C_AFSR_CPU  INT64_C(0x0000008000000000) /* copyout  with  UE  error  */
2357c478bd9Sstevel@tonic-gate #define	C_AFSR_WDC  INT64_C(0x0000004000000000) /* writeback ecache CE error */
2367c478bd9Sstevel@tonic-gate #define	C_AFSR_WDU  INT64_C(0x0000002000000000) /* writeback ecache UE error */
2377c478bd9Sstevel@tonic-gate #define	C_AFSR_EDC  INT64_C(0x0000001000000000) /* ecache  CE  ECC  error    */
2387c478bd9Sstevel@tonic-gate #define	C_AFSR_EDU  INT64_C(0x0000000800000000) /* ecache  UE  ECC  error    */
2397c478bd9Sstevel@tonic-gate #define	C_AFSR_UE   INT64_C(0x0000000400000000) /* uncorrectable ECC error   */
2407c478bd9Sstevel@tonic-gate #define	C_AFSR_CE   INT64_C(0x0000000200000000) /* correctable   ECC error   */
2417c478bd9Sstevel@tonic-gate #define	C_AFSR_M_SYND	INT64_C(0x00000000000f0000) /* mtag  ECC  syndrome   */
2427c478bd9Sstevel@tonic-gate #define	C_AFSR_E_SYND	INT64_C(0x00000000000001ff) /* data  ECC  syndrome   */
2437c478bd9Sstevel@tonic-gate 
2447c478bd9Sstevel@tonic-gate /* AFSR bits that could result in CPU removal due to E$ error */
2457c478bd9Sstevel@tonic-gate #define	C_AFSR_L2_SERD_FAIL_UE	(C_AFSR_UCU | C_AFSR_CPU | C_AFSR_WDU | \
2467c478bd9Sstevel@tonic-gate 				C_AFSR_EDU)
2477c478bd9Sstevel@tonic-gate #define	C_AFSR_L2_SERD_FAIL_CE	(C_AFSR_UCC | C_AFSR_CPC | C_AFSR_WDC | \
2487c478bd9Sstevel@tonic-gate 				C_AFSR_EDC)
2497c478bd9Sstevel@tonic-gate /*
2507c478bd9Sstevel@tonic-gate  * Bits of the Panther Extended Asynchronous Fault Status Register (AFSR_EXT)
2517c478bd9Sstevel@tonic-gate  *
2527c478bd9Sstevel@tonic-gate  * +-----+-------+-----------+-------+-------+---------+------+------+------+
2537c478bd9Sstevel@tonic-gate  * | rsv |RED_ERR|EFA_PAR_ERR|L3_MECC|L3_THCE|L3_TUE_SH|L3_TUE|L3_EDC|L3_EDU|
2547c478bd9Sstevel@tonic-gate  * +-----+-------+-----------+-------+-------+---------+------+------+------+
2557c478bd9Sstevel@tonic-gate  *  63:14   13        12        11       10       9        8      7      6
2567c478bd9Sstevel@tonic-gate  *
2577c478bd9Sstevel@tonic-gate  * +------+------+------+------+------+------+
2587c478bd9Sstevel@tonic-gate  * |L3_UCC|L3_UCU|L3_CPC|L3_CPU|L3_WDC|L3_WDU|
2597c478bd9Sstevel@tonic-gate  * +------+------+------+------+------+------+
2607c478bd9Sstevel@tonic-gate  *     5      4      3      2      1      0
2617c478bd9Sstevel@tonic-gate  *
2627c478bd9Sstevel@tonic-gate  * If the L3_MECC bit is set along with any of the L3 cache errors (bits 0-7)
2637c478bd9Sstevel@tonic-gate  * above, it indicates that an address parity error has occured.
2647c478bd9Sstevel@tonic-gate  */
2657c478bd9Sstevel@tonic-gate #define	C_AFSR_RED_ERR   INT64_C(0x0000000000002000) /* redunancy Efuse error */
2667c478bd9Sstevel@tonic-gate #define	C_AFSR_EFA_PAR_ERR INT64_C(0x0000000000001000) /* Efuse parity error */
2677c478bd9Sstevel@tonic-gate #define	C_AFSR_L3_MECC   INT64_C(0x0000000000000800) /* L3 address parity */
2687c478bd9Sstevel@tonic-gate #define	C_AFSR_L3_THCE   INT64_C(0x0000000000000400) /* tag CE */
2697c478bd9Sstevel@tonic-gate #define	C_AFSR_L3_TUE_SH INT64_C(0x0000000000000200) /* tag UE from snp/cpy */
2707c478bd9Sstevel@tonic-gate #define	C_AFSR_L3_TUE    INT64_C(0x0000000000000100) /* tag UE */
2717c478bd9Sstevel@tonic-gate #define	C_AFSR_L3_EDC    INT64_C(0x0000000000000080) /* L3 cache CE */
2727c478bd9Sstevel@tonic-gate #define	C_AFSR_L3_EDU    INT64_C(0x0000000000000040) /* L3 cache UE */
2737c478bd9Sstevel@tonic-gate #define	C_AFSR_L3_UCC    INT64_C(0x0000000000000020) /* software recover CE */
2747c478bd9Sstevel@tonic-gate #define	C_AFSR_L3_UCU    INT64_C(0x0000000000000010) /* software recover UE */
2757c478bd9Sstevel@tonic-gate #define	C_AFSR_L3_CPC    INT64_C(0x0000000000000008) /* copyout with CE */
2767c478bd9Sstevel@tonic-gate #define	C_AFSR_L3_CPU    INT64_C(0x0000000000000004) /* copyout with UE */
2777c478bd9Sstevel@tonic-gate #define	C_AFSR_L3_WDC    INT64_C(0x0000000000000002) /* writeback CE */
2787c478bd9Sstevel@tonic-gate #define	C_AFSR_L3_WDU    INT64_C(0x0000000000000001) /* writeback UE */
2797c478bd9Sstevel@tonic-gate 
2807c478bd9Sstevel@tonic-gate #if defined(JALAPENO) || defined(SERRANO)
2817c478bd9Sstevel@tonic-gate /*
2827c478bd9Sstevel@tonic-gate  * Bits of Jalapeno Asynchronous Fault Status Register
2837c478bd9Sstevel@tonic-gate  *
2847c478bd9Sstevel@tonic-gate  * +-----+------------------------------------------------------------------
2857c478bd9Sstevel@tonic-gate  * | rsv |JETO|SCE|JEIC|JEIT|ME|PRIV|JEIS|IERR|ISAP|ETP|OM|UMS|IVPE|TO|BERR|
2867c478bd9Sstevel@tonic-gate  * +-----+------------------------------------------------------------------
2877c478bd9Sstevel@tonic-gate  * 63:58   57   56   55  54  53  52   51   50   49  48  47  46  45  44  43
2887c478bd9Sstevel@tonic-gate  *
2897c478bd9Sstevel@tonic-gate  * +---+---+---+---+---+---+---+---+--+--+---+---+--+---+-------+
2907c478bd9Sstevel@tonic-gate  * |UCC|UCU|CPC|CPU|WDC|WDU|EDC|EDU|UE|CE|RUE|RCE|BP|WBP|FRC|FRU|
2917c478bd9Sstevel@tonic-gate  * +---+---+---+---+---+---+---+---+--+--+---+---+--+---+-------+
2927c478bd9Sstevel@tonic-gate  *   42  41  40  39  38  37  36  35 34 33 32  31  30 29  28  27
2937c478bd9Sstevel@tonic-gate  *
2947c478bd9Sstevel@tonic-gate  * +-----+-----+-----+------+-----------+-------+
2957c478bd9Sstevel@tonic-gate  * | JREQ| ETW | rsv |B_SYND| rsv | AID | E_SYND|
2967c478bd9Sstevel@tonic-gate  * +-----+-----+-----+------+-----+-----+-------+
2977c478bd9Sstevel@tonic-gate  *  26:24 23:22 21:20  19:16 15:14 13:9   8:0
2987c478bd9Sstevel@tonic-gate  *
2997c478bd9Sstevel@tonic-gate  */
3007c478bd9Sstevel@tonic-gate 
3017c478bd9Sstevel@tonic-gate /*
3027c478bd9Sstevel@tonic-gate  * Bits of Serrano Asynchronous Fault Status Register
3037c478bd9Sstevel@tonic-gate  *
3047c478bd9Sstevel@tonic-gate  * +-----+------------------------------------------------------------------
3057c478bd9Sstevel@tonic-gate  * | rsv |JETO|SCE|JEIC|JEIT|ME|PRIV|JEIS|IERR|ISAP|ETU|OM|UMS|IVPE|TO|BERR|
3067c478bd9Sstevel@tonic-gate  * +-----+------------------------------------------------------------------
3077c478bd9Sstevel@tonic-gate  * 63:58   57   56   55  54  53  52   51   50   49  48  47  46  45  44  43
3087c478bd9Sstevel@tonic-gate  *
3097c478bd9Sstevel@tonic-gate  * +---+---+---+---+---+---+---+---+--+--+---+---+--+---+-------+
3107c478bd9Sstevel@tonic-gate  * |UCC|UCU|CPC|CPU|WDC|WDU|EDC|EDU|UE|CE|RUE|RCE|BP|WBP|FRC|FRU|
3117c478bd9Sstevel@tonic-gate  * +---+---+---+---+---+---+---+---+--+--+---+---+--+---+-------+
3127c478bd9Sstevel@tonic-gate  *   42  41  40  39  38  37  36  35 34 33 32  31  30 29  28  27
3137c478bd9Sstevel@tonic-gate  *
3147c478bd9Sstevel@tonic-gate  * +-----+-----+------+---+------+---+---+-----+-------+
3157c478bd9Sstevel@tonic-gate  * | JREQ| ETW | EFES |ETS|B_SYND|ETI|ETC| AID | E_SYND|
3167c478bd9Sstevel@tonic-gate  * +-----+-----+------+---+------+---+---+-----+-------+
3177c478bd9Sstevel@tonic-gate  *  26:24 23:22    21   20  19:16  15  14  13:9    8:0
3187c478bd9Sstevel@tonic-gate  *
3197c478bd9Sstevel@tonic-gate  */
3207c478bd9Sstevel@tonic-gate 
3217c478bd9Sstevel@tonic-gate #define	C_AFSR_JETO	INT64_C(0x0200000000000000) /* JBus Timeout */
3227c478bd9Sstevel@tonic-gate #define	C_AFSR_SCE	INT64_C(0x0100000000000000) /* Snoop parity error */
3237c478bd9Sstevel@tonic-gate #define	C_AFSR_JEIC	INT64_C(0x0080000000000000) /* JBus Illegal Cmd */
3247c478bd9Sstevel@tonic-gate #define	C_AFSR_JEIT	INT64_C(0x0040000000000000) /* Illegal ADTYPE */
3257c478bd9Sstevel@tonic-gate #define	C_AFSR_JEIS	INT64_C(0x0008000000000000) /* Illegal Install State */
3267c478bd9Sstevel@tonic-gate #if defined(SERRANO)
3277c478bd9Sstevel@tonic-gate #define	C_AFSR_ETU	INT64_C(0x0001000000000000) /* L2$ tag CE error */
3287c478bd9Sstevel@tonic-gate #elif defined(JALAPENO)
3297c478bd9Sstevel@tonic-gate #define	C_AFSR_ETP	INT64_C(0x0001000000000000) /* L2$ tag parity error */
3307c478bd9Sstevel@tonic-gate #endif /* JALAPENO */
3317c478bd9Sstevel@tonic-gate #define	C_AFSR_OM	INT64_C(0x0000800000000000) /* out of range mem error */
3327c478bd9Sstevel@tonic-gate #define	C_AFSR_UMS	INT64_C(0x0000400000000000) /* Unsupported store */
3337c478bd9Sstevel@tonic-gate #define	C_AFSR_IVPE	INT64_C(0x0000200000000000) /* intr vector parity err */
3347c478bd9Sstevel@tonic-gate #define	C_AFSR_RUE	INT64_C(0x0000000100000000) /* remote mem UE error */
3357c478bd9Sstevel@tonic-gate #define	C_AFSR_RCE	INT64_C(0x0000000080000000) /* remote mem CE error */
3367c478bd9Sstevel@tonic-gate #define	C_AFSR_BP	INT64_C(0x0000000040000000) /* read data parity err */
3377c478bd9Sstevel@tonic-gate #define	C_AFSR_WBP	INT64_C(0x0000000020000000) /* wb/bs data parity err */
3387c478bd9Sstevel@tonic-gate #define	C_AFSR_FRC	INT64_C(0x0000000010000000) /* foregin mem CE error */
3397c478bd9Sstevel@tonic-gate #define	C_AFSR_FRU	INT64_C(0x0000000008000000) /* foregin mem UE error */
3407c478bd9Sstevel@tonic-gate #define	C_AFSR_JREQ	INT64_C(0x0000000007000000) /* Active JBus req at err */
3417c478bd9Sstevel@tonic-gate #define	C_AFSR_ETW	INT64_C(0x0000000000c00000) /* AID causing UE/CE */
3427c478bd9Sstevel@tonic-gate 
3437c478bd9Sstevel@tonic-gate #if defined(SERRANO)
3447c478bd9Sstevel@tonic-gate #define	C_AFSR_EFES	INT64_C(0x0000000000200000) /* E-fuse error summary */
3457c478bd9Sstevel@tonic-gate #define	C_AFSR_ETS	INT64_C(0x0000000000100000) /* L2$ tag SRAM stuck-at */
3467c478bd9Sstevel@tonic-gate #endif /* SERRANO */
3477c478bd9Sstevel@tonic-gate 
3487c478bd9Sstevel@tonic-gate #define	C_AFSR_B_SYND	INT64_C(0x00000000000f0000) /* jbus parity syndrome */
3497c478bd9Sstevel@tonic-gate 
3507c478bd9Sstevel@tonic-gate #if defined(SERRANO)
3517c478bd9Sstevel@tonic-gate #define	C_AFSR_ETI	INT64_C(0x0000000000008000) /* L2$ tag intermittent */
3527c478bd9Sstevel@tonic-gate #define	C_AFSR_ETC	INT64_C(0x0000000000004000) /* L2$ tag CE */
3537c478bd9Sstevel@tonic-gate #endif /* SERRANO */
3547c478bd9Sstevel@tonic-gate 
3557c478bd9Sstevel@tonic-gate #define	C_AFSR_AID	INT64_C(0x0000000000003e00) /* AID causing UE/CE */
3567c478bd9Sstevel@tonic-gate 
3577c478bd9Sstevel@tonic-gate /* bit shifts for selected errors */
3587c478bd9Sstevel@tonic-gate #define	C_AFSR_WDU_SHIFT	37
3597c478bd9Sstevel@tonic-gate #define	C_AFSR_UCU_SHIFT	41
3607c478bd9Sstevel@tonic-gate #define	C_AFSR_UCC_SHIFT	42
3617c478bd9Sstevel@tonic-gate #define	C_AFSR_JREQ_SHIFT	24
3627c478bd9Sstevel@tonic-gate #define	C_AFSR_AID_SHIFT	9
3637c478bd9Sstevel@tonic-gate 
3647c478bd9Sstevel@tonic-gate /*
3657c478bd9Sstevel@tonic-gate  * Overloaded AFSR fields. During error processing, some of the reserved
3667c478bd9Sstevel@tonic-gate  * fields within the saved AFSR are overwritten with extra information.
3677c478bd9Sstevel@tonic-gate  */
3687c478bd9Sstevel@tonic-gate #define	C_AFSR_PANIC_SHIFT		62
3697c478bd9Sstevel@tonic-gate #define	C_AFSR_IPE_SHIFT		59
3707c478bd9Sstevel@tonic-gate #define	C_AFSR_DPE_SHIFT		58
3717c478bd9Sstevel@tonic-gate 
3727c478bd9Sstevel@tonic-gate #else /* JALAPENO || SERRANO */
3737c478bd9Sstevel@tonic-gate 
3747c478bd9Sstevel@tonic-gate /* bit shifts for selected errors */
3757c478bd9Sstevel@tonic-gate #define	C_AFSR_WDU_SHIFT	37
3767c478bd9Sstevel@tonic-gate #define	C_AFSR_UCU_SHIFT	41
3777c478bd9Sstevel@tonic-gate #define	C_AFSR_UCC_SHIFT	42
3787c478bd9Sstevel@tonic-gate #define	C_AFSR_L3_UCU_SHIFT	4
3797c478bd9Sstevel@tonic-gate 
3807c478bd9Sstevel@tonic-gate /*
3817c478bd9Sstevel@tonic-gate  * Overloaded AFSR fields. During error processing, some of the reserved fields
3827c478bd9Sstevel@tonic-gate  * within the saved AFSR are overwritten with extra information.
3837c478bd9Sstevel@tonic-gate  */
3847c478bd9Sstevel@tonic-gate #define	C_AFSR_FIRSTFLT_SHIFT	63
3857c478bd9Sstevel@tonic-gate #define	C_AFSR_PANIC_SHIFT	30
3867c478bd9Sstevel@tonic-gate #define	C_AFSR_DPE_SHIFT	20
3877c478bd9Sstevel@tonic-gate #define	C_AFSR_IPE_SHIFT	21
3887c478bd9Sstevel@tonic-gate 
3897c478bd9Sstevel@tonic-gate #endif /* JALAPENO || SERRANO */
3907c478bd9Sstevel@tonic-gate 
3917c478bd9Sstevel@tonic-gate #if defined(JALAPENO) || defined(SERRANO)
3927c478bd9Sstevel@tonic-gate /*
3937c478bd9Sstevel@tonic-gate  * Jalapeno L2 Cache Control Register Bits.
3947c478bd9Sstevel@tonic-gate  *
3957c478bd9Sstevel@tonic-gate  *	Bit#	Name		Description
3967c478bd9Sstevel@tonic-gate  *	63-24	-		reserved
3977c478bd9Sstevel@tonic-gate  *	23:20	EC_ACT_WAY	(read only) indicates which sets are present
3987c478bd9Sstevel@tonic-gate  *	19:16	EC_BLK_WAY	Bit mask indicating which sets are blocked
3997c478bd9Sstevel@tonic-gate  *				from replacement
4007c478bd9Sstevel@tonic-gate  *	15:14	EC_SIZE		L2 cache size
4017c478bd9Sstevel@tonic-gate  *	13:12	-		reserved
4027c478bd9Sstevel@tonic-gate  *	11	EC_PAR_EN	Enables parity checking on L2 cache tags
4037c478bd9Sstevel@tonic-gate  *	10	EC_ECC_EN	Enables ECC checking on L2 cache data
4047c478bd9Sstevel@tonic-gate  *	9	EC_ECC_FORCE	Enables EC_CHECK[8:0] onto L2 cache ECC bits
4057c478bd9Sstevel@tonic-gate  *	8:0	EC_CHECK	ECC check vector to force onto ECC bits
4067c478bd9Sstevel@tonic-gate  */
4077c478bd9Sstevel@tonic-gate 
4087c478bd9Sstevel@tonic-gate #define	JP_ECCTRL_ECSIZE_MASK		0xc000
4097c478bd9Sstevel@tonic-gate #define	JP_ECCTRL_ECSIZE_SHIFT		14
4107c478bd9Sstevel@tonic-gate #define	JP_ECCTRL_ECSIZE_MIN		0x80000
4117c478bd9Sstevel@tonic-gate 
4127c478bd9Sstevel@tonic-gate /*
4137c478bd9Sstevel@tonic-gate  * Jalapeno L2 Cache Error Enable Register Bits
4147c478bd9Sstevel@tonic-gate  *
4157c478bd9Sstevel@tonic-gate  *	Bit#	Name	Description
4167c478bd9Sstevel@tonic-gate  *	63-33	-	reserved
4177c478bd9Sstevel@tonic-gate  *	32	SCDE	Enable detection of JBUS control parity error
4187c478bd9Sstevel@tonic-gate  *	31:24	-	reserved
4197c478bd9Sstevel@tonic-gate  *	23	IAEN	Enable trap on illegal physical address
4207c478bd9Sstevel@tonic-gate  *	22	IERREN	Enable FERR system reset on CPU internal errors
4217c478bd9Sstevel@tonic-gate  *	21	PERREN	Enable FERR system reset on JBUS protocol errors
4227c478bd9Sstevel@tonic-gate  *	20	SCEN	Enable FERR system reset on JBUS control parity error
4237c478bd9Sstevel@tonic-gate  *	19:11	FMED	Forced error on the memory ECC
4247c478bd9Sstevel@tonic-gate  *	10	FME	Force error on memory ECC
4257c478bd9Sstevel@tonic-gate  *	9:6	FPD	Bits to use when FSP forces JBUS addr/data parity error
4267c478bd9Sstevel@tonic-gate  *	5	FSP	Force error on outgoing JBUS addr/data parity
4277c478bd9Sstevel@tonic-gate  *	4	ETPEN	Enable FERR system reset on L2 tags parity error
4287c478bd9Sstevel@tonic-gate  *	3	UCEEN	Enable trap on SW handled external cache error
4297c478bd9Sstevel@tonic-gate  *	2	ISAPEN	Enable FERR system reset on request parity error
4307c478bd9Sstevel@tonic-gate  *	1	NCEEN	Enable trap on uncorrectable ECC error and system err
4317c478bd9Sstevel@tonic-gate  *	0	CEEN	Enable trap on correctable ECC errors
4327c478bd9Sstevel@tonic-gate  */
4337c478bd9Sstevel@tonic-gate 
4347c478bd9Sstevel@tonic-gate #define	EN_REG_UCEEN	INT64_C(0x0000000000000008) /* enable UCC,UCU */
4357c478bd9Sstevel@tonic-gate #define	EN_REG_ISAPEN	INT64_C(0x0000000000000004) /* enable ISAP */
4367c478bd9Sstevel@tonic-gate #define	EN_REG_NCEEN INT64_C(0x0000000000000002) /* UE,EDU,WDU,BERR,IVU,EMU */
4377c478bd9Sstevel@tonic-gate #define	EN_REG_CEEN INT64_C(0x0000000000000001) /* enable CE,EDC,WDC,IVC,EMC */
4387c478bd9Sstevel@tonic-gate 
4397c478bd9Sstevel@tonic-gate #define	EN_REG_DISABLE	INT64_C(0x0000000000000000) /* no errors enabled */
4407c478bd9Sstevel@tonic-gate #define	EN_REG_ECC_DISABLE (EN_REG_UCEEN | EN_REG_ISAPEN)
4417c478bd9Sstevel@tonic-gate #define	EN_REG_CE_DISABLE (EN_REG_UCEEN | EN_REG_ISAPEN | EN_REG_NCEEN)
4427c478bd9Sstevel@tonic-gate #define	EN_REG_ENABLE \
4437c478bd9Sstevel@tonic-gate 	(EN_REG_UCEEN | EN_REG_ISAPEN | EN_REG_NCEEN | EN_REG_CEEN)
4447c478bd9Sstevel@tonic-gate 
4457c478bd9Sstevel@tonic-gate #else /* JALAPENO || SERRANO */
4467c478bd9Sstevel@tonic-gate #if defined(CHEETAH_PLUS)
4477c478bd9Sstevel@tonic-gate /*
4487c478bd9Sstevel@tonic-gate  * Cheetah+ External Cache Control Register Bits.
4497c478bd9Sstevel@tonic-gate  */
4507c478bd9Sstevel@tonic-gate #define	ECCR_ASSOC	INT64_C(0x0000000001000000) /* Ecache Assoc. */
4517c478bd9Sstevel@tonic-gate #define	ECCR_ASSOC_SHIFT	24
4527c478bd9Sstevel@tonic-gate #endif	/* CHEETAH_PLUS */
4537c478bd9Sstevel@tonic-gate 
4547c478bd9Sstevel@tonic-gate /*
4557c478bd9Sstevel@tonic-gate  * Bits of Cheetah External Cache Error Enable Register
4567c478bd9Sstevel@tonic-gate  *
4577c478bd9Sstevel@tonic-gate  * +-----+-----+-------+-----+-------+-------+--------+-------+------+
4587c478bd9Sstevel@tonic-gate  * | rsv | FMT | FMECC | FMD | FDECC | UCEEN | ISAPEN | NCEEN | CEEN |
4597c478bd9Sstevel@tonic-gate  * +-----+-----+-------+-----+-------+-------+--------+-------+------+
4607c478bd9Sstevel@tonic-gate  *  63:19   18  17  14    13    12:4     3        2       1       0
4617c478bd9Sstevel@tonic-gate  *
4627c478bd9Sstevel@tonic-gate  */
4637c478bd9Sstevel@tonic-gate #define	EN_REG_FMT	INT64_C(0x0000000000040000) /* force system mtag ECC */
4647c478bd9Sstevel@tonic-gate #define	EN_REG_FMECC	INT64_C(0x000000000003C000) /* forced mtag ECC vector */
4657c478bd9Sstevel@tonic-gate #define	EN_REG_FMD	INT64_C(0x0000000000002000) /* force system data ECC */
4667c478bd9Sstevel@tonic-gate #define	EN_REG_FDECC	INT64_C(0x0000000000001ff0) /* forced data ECC vector */
4677c478bd9Sstevel@tonic-gate #define	EN_REG_UCEEN	INT64_C(0x0000000000000008) /* enable UCC,UCU */
4687c478bd9Sstevel@tonic-gate #define	EN_REG_ISAPEN	INT64_C(0x0000000000000004) /* enable ISAP */
4697c478bd9Sstevel@tonic-gate #define	EN_REG_NCEEN INT64_C(0x0000000000000002) /* UE,EDU,WDU,BERR,IVU,EMU */
4707c478bd9Sstevel@tonic-gate #define	EN_REG_CEEN INT64_C(0x0000000000000001) /* enable CE,EDC,WDC,IVC,EMC */
4717c478bd9Sstevel@tonic-gate #define	EN_REG_DISABLE	INT64_C(0x0000000000000000) /* no errors enabled */
4727c478bd9Sstevel@tonic-gate #define	EN_REG_ECC_DISABLE (EN_REG_UCEEN | EN_REG_ISAPEN)
4737c478bd9Sstevel@tonic-gate #define	EN_REG_CE_DISABLE (EN_REG_UCEEN | EN_REG_ISAPEN | EN_REG_NCEEN)
4747c478bd9Sstevel@tonic-gate #define	EN_REG_ENABLE \
4757c478bd9Sstevel@tonic-gate 	(EN_REG_UCEEN | EN_REG_ISAPEN | EN_REG_NCEEN | EN_REG_CEEN)
4767c478bd9Sstevel@tonic-gate #endif	/* JALAPENO || SERRANO */
4777c478bd9Sstevel@tonic-gate 
4787c478bd9Sstevel@tonic-gate /*
4797c478bd9Sstevel@tonic-gate  * bit shifts for selected bits
4807c478bd9Sstevel@tonic-gate  */
4817c478bd9Sstevel@tonic-gate #define	EN_REG_CEEN_SHIFT	0
4827c478bd9Sstevel@tonic-gate 
4837c478bd9Sstevel@tonic-gate /* Cheetah/Cheetah+ Dcache size */
4847c478bd9Sstevel@tonic-gate #define	CH_DCACHE_SIZE		0x10000
4857c478bd9Sstevel@tonic-gate 
4867c478bd9Sstevel@tonic-gate /* Cheetah/Cheetah+ Dcache linesize */
4877c478bd9Sstevel@tonic-gate #define	CH_DCACHE_LSIZE		0x20
4887c478bd9Sstevel@tonic-gate 
4897c478bd9Sstevel@tonic-gate /* Cheetah/Cheetah+/Jaguar Icache size */
4907c478bd9Sstevel@tonic-gate #define	CH_ICACHE_SIZE		0x8000
4917c478bd9Sstevel@tonic-gate 
4927c478bd9Sstevel@tonic-gate /* Cheetah/Cheetah+/Jaguar Icache linesize */
4937c478bd9Sstevel@tonic-gate #define	CH_ICACHE_LSIZE		0x20
4947c478bd9Sstevel@tonic-gate 
4957c478bd9Sstevel@tonic-gate /* Panther Icache size */
4967c478bd9Sstevel@tonic-gate #define	PN_ICACHE_SIZE		0x10000
4977c478bd9Sstevel@tonic-gate 
4987c478bd9Sstevel@tonic-gate /* Panther Icache linesize */
4997c478bd9Sstevel@tonic-gate #define	PN_ICACHE_LSIZE		0x40
5007c478bd9Sstevel@tonic-gate 
5017c478bd9Sstevel@tonic-gate /* Pcache size for the cheetah family of CPUs */
5027c478bd9Sstevel@tonic-gate #define	CH_PCACHE_SIZE		0x800
5037c478bd9Sstevel@tonic-gate 
5047c478bd9Sstevel@tonic-gate /* Pcache linesize  for the cheetah family of CPUs */
5057c478bd9Sstevel@tonic-gate #define	CH_PCACHE_LSIZE		0x40
5067c478bd9Sstevel@tonic-gate 
5077c478bd9Sstevel@tonic-gate /*
5087c478bd9Sstevel@tonic-gate  * The cheetah+ CPU module handles Cheetah+, Jaguar, and Panther so
5097c478bd9Sstevel@tonic-gate  * we have to pick max size and min linesize values for the Icache
5107c478bd9Sstevel@tonic-gate  * accordingly.
5117c478bd9Sstevel@tonic-gate  */
5127c478bd9Sstevel@tonic-gate #define	CHP_ICACHE_MAX_SIZE	PN_ICACHE_SIZE
5137c478bd9Sstevel@tonic-gate #define	CHP_ICACHE_MIN_LSIZE	CH_ICACHE_LSIZE
5147c478bd9Sstevel@tonic-gate 
5157c478bd9Sstevel@tonic-gate /*
5167c478bd9Sstevel@tonic-gate  * The minimum size needed to ensure consistency on a virtually address
5177c478bd9Sstevel@tonic-gate  * cache.  Computed by taking the largest virtually indexed cache and dividing
5187c478bd9Sstevel@tonic-gate  * by its associativity.
5197c478bd9Sstevel@tonic-gate  */
5207c478bd9Sstevel@tonic-gate #define	CH_VAC_SIZE		0x4000
5217c478bd9Sstevel@tonic-gate 
5227c478bd9Sstevel@tonic-gate /*
5237c478bd9Sstevel@tonic-gate  * The following definitions give the syndromes that will be seen when attempts
5247c478bd9Sstevel@tonic-gate  * are made to read data that has been intentionally poisoned.  Intentional
5257c478bd9Sstevel@tonic-gate  * poisoning is performed when an error has been detected, and is designed to
5267c478bd9Sstevel@tonic-gate  * allow software to effectively distinguish between root problems and secondary
5277c478bd9Sstevel@tonic-gate  * effects.  The following syndromes and their descriptions are taken from the
5287c478bd9Sstevel@tonic-gate  * UltraSPARC-III Cu Error Manual, Section 5.4.3.1.
5297c478bd9Sstevel@tonic-gate  */
5307c478bd9Sstevel@tonic-gate 
5317c478bd9Sstevel@tonic-gate /*
5327c478bd9Sstevel@tonic-gate  * For a DSTAT = 2 or 3 event (see Sec 5.3.4.4) from the system bus for a
5337c478bd9Sstevel@tonic-gate  * cacheable load, data bits [1:0] are inverted in the data stored in the
5347c478bd9Sstevel@tonic-gate  * L2-cache.  The syndrome seen when one of these signalling words is read will
5357c478bd9Sstevel@tonic-gate  * be 0x11c.
5367c478bd9Sstevel@tonic-gate  */
5377c478bd9Sstevel@tonic-gate #define	CH_POISON_SYND_FROM_DSTAT23	0x11c
5387c478bd9Sstevel@tonic-gate 
5397c478bd9Sstevel@tonic-gate /*
5407c478bd9Sstevel@tonic-gate  * For an uncorrectable data ECC error from the L2-cache, data bits [127:126]
5417c478bd9Sstevel@tonic-gate  * are inverted in data sent to the system bus as part of a writeback or
5427c478bd9Sstevel@tonic-gate  * copyout.  The syndrome seen when one of these signalling words is read will
5437c478bd9Sstevel@tonic-gate  * be 0x071.
5447c478bd9Sstevel@tonic-gate  */
5457c478bd9Sstevel@tonic-gate #define	CH_POISON_SYND_FROM_XXU_WRITE	0x71
5467c478bd9Sstevel@tonic-gate 
5477c478bd9Sstevel@tonic-gate /*
5487c478bd9Sstevel@tonic-gate  * For uncorrectable data ECC error on the L2-cache read done to complete a
5497c478bd9Sstevel@tonic-gate  * store merge event, where bytes written by the processor are merged with
5507c478bd9Sstevel@tonic-gate  * bytes from an L2-cache line, ECC check bits [1:0] are inverted in the data
5517c478bd9Sstevel@tonic-gate  * scrubbed back to the L2-cache.  The syndrome seen when one of these
5527c478bd9Sstevel@tonic-gate  * signalling words is read will be 0x003.
5537c478bd9Sstevel@tonic-gate  */
5547c478bd9Sstevel@tonic-gate #define	CH_POISON_SYND_FROM_XXU_WRMERGE	0x3
5557c478bd9Sstevel@tonic-gate 
5567c478bd9Sstevel@tonic-gate /*
5577c478bd9Sstevel@tonic-gate  * To help understand the following definitions, this block of comments
5587c478bd9Sstevel@tonic-gate  * provides information on Cheetah's E$.
5597c478bd9Sstevel@tonic-gate  *
5607c478bd9Sstevel@tonic-gate  * Cheetah supports three different E$ sizes (1MB, 4MB, and 8MB). The
5617c478bd9Sstevel@tonic-gate  * number of E$ lines remains constant regardless of the size of the E$
5627c478bd9Sstevel@tonic-gate  * as does the subblock size, however the number of 64-byte subblocks per
5637c478bd9Sstevel@tonic-gate  * line varies depending on the E$ size.
5647c478bd9Sstevel@tonic-gate  *
5657c478bd9Sstevel@tonic-gate  * An E$ tag (for an E$ line) contains an EC_tag field, corresponding to the
5667c478bd9Sstevel@tonic-gate  * high order physical address bits of that E$ line's contents, and 1 to 8
5677c478bd9Sstevel@tonic-gate  * EC_state fields, indicating the state of each subblock. Due to the E$ line
5687c478bd9Sstevel@tonic-gate  * size variance depending on the total size of the E$, the number of bits in
5697c478bd9Sstevel@tonic-gate  * the EC_tag field varies as does the number of subblocks (and EC_state
5707c478bd9Sstevel@tonic-gate  * fields) per E$ line.
5717c478bd9Sstevel@tonic-gate  *
5727c478bd9Sstevel@tonic-gate  * A 1MB E$ has a line size of 64 bytes, containing 1 subblock per line.
5737c478bd9Sstevel@tonic-gate  * A 4MB E$ has a line size of 256 bytes, containing 4 subblocks per line.
5747c478bd9Sstevel@tonic-gate  * An 8MB E$ has a line size of 512 bytes, containing 8 subblocks per line.
5757c478bd9Sstevel@tonic-gate  *
5767c478bd9Sstevel@tonic-gate  * An E$ tag for a particular E$ line can be read via a diagnostic ASI
5777c478bd9Sstevel@tonic-gate  * as a 64-bit value.
5787c478bd9Sstevel@tonic-gate  * Within the E$ tag 64-bit value, the EC_tag field is interpreted as follows:
5797c478bd9Sstevel@tonic-gate  *	- for a 1MB E$, the EC_tag is in bits <43:21> and corresponds
5807c478bd9Sstevel@tonic-gate  *		to physical address bits <42:20> (bits <41:19> for Cheetah+)
5817c478bd9Sstevel@tonic-gate  *	- for a 4MB E$, the EC_tag is in bits <43:23> and corresponds
5827c478bd9Sstevel@tonic-gate  *		to physical address bits <42:22> (bits <41:21> for Cheetah+)
5837c478bd9Sstevel@tonic-gate  *	- for an 8MB E$, the EC_tag is in bits <43:24> and corresponds
5847c478bd9Sstevel@tonic-gate  *		to physical address bits <42:23> (bits <41:22> for Cheetah+)
5857c478bd9Sstevel@tonic-gate  * Within the E$ tag 64-bit value, the EC_state field(s) is(are) interpreted
5867c478bd9Sstevel@tonic-gate  * as follows:
5877c478bd9Sstevel@tonic-gate  *	- for a 1MB E$, EC_state0 is in bits <2:0>
5887c478bd9Sstevel@tonic-gate  *	- for a 4MB E$, EC_state0 is in bits <2:0>, EC_state1 is in
5897c478bd9Sstevel@tonic-gate  *		bits <5:3>, EC_state2 is in bits <8:6>, EC_state3 is
5907c478bd9Sstevel@tonic-gate  *		in bits <11:9>
5917c478bd9Sstevel@tonic-gate  *	- for an 8MB E$, EC_state0 is in bits <2:0>, EC_state1 is in
5927c478bd9Sstevel@tonic-gate  *		bits <5:3>, EC_state2 is in bits <8:6>, EC_state3 is
5937c478bd9Sstevel@tonic-gate  *		in bits <11:9>, EC_state4 is in bits <14:12>, EC_state5
5947c478bd9Sstevel@tonic-gate  *		is in bits <17:15>, EC_state6 is in bits <20:18>,
5957c478bd9Sstevel@tonic-gate  *		EC_state7 is in bits <23:21>
5967c478bd9Sstevel@tonic-gate  * Note that each EC_state field contains a value representing the state
5977c478bd9Sstevel@tonic-gate  * of its corresponding subblock.
5987c478bd9Sstevel@tonic-gate  *
5997c478bd9Sstevel@tonic-gate  */
6007c478bd9Sstevel@tonic-gate /*
6017c478bd9Sstevel@tonic-gate  * Jaguar changes from Cheetah/Cheetah+ Ecache:
6027c478bd9Sstevel@tonic-gate  *
6037c478bd9Sstevel@tonic-gate  * The Jaguar Ecache is similiar to that used for Cheetah/Cheetah+ with a
6047c478bd9Sstevel@tonic-gate  * couple of differences :
6057c478bd9Sstevel@tonic-gate  *	- Jaguar Ecache only comes in 4MB and 8MB versions.
6067c478bd9Sstevel@tonic-gate  *		- 8MB E$ has 2 64 byte subblocks per line.
6077c478bd9Sstevel@tonic-gate  *		- 4MB E$ has 1 64 byte subblock per line.
6087c478bd9Sstevel@tonic-gate  *
6097c478bd9Sstevel@tonic-gate  * An E$ tag for a particular E$ line can be read via a diagnostic ASI
6107c478bd9Sstevel@tonic-gate  * as a 64-bit value.
6117c478bd9Sstevel@tonic-gate  * Within the E$ tag 64-bit value, the EC_tag field is interpreted as follows:
6127c478bd9Sstevel@tonic-gate  *	- for a 4MB E$, the EC_tag is in bits <41:21> and corresponds
6137c478bd9Sstevel@tonic-gate  *		to physical address bits <41:21>
6147c478bd9Sstevel@tonic-gate  *	- for a 8MB E$, the EC_tag is in bits <41:22> and corresponds
6157c478bd9Sstevel@tonic-gate  *		to physical address bits <41:22>
6167c478bd9Sstevel@tonic-gate  *
6177c478bd9Sstevel@tonic-gate  * The Jaguar E$ tag also contains LRU field in bit <42> which must be
6187c478bd9Sstevel@tonic-gate  * masked off when the tag value is being compared to a PA.
6197c478bd9Sstevel@tonic-gate  *
6207c478bd9Sstevel@tonic-gate  * Within the E$ tag 64-bit value, the EC_state field(s) is(are) interpreted
6217c478bd9Sstevel@tonic-gate  * as follows:
6227c478bd9Sstevel@tonic-gate  *	- for 4MB E$, EC_state0 is in bits <2:0>
6237c478bd9Sstevel@tonic-gate  *	- for 8MB E$, EC_state0 is in bits <2:0>, EC_state1 is in bits <5:3>.
6247c478bd9Sstevel@tonic-gate  * Each EC_state field contains a value representing the state of its
6257c478bd9Sstevel@tonic-gate  * corresponding subblock.
6267c478bd9Sstevel@tonic-gate  *
6277c478bd9Sstevel@tonic-gate  * Note that the subblock size and state values are the same for both
6287c478bd9Sstevel@tonic-gate  * Cheetah/Cheetah+ and Jaguar.
6297c478bd9Sstevel@tonic-gate  */
6307c478bd9Sstevel@tonic-gate 
6317c478bd9Sstevel@tonic-gate /* Ecache sizes */
6327c478bd9Sstevel@tonic-gate #define	CH_ECACHE_8M_SIZE	0x800000
6337c478bd9Sstevel@tonic-gate #define	CH_ECACHE_4M_SIZE	0x400000
6347c478bd9Sstevel@tonic-gate #define	CH_ECACHE_1M_SIZE	0x100000
6357c478bd9Sstevel@tonic-gate 
6367c478bd9Sstevel@tonic-gate #define	PN_L2_SIZE		0x200000
6377c478bd9Sstevel@tonic-gate #define	PN_L2_LINESIZE		64
6387c478bd9Sstevel@tonic-gate #define	PN_L2_ECC_WORDS		2
6397c478bd9Sstevel@tonic-gate #define	PN_L2_NWAYS		4
6407c478bd9Sstevel@tonic-gate #define	PN_L2_SET_SIZE		(PN_L2_SIZE / PN_L2_NWAYS)
6417c478bd9Sstevel@tonic-gate #define	PN_L2_MAX_SET		(PN_L2_SIZE - PN_L2_SET_SIZE)
6427c478bd9Sstevel@tonic-gate #define	PN_L2_DATA_ECC_SEL	0x200000 /* bit 21 selects ECC */
6437c478bd9Sstevel@tonic-gate #define	PN_L2_ECC_LO_REG	0x20 /* bit 5 set for L2 tag access */
6447c478bd9Sstevel@tonic-gate #define	PN_L2_INDEX_MASK	0x7ffc0 /* bits 18:6 */
6457c478bd9Sstevel@tonic-gate #define	PN_L2_WAY_INCR		0x80000	/* l2-ec-way = <20:19> */
6467c478bd9Sstevel@tonic-gate #define	PN_L2_WAY_LIM		INT64_C(0x200000)
6477c478bd9Sstevel@tonic-gate #define	PN_L2_WAY_SHIFT		19
648a4673f2eSss #define	PN_L2_WAY_MASK		(3ULL << PN_L2_WAY_SHIFT) /* <20:19> */
649a4673f2eSss #define	PN_L2_HW_ECC_SHIFT	22 /* Set to force HW ECC generation */
650a4673f2eSss #define	PN_L2_SPLIT_EN_SHIFT	2 /* L2_Cache_Ctrl<2> = L2_split_en */
6517c478bd9Sstevel@tonic-gate 
6527c478bd9Sstevel@tonic-gate #define	PN_L3_SIZE		0x2000000
6537c478bd9Sstevel@tonic-gate #define	PN_L3_LINESIZE		64
6547c478bd9Sstevel@tonic-gate #define	PN_L3_NWAYS		4
6557c478bd9Sstevel@tonic-gate #define	PN_L3_SET_SIZE		(PN_L3_SIZE / PN_L3_NWAYS)
6567c478bd9Sstevel@tonic-gate #define	PN_L3_MAX_SET		(PN_L3_SIZE - PN_L3_SET_SIZE)
6577c478bd9Sstevel@tonic-gate #define	PN_L3_WAY_SHIFT		23
658a4673f2eSss #define	PN_L3_HW_ECC_SHIFT	25	/* Set to force HW ECC generation */
6597c478bd9Sstevel@tonic-gate #define	PN_L3_TAG_RD_MASK	0x7fffc0	/* ec_tag = PA<22:6>  */
6607c478bd9Sstevel@tonic-gate #define	PN_L3_WAY_INCR		0x800000	/* ec_way = <24:23> */
661a4673f2eSss #define	PN_L3_WAY_MASK		(3ULL << PN_L3_WAY_SHIFT) /* <24:23> */
6627c478bd9Sstevel@tonic-gate #define	PN_L3_WAY_LIM		INT64_C(0x2000000)
663a4673f2eSss #define	PN_L3_SPLIT_EN_SHIFT	30	/* L3_Cache_Ctrl<30> = L3_split_en */
6647c478bd9Sstevel@tonic-gate 
6657c478bd9Sstevel@tonic-gate /* Pcache Defines */
6667c478bd9Sstevel@tonic-gate #define	PN_PCACHE_ADDR_MASK	0x1c0		/* PC_addr = <8:6> */
6677c478bd9Sstevel@tonic-gate #define	PN_PCACHE_WAY_INCR	0x200		/* PC_way = <10:9> */
6687c478bd9Sstevel@tonic-gate #define	PN_PCACHE_WORD_SHIFT	3		/* PC_dbl_word = <5:3> */
6697c478bd9Sstevel@tonic-gate #define	PN_PCACHE_NWAYS		4
6707c478bd9Sstevel@tonic-gate 
6717c478bd9Sstevel@tonic-gate /* Cheetah Ecache is direct-mapped, Cheetah+ can be 2-way or direct-mapped */
6727c478bd9Sstevel@tonic-gate #define	CH_ECACHE_NWAY		1
6737c478bd9Sstevel@tonic-gate #if defined(CHEETAH_PLUS)
6747c478bd9Sstevel@tonic-gate #define	CHP_ECACHE_NWAY		2
6757c478bd9Sstevel@tonic-gate #define	PN_ECACHE_NWAY		4
6767c478bd9Sstevel@tonic-gate #endif	/* CHEETAH_PLUS */
6777c478bd9Sstevel@tonic-gate #if defined(JALAPENO) || defined(SERRANO)
6787c478bd9Sstevel@tonic-gate #define	JP_ECACHE_NWAY		4
6797c478bd9Sstevel@tonic-gate #define	JP_ECACHE_NWAY_SHIFT	2
6807c478bd9Sstevel@tonic-gate #endif /* JALAPENO || SERRANO */
6817c478bd9Sstevel@tonic-gate 
6827c478bd9Sstevel@tonic-gate /* Maximum Ecache size */
6837c478bd9Sstevel@tonic-gate #define	CH_ECACHE_MAX_SIZE	CH_ECACHE_8M_SIZE
6847c478bd9Sstevel@tonic-gate 
6857c478bd9Sstevel@tonic-gate /* Minimum Ecache line size */
6867c478bd9Sstevel@tonic-gate #define	CH_ECACHE_MIN_LSIZE	64
6877c478bd9Sstevel@tonic-gate 
6887c478bd9Sstevel@tonic-gate /* Maximum Ecache line size - 8Mb Ecache has 512 byte linesize */
6897c478bd9Sstevel@tonic-gate #define	CH_ECACHE_MAX_LSIZE	512
6907c478bd9Sstevel@tonic-gate 
6917c478bd9Sstevel@tonic-gate /* Size of Ecache data staging register size (see Cheetah PRM 10.7.2) */
6927c478bd9Sstevel@tonic-gate #define	CH_ECACHE_STGREG_SIZE	32
6937c478bd9Sstevel@tonic-gate #define	CH_ECACHE_STGREG_TOTALSIZE	40	/* data regs + ecc */
6947c478bd9Sstevel@tonic-gate 
6957c478bd9Sstevel@tonic-gate /* The number of staging registers containing data, for ASI_EC_DATA */
6967c478bd9Sstevel@tonic-gate #define	CH_ECACHE_STGREG_NUM	(CH_ECACHE_STGREG_SIZE / sizeof (uint64_t))
6977c478bd9Sstevel@tonic-gate 
6987c478bd9Sstevel@tonic-gate /* Size of Ecache data subblock which has state field in Ecache tag */
6997c478bd9Sstevel@tonic-gate #define	CH_ECACHE_SUBBLK_SIZE	64
7007c478bd9Sstevel@tonic-gate #define	CH_ECACHE_SUBBLK_SHIFT	6
7017c478bd9Sstevel@tonic-gate 
7027c478bd9Sstevel@tonic-gate #if defined(JALAPENO) || defined(SERRANO)
7037c478bd9Sstevel@tonic-gate #define	JP_ECACHE_MAX_LSIZE	CH_ECACHE_SUBBLK_SIZE
7047c478bd9Sstevel@tonic-gate #define	JP_ECACHE_MAX_SIZE	0x400000
7057c478bd9Sstevel@tonic-gate #endif /* JALAPENO || SERRANO */
7067c478bd9Sstevel@tonic-gate 
7077c478bd9Sstevel@tonic-gate /*
7087c478bd9Sstevel@tonic-gate  * Maximum ecache setsize to support page coloring of heterogenous
7097c478bd9Sstevel@tonic-gate  * cheetah+ cpus. Max ecache setsize is calculated to be the max ecache size
7107c478bd9Sstevel@tonic-gate  * divided by the minimum associativity of the max ecache.
7117c478bd9Sstevel@tonic-gate  *
7127c478bd9Sstevel@tonic-gate  * NOTE: CHP_ECACHE_MAX_SIZE and CHP_ECACHE_MIN_NWAY need to be updated with
7137c478bd9Sstevel@tonic-gate  * new cheetah+ cpus. The maximum setsize may not necessarily be associated with
7147c478bd9Sstevel@tonic-gate  * the max ecache size if the cache associativity is large. If so, MAX_SETSIZE
7157c478bd9Sstevel@tonic-gate  * needs to be updated accordingly.
7167c478bd9Sstevel@tonic-gate  */
7177c478bd9Sstevel@tonic-gate #if defined(CHEETAH_PLUS)
7187c478bd9Sstevel@tonic-gate #define	CHP_ECACHE_MIN_NWAY	1	/* direct-mapped */
7197c478bd9Sstevel@tonic-gate #define	CHP_ECACHE_MAX_SIZE	CH_ECACHE_MAX_SIZE
7207c478bd9Sstevel@tonic-gate #define	CHP_ECACHE_MAX_SETSIZE	(CHP_ECACHE_MAX_SIZE / CHP_ECACHE_MIN_NWAY)
7217c478bd9Sstevel@tonic-gate #endif	/* CHEETAH_PLUS */
7227c478bd9Sstevel@tonic-gate 
7237c478bd9Sstevel@tonic-gate /*
7247c478bd9Sstevel@tonic-gate  * Bits to shift EC_tag field of E$ tag to form PA
7257c478bd9Sstevel@tonic-gate  * (See Cheetah PRM 10.7.4, Cheetah+ Delta PRM 10.7)
7267c478bd9Sstevel@tonic-gate  */
7277c478bd9Sstevel@tonic-gate #if defined(JALAPENO) || defined(SERRANO)
7287c478bd9Sstevel@tonic-gate #define	CH_ECTAG_PA_SHIFT	18
7297c478bd9Sstevel@tonic-gate #elif defined(CHEETAH_PLUS)
7307c478bd9Sstevel@tonic-gate #define	CH_ECTAG_PA_SHIFT	2
7317c478bd9Sstevel@tonic-gate #else	/* CHEETAH_PLUS */
7327c478bd9Sstevel@tonic-gate #define	CH_ECTAG_PA_SHIFT	1
7337c478bd9Sstevel@tonic-gate #endif	/* CHEETAH_PLUS */
7347c478bd9Sstevel@tonic-gate #define	PN_L3TAG_PA_SHIFT	1
7357c478bd9Sstevel@tonic-gate #define	PN_L3TAG_PA_MASK	0xfffff000000	/* tag bits[43:24] */
7367c478bd9Sstevel@tonic-gate #define	PN_L2TAG_PA_MASK	0x7fffff80000	/* tag bits[42:19] */
7377c478bd9Sstevel@tonic-gate 
7387c478bd9Sstevel@tonic-gate #if defined(JALAPENO) || defined(SERRANO)
7397c478bd9Sstevel@tonic-gate /*
7407c478bd9Sstevel@tonic-gate  * Macros for Jalapeno L2 Cache Tag/State/Parity
7417c478bd9Sstevel@tonic-gate  *
7427c478bd9Sstevel@tonic-gate  * +-----------+--------+--------+----------------------+
7437c478bd9Sstevel@tonic-gate  * |   -       | EC_par |EC_state|  EC_tag = PA[42:18]  |
7447c478bd9Sstevel@tonic-gate  * +-----------+--------+--------+----------------------+
7457c478bd9Sstevel@tonic-gate  *    63:29        28      27:25         24:0
7467c478bd9Sstevel@tonic-gate  */
7477c478bd9Sstevel@tonic-gate /*
7487c478bd9Sstevel@tonic-gate  * Constants representing the complete Jalapeno Ecache tag state:
7497c478bd9Sstevel@tonic-gate  */
7507c478bd9Sstevel@tonic-gate #define	JP_ECSTATE_SIZE		3		/* three bits */
7517c478bd9Sstevel@tonic-gate #define	JP_ECSTATE_MASK		0x7		/* three bit field */
7527c478bd9Sstevel@tonic-gate #define	JP_ECSTATE_INV		0x0		/* invalid */
7537c478bd9Sstevel@tonic-gate #define	JP_ECSTATE_SHR		0x1		/* shared */
7547c478bd9Sstevel@tonic-gate #define	JP_ECSTATE_RES1		0x2		/* reserved */
7557c478bd9Sstevel@tonic-gate #define	JP_ECSTATE_EXL		0x3		/* exclusive */
7567c478bd9Sstevel@tonic-gate #define	JP_ECSTATE_RES2		0x4		/* reserved */
7577c478bd9Sstevel@tonic-gate #define	JP_ECSTATE_OWN		0x5		/* owner */
7587c478bd9Sstevel@tonic-gate #define	JP_ECSTATE_MOD		0x7		/* modified */
7597c478bd9Sstevel@tonic-gate #define	JP_ECSTATE_RES3		0x6		/* reserved */
7607c478bd9Sstevel@tonic-gate #define	JP_ECTAG_STATE_SHIFT	25
7617c478bd9Sstevel@tonic-gate 
7627c478bd9Sstevel@tonic-gate #define	CH_ECSTATE_SIZE		JP_ECSTATE_SIZE
7637c478bd9Sstevel@tonic-gate #define	CH_ECSTATE_MASK		JP_ECSTATE_MASK
7647c478bd9Sstevel@tonic-gate #define	CH_ECSTATE_INV		JP_ECSTATE_INV
7657c478bd9Sstevel@tonic-gate #define	CH_ECSTATE_SHR		JP_ECSTATE_SHR
7667c478bd9Sstevel@tonic-gate #define	CH_ECSTATE_EXL		JP_ECSTATE_EXL
7677c478bd9Sstevel@tonic-gate #define	CH_ECSTATE_OWN		JP_ECSTATE_OWN
7687c478bd9Sstevel@tonic-gate #define	CH_ECSTATE_MOD		JP_ECSTATE_MOD
7697c478bd9Sstevel@tonic-gate #define	CH_ECSTATE_RES1		JP_ECSTATE_RES1
7707c478bd9Sstevel@tonic-gate #define	CH_ECSTATE_OWS		JP_ECSTATE_RES3
7717c478bd9Sstevel@tonic-gate #define	CH_ECSTATE_RES2		JP_ECSTATE_RES2
7727c478bd9Sstevel@tonic-gate 
7737c478bd9Sstevel@tonic-gate /* Number of subblock states per Ecache line. */
7747c478bd9Sstevel@tonic-gate #define	CH_ECTAG_NSUBBLKS(totalsize)	1
7757c478bd9Sstevel@tonic-gate 
7767c478bd9Sstevel@tonic-gate /* Mask for Tag state(s) field, 3 bits per subblock state. */
7777c478bd9Sstevel@tonic-gate #define	CH_ECTAG_STATE_SHIFT(subblk)	JP_ECTAG_STATE_SHIFT
7787c478bd9Sstevel@tonic-gate #define	CH_ECTAG_STATE_MASK(totalsize)			\
7797c478bd9Sstevel@tonic-gate 	((uint64_t)(JP_ECSTATE_MASK<<JP_ECTAG_STATE_SHIFT))
7807c478bd9Sstevel@tonic-gate 
7817c478bd9Sstevel@tonic-gate /* For a line to be invalid, all of its subblock states must be invalid. */
7827c478bd9Sstevel@tonic-gate #define	CH_ECTAG_LINE_INVALID(totalsize, tag)		\
7837c478bd9Sstevel@tonic-gate 	(((tag) & CH_ECTAG_STATE_MASK(totalsize)) == 0)
7847c478bd9Sstevel@tonic-gate 
7857c478bd9Sstevel@tonic-gate /* Build address mask for tag physical address bits. */
7867c478bd9Sstevel@tonic-gate #define	CH_ECTAG_PA_MASK(setsize)	P2ALIGN(C_AFAR_PA, (int)(setsize))
7877c478bd9Sstevel@tonic-gate 
7887c478bd9Sstevel@tonic-gate /* Get physical address bits from the EC_tag field of an E$ tag */
7897c478bd9Sstevel@tonic-gate #define	CH_ECTAG_TO_PA(setsize, tag)	(((tag) << CH_ECTAG_PA_SHIFT) &	\
7907c478bd9Sstevel@tonic-gate 	CH_ECTAG_PA_MASK(setsize))
7917c478bd9Sstevel@tonic-gate 
7927c478bd9Sstevel@tonic-gate /* Given a physical address, compute index for subblock tag state. */
7937c478bd9Sstevel@tonic-gate #define	CH_ECTAG_PA_TO_SUBBLK(totalsize, pa)		1
7947c478bd9Sstevel@tonic-gate 
7957c478bd9Sstevel@tonic-gate /* Given a physical address and assoc. tag, get the subblock state. */
7967c478bd9Sstevel@tonic-gate #define	CH_ECTAG_PA_TO_SUBBLK_STATE(totalsize, pa, tag)			\
7977c478bd9Sstevel@tonic-gate 	(((tag) >> JP_ECTAG_STATE_SHIFT) &	JP_ECSTATE_MASK)
7987c478bd9Sstevel@tonic-gate 
7997c478bd9Sstevel@tonic-gate #else /* JALAPENO || SERRANO */
8007c478bd9Sstevel@tonic-gate 
8017c478bd9Sstevel@tonic-gate /*
8027c478bd9Sstevel@tonic-gate  * Constants representing the complete Cheetah Ecache tag state:
8037c478bd9Sstevel@tonic-gate  */
8047c478bd9Sstevel@tonic-gate #define	CH_ECSTATE_SIZE		3		/* three bits per subblock */
8057c478bd9Sstevel@tonic-gate #define	CH_ECSTATE_MASK		0x7		/* three bit field */
8067c478bd9Sstevel@tonic-gate #define	CH_ECSTATE_INV		0x0		/* invalid */
8077c478bd9Sstevel@tonic-gate #define	CH_ECSTATE_SHR		0x1		/* shared */
8087c478bd9Sstevel@tonic-gate #define	CH_ECSTATE_EXL		0x2		/* exclusive */
8097c478bd9Sstevel@tonic-gate #define	CH_ECSTATE_OWN		0x3		/* owner */
8107c478bd9Sstevel@tonic-gate #define	CH_ECSTATE_MOD		0x4		/* modified */
8117c478bd9Sstevel@tonic-gate #define	CH_ECSTATE_RES1		0x5		/* reserved */
8127c478bd9Sstevel@tonic-gate #define	CH_ECSTATE_OWS		0x6		/* owner/shared */
8137c478bd9Sstevel@tonic-gate #define	CH_ECSTATE_RES2		0x7		/* reserved */
8147c478bd9Sstevel@tonic-gate 
8157c478bd9Sstevel@tonic-gate /*
8167c478bd9Sstevel@tonic-gate  * Macros for Cheetah Ecache tags
8177c478bd9Sstevel@tonic-gate  */
8187c478bd9Sstevel@tonic-gate 
8197c478bd9Sstevel@tonic-gate /* Number of subblock states per Ecache line. */
8207c478bd9Sstevel@tonic-gate #define	CH_ECTAG_NSUBBLKS(totalsize)	((totalsize) / CH_ECACHE_1M_SIZE)
8217c478bd9Sstevel@tonic-gate 
8227c478bd9Sstevel@tonic-gate /* Mask for Tag state(s) field, 3 bits per subblock state. */
8237c478bd9Sstevel@tonic-gate #define	CH_ECTAG_STATE_SHIFT(subblk)	(subblk * CH_ECSTATE_SIZE)
8247c478bd9Sstevel@tonic-gate #define	CH_ECTAG_STATE_MASK(totalsize)			\
8257c478bd9Sstevel@tonic-gate 	((uint64_t)					\
8267c478bd9Sstevel@tonic-gate 	((1 << (CH_ECTAG_NSUBBLKS(totalsize) * CH_ECSTATE_SIZE)) - 1))
8277c478bd9Sstevel@tonic-gate 
8287c478bd9Sstevel@tonic-gate /* For a line to be invalid, all of its subblock states must be invalid. */
8297c478bd9Sstevel@tonic-gate #define	CH_ECTAG_LINE_INVALID(totalsize, tag)		\
8307c478bd9Sstevel@tonic-gate 	(((tag) & CH_ECTAG_STATE_MASK(totalsize)) == 0)
8317c478bd9Sstevel@tonic-gate 
8327c478bd9Sstevel@tonic-gate /* Build address mask for tag physical address bits. */
8337c478bd9Sstevel@tonic-gate #define	CH_ECTAG_PA_MASK(setsize)	P2ALIGN(C_AFAR_PA, (int)(setsize))
8347c478bd9Sstevel@tonic-gate 
8357c478bd9Sstevel@tonic-gate /* Get physical address bits from the EC_tag field of an E$ tag */
8367c478bd9Sstevel@tonic-gate #define	CH_ECTAG_TO_PA(setsize, tag)	(((tag) >> CH_ECTAG_PA_SHIFT) &	\
8377c478bd9Sstevel@tonic-gate 	CH_ECTAG_PA_MASK(setsize))
8387c478bd9Sstevel@tonic-gate 
8397c478bd9Sstevel@tonic-gate /* Given a physical address, compute index for subblock tag state. */
8407c478bd9Sstevel@tonic-gate #define	CH_ECTAG_PA_TO_SUBBLK(totalsize, pa)		\
8417c478bd9Sstevel@tonic-gate 	(((pa) >> CH_ECACHE_SUBBLK_SHIFT) & (CH_ECTAG_NSUBBLKS(totalsize) - 1))
8427c478bd9Sstevel@tonic-gate 
8437c478bd9Sstevel@tonic-gate /* Given a physical address and assoc. tag, get the subblock state. */
8447c478bd9Sstevel@tonic-gate #define	CH_ECTAG_PA_TO_SUBBLK_STATE(totalsize, pa, tag)			\
8457c478bd9Sstevel@tonic-gate 	(((tag) >>							\
8467c478bd9Sstevel@tonic-gate 	(CH_ECTAG_PA_TO_SUBBLK(totalsize, pa) * CH_ECSTATE_SIZE)) &	\
8477c478bd9Sstevel@tonic-gate 	CH_ECSTATE_MASK)
8487c478bd9Sstevel@tonic-gate #endif /* JALAPENO || SERRANO */
8497c478bd9Sstevel@tonic-gate 
8507c478bd9Sstevel@tonic-gate /* Panther only has one EC_State field in the L3 tag */
8517c478bd9Sstevel@tonic-gate #define	PN_L3_LINE_INVALID(tag)		(((tag) & CH_ECSTATE_MASK) == 0)
8527c478bd9Sstevel@tonic-gate 
8537c478bd9Sstevel@tonic-gate /* Panther only has one State field in the L2 tag */
8547c478bd9Sstevel@tonic-gate #define	PN_L2_LINE_INVALID(tag)		(((tag) & CH_ECSTATE_MASK) == 0)
8557c478bd9Sstevel@tonic-gate 
8567c478bd9Sstevel@tonic-gate /* Get physical address bits from the EC_tag field of an L3$ tag */
8577c478bd9Sstevel@tonic-gate #define	PN_L3TAG_TO_PA(tag)		(((tag) & PN_L3TAG_PA_MASK) >> \
8587c478bd9Sstevel@tonic-gate 	PN_L3TAG_PA_SHIFT)
8597c478bd9Sstevel@tonic-gate 
8607c478bd9Sstevel@tonic-gate /* Get physical address bits from the tag field of an L2$ tag */
8617c478bd9Sstevel@tonic-gate #define	PN_L2TAG_TO_PA(tag)		((tag) & PN_L2TAG_PA_MASK)
8627c478bd9Sstevel@tonic-gate 
8637c478bd9Sstevel@tonic-gate #if defined(JALAPENO) || defined(SERRANO)
8647c478bd9Sstevel@tonic-gate /*
8657c478bd9Sstevel@tonic-gate  * Jalapeno L2 Cache ASI_ECACHE_FLUSH:
8667c478bd9Sstevel@tonic-gate  * +-------+-----------------+--------+---+-----+-------------+------+
8677c478bd9Sstevel@tonic-gate  * |   -   | Port_ID |   -   | EC_Way | 1 |  -  | EC_Tag_Addr |   -  |
8687c478bd9Sstevel@tonic-gate  * +-------+-----------------+--------+---+-----+-------------+------+
8697c478bd9Sstevel@tonic-gate  *  63:41     40:36    35:34    33:32  31  30:18      17:6       5:0
8707c478bd9Sstevel@tonic-gate  */
8717c478bd9Sstevel@tonic-gate 
8727c478bd9Sstevel@tonic-gate #define	JP_EC_TO_SET_SIZE_SHIFT		2
8737c478bd9Sstevel@tonic-gate #define	JP_ECACHE_IDX_DISP_FLUSH	INT64_C(0x0000000080000000)
8747c478bd9Sstevel@tonic-gate #define	JP_ECFLUSH_PORTID_SHIFT		36
8757c478bd9Sstevel@tonic-gate #define	JP_ECFLUSH_EC_WAY_SHIFT		32
8767c478bd9Sstevel@tonic-gate #define	JP_EC_TAG_DATA_WAY_SHIFT	JP_ECFLUSH_EC_WAY_SHIFT
8777c478bd9Sstevel@tonic-gate #endif	/* JALAPENO || SERRANO */
8787c478bd9Sstevel@tonic-gate 
8797c478bd9Sstevel@tonic-gate /*
8807c478bd9Sstevel@tonic-gate  * Macros for Jaguar Ecache tags
8817c478bd9Sstevel@tonic-gate  */
8827c478bd9Sstevel@tonic-gate 
8837c478bd9Sstevel@tonic-gate /* Ecache sizes */
8847c478bd9Sstevel@tonic-gate #define	JG_ECACHE_8M_SIZE	0x800000
8857c478bd9Sstevel@tonic-gate #define	JG_ECACHE_4M_SIZE	0x400000
8867c478bd9Sstevel@tonic-gate 
8877c478bd9Sstevel@tonic-gate /* Jaguar E$ tag LRU mask */
8887c478bd9Sstevel@tonic-gate #define	JG_LRU_MASK UINT64_C(0x0000040000000000) /* PA<42> LRU bit */
8897c478bd9Sstevel@tonic-gate 
8907c478bd9Sstevel@tonic-gate /*
8917c478bd9Sstevel@tonic-gate  * Note that Jaguar and Cheetah/Cheetah+ have the same subblock state size
8927c478bd9Sstevel@tonic-gate  * so rather than duplicating existing defn's we can use the Cheetah+ versions
8937c478bd9Sstevel@tonic-gate  * in the Jaguar defn's below.
8947c478bd9Sstevel@tonic-gate  */
8957c478bd9Sstevel@tonic-gate /* Number of subblock states per Ecache line. */
8967c478bd9Sstevel@tonic-gate #define	JG_ECTAG_NSUBBLKS(cachesize)	((cachesize) / JG_ECACHE_4M_SIZE)
8977c478bd9Sstevel@tonic-gate 
8987c478bd9Sstevel@tonic-gate /* Mask for Tag state(s) field, 3 bits per subblock state. */
8997c478bd9Sstevel@tonic-gate #define	JG_ECTAG_STATE_MASK(totalsize)			\
9007c478bd9Sstevel@tonic-gate 	((uint64_t)					\
9017c478bd9Sstevel@tonic-gate 	((1 << (JG_ECTAG_NSUBBLKS(totalsize) * CH_ECSTATE_SIZE)) - 1))
9027c478bd9Sstevel@tonic-gate 
9037c478bd9Sstevel@tonic-gate /* For a line to be invalid, all of its subblock states must be invalid. */
9047c478bd9Sstevel@tonic-gate #define	JG_ECTAG_LINE_INVALID(totalsize, tag)		\
9057c478bd9Sstevel@tonic-gate 	(((tag) & JG_ECTAG_STATE_MASK(totalsize)) == 0)
9067c478bd9Sstevel@tonic-gate 
9077c478bd9Sstevel@tonic-gate /* Build address mask for tag physical address bits. */
9087c478bd9Sstevel@tonic-gate #define	JG_ECTAG_PA_MASK(setsize)	P2ALIGN(((~JG_LRU_MASK) & C_AFAR_PA), \
9097c478bd9Sstevel@tonic-gate 							(int)(setsize))
9107c478bd9Sstevel@tonic-gate 
9117c478bd9Sstevel@tonic-gate /* Get physical address bits from the EC_tag field of an E$ tag */
9127c478bd9Sstevel@tonic-gate #define	JG_ECTAG_TO_PA(setsize, tag)	((tag & JG_ECTAG_PA_MASK(setsize)))
9137c478bd9Sstevel@tonic-gate 
9147c478bd9Sstevel@tonic-gate /* Given a physical address, compute index for subblock tag state. */
9157c478bd9Sstevel@tonic-gate #define	JG_ECTAG_PA_TO_SUBBLK(totalsize, pa)		\
9167c478bd9Sstevel@tonic-gate 	(((pa) >> CH_ECACHE_SUBBLK_SHIFT) & (JG_ECTAG_NSUBBLKS(totalsize) - 1))
9177c478bd9Sstevel@tonic-gate 
9187c478bd9Sstevel@tonic-gate /* Given a physical address and assoc. tag, get the subblock state. */
9197c478bd9Sstevel@tonic-gate #define	JG_ECTAG_PA_TO_SUBBLK_STATE(totalsize, pa, tag)			\
9207c478bd9Sstevel@tonic-gate 	(((tag) >>							\
9217c478bd9Sstevel@tonic-gate 	(JG_ECTAG_PA_TO_SUBBLK(totalsize, pa) * CH_ECSTATE_SIZE)) &	\
9227c478bd9Sstevel@tonic-gate 	CH_ECSTATE_MASK)
9237c478bd9Sstevel@tonic-gate 
9247c478bd9Sstevel@tonic-gate 
9257c478bd9Sstevel@tonic-gate #if defined(CHEETAH_PLUS)
9267c478bd9Sstevel@tonic-gate /*
9277c478bd9Sstevel@tonic-gate  * Cheetah+ Tag ECC Bit and Displacement Flush Bit in Ecache Tag Access.
9287c478bd9Sstevel@tonic-gate  * See Cheetah+ Delta PRM 10.7
9297c478bd9Sstevel@tonic-gate  */
9307c478bd9Sstevel@tonic-gate #define	CHP_ECACHE_IDX_TAG_ECC		INT64_C(0x0000000000800000)
9317c478bd9Sstevel@tonic-gate #define	CHP_ECACHE_IDX_DISP_FLUSH	INT64_C(0x0000000001000000)
9327c478bd9Sstevel@tonic-gate #define	PN_L2_IDX_DISP_FLUSH		INT64_C(0x0000000000800000)
9337c478bd9Sstevel@tonic-gate #define	PN_L3_IDX_DISP_FLUSH		INT64_C(0x0000000004000000)
9347c478bd9Sstevel@tonic-gate #endif	/* CHEETAH_PLUS */
9357c478bd9Sstevel@tonic-gate 
9367c478bd9Sstevel@tonic-gate /*
9377c478bd9Sstevel@tonic-gate  * Macros for Cheetah Dcache diagnostic accesses.
9387c478bd9Sstevel@tonic-gate  */
9397c478bd9Sstevel@tonic-gate 
9407c478bd9Sstevel@tonic-gate /*
9417c478bd9Sstevel@tonic-gate  * Dcache Index Mask for bits from *AFAR*.  Note that Dcache is virtually
9427c478bd9Sstevel@tonic-gate  * indexed, so only bits [12:5] are valid from the AFAR.  This
9437c478bd9Sstevel@tonic-gate  * means we have to search through the 4 ways + bit 13 (i.e. we have
9447c478bd9Sstevel@tonic-gate  * to try 8 indexes).
9457c478bd9Sstevel@tonic-gate  */
9467c478bd9Sstevel@tonic-gate #define	CH_DCACHE_IDX_MASK		0x01fe0
9477c478bd9Sstevel@tonic-gate #define	CH_DCACHE_IDX_INCR		0x02000
9487c478bd9Sstevel@tonic-gate #define	CH_DCACHE_IDX_LIMIT		0x10000
9497c478bd9Sstevel@tonic-gate #define	CH_DCACHE_NWAY			4
9507c478bd9Sstevel@tonic-gate #define	CH_DCACHE_WAY_MASK		0x0c000
9517c478bd9Sstevel@tonic-gate #define	CH_DCACHE_WAY_SHIFT		14
9527c478bd9Sstevel@tonic-gate #define	CH_DCIDX_TO_WAY(idx)		(((idx) & CH_DCACHE_WAY_MASK) >> \
9537c478bd9Sstevel@tonic-gate 						CH_DCACHE_WAY_SHIFT)
9547c478bd9Sstevel@tonic-gate #define	CH_DCTAG_PA_MASK		INT64_C(0x000007ffffffe000)
9557c478bd9Sstevel@tonic-gate #define	CH_DCTAG_PA_SHIFT		12
9567c478bd9Sstevel@tonic-gate #define	CH_DCTAG_VALID_BIT		INT64_C(0x0000000000000001)
9577c478bd9Sstevel@tonic-gate #define	CH_DCTAG_LINE_INVALID(tag)	(((tag) & CH_DCTAG_VALID_BIT) == 0)
9587c478bd9Sstevel@tonic-gate #define	CH_DCIDX_TO_ADDR(idx)		((idx) & CH_DCACHE_IDX_MASK)
9597c478bd9Sstevel@tonic-gate #define	CH_DCTAG_TO_PA(tag)		(((tag) << CH_DCTAG_PA_SHIFT) & \
9607c478bd9Sstevel@tonic-gate 					    CH_DCTAG_PA_MASK)
9617c478bd9Sstevel@tonic-gate #define	CH_DCTAG_MATCH(tag, pa)		(!CH_DCTAG_LINE_INVALID(tag) && \
9627c478bd9Sstevel@tonic-gate 			    ((pa) & CH_DCTAG_PA_MASK) == CH_DCTAG_TO_PA(tag))
9637c478bd9Sstevel@tonic-gate #define	CH_DCSNTAG_MASK			INT64_C(0x000007ffffffe000)
9647c478bd9Sstevel@tonic-gate #define	CH_DCSNTAG_TO_PA(tag)		((tag << CH_DCTAG_PA_SHIFT) \
9657c478bd9Sstevel@tonic-gate 							& CH_DCSNTAG_MASK)
9667c478bd9Sstevel@tonic-gate #define	CH_DCUTAG_TO_UTAG(tag)		((tag) & 0xff)
9677c478bd9Sstevel@tonic-gate #define	CH_DCUTAG_TO_VA(tag)		((tag & 0xff) << 14)
9687c478bd9Sstevel@tonic-gate #define	CH_DCUTAG_IDX_MASK		0x03fe0
9697c478bd9Sstevel@tonic-gate #define	CH_DC_DATA_REG_SIZE		32
9707c478bd9Sstevel@tonic-gate #define	CH_DC_UTAG_MASK			0xff
9717c478bd9Sstevel@tonic-gate #if defined(CHEETAH_PLUS) || defined(JALAPENO) || defined(SERRANO)
9727c478bd9Sstevel@tonic-gate #define	CHP_DCTAG_PARMASK		INT64_C(0x000000007ffffffe)
9737c478bd9Sstevel@tonic-gate #define	CHP_DCSNTAG_PARMASK		INT64_C(0x000000007ffffffe)
9747c478bd9Sstevel@tonic-gate #define	CHP_DCTAG_MASK			INT64_C(0x000003ffffffe000)
9757c478bd9Sstevel@tonic-gate #define	CHP_DCSNTAG_MASK		INT64_C(0x000003ffffffe000)
9767c478bd9Sstevel@tonic-gate #define	CHP_DCWAY_MASK			INT64_C(0x0000000000003fe0)
9777c478bd9Sstevel@tonic-gate #define	CHP_DCUTAG_TO_UTAG(tag)		((tag) & 0xffff)
9787c478bd9Sstevel@tonic-gate #define	CHP_DCPATAG_TO_PA(tag)		((tag << CH_DCTAG_PA_SHIFT) \
9797c478bd9Sstevel@tonic-gate 							& CHP_DCTAG_MASK)
9807c478bd9Sstevel@tonic-gate #define	CHP_DCSNTAG_TO_PA(tag)		((tag << CH_DCTAG_PA_SHIFT) \
9817c478bd9Sstevel@tonic-gate 							& CHP_DCSNTAG_MASK)
9827c478bd9Sstevel@tonic-gate #define	CHP_DC_IDX(dcp)			((dcp->dc_idx & 0x1fc0) >> 5)
9837c478bd9Sstevel@tonic-gate #define	CHP_DCTAG_PARITY(tag)		(tag & CHP_DC_TAG)
9847c478bd9Sstevel@tonic-gate #define	CHP_DCSNTAG_PARITY(tag)		(tag & CHP_DC_SNTAG)
9857c478bd9Sstevel@tonic-gate #define	CHP_DC_TAG			0x1
9867c478bd9Sstevel@tonic-gate #define	CHP_DC_SNTAG			0x2
9877c478bd9Sstevel@tonic-gate #define	PN_DC_DATA_PARITY_SHIFT    	8
9887c478bd9Sstevel@tonic-gate #define	PN_DC_DATA_PARITY_MASK    	0xff
9897c478bd9Sstevel@tonic-gate #define	PN_DC_DATA_ALL_PARITY_MASK    	0xffffffff
9907c478bd9Sstevel@tonic-gate #endif	/* CHEETAH_PLUS || JALAPENO || SERRANO */
9917c478bd9Sstevel@tonic-gate #define	PN_DC_DATA_PARITY_BIT_SHIFT    	16
9927c478bd9Sstevel@tonic-gate 
9937c478bd9Sstevel@tonic-gate /*
9947c478bd9Sstevel@tonic-gate  * Macros for Cheetah Icache diagnostic accesses.
9957c478bd9Sstevel@tonic-gate  */
9967c478bd9Sstevel@tonic-gate 
9977c478bd9Sstevel@tonic-gate /*
9987c478bd9Sstevel@tonic-gate  * Icache Index Mask for bits from *AFAR*. Note that the Icache is virtually
9997c478bd9Sstevel@tonic-gate  * indexed for Panther and physically indexed for other CPUs. For Panther,
10007c478bd9Sstevel@tonic-gate  * we obtain an index by looking at bits[12:6] of the AFAR PA and we check
10017c478bd9Sstevel@tonic-gate  * both lines associated with bit 13 = 0 or 1 (total of 8 entries to check).
10027c478bd9Sstevel@tonic-gate  * For non-Panther CPUs we get our index by just looking at bits[12:5] of
10037c478bd9Sstevel@tonic-gate  * the AFAR PA (total of 4 entries to check). The Icache index is also
10047c478bd9Sstevel@tonic-gate  * confusing because we need to shift the virtual address bits left by one
10057c478bd9Sstevel@tonic-gate  * for the index.
10067c478bd9Sstevel@tonic-gate  */
10077c478bd9Sstevel@tonic-gate #define	CH_ICACHE_IDX_MASK		0x01fe0
10087c478bd9Sstevel@tonic-gate #define	PN_ICACHE_IDX_MASK		0x03fc0
10097c478bd9Sstevel@tonic-gate #define	PN_ICACHE_VA_IDX_MASK		0x01fc0
10107c478bd9Sstevel@tonic-gate #define	CH_ICACHE_IDX_SHIFT		1
10117c478bd9Sstevel@tonic-gate #define	CH_ICACHE_IDX_INCR		0x04000
10127c478bd9Sstevel@tonic-gate #define	PN_ICACHE_IDX_INCR		0x08000
10137c478bd9Sstevel@tonic-gate #define	CH_ICACHE_IDX_LIMIT		0x10000
10147c478bd9Sstevel@tonic-gate #define	PN_ICACHE_IDX_LIMIT		0x20000
10157c478bd9Sstevel@tonic-gate #define	CH_ICACHE_NWAY			4
10167c478bd9Sstevel@tonic-gate #define	CH_ICACHE_WAY_MASK		0x0c000
10177c478bd9Sstevel@tonic-gate #define	CH_ICACHE_WAY_SHIFT		14
10187c478bd9Sstevel@tonic-gate #define	PN_ICACHE_WAY_MASK		0x18000
10197c478bd9Sstevel@tonic-gate #define	PN_ICACHE_WAY_SHIFT		15
10207c478bd9Sstevel@tonic-gate #define	CH_ICTAG_PA			0x00
10217c478bd9Sstevel@tonic-gate #define	CH_ICTAG_UTAG			0x08
10227c478bd9Sstevel@tonic-gate #define	CH_ICTAG_UPPER			0x10
10237c478bd9Sstevel@tonic-gate #define	CH_ICTAG_LOWER			0x30
10247c478bd9Sstevel@tonic-gate #define	CH_ICTAG_TMASK			0x3f
10257c478bd9Sstevel@tonic-gate #define	CH_ICPATAG_MASK			INT64_C(0x000007ffffffe000)
10267c478bd9Sstevel@tonic-gate #define	CH_ICPATAG_LBITS		0xff	/* lower 8 bits undefined */
10277c478bd9Sstevel@tonic-gate #define	CH_ICPATAG_SHIFT		5
10287c478bd9Sstevel@tonic-gate #define	CH_ICIDX_TO_WAY(idx)		(((idx) & CH_ICACHE_WAY_MASK) >> \
10297c478bd9Sstevel@tonic-gate 						CH_ICACHE_WAY_SHIFT)
10307c478bd9Sstevel@tonic-gate #define	PN_ICIDX_TO_WAY(idx)		(((idx) & PN_ICACHE_WAY_MASK) >> \
10317c478bd9Sstevel@tonic-gate 						PN_ICACHE_WAY_SHIFT)
10327c478bd9Sstevel@tonic-gate #define	CH_ICIDX_TO_ADDR(idx)		(((idx) >> CH_ICACHE_IDX_SHIFT) & \
10337c478bd9Sstevel@tonic-gate 						CH_ICACHE_IDX_MASK)
10347c478bd9Sstevel@tonic-gate #define	PN_ICIDX_TO_ADDR(idx)		(((idx) >> CH_ICACHE_IDX_SHIFT) & \
10357c478bd9Sstevel@tonic-gate 						PN_ICACHE_IDX_MASK)
10367c478bd9Sstevel@tonic-gate #define	CH_ICPATAG_TO_PA(tag)		(((tag) << CH_ICPATAG_SHIFT) & \
10377c478bd9Sstevel@tonic-gate 						CH_ICPATAG_MASK)
10387c478bd9Sstevel@tonic-gate #define	CH_ICPATAG_MATCH(tag, pa)	(CH_ICPATAG_TO_PA(tag) == \
10397c478bd9Sstevel@tonic-gate 						((pa) & CH_ICPATAG_MASK))
10407c478bd9Sstevel@tonic-gate #define	CH_ICUTAG_MASK			INT64_C(0x00000000001fe000)
10417c478bd9Sstevel@tonic-gate #define	CH_ICUTAG_TO_UTAG(tag)		(((tag) >> 38) & 0xff)
10427c478bd9Sstevel@tonic-gate #define	CH_ICUTAG_TO_VA(tag)		(((tag) >> 25) & CH_ICUTAG_MASK)
10437c478bd9Sstevel@tonic-gate #define	CH_ICSNTAG_MASK			INT64_C(0x000007ffffffe000)
10447c478bd9Sstevel@tonic-gate #define	CH_ICSNTAG_TO_PA(tag)		(((tag) << 5) & CH_ICSNTAG_MASK)
10457c478bd9Sstevel@tonic-gate #define	CH_ICLOWER_VALID		INT64_C(0x0004000000000000)
10467c478bd9Sstevel@tonic-gate #define	CH_ICUPPER_VALID		INT64_C(0x0004000000000000)
10477c478bd9Sstevel@tonic-gate #define	CH_ICLOWER_TO_VPRED(lower)	(((lower) >> 46) & 0xf)
10487c478bd9Sstevel@tonic-gate #define	CH_ICUPPER_TO_VPRED(upper)	(((upper) >> 46) & 0xf)
10497c478bd9Sstevel@tonic-gate #if defined(CHEETAH_PLUS)
10507c478bd9Sstevel@tonic-gate #define	CH_ICTAG_MATCH(icp, pa)		(((icp->ic_lower | icp->ic_upper) & \
10517c478bd9Sstevel@tonic-gate 					    CH_ICLOWER_VALID) && \
10527c478bd9Sstevel@tonic-gate 					    CH_ICPATAG_MATCH(icp->ic_patag, pa))
10537c478bd9Sstevel@tonic-gate #define	PN_ICUTAG_TO_VA(tag)		((tag >> 24) & PN_ICUTAG_MASK)
10547c478bd9Sstevel@tonic-gate #else	/* CHEETAH_PLUS */
10557c478bd9Sstevel@tonic-gate #define	CH_ICTAG_MATCH(icp, pa)		((icp->ic_lower & CH_ICLOWER_VALID) &&\
10567c478bd9Sstevel@tonic-gate 					    CH_ICPATAG_MATCH(icp->ic_patag, pa))
10577c478bd9Sstevel@tonic-gate #define	PN_ICUTAG_TO_VA(tag)		0
10587c478bd9Sstevel@tonic-gate #endif	/* CHEETAH_PLUS */
10597c478bd9Sstevel@tonic-gate 
10607c478bd9Sstevel@tonic-gate #define	CH_IC_DATA_REG_SIZE		64
10617c478bd9Sstevel@tonic-gate #define	PN_IC_DATA_REG_SIZE		128
10627c478bd9Sstevel@tonic-gate #if defined(CHEETAH_PLUS) || defined(JALAPENO) || defined(SERRANO)
10637c478bd9Sstevel@tonic-gate #define	CHP_IC_IDX(icp)			((icp->ic_idx & 0x3fc0) >> 6)
10647c478bd9Sstevel@tonic-gate #define	PN_IC_IDX(icp)			((icp->ic_idx & 0x7f80) >> 7)
10657c478bd9Sstevel@tonic-gate #define	CHP_ICPATAG_MASK		INT64_C(0x000003ffffffe000)
10667c478bd9Sstevel@tonic-gate #define	CHP_ICSNTAG_MASK		INT64_C(0x000003ffffffe000)
10677c478bd9Sstevel@tonic-gate #define	CHP_ICUTAG_MASK			INT64_C(0x00000000001fe000)
10687c478bd9Sstevel@tonic-gate #define	PN_ICUTAG_MASK			INT64_C(0x00000000003fc000)
10697c478bd9Sstevel@tonic-gate #define	CHP_ICWAY_MASK			INT64_C(0x0000000000003fe0)
10707c478bd9Sstevel@tonic-gate #define	CHP_ICPATAG_TO_PA(tag)		((tag << 5) & CHP_ICPATAG_MASK)
10717c478bd9Sstevel@tonic-gate #define	CHP_ICSNTAG_TO_PA(tag)		((tag << 5) & CHP_ICSNTAG_MASK)
10727c478bd9Sstevel@tonic-gate #define	CHP_ICUTAG_TO_VA(tag)		((tag >> 25) & CHP_ICUTAG_MASK)
10737c478bd9Sstevel@tonic-gate #define	CHP_ICPATAG_PARMASK		INT64_C(0x0000003fffffff00)
10747c478bd9Sstevel@tonic-gate #define	CHP_ICSNTAG_PARMASK		INT64_C(0x0000003fffffff00)
10757c478bd9Sstevel@tonic-gate 
10767c478bd9Sstevel@tonic-gate /*
10777c478bd9Sstevel@tonic-gate  * Cheetah+ Icache data parity masks, see Cheetah+ Delta PRM 7.3
10787c478bd9Sstevel@tonic-gate  * PC-relative instructions have different bits protected by parity.
10797c478bd9Sstevel@tonic-gate  * Predecode bit 7 is not parity protected and indicates if the instruction
10807c478bd9Sstevel@tonic-gate  * is PC-relative or not.
10817c478bd9Sstevel@tonic-gate  */
10827c478bd9Sstevel@tonic-gate #define	CH_ICDATA_PRED_ISPCREL		INT64_C(0x0000008000000000)
10837c478bd9Sstevel@tonic-gate #define	CHP_ICDATA_PCREL_PARMASK	INT64_C(0x0000039ffffff800)
10847c478bd9Sstevel@tonic-gate #define	CHP_ICDATA_NPCREL_PARMASK	INT64_C(0x000003bfffffffff)
10857c478bd9Sstevel@tonic-gate #define	PN_ICDATA_PARITY_BIT_MASK	INT64_C(0x40000000000)
10867c478bd9Sstevel@tonic-gate #define	CHP_ICTAG_PARITY(tag)		(tag & CHP_IC_TAG)
10877c478bd9Sstevel@tonic-gate #define	CHP_ICSNTAG_PARITY(tag)		(tag & CHP_IC_SNTAG)
10887c478bd9Sstevel@tonic-gate #define	CHP_IC_TAG			0x1
10897c478bd9Sstevel@tonic-gate #define	CHP_IC_SNTAG			0x2
10907c478bd9Sstevel@tonic-gate #endif	/* CHEETAH_PLUS || JALAPENO || SERRANO */
10917c478bd9Sstevel@tonic-gate #if defined(CHEETAH_PLUS)
10927c478bd9Sstevel@tonic-gate #define	PN_IPB_TAG_ADDR_LINESIZE	0x40
10937c478bd9Sstevel@tonic-gate #define	PN_IPB_TAG_ADDR_MAX		0x3c0
10947c478bd9Sstevel@tonic-gate #endif	/* CHEETAH_PLUS */
10957c478bd9Sstevel@tonic-gate 
10967c478bd9Sstevel@tonic-gate /*
10977c478bd9Sstevel@tonic-gate  * Macros for Pcache diagnostic accesses.
10987c478bd9Sstevel@tonic-gate  */
10997c478bd9Sstevel@tonic-gate #define	CH_PC_WAY_MASK			0x600
11007c478bd9Sstevel@tonic-gate #define	CH_PC_WAY_SHIFT			9
11017c478bd9Sstevel@tonic-gate #define	CH_PCIDX_TO_WAY(idx)		(((idx) & CH_PC_WAY_MASK) >> \
11027c478bd9Sstevel@tonic-gate 						CH_PC_WAY_SHIFT)
11037c478bd9Sstevel@tonic-gate #define	CH_PC_DATA_REG_SIZE		64
11047c478bd9Sstevel@tonic-gate #define	CH_PCACHE_NWAY			4
11057c478bd9Sstevel@tonic-gate #define	PN_PC_PARITY_SHIFT		50
11067c478bd9Sstevel@tonic-gate #define	PN_PC_PARITY_MASK		0xff
11077c478bd9Sstevel@tonic-gate #define	PN_PC_PARITY_BITS(status)	\
11087c478bd9Sstevel@tonic-gate 	(((status) >> PN_PC_PARITY_SHIFT) & PN_PC_PARITY_MASK)
11097c478bd9Sstevel@tonic-gate #define	CH_PC_IDX_ADR(pcp)		((pcp->pc_idx & 0x1c0) >> 6)
11107c478bd9Sstevel@tonic-gate #define	CH_PCTAG_ADDR_SHIFT		6
11117c478bd9Sstevel@tonic-gate #define	CH_PC_PA_MASK			0x7ffffffffc0
11127c478bd9Sstevel@tonic-gate #define	CH_PCTAG_TO_VA(tag)		((tag) << CH_PCTAG_ADDR_SHIFT)
11137c478bd9Sstevel@tonic-gate #define	CH_PCSTAG_TO_PA(tag)		(((tag) << CH_PCTAG_ADDR_SHIFT) & \
11147c478bd9Sstevel@tonic-gate 					    CH_PC_PA_MASK)
11157c478bd9Sstevel@tonic-gate #define	CH_PCTAG_BNK0_VALID_MASK	0x2000000000000000
11167c478bd9Sstevel@tonic-gate #define	CH_PCTAG_BNK1_VALID_MASK	0x1000000000000000
11177c478bd9Sstevel@tonic-gate #define	CH_PCTAG_BNK0_INVALID(tag)	(((tag) & CH_PCTAG_BNK0_VALID_MASK) == \
11187c478bd9Sstevel@tonic-gate 					    0)
11197c478bd9Sstevel@tonic-gate #define	CH_PCTAG_BNK1_INVALID(tag)	(((tag) & CH_PCTAG_BNK1_VALID_MASK) == \
11207c478bd9Sstevel@tonic-gate 					    0)
11217c478bd9Sstevel@tonic-gate 
11227c478bd9Sstevel@tonic-gate /*
11237c478bd9Sstevel@tonic-gate  * CPU Log Out Structure parameters.
11247c478bd9Sstevel@tonic-gate  * This structure is filled in by the Error Trap handlers and captures the
11257c478bd9Sstevel@tonic-gate  * Ecache/Dcache/Icache line(s) associated with the AFAR.
11267c478bd9Sstevel@tonic-gate  * For Cheetah Phase II, this structure is filled in at the TL=0 code.  For
11277c478bd9Sstevel@tonic-gate  * Cheetah Phase III, this will be filled in at the trap handlers.
11287c478bd9Sstevel@tonic-gate  */
11297c478bd9Sstevel@tonic-gate 
11307c478bd9Sstevel@tonic-gate /*
11317c478bd9Sstevel@tonic-gate  * We use this to mark the LOGOUT structure as invalid.  Note that
11327c478bd9Sstevel@tonic-gate  * this cannot be a valid AFAR, as AFAR bits outside of [41:5] should always
11337c478bd9Sstevel@tonic-gate  * be zero.
11347c478bd9Sstevel@tonic-gate  */
11357c478bd9Sstevel@tonic-gate #define	LOGOUT_INVALID_U32	0xecc1ecc1
11367c478bd9Sstevel@tonic-gate #define	LOGOUT_INVALID_L32	0xecc1ecc1
11377c478bd9Sstevel@tonic-gate #define	LOGOUT_INVALID		UINT64_C(0xecc1ecc1ecc1ecc1)
11387c478bd9Sstevel@tonic-gate 
11397c478bd9Sstevel@tonic-gate /*
11407c478bd9Sstevel@tonic-gate  * Max number of TLs to support for Fast ECC or Cache Parity Errors
11417c478bd9Sstevel@tonic-gate  * at TL>0.  Traps are OK from TL=1-2, at TL>=3, we will Red Mode.
11427c478bd9Sstevel@tonic-gate  */
11437c478bd9Sstevel@tonic-gate #define	CH_ERR_TL1_TLMAX	2
11447c478bd9Sstevel@tonic-gate 
11457c478bd9Sstevel@tonic-gate /*
11467c478bd9Sstevel@tonic-gate  * Software traps used by TL>0 handlers.
11477c478bd9Sstevel@tonic-gate  */
11487c478bd9Sstevel@tonic-gate #define	SWTRAP_0		0	/* Used by Fast ECC */
11497c478bd9Sstevel@tonic-gate #define	SWTRAP_1		1	/* Used by Dcache Parity */
11507c478bd9Sstevel@tonic-gate #define	SWTRAP_2		2	/* Used by Icache Parity */
11517c478bd9Sstevel@tonic-gate 
11527c478bd9Sstevel@tonic-gate /*
11537c478bd9Sstevel@tonic-gate  * Bit mask defines for various Cheetah Error conditions.
11547c478bd9Sstevel@tonic-gate  */
11557c478bd9Sstevel@tonic-gate #define	CH_ERR_FECC	0x01	/* Data/Event is Fast ECC */
11567c478bd9Sstevel@tonic-gate #define	CH_ERR_IPE	0x02	/* Data/Event is Icache Parity Error */
11577c478bd9Sstevel@tonic-gate #define	CH_ERR_DPE	0x04	/* Data/Event is Dcache Parity Error */
11587c478bd9Sstevel@tonic-gate #define	CH_ERR_PANIC	0x08	/* Fatal error in TL>0 handler */
11597c478bd9Sstevel@tonic-gate #define	CH_ERR_TL	0x10	/* Error occured at TL>0 */
11607c478bd9Sstevel@tonic-gate #define	CH_ERR_ME_SHIFT	   8	/* If multiple errors, shift left newest */
11617c478bd9Sstevel@tonic-gate #define	CH_ERR_ME_FLAGS(x)	((x) >> CH_ERR_ME_SHIFT)
11627c478bd9Sstevel@tonic-gate 
11637c478bd9Sstevel@tonic-gate /*
11647c478bd9Sstevel@tonic-gate  * Defines for Bit8 (CH_ERR_TSTATE_IC_ON) and Bit9 (CH_ERR_TSTATE_DC_ON)
11657c478bd9Sstevel@tonic-gate  * in %tstate, which is used to remember D$/I$ state on Fast ECC handler
11667c478bd9Sstevel@tonic-gate  * at TL>0.  Note that DCU_IC=0x1, DCU_DC=0x2.
11677c478bd9Sstevel@tonic-gate  */
11687c478bd9Sstevel@tonic-gate #define	CH_ERR_G2_TO_TSTATE_SHFT	10
11697c478bd9Sstevel@tonic-gate #define	CH_ERR_DCU_TO_TSTATE_SHFT	8
11707c478bd9Sstevel@tonic-gate #define	CH_ERR_TSTATE_IC_ON	(DCU_IC << CH_ERR_DCU_TO_TSTATE_SHFT)
11717c478bd9Sstevel@tonic-gate #define	CH_ERR_TSTATE_DC_ON	(DCU_DC << CH_ERR_DCU_TO_TSTATE_SHFT)
11727c478bd9Sstevel@tonic-gate 
11737c478bd9Sstevel@tonic-gate /*
11747c478bd9Sstevel@tonic-gate  * Multiple offset TL>0 handler structure elements
11757c478bd9Sstevel@tonic-gate  */
11767c478bd9Sstevel@tonic-gate #define	CH_ERR_TL1_DATA		(CH_ERR_TL1_LOGOUT + CH_CLO_DATA)
11777c478bd9Sstevel@tonic-gate #define	CH_ERR_TL1_SDW_DATA	(CH_ERR_TL1_LOGOUT + CH_CLO_SDW_DATA)
1178