1*25cf1a30Sjl /*
2*25cf1a30Sjl  * CDDL HEADER START
3*25cf1a30Sjl  *
4*25cf1a30Sjl  * The contents of this file are subject to the terms of the
5*25cf1a30Sjl  * Common Development and Distribution License (the "License").
6*25cf1a30Sjl  * You may not use this file except in compliance with the License.
7*25cf1a30Sjl  *
8*25cf1a30Sjl  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9*25cf1a30Sjl  * or http://www.opensolaris.org/os/licensing.
10*25cf1a30Sjl  * See the License for the specific language governing permissions
11*25cf1a30Sjl  * and limitations under the License.
12*25cf1a30Sjl  *
13*25cf1a30Sjl  * When distributing Covered Code, include this CDDL HEADER in each
14*25cf1a30Sjl  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15*25cf1a30Sjl  * If applicable, add the following below this CDDL HEADER, with the
16*25cf1a30Sjl  * fields enclosed by brackets "[]" replaced with your own identifying
17*25cf1a30Sjl  * information: Portions Copyright [yyyy] [name of copyright owner]
18*25cf1a30Sjl  *
19*25cf1a30Sjl  * CDDL HEADER END
20*25cf1a30Sjl  */
21*25cf1a30Sjl /*
22*25cf1a30Sjl  * Copyright 2006 Sun Microsystems, Inc.  All rights reserved.
23*25cf1a30Sjl  * Use is subject to license terms.
24*25cf1a30Sjl  */
26*25cf1a30Sjl #ifndef	_SYS_PCMU_PBM_H
27*25cf1a30Sjl #define	_SYS_PCMU_PBM_H
29*25cf1a30Sjl #pragma ident	"%Z%%M%	%I%	%E% SMI"
31*25cf1a30Sjl #include <sys/types.h>
32*25cf1a30Sjl #include <sys/dditypes.h>
33*25cf1a30Sjl #include <sys/ontrap.h>
34*25cf1a30Sjl #include <sys/callb.h>
36*25cf1a30Sjl #ifdef	__cplusplus
37*25cf1a30Sjl extern "C" {
38*25cf1a30Sjl #endif
40*25cf1a30Sjl /*
41*25cf1a30Sjl  * The following structure represents the pci configuration header
42*25cf1a30Sjl  * for CMU-CH PBM.
43*25cf1a30Sjl  */
44*25cf1a30Sjl typedef struct config_header {
45*25cf1a30Sjl 	volatile uint16_t ch_vendor_id;
46*25cf1a30Sjl 	volatile uint16_t ch_device_id;
47*25cf1a30Sjl 	volatile uint16_t ch_command_reg;
48*25cf1a30Sjl 	volatile uint16_t ch_status_reg;
49*25cf1a30Sjl 	volatile uint8_t ch_revision_id_reg;
50*25cf1a30Sjl 	volatile uint8_t ch_programming_if_code_reg;
51*25cf1a30Sjl 	volatile uint8_t ch_sub_class_reg;
52*25cf1a30Sjl 	volatile uint8_t ch_base_class_reg;
53*25cf1a30Sjl 	volatile uint8_t ch_cache_line_size_reg;
54*25cf1a30Sjl 	volatile uint8_t ch_latency_timer_reg;
55*25cf1a30Sjl 	volatile uint8_t ch_header_type_reg;
56*25cf1a30Sjl } config_header_t;
58*25cf1a30Sjl #define	PBM_NAMESTR_BUFLEN	64
60*25cf1a30Sjl /*
61*25cf1a30Sjl  * CMU-CH pbm block soft state structure:
62*25cf1a30Sjl  */
63*25cf1a30Sjl struct pcmu_pbm {
64*25cf1a30Sjl 	pcmu_t *pcbm_pcmu_p;		/* link back to the soft state */
66*25cf1a30Sjl 	volatile uint64_t *pcbm_ctrl_reg;		/* PBM control reg */
67*25cf1a30Sjl 	volatile uint64_t *pcbm_async_flt_status_reg;	/* PBM AFSR reg */
68*25cf1a30Sjl 	volatile uint64_t *pcbm_async_flt_addr_reg;	/* PBM AFAR reg */
69*25cf1a30Sjl 	volatile uint64_t *pcbm_diag_reg;		/* PBM diag reg */
71*25cf1a30Sjl 	config_header_t *pcbm_config_header;		/* PBM config header */
72*25cf1a30Sjl 	uint64_t pcbm_imr_save;				/* intr map save area */
73*25cf1a30Sjl 	ddi_iblock_cookie_t pcbm_iblock_cookie;	/* PBM error intr priority */
75*25cf1a30Sjl 	on_trap_data_t *pcbm_ontrap_data;	/* ddi_poke support */
76*25cf1a30Sjl 	kmutex_t pcbm_pokeflt_mutex;		/* poke mutex */
77*25cf1a30Sjl 	ddi_acc_handle_t pcbm_excl_handle;	/* cautious IO access handle */
78*25cf1a30Sjl 	char pcbm_nameinst_str[PBM_NAMESTR_BUFLEN]; /* driver name & inst */
79*25cf1a30Sjl 	char *pcbm_nameaddr_str;		/* node name & address */
80*25cf1a30Sjl };
82*25cf1a30Sjl /*
83*25cf1a30Sjl  * Prototypes
84*25cf1a30Sjl  */
85*25cf1a30Sjl extern void pcmu_pbm_create(pcmu_t *pcmu_p);
86*25cf1a30Sjl extern void pcmu_pbm_destroy(pcmu_t *pcmu_p);
87*25cf1a30Sjl extern void pcmu_pbm_configure(pcmu_pbm_t *pcbm_p);
88*25cf1a30Sjl extern void pcmu_pbm_suspend(pcmu_pbm_t *pcbm_p);
89*25cf1a30Sjl extern void pcmu_pbm_resume(pcmu_pbm_t *pcbm_p);
90*25cf1a30Sjl extern void pcmu_pbm_intr_dist(void *arg);
91*25cf1a30Sjl extern int pcmu_pbm_register_intr(pcmu_pbm_t *pcbm_p);
92*25cf1a30Sjl extern int pcmu_pbm_afsr_report(dev_info_t *dip, uint64_t fme_ena,
93*25cf1a30Sjl     pcmu_pbm_errstate_t *pbm_err_p);
95*25cf1a30Sjl #ifdef	__cplusplus
96*25cf1a30Sjl }
97*25cf1a30Sjl #endif
99*25cf1a30Sjl #endif	/* _SYS_PCMU_PBM_H */