1*25cf1a30Sjl /*
2*25cf1a30Sjl  * CDDL HEADER START
3*25cf1a30Sjl  *
4*25cf1a30Sjl  * The contents of this file are subject to the terms of the
5*25cf1a30Sjl  * Common Development and Distribution License (the "License").
6*25cf1a30Sjl  * You may not use this file except in compliance with the License.
7*25cf1a30Sjl  *
8*25cf1a30Sjl  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9*25cf1a30Sjl  * or http://www.opensolaris.org/os/licensing.
10*25cf1a30Sjl  * See the License for the specific language governing permissions
11*25cf1a30Sjl  * and limitations under the License.
12*25cf1a30Sjl  *
13*25cf1a30Sjl  * When distributing Covered Code, include this CDDL HEADER in each
14*25cf1a30Sjl  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15*25cf1a30Sjl  * If applicable, add the following below this CDDL HEADER, with the
16*25cf1a30Sjl  * fields enclosed by brackets "[]" replaced with your own identifying
17*25cf1a30Sjl  * information: Portions Copyright [yyyy] [name of copyright owner]
18*25cf1a30Sjl  *
19*25cf1a30Sjl  * CDDL HEADER END
20*25cf1a30Sjl  */
21*25cf1a30Sjl /*
22*25cf1a30Sjl  * Copyright 2006 Sun Microsystems, Inc.  All rights reserved.
23*25cf1a30Sjl  * Use is subject to license terms.
24*25cf1a30Sjl  */
26*25cf1a30Sjl #ifndef	_SYS_PCMU_CB_H
27*25cf1a30Sjl #define	_SYS_PCMU_CB_H
29*25cf1a30Sjl #pragma ident	"%Z%%M%	%I%	%E% SMI"
31*25cf1a30Sjl #ifdef	__cplusplus
32*25cf1a30Sjl extern "C" {
33*25cf1a30Sjl #endif
35*25cf1a30Sjl enum pcmu_cb_nintr_index {
36*25cf1a30Sjl 	CBNINTR_PBM = 0,		/* not shared */
37*25cf1a30Sjl 	CBNINTR_UE = 1,			/* shared */
38*25cf1a30Sjl 	CBNINTR_CE = 2,			/* shared */
39*25cf1a30Sjl 	CBNINTR_POWER_FAIL	= 3,	/* shared */
40*25cf1a30Sjl 	CBNINTR_THERMAL		= 4,	/* shared */
41*25cf1a30Sjl 	CBNINTR_MAX			/* max */
42*25cf1a30Sjl };
44*25cf1a30Sjl /*
45*25cf1a30Sjl  * control block soft state structure:
46*25cf1a30Sjl  */
47*25cf1a30Sjl struct pcmu_cb {
48*25cf1a30Sjl 	pcmu_t *pcb_pcmu_p;
49*25cf1a30Sjl 	pcmu_ign_t pcb_ign;		/* interrupt grp# */
50*25cf1a30Sjl 	kmutex_t pcb_intr_lock;		/* guards add/rem intr and intr dist */
51*25cf1a30Sjl 	uint32_t pcb_no_of_inos;	/* # of actual inos, including PBM */
52*25cf1a30Sjl 	uint32_t pcb_inos[CBNINTR_MAX];	/* subset of pcmu_p->pcmu_inos array */
53*25cf1a30Sjl 	uint64_t pcb_base_pa;		/* PA of CSR bank, 2nd "reg" */
54*25cf1a30Sjl 	uint64_t pcb_map_pa;		/* map reg base PA */
55*25cf1a30Sjl 	uint64_t pcb_clr_pa;		/* clr reg base PA */
56*25cf1a30Sjl 	uint64_t pcb_obsta_pa;		/* sta reg base PA */
57*25cf1a30Sjl 	uint64_t *pcb_imr_save;
58*25cf1a30Sjl 	caddr_t pcb_ittrans_cookie;	/* intr tgt translation */
59*25cf1a30Sjl };
61*25cf1a30Sjl #define	PCMU_CB_INO_TO_MONDO(pcb_p, ino)			\
62*25cf1a30Sjl 	    ((pcb_p)->pcb_ign << PCMU_INO_BITS |  (ino))
64*25cf1a30Sjl /*
65*25cf1a30Sjl  * Prototypes.
66*25cf1a30Sjl  */
67*25cf1a30Sjl extern void pcmu_cb_create(pcmu_t *pcmu_p);
68*25cf1a30Sjl extern void pcmu_cb_destroy(pcmu_t *pcmu_p);
69*25cf1a30Sjl extern void pcmu_cb_suspend(pcmu_cb_t *cb_p);
70*25cf1a30Sjl extern void pcmu_cb_resume(pcmu_cb_t *cb_p);
71*25cf1a30Sjl extern void pcmu_cb_enable_nintr(pcmu_t *pcmu_p, pcmu_cb_nintr_index_t idx);
72*25cf1a30Sjl extern void pcmu_cb_disable_nintr(pcmu_cb_t *cb_p,
73*25cf1a30Sjl     pcmu_cb_nintr_index_t idx, int wait);
74*25cf1a30Sjl extern void pcmu_cb_clear_nintr(pcmu_cb_t *cb_p, pcmu_cb_nintr_index_t idx);
75*25cf1a30Sjl extern void pcmu_cb_intr_dist(void *arg);
77*25cf1a30Sjl #ifdef	__cplusplus
78*25cf1a30Sjl }
79*25cf1a30Sjl #endif
81*25cf1a30Sjl #endif	/* _SYS_PCMU_CB_H */