125cf1a30Sjl /* 225cf1a30Sjl * CDDL HEADER START 325cf1a30Sjl * 425cf1a30Sjl * The contents of this file are subject to the terms of the 525cf1a30Sjl * Common Development and Distribution License (the "License"). 625cf1a30Sjl * You may not use this file except in compliance with the License. 725cf1a30Sjl * 825cf1a30Sjl * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 925cf1a30Sjl * or http://www.opensolaris.org/os/licensing. 1025cf1a30Sjl * See the License for the specific language governing permissions 1125cf1a30Sjl * and limitations under the License. 1225cf1a30Sjl * 1325cf1a30Sjl * When distributing Covered Code, include this CDDL HEADER in each 1425cf1a30Sjl * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 1525cf1a30Sjl * If applicable, add the following below this CDDL HEADER, with the 1625cf1a30Sjl * fields enclosed by brackets "[]" replaced with your own identifying 1725cf1a30Sjl * information: Portions Copyright [yyyy] [name of copyright owner] 1825cf1a30Sjl * 1925cf1a30Sjl * CDDL HEADER END 2025cf1a30Sjl */ 2125cf1a30Sjl /* 22*c9b6d37cSfherard * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 2325cf1a30Sjl * Use is subject to license terms. 2425cf1a30Sjl */ 2525cf1a30Sjl 2625cf1a30Sjl #ifndef _SYS_PCICMU_H 2725cf1a30Sjl #define _SYS_PCICMU_H 2825cf1a30Sjl 2925cf1a30Sjl #pragma ident "%Z%%M% %I% %E% SMI" 3025cf1a30Sjl 3125cf1a30Sjl 3225cf1a30Sjl #ifdef __cplusplus 3325cf1a30Sjl extern "C" { 3425cf1a30Sjl #endif 3525cf1a30Sjl 3625cf1a30Sjl #include <sys/pci.h> 3725cf1a30Sjl #include <sys/pci_intr_lib.h> 3825cf1a30Sjl #include <sys/pcicmu/pcmu_types.h> 3925cf1a30Sjl #include <sys/pcicmu/pcmu_ib.h> 4025cf1a30Sjl #include <sys/pcicmu/pcmu_cb.h> 4125cf1a30Sjl #include <sys/pcicmu/pcmu_ecc.h> 4225cf1a30Sjl #include <sys/pcicmu/pcmu_pbm.h> 4325cf1a30Sjl #include <sys/pcicmu/pcmu_counters.h> 4425cf1a30Sjl #include <sys/pcicmu/pcmu_util.h> 4525cf1a30Sjl #include <sys/pcicmu/pcmu_err.h> 4625cf1a30Sjl 4725cf1a30Sjl 4825cf1a30Sjl /* 4925cf1a30Sjl * The following typedef is used to represent a 5025cf1a30Sjl * 1275 "bus-range" property of a PCI Bus node. 5125cf1a30Sjl */ 5225cf1a30Sjl struct pcmu_bus_range { 5325cf1a30Sjl uint32_t lo; 5425cf1a30Sjl uint32_t hi; 5525cf1a30Sjl }; 5625cf1a30Sjl 5725cf1a30Sjl /* 5825cf1a30Sjl * Structure to represent an entry in the 5925cf1a30Sjl * "ranges" property of a device node. 6025cf1a30Sjl */ 6125cf1a30Sjl struct pcmu_ranges { 6225cf1a30Sjl uint32_t child_high; 6325cf1a30Sjl uint32_t child_mid; 6425cf1a30Sjl uint32_t child_low; 6525cf1a30Sjl uint32_t parent_high; 6625cf1a30Sjl uint32_t parent_low; 6725cf1a30Sjl uint32_t size_high; 6825cf1a30Sjl uint32_t size_low; 6925cf1a30Sjl }; 7025cf1a30Sjl 7125cf1a30Sjl typedef enum { 7225cf1a30Sjl PCMU_NEW, 7325cf1a30Sjl PCMU_ATTACHED, 7425cf1a30Sjl PCMU_DETACHED, 7525cf1a30Sjl PCMU_SUSPENDED 7625cf1a30Sjl } pcmu_state_t; 7725cf1a30Sjl 7825cf1a30Sjl typedef enum { 7925cf1a30Sjl PCMU_PBM_OBJ, 8025cf1a30Sjl PCMU_ECC_OBJ, 8125cf1a30Sjl PCMU_CB_OBJ 8225cf1a30Sjl } pcmu_obj_t; 8325cf1a30Sjl 8425cf1a30Sjl typedef enum { 8525cf1a30Sjl PCMU_OBJ_INTR_ADD, 8625cf1a30Sjl PCMU_OBJ_INTR_REMOVE 8725cf1a30Sjl } pcmu_obj_op_t; 8825cf1a30Sjl 8925cf1a30Sjl #define PCI_OPLCMU "pcicmu" 9025cf1a30Sjl 9125cf1a30Sjl /* 9225cf1a30Sjl * pcicmu soft state structure. 9325cf1a30Sjl */ 9425cf1a30Sjl struct pcicmu { 9525cf1a30Sjl /* 9625cf1a30Sjl * State flags and mutex: 9725cf1a30Sjl */ 9825cf1a30Sjl pcmu_state_t pcmu_state; 9925cf1a30Sjl uint_t pcmu_soft_state; 10025cf1a30Sjl uint_t pcmu_open_count; 10125cf1a30Sjl kmutex_t pcmu_mutex; 10225cf1a30Sjl 10325cf1a30Sjl /* 10425cf1a30Sjl * Links to other state structures: 10525cf1a30Sjl */ 10625cf1a30Sjl dev_info_t *pcmu_dip; /* devinfo structure */ 10725cf1a30Sjl pcmu_ib_t *pcmu_ib_p; /* interrupt block */ 10825cf1a30Sjl pcmu_cb_t *pcmu_cb_p; /* control block */ 10925cf1a30Sjl pcmu_pbm_t *pcmu_pcbm_p; /* PBM block */ 11025cf1a30Sjl pcmu_ecc_t *pcmu_pecc_p; /* ECC error block */ 11125cf1a30Sjl 11225cf1a30Sjl /* 11325cf1a30Sjl * other state info: 11425cf1a30Sjl */ 11525cf1a30Sjl uint_t pcmu_id; /* Jupiter device id */ 11625cf1a30Sjl uint32_t pcmu_rev; /* Bus bridge chip identification */ 11725cf1a30Sjl 11825cf1a30Sjl /* 11925cf1a30Sjl * pci device node properties: 12025cf1a30Sjl */ 12125cf1a30Sjl pcmu_bus_range_t pcmu_bus_range; /* "bus-range" */ 12225cf1a30Sjl pcmu_ranges_t *pcmu_ranges; /* "ranges" data & length */ 12325cf1a30Sjl int pcmu_ranges_length; 12425cf1a30Sjl uint32_t *pcmu_inos; /* inos from "interrupts" prop */ 12525cf1a30Sjl int pcmu_inos_len; /* "interrupts" length */ 12625cf1a30Sjl int pcmu_numproxy; /* upa interrupt proxies */ 12725cf1a30Sjl 12825cf1a30Sjl /* 12925cf1a30Sjl * register mapping: 13025cf1a30Sjl */ 13125cf1a30Sjl caddr_t pcmu_address[4]; 13225cf1a30Sjl ddi_acc_handle_t pcmu_ac[4]; 13325cf1a30Sjl 13425cf1a30Sjl /* 13525cf1a30Sjl * Performance counters kstat. 13625cf1a30Sjl */ 13725cf1a30Sjl pcmu_cntr_pa_t pcmu_uks_pa; 13825cf1a30Sjl kstat_t *pcmu_uksp; /* ptr to upstream kstat */ 13925cf1a30Sjl kmutex_t pcmu_err_mutex; /* per chip error handling mutex */ 14025cf1a30Sjl 14125cf1a30Sjl /* Fault Management support */ 14225cf1a30Sjl int pcmu_fm_cap; 14325cf1a30Sjl ddi_iblock_cookie_t pcmu_fm_ibc; 14425cf1a30Sjl }; 14525cf1a30Sjl 14625cf1a30Sjl /* 14725cf1a30Sjl * pcmu_soft_state values. 14825cf1a30Sjl */ 14925cf1a30Sjl #define PCMU_SOFT_STATE_OPEN 0x01 15025cf1a30Sjl #define PCMU_SOFT_STATE_OPEN_EXCL 0x02 15125cf1a30Sjl #define PCMU_SOFT_STATE_CLOSED 0x04 15225cf1a30Sjl 15325cf1a30Sjl /* 15425cf1a30Sjl * CMU-CH and PBM soft state macros: 15525cf1a30Sjl */ 15625cf1a30Sjl #define PCMU_AP_MINOR_NUM_TO_INSTANCE(x) ((x) >> 8) 15725cf1a30Sjl 15825cf1a30Sjl #define get_pcmu_soft_state(i) \ 15925cf1a30Sjl ((pcmu_t *)ddi_get_soft_state(per_pcmu_state, (i))) 16025cf1a30Sjl 16125cf1a30Sjl #define alloc_pcmu_soft_state(i) \ 16225cf1a30Sjl ddi_soft_state_zalloc(per_pcmu_state, (i)) 16325cf1a30Sjl 16425cf1a30Sjl #define free_pcmu_soft_state(i) \ 16525cf1a30Sjl ddi_soft_state_free(per_pcmu_state, (i)) 16625cf1a30Sjl 16725cf1a30Sjl #define DEV_TO_SOFTSTATE(dev) ((pcmu_t *)ddi_get_soft_state(per_pcmu_state, \ 16825cf1a30Sjl PCMU_AP_MINOR_NUM_TO_INSTANCE(getminor(dev)))) 16925cf1a30Sjl 17025cf1a30Sjl #define PCMU_ATTACH_RETCODE(obj, op, err) \ 17125cf1a30Sjl ((err) ? (obj) << 8 | (op) << 4 | (err) & 0xf : DDI_SUCCESS) 17225cf1a30Sjl 17325cf1a30Sjl 17425cf1a30Sjl /* 17525cf1a30Sjl * Performance counters information. 17625cf1a30Sjl */ 17725cf1a30Sjl #define PCMU_SHIFT_PIC0 8 17825cf1a30Sjl #define PCMU_SHIFT_PIC1 0 17925cf1a30Sjl 18025cf1a30Sjl /* 18125cf1a30Sjl * CMU-CH-specific register offsets & bit field positions. 18225cf1a30Sjl */ 18325cf1a30Sjl 18425cf1a30Sjl /* 18525cf1a30Sjl * Offsets of global registers: 18625cf1a30Sjl */ 18725cf1a30Sjl #define PCMU_CB_DEVICE_ID_REG_OFFSET 0x00000000 /* RAGS */ 18825cf1a30Sjl #define PCMU_CB_CONTROL_STATUS_REG_OFFSET 0x00000010 18925cf1a30Sjl 19025cf1a30Sjl /* 19125cf1a30Sjl * CMU-CH performance counters offsets. 19225cf1a30Sjl */ 19325cf1a30Sjl #define PCMU_PERF_PCR_OFFSET 0x00000100 19425cf1a30Sjl #define PCMU_PERF_PIC_OFFSET 0x00000108 19525cf1a30Sjl 19625cf1a30Sjl /* 19725cf1a30Sjl * Offsets of registers in the interrupt block: 19825cf1a30Sjl */ 19925cf1a30Sjl #define PCMU_IB_OBIO_INTR_MAP_REG_OFFSET 0x00001000 20025cf1a30Sjl #define PCMU_IB_OBIO_CLEAR_INTR_REG_OFFSET 0x00001800 20125cf1a30Sjl 20225cf1a30Sjl /* 20325cf1a30Sjl * Offsets of registers in the PBM block: 20425cf1a30Sjl */ 20525cf1a30Sjl #define PCMU_PCI_PBM_REG_BASE 0x00002000 /* RAGS */ 20625cf1a30Sjl #define PCMU_PCI_CTRL_REG_OFFSET 0x00000000 20725cf1a30Sjl #define PCMU_PCI_ASYNC_FLT_STATUS_REG_OFFSET 0x00000010 20825cf1a30Sjl #define PCMU_PCI_ASYNC_FLT_ADDR_REG_OFFSET 0x00000018 20925cf1a30Sjl #define PCMU_PCI_DIAG_REG_OFFSET 0x00000020 21025cf1a30Sjl 21125cf1a30Sjl /* 21225cf1a30Sjl * CMU-CH control register bit definitions: 21325cf1a30Sjl */ 21425cf1a30Sjl #define PCMU_CB_CONTROL_STATUS_MODE 0x0000000000000001ull 21525cf1a30Sjl #define PCMU_CB_CONTROL_STATUS_IMPL 0xf000000000000000ull 21625cf1a30Sjl #define PCMU_CB_CONTROL_STATUS_IMPL_SHIFT 60 21725cf1a30Sjl #define PCMU_CB_CONTROL_STATUS_VER 0x0f00000000000000ull 21825cf1a30Sjl #define PCMU_CB_CONTROL_STATUS_VER_SHIFT 56 21925cf1a30Sjl 22025cf1a30Sjl /* 22125cf1a30Sjl * CMU-CH ECC UE AFSR bit definitions: 22225cf1a30Sjl */ 22325cf1a30Sjl #define PCMU_ECC_UE_AFSR_BYTEMASK 0x0000ffff00000000ull 22425cf1a30Sjl #define PCMU_ECC_UE_AFSR_BYTEMASK_SHIFT 32 22525cf1a30Sjl #define PCMU_ECC_UE_AFSR_DW_OFFSET 0x00000000e0000000ull 22625cf1a30Sjl #define PCMU_ECC_UE_AFSR_DW_OFFSET_SHIFT 29 22725cf1a30Sjl #define PCMU_ECC_UE_AFSR_ID 0x000000001f000000ull 22825cf1a30Sjl #define PCMU_ECC_UE_AFSR_ID_SHIFT 24 22925cf1a30Sjl #define PCMU_ECC_UE_AFSR_BLK 0x0000000000800000ull 23025cf1a30Sjl 23125cf1a30Sjl /* 23225cf1a30Sjl * CMU-CH pci control register bits: 23325cf1a30Sjl */ 23425cf1a30Sjl #define PCMU_PCI_CTRL_ARB_PARK 0x0000000000200000ull 23525cf1a30Sjl #define PCMU_PCI_CTRL_WAKEUP_EN 0x0000000000000200ull 23625cf1a30Sjl #define PCMU_PCI_CTRL_ERR_INT_EN 0x0000000000000100ull 23725cf1a30Sjl #define PCMU_PCI_CTRL_ARB_EN_MASK 0x000000000000000full 23825cf1a30Sjl 23925cf1a30Sjl /* 24025cf1a30Sjl * CMU-CH PCI asynchronous fault status register bit definitions: 24125cf1a30Sjl */ 24225cf1a30Sjl #define PCMU_PCI_AFSR_PE_SHIFT 60 24325cf1a30Sjl #define PCMU_PCI_AFSR_SE_SHIFT 56 24425cf1a30Sjl #define PCMU_PCI_AFSR_E_MA 0x0000000000000008ull 24525cf1a30Sjl #define PCMU_PCI_AFSR_E_TA 0x0000000000000004ull 24625cf1a30Sjl #define PCMU_PCI_AFSR_E_RTRY 0x0000000000000002ull 24725cf1a30Sjl #define PCMU_PCI_AFSR_E_PERR 0x0000000000000001ull 24825cf1a30Sjl #define PCMU_PCI_AFSR_E_MASK 0x000000000000000full 24925cf1a30Sjl #define PCMU_PCI_AFSR_BYTEMASK 0x0000ffff00000000ull 25025cf1a30Sjl #define PCMU_PCI_AFSR_BYTEMASK_SHIFT 32 25125cf1a30Sjl #define PCMU_PCI_AFSR_BLK 0x0000000080000000ull 25225cf1a30Sjl #define PCMU_PCI_AFSR_MID 0x000000003e000000ull 25325cf1a30Sjl #define PCMU_PCI_AFSR_MID_SHIFT 25 25425cf1a30Sjl 25525cf1a30Sjl /* 25625cf1a30Sjl * CMU-CH PCI diagnostic register bit definitions: 25725cf1a30Sjl */ 25825cf1a30Sjl #define PCMU_PCI_DIAG_DIS_DWSYNC 0x0000000000000010ull 25925cf1a30Sjl 26025cf1a30Sjl #define PBM_AFSR_TO_PRIERR(afsr) \ 26125cf1a30Sjl (afsr >> PCMU_PCI_AFSR_PE_SHIFT & PCMU_PCI_AFSR_E_MASK) 26225cf1a30Sjl #define PBM_AFSR_TO_SECERR(afsr) \ 26325cf1a30Sjl (afsr >> PCMU_PCI_AFSR_SE_SHIFT & PCMU_PCI_AFSR_E_MASK) 26425cf1a30Sjl 26525cf1a30Sjl #define PCMU_ID_TO_IGN(pcmu_id) ((pcmu_ign_t)UPAID_TO_IGN(pcmu_id)) 26625cf1a30Sjl 26725cf1a30Sjl 26825cf1a30Sjl /* 26925cf1a30Sjl * Number of dispatch target entries. 27025cf1a30Sjl */ 27125cf1a30Sjl #define U2U_DATA_NUM 16 27225cf1a30Sjl 27325cf1a30Sjl /* 27425cf1a30Sjl * Offsets of registers in the Interrupt Dispatch Table: 27525cf1a30Sjl */ 27625cf1a30Sjl #define U2U_MODE_STATUS_REGISTER_OFFSET 0x00000000 27725cf1a30Sjl #define U2U_PID_REGISTER_OFFSET 0x00000008 27825cf1a30Sjl #define U2U_DATA_REGISTER_OFFSET 0x00000010 27925cf1a30Sjl 28025cf1a30Sjl /* 28125cf1a30Sjl * Mode Status register bit definitions: 28225cf1a30Sjl */ 28325cf1a30Sjl #define U2U_MS_IEV 0x00000040 /* bit-6: Interrupt Extension enable */ 28425cf1a30Sjl 28525cf1a30Sjl /* 28625cf1a30Sjl * Index number of U2U registers in OBP's "regs-property" of CMU-CH 28725cf1a30Sjl */ 28825cf1a30Sjl #define REGS_INDEX_OF_U2U 3 28925cf1a30Sjl 29025cf1a30Sjl /* 29125cf1a30Sjl * The following two difinitions are used to control target id 29225cf1a30Sjl * for Interrupt dispatch data by software. 29325cf1a30Sjl */ 29425cf1a30Sjl typedef struct u2u_ittrans_id { 29525cf1a30Sjl uint_t u2u_tgt_cpu_id; /* target CPU ID */ 29625cf1a30Sjl uint_t u2u_rsv1; /* reserved */ 29725cf1a30Sjl volatile uint64_t *u2u_ino_map_reg; /* u2u intr. map register */ 29825cf1a30Sjl } u2u_ittrans_id_t; 29925cf1a30Sjl 30025cf1a30Sjl typedef struct u2u_ittrans_data { 30125cf1a30Sjl kmutex_t u2u_ittrans_lock; 30225cf1a30Sjl uintptr_t u2u_regs_base; /* "reg" property */ 30325cf1a30Sjl ddi_acc_handle_t u2u_acc; /* pointer to acc */ 30425cf1a30Sjl uint_t u2u_port_id; /* "PID" register n U2U */ 30525cf1a30Sjl uint_t u2u_board; /* "board#" property */ 30625cf1a30Sjl u2u_ittrans_id_t u2u_ittrans_id[U2U_DATA_NUM]; 30725cf1a30Sjl } u2u_ittrans_data_t; 30825cf1a30Sjl 309*c9b6d37cSfherard /* 310*c9b6d37cSfherard * Driver binding name for OPL DC system 311*c9b6d37cSfherard */ 312*c9b6d37cSfherard #define PCICMU_OPL_DC_BINDING_NAME "pci10cf,1390" 31325cf1a30Sjl 31425cf1a30Sjl /* 31525cf1a30Sjl * Offsets of registers in the interrupt block: 31625cf1a30Sjl */ 31725cf1a30Sjl 31825cf1a30Sjl #define PCMU_IB_UPA0_INTR_MAP_REG_OFFSET 0x6000 31925cf1a30Sjl #define PCMU_IB_UPA1_INTR_MAP_REG_OFFSET 0x8000 32025cf1a30Sjl #define PCMU_IB_SLOT_CLEAR_INTR_REG_OFFSET 0x1400 32125cf1a30Sjl #define PCMU_IB_OBIO_INTR_STATE_DIAG_REG 0xA808 32225cf1a30Sjl #define PCMU_IB_INTR_RETRY_TIMER_OFFSET 0x1A00 32325cf1a30Sjl 32425cf1a30Sjl /* 32525cf1a30Sjl * Offsets of registers in the ECC block: 32625cf1a30Sjl */ 32725cf1a30Sjl #define PCMU_ECC_CSR_OFFSET 0x20 32825cf1a30Sjl #define PCMU_UE_AFSR_OFFSET 0x30 32925cf1a30Sjl #define PCMU_UE_AFAR_OFFSET 0x38 33025cf1a30Sjl 33125cf1a30Sjl /* 33225cf1a30Sjl * CMU-CH control register bit definitions: 33325cf1a30Sjl */ 33425cf1a30Sjl #define PCMU_CB_CONTROL_STATUS_IGN 0x0007c00000000000ull 33525cf1a30Sjl #define PCMU_CB_CONTROL_STATUS_IGN_SHIFT 46 33625cf1a30Sjl #define PCMU_CB_CONTROL_STATUS_APCKEN 0x0000000000000008ull 33725cf1a30Sjl #define PCMU_CB_CONTROL_STATUS_APERR 0x0000000000000004ull 33825cf1a30Sjl #define PCMU_CB_CONTROL_STATUS_IAP 0x0000000000000002ull 33925cf1a30Sjl 34025cf1a30Sjl /* 34125cf1a30Sjl * CMU-CH interrupt mapping register bit definitions: 34225cf1a30Sjl */ 34325cf1a30Sjl #define PCMU_INTR_MAP_REG_VALID 0x0000000080000000ull 34425cf1a30Sjl #define PCMU_INTR_MAP_REG_TID 0x000000007C000000ull 34525cf1a30Sjl #define PCMU_INTR_MAP_REG_IGN 0x00000000000007C0ull 34625cf1a30Sjl #define PCMU_INTR_MAP_REG_INO 0x000000000000003full 34725cf1a30Sjl #define PCMU_INTR_MAP_REG_TID_SHIFT 26 34825cf1a30Sjl #define PCMU_INTR_MAP_REG_IGN_SHIFT 6 34925cf1a30Sjl 35025cf1a30Sjl /* 35125cf1a30Sjl * CMU-CH clear interrupt register bit definitions: 35225cf1a30Sjl */ 35325cf1a30Sjl #define PCMU_CLEAR_INTR_REG_MASK 0x0000000000000003ull 35425cf1a30Sjl #define PCMU_CLEAR_INTR_REG_IDLE 0x0000000000000000ull 35525cf1a30Sjl #define PCMU_CLEAR_INTR_REG_RECEIVED 0x0000000000000001ull 35625cf1a30Sjl #define PCMU_CLEAR_INTR_REG_RSVD 0x0000000000000002ull 35725cf1a30Sjl #define PCMU_CLEAR_INTR_REG_PENDING 0x0000000000000003ull 35825cf1a30Sjl 35925cf1a30Sjl /* 36025cf1a30Sjl * CMU-CH ECC control register bit definitions: 36125cf1a30Sjl */ 36225cf1a30Sjl #define PCMU_ECC_CTRL_ECC_EN 0x8000000000000000ull 36325cf1a30Sjl #define PCMU_ECC_CTRL_UE_INTEN 0x4000000000000000ull 36425cf1a30Sjl 36525cf1a30Sjl /* 36625cf1a30Sjl * CMU-CH ECC UE AFSR bit definitions: 36725cf1a30Sjl */ 36825cf1a30Sjl #define PCMU_ECC_UE_AFSR_PE_SHIFT 61 36925cf1a30Sjl #define PCMU_ECC_UE_AFSR_SE_SHIFT 58 37025cf1a30Sjl #define PCMU_ECC_UE_AFSR_E_MASK 0x0000000000000007ull 37125cf1a30Sjl #define PCMU_ECC_UE_AFSR_E_PIO 0x0000000000000004ull 37225cf1a30Sjl 37325cf1a30Sjl /* 37425cf1a30Sjl * CMU-CH PCI diagnostic register bit definitions: 37525cf1a30Sjl */ 37625cf1a30Sjl #define PCMU_PCI_DIAG_DIS_RETRY 0x0000000000000040ull 37725cf1a30Sjl #define PCMU_PCI_DIAG_DIS_INTSYNC 0x0000000000000020ull 37825cf1a30Sjl 37925cf1a30Sjl 38025cf1a30Sjl #define NAMEINST(dip) ddi_driver_name(dip), ddi_get_instance(dip) 38125cf1a30Sjl #define NAMEADDR(dip) ddi_node_name(dip), ddi_get_name_addr(dip) 38225cf1a30Sjl 38325cf1a30Sjl 38425cf1a30Sjl /* 38525cf1a30Sjl * CMU-CH Tunables 38625cf1a30Sjl */ 38725cf1a30Sjl extern uint32_t pcmu_spurintr_duration; /* spurious interupt duration */ 38825cf1a30Sjl extern ushort_t pcmu_command_default; /* default command */ 38925cf1a30Sjl extern uint_t ecc_error_intr_enable; /* ECC error intr */ 39025cf1a30Sjl extern uint_t pcmu_ecc_afsr_retries; /* num ECC afsr retries */ 39125cf1a30Sjl extern uint_t pcmu_intr_retry_intv; /* intr retry interval */ 39225cf1a30Sjl extern uint_t pcmu_panic_on_fatal_errors; /* PANIC on fatal errors */ 39325cf1a30Sjl extern uint_t pcmu_unclaimed_intr_max; /* Max unclaimed interrupts */ 39425cf1a30Sjl extern hrtime_t pcmu_intrpend_timeout; /* intr pending timeout */ 39525cf1a30Sjl 39625cf1a30Sjl 39725cf1a30Sjl extern void *per_pcmu_state; /* per-pbm soft state pointer */ 39825cf1a30Sjl extern kmutex_t pcmu_global_mutex; /* attach/detach common struct lock */ 39925cf1a30Sjl extern uint64_t pcmu_errtrig_pa; 40025cf1a30Sjl 40125cf1a30Sjl 40225cf1a30Sjl /* 40325cf1a30Sjl * Prototypes. 40425cf1a30Sjl */ 40525cf1a30Sjl extern void pcmu_post_uninit_child(pcmu_t *); 40625cf1a30Sjl extern void pcmu_kstat_init(void); 40725cf1a30Sjl extern void pcmu_kstat_fini(void); 40825cf1a30Sjl extern void pcmu_add_upstream_kstat(pcmu_t *); 40925cf1a30Sjl extern void pcmu_fix_ranges(pcmu_ranges_t *, int); 41025cf1a30Sjl extern uint_t pcmu_pbm_disable_errors(pcmu_pbm_t *); 41125cf1a30Sjl extern uint32_t ib_map_reg_get_cpu(volatile uint64_t); 41225cf1a30Sjl extern uint64_t *ib_intr_map_reg_addr(pcmu_ib_t *, pcmu_ib_ino_t); 41325cf1a30Sjl extern uint64_t *ib_clear_intr_reg_addr(pcmu_ib_t *, pcmu_ib_ino_t); 41425cf1a30Sjl extern void pcmu_cb_setup(pcmu_t *); 41525cf1a30Sjl extern void pcmu_cb_teardown(pcmu_t *); 41625cf1a30Sjl extern int cb_register_intr(pcmu_t *); 41725cf1a30Sjl extern void cb_enable_intr(pcmu_t *); 41825cf1a30Sjl extern uint64_t cb_ino_to_map_pa(pcmu_cb_t *, pcmu_ib_ino_t); 41925cf1a30Sjl extern uint64_t cb_ino_to_clr_pa(pcmu_cb_t *, pcmu_ib_ino_t); 42025cf1a30Sjl extern int cb_remove_xintr(pcmu_t *, dev_info_t *, dev_info_t *, 42125cf1a30Sjl pcmu_ib_ino_t, pcmu_ib_mondo_t); 42225cf1a30Sjl extern uint32_t pcmu_intr_dist_cpuid(pcmu_ib_t *, pcmu_ib_ino_info_t *); 42325cf1a30Sjl extern void pcmu_ecc_setup(pcmu_ecc_t *); 42425cf1a30Sjl extern ushort_t pcmu_ecc_get_synd(uint64_t); 42525cf1a30Sjl extern void pcmu_pbm_setup(pcmu_pbm_t *); 42625cf1a30Sjl extern void pcmu_pbm_teardown(pcmu_pbm_t *); 42725cf1a30Sjl extern uintptr_t pcmu_ib_setup(pcmu_ib_t *); 42825cf1a30Sjl extern int pcmu_get_numproxy(dev_info_t *); 42925cf1a30Sjl extern int pcmu_ecc_add_intr(pcmu_t *, int, pcmu_ecc_intr_info_t *); 43025cf1a30Sjl extern void pcmu_ecc_rem_intr(pcmu_t *, int, pcmu_ecc_intr_info_t *); 43125cf1a30Sjl extern int pcmu_pbm_err_handler(dev_info_t *, ddi_fm_error_t *, 43225cf1a30Sjl const void *, int); 43325cf1a30Sjl extern void pcmu_ecc_classify(uint64_t, pcmu_ecc_errstate_t *); 43425cf1a30Sjl extern int pcmu_pbm_classify(pcmu_pbm_errstate_t *); 43525cf1a30Sjl extern int pcmu_check_error(pcmu_t *); 43625cf1a30Sjl extern void set_intr_mapping_reg(int, uint64_t *, int); 43725cf1a30Sjl extern uint32_t pcmu_class_to_pil(dev_info_t *rdip); 43825cf1a30Sjl extern int pcmu_add_intr(dev_info_t *dip, dev_info_t *rdip, 43925cf1a30Sjl ddi_intr_handle_impl_t *hdlp); 44025cf1a30Sjl extern int pcmu_remove_intr(dev_info_t *dip, dev_info_t *rdip, 44125cf1a30Sjl ddi_intr_handle_impl_t *hdlp); 44225cf1a30Sjl extern void pcmu_intr_teardown(pcmu_t *pcmu_p); 44325cf1a30Sjl 44425cf1a30Sjl extern int u2u_translate_tgtid(pcmu_t *, uint_t, volatile uint64_t *); 44525cf1a30Sjl extern void u2u_ittrans_cleanup(u2u_ittrans_data_t *, volatile uint64_t *); 44625cf1a30Sjl void pcmu_err_create(pcmu_t *pcmu_p); 44725cf1a30Sjl void pcmu_err_destroy(pcmu_t *pcmu_p); 44825cf1a30Sjl void pcmu_pbm_ereport_post(dev_info_t *dip, uint64_t ena, 44925cf1a30Sjl pcmu_pbm_errstate_t *pbm_err); 45025cf1a30Sjl #ifdef __cplusplus 45125cf1a30Sjl } 45225cf1a30Sjl #endif 45325cf1a30Sjl 45425cf1a30Sjl #endif /* _SYS_PCICMU_H */ 455